WO2022188330A1 - 半导体结构的形成方法及半导体结构 - Google Patents

半导体结构的形成方法及半导体结构 Download PDF

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Publication number
WO2022188330A1
WO2022188330A1 PCT/CN2021/107423 CN2021107423W WO2022188330A1 WO 2022188330 A1 WO2022188330 A1 WO 2022188330A1 CN 2021107423 W CN2021107423 W CN 2021107423W WO 2022188330 A1 WO2022188330 A1 WO 2022188330A1
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sacrificial layer
forming
bit line
sacrificial
layer
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PCT/CN2021/107423
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English (en)
French (fr)
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洪玟基
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长鑫存储技术有限公司
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Priority to US17/452,272 priority Critical patent/US20220293609A1/en
Publication of WO2022188330A1 publication Critical patent/WO2022188330A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

Definitions

  • the present disclosure relates to, but is not limited to, a method of forming a semiconductor structure and a semiconductor structure.
  • DRAM Dynamic Random Access Memory
  • the patterned trenches In the process of patterning the sacrificial layer to form the required trenches for the dielectric layer between adjacent bit line structures, due to the large aspect ratio of the dielectric layer, the patterned trenches also have a large aspect ratio, which may It will cause etching residues in the bottom sacrificial layer, and the etching residues in the subsequent process of forming capacitor contact holes will cause adjacent capacitor contact holes to be connected, thereby affecting the yield of the semiconductor structure; if the etching residues are etched a second time Etching will cause the size of the trench to become larger, thereby affecting the size of the subsequent formation of the capacitor contact hole.
  • the present disclosure provides a method for forming a semiconductor structure and a semiconductor structure.
  • a first aspect of the present disclosure provides a method for forming a semiconductor structure, including: providing a substrate on which discrete bit line structures are formed; forming a first sacrificial layer on a surface of the substrate at the bottom of a gap between the bit line structures; a second sacrificial layer in the gap of the bit line structure, the second sacrificial layer is located on top of the first sacrificial layer, and the materials of the first sacrificial layer and the second sacrificial layer are different; patterning the second sacrificial layer and the first sacrificial layer to form an opening, In the extending direction of the bit line structure, the formed openings and the remaining second sacrificial layers are alternately arranged; the dielectric layer filling the openings is formed; In the extending direction, the formed capacitor contact holes and the dielectric layers are alternately arranged.
  • the sacrificial layer formed in the gap of the discrete bit line structure includes a first sacrificial layer located at the bottom and a second sacrificial layer located at the top, and the materials of the first sacrificial layer and the second sacrificial layer are different, that is, etching
  • the thickness of the sacrificial layer to be etched in each etching process is reduced, that is, the aspect ratio of the trench to be formed in a single etching process is reduced, and each etching process is guaranteed.
  • the groove is formed to form a fully etched groove without affecting the size of the dielectric layer and the size of the capacitor contact hole.
  • a second aspect of the present disclosure provides a semiconductor structure, including: a substrate, and discrete bit line structures on the substrate; a first sacrificial layer on a surface of the substrate at the bottom of a gap of the bit line structure, the thickness of the first sacrificial layer being less than The thickness of the line structure; the second sacrificial layer, located on the surface of the first sacrificial layer at the bottom of the gap of the bit line structure, the materials of the first sacrificial layer and the second sacrificial layer are different; the first sacrificial layer and the second sacrificial layer are used to form Dielectric layer and capacitor contact holes between discrete bit line structures.
  • the sacrificial layer in the gap of the discrete bit line structure includes a first sacrificial layer located at the bottom and a second sacrificial layer located at the top, and the materials of the first sacrificial layer and the second sacrificial layer are different, that is, The aspect ratio of the trench formed by etching the sacrificial layer required in a single etching process is reduced, ensuring that there is no etching residue at the bottom of the trench formed by each etching process; in addition, due to the first sacrificial layer and the second sacrificial layer Different materials, the process of etching the first sacrificial layer will not affect the trench formed by etching the second sacrificial layer, so as to ensure that the size of the dielectric layer and the size of the capacitor contact hole are not affected. groove.
  • FIG. 1 is a top-view structural schematic diagram of a substrate and a bit line structure provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a cross-section of the substrate and the bit line structure shown in FIG. 1 along the A-A' direction.
  • FIG. 3 is a schematic view of the structure after forming the first sacrificial layer on the substrate surface at the bottom of the bit line structure gap in the structure shown in FIG. 2 .
  • FIG. 4 is a schematic structural diagram of the structure shown in FIG. 3 after forming a second sacrificial layer filling the gaps of the discrete bit line structures.
  • FIG. 5 is a schematic view of the structure after patterned photoresist is formed on the top surface of the second sacrificial layer in the structure shown in FIG. 4 .
  • FIG. 6 is a schematic view of the structure shown in FIG. 5 after removing part of the second sacrificial layer based on patterned photoresist to form a pre-opening.
  • FIG. 7 is a schematic view of the structure shown in FIG. 6 after removing the first sacrificial layer exposed by the pre-opening to form an opening.
  • FIG. 8 is a schematic structural diagram of the structure shown in FIG. 7 after forming a dielectric layer filling the openings.
  • FIG. 9 is a schematic view of the structure shown in FIG. 8 after removing the remaining second sacrificial layer to form through holes.
  • FIG. 10 is a schematic view of the structure shown in FIG. 9 after removing the first sacrificial layer at the bottom of the through hole to form a capacitor contact hole.
  • FIG. 11 is a schematic top-view structural diagram of a dielectric layer and a second sacrificial layer according to an embodiment of the disclosure.
  • the spacing between adjacent bit line structures is also gradually reduced, which will lead to an increase in the aspect ratio of the dielectric layer and the capacitor contact hole formed between the adjacent bit line structures subsequently;
  • the patterned trench In the process of patterning the sacrificial layer to form the required trench for the dielectric layer between adjacent bit line structures, due to the large aspect ratio of the dielectric layer, the patterned trench also has a large aspect ratio, which may Cause the bottom sacrificial layer to have etching residues, which will cause adjacent capacitor contact holes to be connected during the subsequent formation of capacitor contact holes, thereby affecting the yield of the semiconductor structure; if the etching residue is subjected to secondary etching , which will cause the size of the trench to become larger, thereby affecting the size of the subsequent formation of the capacitor contact hole.
  • An embodiment of the present disclosure provides a method for forming a semiconductor structure, including: providing a substrate on which discrete bit line structures are formed; forming a first sacrificial layer on the surface of the substrate at the bottom of a gap between the bit line structures; The second sacrificial layer in the gap of the bit line structure, the second sacrificial layer is located on top of the first sacrificial layer, and the materials of the first sacrificial layer and the second sacrificial layer are different; the patterning of the second sacrificial layer and the first sacrificial layer forms an opening, In the extending direction of the bit line structure, the formed openings and the remaining second sacrificial layers are alternately arranged; the dielectric layer filling the openings is formed; In the extending direction, the formed capacitor contact holes and the dielectric layers are alternately arranged.
  • FIG. 1 is a schematic top-view structural diagram of a substrate and a bit line structure provided by this embodiment
  • FIGS. 2 to 10 are schematic cross-sectional structural diagrams corresponding to each step of a method for forming a semiconductor structure provided by this embodiment
  • FIG. 11 is provided by this embodiment.
  • a substrate 100 is provided on which discrete bit line structures 130 are formed.
  • a substrate 100 of active regions 120 and word line structures 101 is provided.
  • the plurality of active regions 120 are arranged in parallel and spaced apart from each other.
  • the substrate 100 also includes other memory structures other than the word line structure 101 and the active region 120 , such as the shallow trench isolation structure 110 (refer to FIG. 2 ), etc., since other memory structures are not related to the present disclosure The core technology is not repeated here; those skilled in the art can understand that the substrate 100 also includes other memory structures other than the word line structure 101 and the active region 120 for the normal operation of the memory.
  • the material of the substrate 100 may include sapphire, silicon, silicon carbide, gallium arsenide, aluminum nitride or zinc oxide, etc.
  • the substrate 100 is made of silicon material, and those skilled in the art will know that this embodiment uses silicon material as the substrate 100 is for the convenience of those skilled in the art to understand the subsequent formation method, and does not constitute a limitation. In the actual application process, a suitable substrate material can be selected according to requirements.
  • the word line structure 101 is a buried word line structure located in the substrate 100 .
  • the word line structure 101 is located in the shallow trench isolation structure 110 , and the word line An isolation layer 120 is formed on the top of the structure 101 , and the isolation layer 120 is used to electrically isolate the word line structure 101 from the conductive structure on the top of the substrate 100 .
  • discrete bit line structures 130 are formed on the substrate 100 .
  • the extending direction of the bit line structure 130 and the extending direction of the word line structure 101 are perpendicular to each other.
  • the bit line structure 130 includes a bit line contact layer, a metal layer and a top dielectric layer which are stacked in sequence.
  • the material of the bit line contact layer includes tungsten or polysilicon; the metal layer can be a conductive material or composed of a variety of conductive materials, such as doped polysilicon, titanium, titanium nitride, tungsten and tungsten composites, etc.; the material of the top dielectric Including silicon nitride, silicon dioxide or silicon oxynitride.
  • a first sacrificial layer 201 is formed on the surface of the substrate 100 at the bottom of the gap of the bit line structure 130 .
  • Forming the first sacrificial layer 201 on the surface of the substrate 100 at the bottom of the gap of the bit line structure 130 includes the following steps:
  • a first sacrificial film (not shown) is formed to cover the top and sidewalls of the bit line structures 130 and to cover the bottom substrate 100 in the gaps of the bit line structures 130 .
  • the first sacrificial film (not shown) is formed by atomic layer deposition, and the first sacrificial film (not shown) formed by atomic layer deposition has good coverage and compactness, and is formed
  • the first sacrificial film (not shown) located on the sidewall of the bit line structure 130 is relatively thin and can be easily removed in subsequent processes; in other embodiments, the first sacrificial film (not shown) can also be formed by chemical vapor deposition. ).
  • the material of the first sacrificial film (not shown) is a carbon-containing material or an oxygen-containing material, and in the subsequent process of removing the first sacrificial film (not shown) or the first sacrificial layer 201, ash can be used.
  • the first sacrificial film (not shown) or the first sacrificial layer 201 is removed by ashing; the ashing gas reacts with the carbon-containing material or the oxygen-containing material to generate carbon dioxide gas or water, and the first sacrificial film (not shown) or the first sacrificial film (not shown) or the first sacrificial film (not shown) is removed.
  • a sacrificial layer 201 is converted into gaseous carbon dioxide or liquid water, thereby removing the first sacrificial film (not shown) or the first sacrificial layer 201; and avoiding secondary etching to remove other semiconductor materials, thereby affecting the yield of the semiconductor structure .
  • the first sacrificial film (not shown) on the top and sidewalls of the bit line structure 130 is removed, and the remaining first sacrificial film (not shown) constitutes the first sacrificial layer 201 .
  • the thickness of the formed first sacrificial layer 201 ranges from 3 to 10 nm, such as 5 nm, 7 nm or 9 nm.
  • the first sacrificial layer 201 is formed with a thickness of 3 to 10 nm to improve the first sacrificial layer. 201 and the stability of the second sacrificial layer 202. If the thickness of the first sacrificial layer 201 is greater than 10 nm, the trench formed by patterning the first sacrificial layer 201 also has a large aspect ratio, which may cause the problem of etching residues on the first sacrificial layer 201 at the bottom.
  • the thickness of a sacrificial layer is less than 3 nm, which causes the thickness difference between the first sacrificial layer 201 and the second sacrificial layer 202 to be too large, resulting in unstable structures of the first sacrificial layer 201 and the second sacrificial layer 202 formed, which leads to the subsequent formation of Semiconductor structures have structural defects.
  • a second sacrificial layer 202 is formed to fill the gaps of the discrete bit line structures 130 , the second sacrificial layer 202 is located on top of the first sacrificial layer 201 , and the materials of the first sacrificial layer 201 and the second sacrificial layer 202 are different.
  • the materials of the first sacrificial layer 201 and the second sacrificial layer 202 are different; the etching selectivity ratio of the material of the first sacrificial layer 201 and the material of the second sacrificial layer 202 being etched by the same etching material is greater than 5:1.
  • the larger etching selectivity ratio ensures that the trenches formed by etching the second sacrificial layer 202 will not be affected in the process of etching the first sacrificial layer 201 .
  • Forming a second sacrificial layer filling the gaps of the discrete bit line structures 130 includes the following steps:
  • a second sacrificial film (not shown) is formed on the surface of the first sacrificial layer 201 to fill the gap of the bit line structure 130 and cover the bit line structure 130 .
  • the second sacrificial film (not shown) is formed by chemical vapor deposition, and the second sacrificial film (not shown) formed by chemical vapor deposition has a higher deposition rate, which is beneficial to shorten the process cycle; in other embodiments, the second sacrificial film (not shown) is a hard mask formed by spin coating, and the second sacrificial film (not shown) formed by spin coating also has higher The deposition rate is favorable for shortening the process cycle.
  • the second sacrificial film (not shown) is made of an insulating material with a lower density, such as silicon oxide, silicon oxynitride, etc., and the insulating material with a lower density is used, so that the second sacrificial film is subsequently
  • the etching of the layer 202 has a higher etching rate, which is beneficial to shorten the process cycle.
  • the second sacrificial film (not shown) is planarized until the height of the remaining second sacrificial film (not shown) is the same as the height of the bit line structure 130, and the remaining second sacrificial film (not shown) constitutes the first Two sacrificial layers.
  • the density of the first sacrificial layer 201 is lower than that of the second sacrificial layer 202.
  • the density of the material is related to the etching rate of the material. The slower the rate is, through the limitation that the density of the first sacrificial layer 201 is smaller than that of the second sacrificial layer 202 , the first sacrificial layer 201 is easier to be removed, preventing etching during the etching of the first sacrificial layer 201 The material will etch the trenches formed by the second sacrificial layer 202 .
  • the thickness ratio of the first sacrificial layer 201 and the second sacrificial layer 202 is less than or equal to 1:10, for example, the thickness ratio of the first sacrificial layer 201 and the second sacrificial layer 202 is 1:3, 1 : 5, 1:7 or 1:9; in this embodiment, by forming the first sacrificial layer 201 and the second sacrificial layer 202 with a thickness ratio of 1:10 or less, to ensure that the first sacrificial layer 201 and the second sacrificial layer are formed 202 stability.
  • the material of the first sacrificial layer 201 includes but is not limited to silicon oxide
  • the material of the second sacrificial layer 202 includes but is not limited to SOH; in other embodiments, the material of the first sacrificial layer and the second sacrificial layer The material only needs to satisfy the above-mentioned thickness range and thickness relationship to achieve the technical effect to be achieved by this embodiment, which falls within the protection scope of the present disclosure.
  • the second sacrificial layer 202 and the first sacrificial layer 201 are patterned to form openings 214 (refer to FIG. 7 ).
  • the openings 214 and the remaining second sacrificial layers 202 are formed. Alternate arrangement.
  • patterning the second sacrificial layer 202 and the first sacrificial layer 201 to form the opening 214 includes the following steps:
  • a patterned photoresist 203 is formed on the top surface of the second sacrificial layer 202 .
  • pre-openings 204 are formed by removing part of the second sacrificial layer 202 based on patterned photoresist. In the extending direction of the bit line structure 130 , the formed pre-openings 204 and the remaining second sacrificial layers 202 are alternately arranged.
  • the first sacrificial layer 201 exposed by the pre-opening 204 is removed to form an opening 214 .
  • the etching selection ratio of the selected etching material to the material of the first sacrificial layer 201 and the material of the second sacrificial layer 202 is greater than 5:1.
  • the larger etching selectivity ratio ensures that the trenches formed by etching the second sacrificial layer 202 will not be affected in the process of etching the first sacrificial layer 201 .
  • the opening may be formed by removing part of the second sacrificial layer and the first sacrificial layer using a uniform etching material directly based on the imaged photoresist in a one-step process.
  • the etching selection ratio of the selected etching material to the material of the first sacrificial layer and that of the second sacrificial layer is greater than 5:1.
  • the larger etching selectivity ratio ensures that the trench formed by etching the second sacrificial layer will not be affected in the process of etching the first sacrificial layer.
  • a dielectric layer 205 filling the openings 214 is formed.
  • Forming the dielectric layer 205 filling the openings 214 includes the following steps: forming a dielectric film (not shown) filling the openings 214 and covering the second sacrificial layer 202 ; planarizing the dielectric film until the remaining dielectric film (not shown) is The height is the same as the height of the second sacrificial layer 202 , and the remaining dielectric film (not shown) constitutes the dielectric layer 205 .
  • the formed dielectric layers 205 and the second sacrificial layers 202 are alternately arranged.
  • the dielectric film (not shown) is formed by chemical vapor deposition, and the dielectric film (not shown) formed by chemical vapor deposition has a higher deposition rate, which is beneficial to shorten the process cycle.
  • the material of the dielectric layer 205 is silicon nitride, so as to ensure that it is difficult to cause damage to the dielectric layer 205 during the subsequent removal of the second sacrificial layer 202 and the removal of the first sacrificial layer 201 .
  • the material of the dielectric layer may also be an insulating material such as silicon oxynitride and silicon nitride carbide.
  • the remaining first sacrificial layer 201 and the second sacrificial layer 202 are removed to form a capacitor contact hole 216 (refer to FIG. 10 ).
  • the formed capacitor contact hole 216 and the dielectric are arranged alternately.
  • Removing the remaining first sacrificial layer 201 and the second sacrificial layer 202 to form a capacitor contact hole 216 includes the following steps:
  • the remaining second sacrificial layer 202 is removed to form through holes 206 , which expose the first sacrificial layer 201 .
  • the remaining second sacrificial layer 202 is removed by ashing.
  • the sacrificial layer is removed by an ashing process to form through holes 206 , and the size of the formed through holes 206 is approximately equal to the size of the second sacrificial layer 202 .
  • the ashing gas used in the ashing process includes one or a combination of nitrogen, hydrogen or oxygen; the ashing gas chemically reacts with the sacrificial layer formed by the carbon-containing material or the oxygen-containing material, and the solid second sacrificial layer After the reaction of 202 , gaseous carbon dioxide or liquid water is generated, which changes from solid state to gaseous state or liquid state, thereby forming through holes 206 .
  • a large impact force will not be caused to the side wall of the through hole 206, and the phenomenon of the collapse of the side wall is avoided.
  • the first sacrificial layer 201 at the bottom of the through hole 206 is removed to form a capacitor contact hole 216 .
  • the first sacrificial layer 201 is a single-layer structure; in other embodiments, the first sacrificial layer may be a multi-layer structure.
  • the sacrificial layer includes the following steps: forming a first sub-sacrificial layer on the substrate surface at the bottom of the bit line structure gap; forming a second sub-sacrificial layer on the top surface of the first sub-sacrificial layer, and the material of the first sub-sacrificial layer is the same as that of the second sub-sacrificial layer.
  • the materials of the sub-sacrificial layers are different, and the first sub-sacrificial layer and the second sub-sacrificial layer together constitute the first sacrificial layer.
  • the above example illustrates the formation method of the first sacrificial layer as a double-layer structure, and structures such as the third sub-sacrificial layer and the fourth sub-sacrificial layer can be formed on the top surface of the second sub-sacrificial layer, so as to realize the first sacrificial layer.
  • the sacrificial layer is a multi-layer structure.
  • the sacrificial layers formed in the gaps of the discrete bit line structures include a first sacrificial layer located at the bottom and a second sacrificial layer located at the top, and the materials of the first sacrificial layer and the second sacrificial layer are different.
  • the thickness of the sacrificial layer to be etched in each etching process is reduced, that is, the aspect ratio of the trench to be formed in a single etching process is reduced, ensuring that each etching process is performed.
  • the trench is formed to form a fully etched trench without affecting the size of the dielectric layer and the size of the capacitor contact hole.
  • a semiconductor structure including: a substrate, and discrete bit line structures on the substrate; a first sacrificial layer, on a surface of the substrate at the bottom of a gap of the bit line structure, the thickness of the first sacrificial layer is less than The thickness of the line structure; the second sacrificial layer, located on the surface of the first sacrificial layer at the bottom of the gap of the bit line structure, the materials of the first sacrificial layer and the second sacrificial layer are different; the first sacrificial layer and the second sacrificial layer are used to form Dielectric layer and capacitor contact holes between discrete bit line structures.
  • FIG. 4 is a schematic cross-sectional structure diagram of the semiconductor structure provided in this embodiment.
  • the semiconductor structure provided in this embodiment is described in detail below with reference to the accompanying drawings, and the details are as follows:
  • a semiconductor structure including:
  • the substrate 100 and the discrete bit line structures 130 on the substrate 100 are identical to the substrate 100 and the discrete bit line structures 130 on the substrate 100 .
  • the substrate 100 includes an active region 120 and a word line structure 101 ; a plurality of active regions 120 are arranged in parallel and spaced apart from each other. It should be noted that the substrate 100 also includes other memory structures other than the word line structure 101 and the active region 120 , such as the shallow trench isolation structure 110 (refer to FIG. 2 ), etc., since other memory structures are not related to the present disclosure The core technology is not repeated here; those skilled in the art can understand that the substrate 100 also includes other memory structures other than the word line structure 101 and the active region 120 for the normal operation of the memory.
  • the material of the substrate 100 may include sapphire, silicon, silicon carbide, gallium arsenide, aluminum nitride or zinc oxide, etc.
  • the substrate 100 is made of silicon material, and those skilled in the art will know that this embodiment uses silicon material as the substrate 100 is for the convenience of those skilled in the art to understand the subsequent formation method, and does not constitute a limitation. In the actual application process, a suitable substrate material can be selected according to requirements.
  • the word line structure 101 is a buried word line structure located in the substrate 100.
  • the word line structure 101 is located in the shallow trench isolation structure 110, and the top of the word line structure 101 is formed There is an isolation layer 120 , and the isolation layer 120 is used to electrically isolate the word line structure 101 from the conductive structure on top of the substrate 100 .
  • discrete bit line structures 130 are formed on a substrate 100 .
  • the extending direction of the bit line structure 130 and the extending direction of the word line structure 101 are perpendicular to each other.
  • the bit line structure 130 includes a bit line contact layer, a metal layer and a top dielectric layer which are stacked in sequence.
  • the material of the bit line contact layer includes tungsten or polysilicon; the metal layer can be a conductive material or composed of a variety of conductive materials, such as doped polysilicon, titanium, titanium nitride, tungsten and tungsten composites, etc.; the material of the top dielectric Including silicon nitride, silicon dioxide or silicon oxynitride.
  • the first sacrificial layer 201 is located on the surface of the substrate 100 at the bottom of the gap of the bit line structure 130 , and the thickness of the first sacrificial layer 201 is smaller than the thickness of the bit line structure 130 .
  • the second sacrificial layer 202 is located on the surface of the first sacrificial layer 201 at the bottom of the gap of the bit line structure 130 , and the materials of the first sacrificial layer 201 and the second sacrificial layer 202 are different.
  • the thickness of the formed first sacrificial layer 201 is in the range of 3-10 nm, such as 5 nm, 7 nm or 9 nm; in this embodiment, the first sacrificial layer 201 is formed with a thickness of 3-10 nm to improve the first sacrificial layer 201 and the stability of the second sacrificial layer 202. If the thickness of the first sacrificial layer 201 is greater than 10 nm, the trench formed by patterning the first sacrificial layer 201 also has a large aspect ratio, which may cause the problem of etching residues on the first sacrificial layer 201 at the bottom.
  • the thickness of a sacrificial layer is less than 3 nm, which causes the thickness difference between the first sacrificial layer 201 and the second sacrificial layer 202 to be too large, resulting in unstable structures of the first sacrificial layer 201 and the second sacrificial layer 202 formed, which leads to the subsequent formation of Semiconductor structures have structural defects.
  • the thickness ratio of the formed first sacrificial layer 201 and the second sacrificial layer 202 is less than or equal to 1:10, for example, the thickness ratio of the first sacrificial layer 201 and the second sacrificial layer 202 is 1:3, 1 : 5, 1:7 or 1:9; in this embodiment, by forming the first sacrificial layer 201 and the second sacrificial layer 202 with a thickness ratio of 1:10 or less, to ensure that the first sacrificial layer 201 and the second sacrificial layer are formed 202 stability.
  • the materials of the first sacrificial layer 201 and the second sacrificial layer 202 are different; the etching selectivity ratio of the material of the first sacrificial layer 201 and the material of the second sacrificial layer 202 being etched by the same etching material is greater than 5:1.
  • the larger etching selectivity ratio ensures that the trenches formed by etching the second sacrificial layer 202 will not be affected in the process of etching the first sacrificial layer 201 .
  • the first sacrificial layer 201 and the second sacrificial layer 202 are used to form dielectric layers and capacitor contact holes between the discrete bit line structures.
  • the sacrificial layer in the gap of the discrete bit line structure includes a first sacrificial layer located at the bottom and a second sacrificial layer located at the top, and the materials of the first sacrificial layer and the second sacrificial layer are different, that is, The aspect ratio of the trench formed by etching the sacrificial layer required in a single etching process is reduced, ensuring that there is no etching residue at the bottom of the trench formed by each etching process; in addition, due to the first sacrificial layer and the second sacrificial layer Different materials, the process of etching the first sacrificial layer will not affect the trench formed by etching the second sacrificial layer, so as to ensure that the size of the dielectric layer and the size of the capacitor contact hole are not affected. groove.
  • the sacrificial layers in the gaps of the discrete bit line structures include a first sacrificial layer at the bottom and a second sacrificial layer at the top, the first sacrificial layer and the The material of the second sacrificial layer is different, that is, the aspect ratio of the trench formed by etching the sacrificial layer required by the single etching process is reduced, so as to ensure that there is no etching residue at the bottom of the trench formed by each etching process; The materials of the first sacrificial layer and the second sacrificial layer are different.
  • the trench formed by etching the second sacrificial layer will not be affected, so as to ensure that the size of the dielectric layer and the size of the capacitor contact hole will not be affected. Under the premise of forming a fully etched trench.

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Abstract

本公开提供一种半导体结构的形成方法及半导体结构，其中，半导体结构的形成方法，包括：提供基底，基底上形成有分立的位线结构；在位线结构间隙底部的基底表面上形成第一牺牲层；形成填充分立的位线结构间隙的第二牺牲层，第二牺牲层位于第一牺牲层顶部，且第一牺牲层和第二牺牲层的材料不相同；图形化第二牺牲层和第一牺牲层形成开口，在位线结构延伸的方向上，形成的开口和剩余第二牺牲层交替排布；形成填充开口的介质层；去除剩余的第一牺牲层和第二牺牲层形成电容接触孔，在位线结构延伸的方向上，形成的电容接触孔和介质层交替排布。

Description

半导体结构的形成方法及半导体结构
本公开基于申请号为202110258133.9，申请日为2021年03月09日，申请名称为“半导体结构的形成方法及半导体结构”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种半导体结构的形成方法及半导体结构。
背景技术
随着动态随机存取存储器(Dynamic Random Access Memory，DRAM)的线宽逐渐减小，相邻位线结构之间的间距也逐渐减小，会导致后续在相邻位线结构之间形成的介质层和电容接触孔的深宽比变大。
在图形化牺牲层，形成相邻位线结构之间的介质层所需沟槽的过程中，由于介质层的深宽比较大，图形化形成的沟槽也具有较大的深宽比，可能会造成底部牺牲层存在刻蚀残留，刻蚀残留在后续形成电容接触孔的过程中会导致相邻的电容接触孔相连通，从而影响半导体结构的良率；若对刻蚀残留进行二次刻蚀，会导致沟槽的尺寸变大，从而影响后续形成电容接触孔的尺寸。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供一种半导体结构的形成方法及半导体结构。
本公开的第一方面提供一种半导体结构的形成方法，包括：提供基底，基底上形成有分立的位线结构；在位线结构间隙底部的基底表面上形成第一牺牲层；形成填充分立的位线结构间隙的第二牺牲层，第二牺牲层位于第一牺牲层顶部，且第一牺牲层和第二牺牲层的材料不相同； 图形化第二牺牲层和第一牺牲层形成开口，在位线结构延伸的方向上，形成的开口和剩余第二牺牲层交替排布；形成填充开口的介质层；去除剩余的第一牺牲层和第二牺牲层形成电容接触孔，在位线结构延伸的方向上，形成的电容接触孔和介质层交替排布。
与相关技术相比，在分立的位线结构的间隙形成的牺牲层包括位于底部的第一牺牲层和位于顶部的第二牺牲层，第一牺牲层和第二牺牲层的材料不同，即刻蚀牺牲层形成开口的过程中，减小了每次刻蚀工艺所需刻蚀的牺牲层的厚度，即降低了单次刻蚀工艺所需形成沟槽的深宽比，保证每次刻蚀工艺形成的沟槽底部不存在刻蚀残留；另外，由于第一牺牲层和第二牺牲层的材料不同，在刻蚀第一牺牲层的过程中并不会影响刻蚀第二牺牲层形成的沟槽，从而保证不影响介质层尺寸和电容接触孔尺寸的前提下，形成刻蚀完全的沟槽。
本公开的第二方面提供一种半导体结构，包括：基底，以及位于基底上分立的位线结构；第一牺牲层，位于位线结构的间隙底部的基底表面，第一牺牲层的厚度小于位线结构的厚度；第二牺牲层，位于位线结构的间隙底部的第一牺牲层表面，第一牺牲层和第二牺牲层的材料不相同；第一牺牲层和第二牺牲层用于形成分立的位线结构之间的介质层和电容接触孔。
相比于相关技术而言，在分立的位线结构的间隙的牺牲层包括位于底部的第一牺牲层和位于顶部的第二牺牲层，第一牺牲层和第二牺牲层的材料不同，即降低了单次刻蚀工艺所需刻蚀牺牲层形成沟槽的深宽比，保证每次刻蚀工艺形成的沟槽底部不存在刻蚀残留；另外，由于第一牺牲层和第二牺牲层的材料不同，在刻蚀第一牺牲层的过程中并不会影响刻蚀第二牺牲层形成的沟槽，从而保证不影响介质层尺寸和电容接触孔尺寸的前提下，形成刻蚀完全的沟槽。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中， 类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1为本公开一实施例提供的基底及位线结构的俯视结构示意图；
图2为图1所示出的基底及位线结构沿A-A’方向的截面的结构示意图。
图3为图2所示出的结构中的位线结构间隙底部的基底表面上形成第一牺牲层后的结构示意图。
图4为图3所示出的结构中形成填充分立的位线结构间隙的第二牺牲层后的结构示意图。
图5为图4所示出的结构中的第二牺牲层顶部表面形成图形化光刻胶后的结构示意图。
图6为图5所示出的结构中基于图形化的光刻胶去除部分第二牺牲层形成预开口后的结构示意图。
图7为图6所示出的结构中去除预开口暴露出的第一牺牲层形成开口后的结构示意图。
图8为图7所示出的结构中形成填充开口的介质层后的结构示意图。
图9为图8所示出的结构中去除剩余第二牺牲层形成通孔后的结构示意图。
图10为图9所示出的结构中去除通孔底部的第一牺牲层形成电容接触孔后的结构示意图。
图11为本公开一实施例提供的介质层及第二牺牲层的俯视结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意 组合。
现有形成半导体结构的方法中，相邻位线结构之间的间距也逐渐减小，会导致后续在相邻位线结构之间形成的介质层和电容接触孔的深宽比变大；在图形化牺牲层，形成相邻位线结构之间的介质层所需沟槽的过程中，由于介质层的深宽比较大，图形化形成的沟槽也具有较大的深宽比，可能会造成底部牺牲层存在刻蚀残留，刻蚀残留在后续形成电容接触孔的过程中会导致相邻的电容接触孔相连通，从而影响半导体结构的良率；若对刻蚀残留进行二次刻蚀，会导致沟槽的尺寸变大，从而影响后续形成电容接触孔的尺寸。
本公开一实施例提供了一种半导体结构的形成方法，包括：提供基底，基底上形成有分立的位线结构；在位线结构间隙底部的基底表面上形成第一牺牲层；形成填充分立的位线结构间隙的第二牺牲层，第二牺牲层位于第一牺牲层顶部，且第一牺牲层和第二牺牲层的材料不相同；图形化第二牺牲层和第一牺牲层形成开口，在位线结构延伸的方向上，形成的开口和剩余第二牺牲层交替排布；形成填充开口的介质层；去除剩余的第一牺牲层和第二牺牲层形成电容接触孔，在位线结构延伸的方向上，形成的电容接触孔和介质层交替排布。
图1为本实施例提供的基底及位线结构的俯视结构示意图，图2～图10为本实施例提供的半导体结构的形成方法各步骤对应的剖面结构示意图，图11为本实施例提供的介质层及第二牺牲层的俯视结构示意图，下面结合附图对本实施例提供的半导体结构的形成方法进行详细说明，具体如下：
参考图1和图2，提供基底100，基底100上形成有分立的位线结构130。
参考图1，提供有源区120和字线结构101的基底100。
多个有源区120相互平行间隔排布。需要说明的是，基底100中还包括除字线结构101和有源区120外的其他存储器结构，例如浅沟槽隔离结构110(参考图2)等，由于其他存储器结构并不涉及到本公开的核心技术，在此不过多进行赘述；本领域技术人员可以理解基底100中还包括除字线结构101和有源区120外的其他存储器结构，用于存储器的正常运行。
基底100的材料可以包括蓝宝石、硅、碳化硅、砷化镓、氮化铝或者氧化锌等；在本实施例中基底100采用硅材料，本领域技术人员清楚，本实施例采用硅材料作为基底100是为了方便本领域技术人员对后续形成方法的理 解，并不构成限定，在实际应用过程中，可以根据需求选择合适的基底的材料。
参考图2，字线结构101为埋入式字线结构，位于基底100中，在AA1截面(参考图1)的剖面示意图中，字线结构101位于浅沟槽隔离结构110中，且字线结构101顶部形成有隔离层120，隔离层120用于字线结构101与基底100顶部导电结构的电隔离。
继续参考图1，基底100上形成有分立的位线结构130。
位线结构130延伸的方向与字线结构101延伸的方向相互垂直。位线结构130包括依次堆叠设置的位线接触层、金属层以及顶层介质层。位线接触层的材料包括钨或多晶硅；金属层可以为一种导电材料或者由多种导电材料构成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等；顶层介质的材料包括氮化硅、二氧化硅或氮氧化硅。
参考图3，在位线结构130间隙底部的基底100表面上形成第一牺牲层201。
在位线结构130间隙底部的基底100表面上形成第一牺牲层201，包括以下步骤：
形成覆盖位线结构130顶部和侧壁，以及覆盖位线结构130间隙底部基底100的第一牺牲膜(未图示)。
在本实施例中，第一牺牲膜(未图示)采用原子层沉积的方式形成，采用原子层沉积的方式形成第一牺牲膜(未图示)具有良好的覆盖性和致密性，且形成位于位线结构130侧壁的第一牺牲膜(未图示)较薄，在后续工艺中容易去除；在其他实施例中，也可以采用化学气相沉积的方法形成第一牺牲膜(未图示)。
在一个例子中，第一牺牲膜(未图示)的材料为含碳材料或者含氧材料，后续在去除第一牺牲膜(未图示)或者第一牺牲层201的过程中，可采用灰化的方式去除第一牺牲膜(未图示)或者第一牺牲层201；灰化气体与含碳材料或含氧材料反应生成二氧化碳气体或者水，将第一牺牲膜(未图示)或者第一牺牲层201转换成气体二氧化碳或者液体水，从而除去第一牺牲膜(未图示)或者第一牺牲层201；并且避免了去其他半导体材料的二次刻蚀，从而影响半导体结构的良率。
去除位于位线结构130顶部和侧壁的第一牺牲膜(未图示)，剩余第一牺牲膜(未图示)构成第一牺牲层201。
在本实施例中，形成的第一牺牲层201的厚度范围为3～10nm，例如5nm、7nm或9nm；本实施例通过形成厚度为3～10nm的第一牺牲层201以提高第一牺牲层201和第二牺牲层202的稳定性。若第一牺牲层201的厚度大于10nm，图形化第一牺牲层201形成的沟槽同样具备较大的深宽比，可能会造成底部的第一牺牲层201存在刻蚀残留的问题；若第一牺牲层的厚度小于3nm，导致第一牺牲层201和第二牺牲层202的厚度差过大，导致形成的第一牺牲层201和第二牺牲层202的结构不稳定，从而导致后续形成的半导体结构存在结构缺陷。
参考图4，形成填充分立的位线结构130间隙的第二牺牲层202，第二牺牲层202位于第一牺牲层201顶部，且第一牺牲层201与第二牺牲层202的材料不相同。
第一牺牲层201与第二牺牲层202的材料不相同；第一牺牲层201的材料和第二牺牲层202的材料被同一刻蚀材料刻蚀的刻蚀选择比大于5：1。通过较大的刻蚀选择比，保证在刻蚀第一牺牲层201的过程中并不会影响刻蚀第二牺牲层202形成的沟槽。
形成填充分立的位线结构130间隙的第二牺牲层，包括以下步骤：
在第一牺牲层201表面形成填充位线结构130间隙且覆盖位线结构130的第二牺牲膜(未图示)。
在本实施例中，第二牺牲膜(未图示)采用化学气相沉积的方式形成，采用化学气相沉积的方式形成的第二牺牲膜(未图示)具有较高的沉积速率，有利于缩短工艺周期；在其他实施例中，第二牺牲膜(未图示)为采用旋涂的方式形成的硬掩模，采用旋涂的方式形成的第二牺牲膜(未图示)同样具有较高的沉积速率，有利于缩短工艺周期。
在本实施例中，第二牺牲膜(未图示)的材料致密度较小的绝缘材料，例如，氧化硅，氮氧化硅等材料，采用致密度较小的绝缘材料使得后续对第二牺牲层202的刻蚀具有较高的刻蚀速率，有利于缩短工艺周期。
对第二牺牲膜(未图示)进行平坦化处理，直至剩余的第二牺牲膜(未图示)的高度与位线结构130的高度一致，剩余第二牺牲膜(未图示)构成 第二牺牲层。
在本实施例中，第一牺牲层201的致密度小于第二牺牲层202的致密度，本领域技术人员可知，材料的致密度与材料的被刻蚀速率有关，致密度越大被刻蚀速率越慢，通过第一牺牲层201的致密度小于第二牺牲层202的致密度的限制，使得第一牺牲层201更容易被去除，防止在刻蚀第一牺牲层201的过程中刻蚀材料会刻蚀第二牺牲层202形成的沟槽。
在一个例子中，形成的第一牺牲层201和第二牺牲层202的厚度比为小于或等于1：10，例如第一牺牲层201和第二牺牲层202的厚度比为1：3、1：5、1：7或1：9；本实施例通过形成厚度比小于等于1：10的第一牺牲层201和第二牺牲层202，以保证形成的第一牺牲层201和第二牺牲层202的稳定性。
另外，需要说明的是，第一牺牲层201的材料包括但不限于氧化硅，第二牺牲层202的材料包括但不限于SOH；在其他实施例中，第一牺牲层和第二牺牲层的材料仅需满足上述厚度范围和厚度关系，便可实现本实施例所要达到的技术效果，属于本公开的保护范围内。
参考图5～图7，图形化第二牺牲层202和第一牺牲层201形成开口214(参考图7)，在位线结构130延伸的方向上，形成的开口214和剩余第二牺牲层202交替排布。
在本实施例中，图形化第二牺牲层202和第一牺牲层201形成开口214，包括以下步骤：
参考图5，在第二牺牲层202顶部表面形成图形化光刻胶203。
参考图6，基于图形化的光刻胶去除部分第二牺牲层202形成预开口204，在位线结构130延伸的方向上，形成的预开口204和剩余第二牺牲层202交替排布。
参考图7，去除预开口204暴露出的第一牺牲层201，形成开口214。
选用的刻蚀材料对第一牺牲层201的材料和第二牺牲层202的刻蚀选择比大于5：1。通过较大的刻蚀选择比，保证在刻蚀第一牺牲层201的过程中并不会影响刻蚀第二牺牲层202形成的沟槽。
在其他实施例中，可以在一步工艺中，直接基于图像化的光刻胶，采用统一刻蚀材料去除部分第二牺牲层和第一牺牲层，形成开口。此时选用的刻 蚀材料对第一牺牲层的材料和第二牺牲的刻蚀选择比大于5：1。通过较大的刻蚀选择比，保证在刻蚀第一牺牲层的过程中并不会影响刻蚀第二牺牲层形成的沟槽。
参考图8，形成填充开口214的介质层205。
形成填充开口214的介质层205包括以下步骤：形成填充开口214且覆盖第二牺牲层202的介质膜(未图示)；对介质膜进行平坦化处理，直至剩余介质膜(未图示)的高度与第二牺牲层202的高度一致，剩余介质膜(未图示)构成介质层205。
参考图11，在位线结构130延伸的方向上，形成的介质层205和第二牺牲层202交替排布。
在本实施例中，介质膜(未图示)采用化学气相沉积的方式形成，采用化学气相沉积的方式形成的介质膜(未图示)具有较高的沉积速率，有利于缩短工艺周期。
在本实施例中，介质层205的材料为氮化硅，从而保证后续在去除第二牺牲层202和去除第一牺牲层201的过程中，难以对介质层205造成损伤。在其他实施例中，介质层的材料还可以为氮氧化硅、氮碳化硅等绝缘材料。
参考图9和图10，去除剩余的第一牺牲层201和第二牺牲层202形成电容接触孔216(参考图10)，在位线结构130延伸的方向上，形成的电容接触孔216和介质层205交替排布。
去除剩余的第一牺牲层201和第二牺牲层202形成电容接触孔216，包括以下步骤：
参考图9，基于介质层205和位线结构130，去除剩余第二牺牲层202，形成通孔206，通孔206暴露出第一牺牲层201。
在一个例子中，采用灰化的方式去除剩余第二牺牲层202。
采用灰化工艺去除牺牲层形成通孔206，形成的通孔206的尺寸约等于第二牺牲层202的尺寸。灰化工艺采用的灰化气体包括氮气、氢气或氧气其中的一种或几种的组合；灰化气体与采用含碳材料或者含氧材料形成的牺牲层发生化学反应，固态的第二牺牲层202反应后生成气态的二氧化碳或者液态的水，从固态变为气态或液态，从而形成通孔206。采用灰化工艺形成通孔206时，不会对通孔206的侧壁造成较大的冲击力，避免了侧壁坍塌的现 象。
参考图10，基于介质层205和位线结构130，去除通孔206底部的第一牺牲层201，形成电容接触孔216。
另外，在本实施例中，第一牺牲层201为单层结构；在其他实施例中，第一牺牲层可以为多层结构，此时，在位线结构间隙底部的基底表面上形成第一牺牲层，包括以下步骤：在位线结构间隙底部的基底表面上形成第一子牺牲层；在第一子牺牲层的顶部表面形成第二子牺牲层，第一子牺牲层的材料与第二子牺牲层的材料不同，第一子牺牲层与第二子牺牲层共同构成第一牺牲层。通过多层结构的第一牺牲层，可以减小每次刻蚀工艺所需刻蚀的牺牲层的厚度，保证每次刻蚀工艺形成的沟槽底部不存在刻蚀残留。
需要说明的是，上述举例说明了第一牺牲层为双层结构的形成方法，可以在第二子牺牲层的顶部表面形成第三子牺牲层、第四子牺牲层等结构，从而实现第一牺牲层为多层结构。
相对于相关技术而言，在分立的位线结构的间隙形成的牺牲层包括位于底部的第一牺牲层和位于顶部的第二牺牲层，第一牺牲层和第二牺牲层的材料不同，即刻蚀牺牲层形成开口的过程中，减小了每次刻蚀工艺所需刻蚀的牺牲层的厚度，即降低了单次刻蚀工艺所需形成沟槽的深宽比，保证每次刻蚀工艺形成的沟槽底部不存在刻蚀残留；另外，由于第一牺牲层和第二牺牲层的材料不同，在刻蚀第一牺牲层的过程中并不会影响刻蚀第二牺牲层形成的沟槽，从而保证不影响介质层尺寸和电容接触孔尺寸的前提下，形成刻蚀完全的沟槽。
上面各种步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本专利的保护范围内；对流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其流程的核心设计都在该专利的保护范围内。
本公开另一实施例涉及一种半导体结构，包括：基底，以及位于基底上分立的位线结构；第一牺牲层，位于位线结构的间隙底部的基底表面，第一牺牲层的厚度小于位线结构的厚度；第二牺牲层，位于位线结构的间隙底部的第一牺牲层表面，第一牺牲层和第二牺牲层的材料不相同；第一牺牲层和第二牺牲层用于形成分立的位线结构之间的介质层和电容接触孔。
图4为本实施例提供的半导体结构的剖面结构示意图，下面结合附图对本实施例提供的半导体结构进行详细说明，具体如下：
参考图4，半导体结构，包括：
基底100，以及位于基底100上分立的位线结构130。
基底100包括有源区120和字线结构101；多个有源区120相互平行间隔排布。需要说明的是，基底100中还包括除字线结构101和有源区120外的其他存储器结构，例如浅沟槽隔离结构110(参考图2)等，由于其他存储器结构并不涉及到本公开的核心技术，在此不过多进行赘述；本领域技术人员可以理解基底100中还包括除字线结构101和有源区120外的其他存储器结构，用于存储器的正常运行。
基底100的材料可以包括蓝宝石、硅、碳化硅、砷化镓、氮化铝或者氧化锌等；在本实施例中基底100采用硅材料，本领域技术人员清楚，本实施例采用硅材料作为基底100是为了方便本领域技术人员对后续形成方法的理解，并不构成限定，在实际应用过程中，可以根据需求选择合适的基底的材料。
字线结构101为埋入式字线结构，位于基底100中，在AA1截面(参考图1)的剖面示意图中，字线结构101位于浅沟槽隔离结构110中，且字线结构101顶部形成有隔离层120，隔离层120用于字线结构101与基底100顶部导电结构的电隔离。
参考图1，基底100上形成有分立的位线结构130。
位线结构130延伸的方向与字线结构101延伸的方向相互垂直。位线结构130包括依次堆叠设置的位线接触层、金属层以及顶层介质层。位线接触层的材料包括钨或多晶硅；金属层可以为一种导电材料或者由多种导电材料构成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等；顶层介质的材料包括氮化硅、二氧化硅或氮氧化硅。
第一牺牲层201，位于位线结构130的间隙底部的基底100表面，第一牺牲层201的厚度小于所位线结构130的厚度。
第二牺牲层202，位于位线结构130的间隙底部的第一牺牲层201表面，第一牺牲层201和第二牺牲层202的材料不相同。
在本实施例中，形成的第一牺牲层201的厚度范围为3～10nm，例如5nm、 7nm或9nm；本实施例通过形成厚度为3～10nm的第一牺牲层201以提高第一牺牲层201和第二牺牲层202的稳定性。若第一牺牲层201的厚度大于10nm，图形化第一牺牲层201形成的沟槽同样具备较大的深宽比，可能会造成底部的第一牺牲层201存在刻蚀残留的问题；若第一牺牲层的厚度小于3nm，导致第一牺牲层201和第二牺牲层202的厚度差过大，导致形成的第一牺牲层201和第二牺牲层202的结构不稳定，从而导致后续形成的半导体结构存在结构缺陷。
在本实施例中，形成的第一牺牲层201和第二牺牲层202的厚度比小于或等于1：10，例如第一牺牲层201和第二牺牲层202的厚度比为1：3、1：5、1：7或1：9；本实施例通过形成厚度比小于等于1：10的第一牺牲层201和第二牺牲层202，以保证形成的第一牺牲层201和第二牺牲层202的稳定性。
第一牺牲层201与第二牺牲层202的材料不相同；第一牺牲层201的材料和第二牺牲层202的材料被同一刻蚀材料刻蚀的刻蚀选择比大于5：1。通过较大的刻蚀选择比，保证在刻蚀第一牺牲层201的过程中并不会影响刻蚀第二牺牲层202形成的沟槽。
第一牺牲层201和第二牺牲层202用于形成分立的位线结构之间的介质层和电容接触孔。
相比于相关技术而言，在分立的位线结构的间隙的牺牲层包括位于底部的第一牺牲层和位于顶部的第二牺牲层，第一牺牲层和第二牺牲层的材料不同，即降低了单次刻蚀工艺所需刻蚀牺牲层形成沟槽的深宽比，保证每次刻蚀工艺形成的沟槽底部不存在刻蚀残留；另外，由于第一牺牲层和第二牺牲层的材料不同，在刻蚀第一牺牲层的过程中并不会影响刻蚀第二牺牲层形成的沟槽，从而保证不影响介质层尺寸和电容接触孔尺寸的前提下，形成刻蚀完全的沟槽。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例 描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的半导体结构的形成方法及半导体结构中，在分立的位线结构的间隙的牺牲层包括位于底部的第一牺牲层和位于顶部的第二牺牲层，第一牺牲层和第二牺牲层的材料不同，即降低了单次刻蚀工艺所需刻蚀牺牲层形成沟槽的深宽比，保证每次刻蚀工艺形成的沟槽底部不存在刻蚀 残留；另外，由于第一牺牲层和第二牺牲层的材料不同，在刻蚀第一牺牲层的过程中并不会影响刻蚀第二牺牲层形成的沟槽，从而保证不影响介质层尺寸和电容接触孔尺寸的前提下，形成刻蚀完全的沟槽。

Claims (19)

  1. 一种半导体结构的形成方法，包括：
    提供基底，所述基底上形成有分立的位线结构；
    在所述位线结构间隙底部的所述基底表面上形成第一牺牲层；
    形成填充所述分立的位线结构间隙的第二牺牲层，所述第二牺牲层位于所述第一牺牲层顶部，且所述第一牺牲层和所述第二牺牲层的材料不相同；
    图形化所述第二牺牲层和所述第一牺牲层形成开口，在所述位线结构延伸的方向上，形成的所述开口和剩余所述第二牺牲层交替排布；
    形成填充所述开口的介质层；
    去除剩余的所述第一牺牲层和所述第二牺牲层形成电容接触孔，在所述位线结构延伸的方向上，形成的所述电容接触孔和所述介质层交替排布。
  2. 根据权利要求1所述的半导体结构的形成方法，其中，在所述位线结构间隙底部的所述基底表面上形成第一牺牲层，包括以下步骤：
    形成覆盖所述位线结构顶部和侧壁，以及覆盖所述位线结构间隙底部所述基底的第一牺牲膜；
    去除位于所述位线结构顶部和侧壁的所述第一牺牲膜，剩余所述第一牺牲膜构成所述第一牺牲层。
  3. 根据权利要求2所述的半导体结构的形成方法，其中，所述第一牺牲膜采用原子层沉积的方式形成。
  4. 根据权利要求1所述的半导体结构的形成方法，其中，形成的所述第一牺牲层的厚度范围为3～10nm。
  5. 根据权利要求4所述的半导体结构的形成方法，其中，所述第一牺牲层和所述第二牺牲层的厚度比小于或等于1：10。
  6. 根据权利要求1所述的半导体结构的形成方法，其中，在所述位线结构间隙底部的所述基底表面上形成第一牺牲层，包括以下步骤：
    在所述位线结构间隙底部的所述基底表面上形成第一子牺牲层；
    在所述第一子牺牲层的顶部表面形成第二子牺牲层，所述第一子牺牲层的材料与所述第二子牺牲层的材料不同，所述第一子牺牲层与所述第二子牺牲层共同构成所述第一牺牲层。
  7. 根据权利要求1所述的半导体结构的形成方法，其中，形成填充所述分立的位线结构间隙的第二牺牲层，包括以下步骤：
    在所述第一牺牲层表面形成填充所述位线结构间隙且覆盖所述位线结构的第二牺牲膜；
    对所述第二牺牲膜进行平坦化处理，直至剩余所述第二牺牲膜的高度与所述位线结构的高度一致，剩余所述第二牺牲膜构成所述第二牺牲层。
  8. 根据权利要求7所述的半导体结构的形成方法，其中，所述第二牺牲膜采用化学气相沉积的方式形成。
  9. 根据权利要求1所述的半导体结构的形成方法，其中，所述第一牺牲层的材料和所述第二牺牲层的材料被同一刻蚀材料刻蚀的刻蚀选择比大于5：1。
  10. 根据权利要求1所述的半导体结构的形成方法，其中，所述第一牺牲层的致密度小于所述第二牺牲层的材料的致密度。
  11. 根据权利要求1所述的半导体结构的形成方法，其中，图形化所述第二牺牲层和所述第一牺牲层形成开口，包括以下步骤：
    在所述第二牺牲层顶部表面形成图形化的光刻胶；
    基于所述图形化的光刻胶去除部分所述第二牺牲层形成预开口，在所述位线结构延伸的方向上，形成的所述预开口和剩余所述第二牺牲层交替排布；
    去除所述预开口暴露出的所述第一牺牲层，形成所述开口。
  12. 根据权利要求1所述的半导体结构的形成方法，其中，图形化所述第二牺牲层和所述第一牺牲层形成开口，包括以下步骤：
    在所述第二牺牲层顶部表面形成图形化的光刻胶；
    基于所述图形化的光刻胶，采用同一刻蚀材料去除部分所述第二牺牲层和所述第一牺牲层，形成所述开口。
  13. 根据权利要求1所述的半导体结构的形成方法，其中，形成填充所述开口的介质层，包括以下步骤：
    形成填充所述开口且覆盖所述第二牺牲层的介质膜；
    对所述介质膜进行平坦化处理，直至剩余所述介质膜的高度与所述第二牺牲层的高度一致，剩余所述介质膜构成所述介质层。
  14. 根据权利要求1所述的半导体结构的形成方法，其中，去除剩余的所述第一牺牲层和所述第二牺牲层形成电容接触孔，包括以下步骤：
    基于所述介质层和所述位线结构，去除剩余所述第二牺牲层，形成通孔，所述通孔暴露出所述第一牺牲层；
    基于所述介质层和所述位线结构，去除所述通孔底部的所述第一牺牲层，形成所述电容接触孔。
  15. 根据权利要求14所述的半导体结构的形成方法，其中，采用灰化的方式去除剩余所述第二牺牲层。
  16. 一种半导体结构，包括：
    基底，以及位于所述基底上分立的位线结构；
    第一牺牲层，位于所述位线结构的间隙底部的所述基底表面，所述第一牺牲层的厚度小于所述位线结构的厚度；
    第二牺牲层，位于所述位线结构的间隙底部的所述第一牺牲层表面，所述第一牺牲层和所述第二牺牲层的材料不相同；
    所述第一牺牲层和所述第二牺牲层用于形成分立的所述位线结构之间的介质层和电容接触孔。
  17. 根据权利要求16所述的半导体结构，其中，所述第一牺牲层的厚度范围为3～10nm。
  18. 根据权利要求16所述的半导体结构，其中，所述第一牺牲层和所述第二牺牲层的厚度比小于或等于1：10。
  19. 根据权利要求16所述的半导体结构，其中，所述第一牺牲层的材料和所述第二牺牲层的材料被同一刻蚀材料刻蚀的刻蚀选择比大于5：1。
PCT/CN2021/107423 2021-03-09 2021-07-20 半导体结构的形成方法及半导体结构 WO2022188330A1 (zh)

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