WO2022188311A1 - 半导体结构的制备方法及半导体结构 - Google Patents

半导体结构的制备方法及半导体结构 Download PDF

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Publication number
WO2022188311A1
WO2022188311A1 PCT/CN2021/104158 CN2021104158W WO2022188311A1 WO 2022188311 A1 WO2022188311 A1 WO 2022188311A1 CN 2021104158 W CN2021104158 W CN 2021104158W WO 2022188311 A1 WO2022188311 A1 WO 2022188311A1
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Prior art keywords
layer
conductive
semiconductor structure
conductive layer
bit line
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PCT/CN2021/104158
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English (en)
French (fr)
Inventor
平尔萱
白杰
黄娟娟
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长鑫存储技术有限公司
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Priority to KR1020237027229A priority Critical patent/KR20230128379A/ko
Priority to JP2023555668A priority patent/JP2024509969A/ja
Priority to EP21929781.9A priority patent/EP4276895A4/en
Priority to US17/643,085 priority patent/US20220293611A1/en
Publication of WO2022188311A1 publication Critical patent/WO2022188311A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Definitions

  • Embodiments of the present application relate to the technical field of semiconductor manufacturing, and in particular, to a method for fabricating a semiconductor structure and a semiconductor structure.
  • the dynamic random access memory includes a bit line structure, a capacitor structure and a transistor structure.
  • the bit line structure and the capacitor structure are respectively connected with the transistor structure, and the data stored in the capacitor structure is controlled to be read by the transistor structure.
  • an embodiment of the present application provides a method for fabricating a semiconductor structure, including:
  • bit line structures distributed at intervals are formed on the substrate, the bit line structures include a conductive layer, a transition layer and a cover layer stacked in sequence, and the width of the transition layer is smaller than the width of the conductive layer;
  • Air gaps are formed on the top surface of the conductive layer and the side surfaces of the transition layer.
  • the width of the cover layer is greater than the width of the conductive layer; the air gap protrudes from the side of the conductive layer.
  • the embodiments of the present application further provide a semiconductor structure, including:
  • bit line structures distributed on the substrate at intervals, the bit line structures comprising a conductive layer, a transition layer and a cover layer stacked in sequence, and the width of the transition layer is smaller than the width of the conductive layer;
  • the air gap is located on the top surface of the conductive layer and the side surface of the transition layer.
  • a plurality of bit line structures are distributed on the substrate, and the bit line structure includes a conductive layer, a transition layer and a cover layer that are stacked in sequence, and the width of the transition layer is smaller than the width of the conductive layer; and Air gaps are formed on the top surface of the conductive layer and on the sides of the transition layer.
  • FIG. 1 is a flowchart of a method for preparing a semiconductor structure provided by an embodiment of the present application
  • FIG. 2 is a schematic structural diagram after forming a mask layer in a method for preparing a semiconductor structure provided by an embodiment of the present application;
  • FIG. 3 is a schematic structural diagram of a semiconductor structure after forming a groove in a method for preparing a semiconductor structure provided by an embodiment of the present application;
  • FIG. 4 is a schematic structural diagram after forming an insulating sealing layer in a method for preparing a semiconductor structure provided by an embodiment of the present application;
  • FIG. 5 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present application.
  • This embodiment provides a method for fabricating a semiconductor structure and a semiconductor structure for improving the performance of the semiconductor structure.
  • the preparation method of the semiconductor structure provided in this embodiment includes:
  • the substrate serves as the basis of the subsequent film layer and can play a supporting role for the subsequent film layer.
  • the material of the substrate may be a semiconductor material, including silicon, germanium, silicon germanium, etc., and the material of the substrate is not limited in this embodiment.
  • a shallow trench isolation structure 10 and an active region structure 20 may be formed on a substrate (not shown) at intervals, so as to facilitate the formation of a transistor structure.
  • bit line structure includes a conductive layer, a transition layer and a cover layer stacked in sequence, and the width of the transition layer is smaller than that of the conductive layer.
  • the conductive layer 301, the transition layer 302 and the cover layer 3031 are stacked, the transition layer 302 is located between the cover layer 3031 and the conductive layer 301, and the conductive layer 301 is disposed close to the substrate.
  • the conductive layer 301 may be connected to the active structure 20 , for example, may be connected to the source or the gate of the active structure 20 .
  • the specific steps of forming the conductive layer 301 may include: as shown in FIG. 2 , forming a conductive initial layer 311 , for example, sequentially stacking a first conductive initial layer 3111 , a conductive contact initial layer 3112 and a second conductive initial layer along a direction away from the substrate. layer 3113, wherein the conductive contact initial layer 3112 is located between the first conductive initial layer 3111 and the second conductive initial layer 3113, and the conductive contact initial layer 3112 can prevent the material constituting the first conductive initial layer 3111 and the second conductive initial layer 3113 Penetration occurs, and the contact resistance between the first conductive initial layer 3111 and the second conductive initial layer 3113 can also be reduced.
  • the material of the first conductive initial layer 3111 may include polysilicon
  • the material of the second conductive initial layer 3113 may include tungsten
  • the material of the conductive contact initial layer 3112 may include titanium nitride or tungsten nitride.
  • the width of the transition layer 302 is smaller than the width of the conductive layer 301 (taking the orientation shown in FIG. 3 as an example, the width is the dimension in the horizontal direction); after the conductive initial layer 311 is formed, a stacked transition initial layer 312 and a covering layer are formed. The initial layer 313, and a mask layer 50 with a mask pattern is formed on the covering initial layer 313; as shown in FIG. layer 311 to form a cover layer 3031, a transition layer 302 and a conductive layer 301; at this time, the widths of the cover layer 3031, the transition layer 302 and the conductive layer 301 are equal.
  • the transition layer 302 may be etched laterally to remove part of the transition layer 302 to form the grooves 304 , so that the width of the finally formed transition layer 302 is smaller than the width of the conductive layer 301 .
  • a portion of the transition layer 302 may be removed by a wet process.
  • the cover initial layer 313, the transition initial layer 312 and the conductive initial layer 311 are etched using the mask layer 50 as a mask, a portion of the transition initial layer 312 located under the cover layer 3031 may be etched simultaneously, so that the formation of The width of the transition layer 302 is smaller than the width of the conductive layer 301 .
  • the transition initial layer 312 when etching to the transition initial layer 312, the transition initial layer 312, the conductive initial layer 311 and the cover initial layer 313 may be selected for etching with a gas having a higher etch selectivity, so that the etching can be performed along the width direction at the cover layer.
  • the portion directly under the layer 3031 transitions to the initial layer 312 , so that the width of the transition layer 302 finally formed is smaller than the width of the conductive layer 301 .
  • the plurality of bit line structures 30 are spaced apart.
  • the plurality of bit line structures 30 extend in a line shape along a direction parallel to the substrate, and the plurality of bit line structures 30 may be located in the same plane parallel to the substrate, and Several bit line structures 30 are arranged in parallel and spaced apart.
  • the bit line structures 30 in this embodiment may also be distributed on the substrate in other forms, which are not limited in this embodiment.
  • the method for fabricating the semiconductor structure provided in this embodiment further includes: after forming a plurality of spaced bit line structures 30:
  • Air gaps are formed on the top surface of the conductive layer and the side surfaces of the transition layer.
  • the width of the transition layer 302 in the bit line structure 30 is smaller than the width of the conductive layer 301 , so that the bit line structure 30 forms grooves 304 on both sides of the transition layer 302 along the width direction.
  • the bit line structure 30 may include a sidewall covering the conductive layer 301 and an insulating sealing layer 3032 on the sidewall of the covering layer 3031. At this time, the insulating sealing layer 3032 seals the groove 304 to form a transition layer. 302 along the air gap 305 on both sides in the width direction.
  • the insulating sealing layer 3032 may be formed by CVD or ALD, while preventing the insulating sealing layer 3032 from filling the groove 304, so that the insulating sealing layer 3032, the conductive layer 301, the transition layer 302 and the cover layer 3031 are surrounded by An air gap 305 is formed.
  • the material of the insulating sealing layer 3032 may be the same as the material of the covering layer 3031, for example, the materials of the insulating sealing layer 3032 and the covering layer 3031 may be silicon nitride, silicon oxide, etc.; The materials are the same.
  • the covering layer 3031 and the insulating sealing layer 3032 can be formed into an integrated structure to improve the strength of the covering layer 303 .
  • bit line structure 30 includes a conductive layer 301 , a transition layer 302 and a cover layer 3031 which are stacked in sequence, and the width of the transition layer 302 is smaller than that of the conductive layer 301 and the air gap 305 is formed on the top surface of the conductive layer 301 and the side surface of the transition layer 302 .
  • the air gap 305 By forming the air gap 305 on the top surface of the conductive layer 301 and the side surface of the transition layer 302, the influence of the cover layer 3031 on the conductive layer 301 can be reduced.
  • the material of the cover layer 3031 is silicon nitride
  • the material of the conductive layer 301 is In the case of tungsten
  • the existence of the air gap 305 can reduce the migration of nitrogen in the cover layer 3031 to the conductive layer 301 to nitride the conductive layer 301 to form tungsten nitride, prevent the resistance of the conductive layer 301 from increasing, and at the same time, reduce the bit line Parasitic capacitance between the structure 30 and its surrounding structures, thereby improving the performance of the semiconductor structure.
  • the width of the capping layer 3031 may be greater than the width of the conductive layer 301 ; the formed air gap 305 may protrude from the side surface of the conductive layer 301 . In this way, the contact area between the air gap 305 and the top surface of the conductive layer 301 can be increased to improve the protection effect on the top surface of the conductive layer 301; at the same time, by increasing the volume of the air gap 305, the bit line structure 30 and the surrounding structure ( Such as the parasitic capacitance between the conductive plugs 40).
  • the method for fabricating a semiconductor structure provided in this embodiment further includes: forming conductive plugs 40 on the substrate between the bit line structures 30 , and the conductive plugs 40 are located between adjacent bit line structures 30 , The conductive plugs 40 are used to connect the active region structures 20 .
  • the conductive plug 40 is also used to connect the capacitive storage structure.
  • the conductive plug 40 includes a first conductive portion 401 and a second conductive portion 402 that are sequentially stacked along a direction perpendicular to the substrate, that is, the second conductive portion 402 is located above the first conductive portion 401, wherein the first conductive portion 402
  • the conductive portion 401 is connected to the active region structure 20, and the second conductive portion 402 can be used to connect a capacitor.
  • the material of the first conductive portion 401 may include polysilicon or the like, and the material of the second conductive portion 402 may include tungsten or the like.
  • a conductive barrier film is disposed between the conductive portion 401 and the second conductive portion 402, and the material of the conductive barrier film may include titanium nitride or the like.
  • the bottom of the second conductive portion 402 has a slope 4021 facing the bit line structure 30 .
  • the bottom of the bevel 4021 is higher than the top of the conductive layer 301 , and the top of the bevel 4021 is lower than the top of the transition layer 302 . such that the top of the transition layer 302 is located between the top and bottom of the inclined plane 4021 .
  • the conductive layer 301 formed at this time can be as high as possible and has a lower resistance.
  • the bottom of the second conductive portion 402 further includes a bottom surface 4024, a first straight surface 4022 and a second straight surface 4023, the bottom surface 4024 is in direct contact with the top surface of the first conductive portion 401, and two ends of the bottom surface 4024 are respectively in contact with the first straight surface
  • the surface 4022 is connected with the second straight surface 4023 ; wherein, the first straight surface 4022 is also connected with the inclined surface 4021 .
  • the vertical distance between the top angle of the transition layer 302 and the inclined surface 4021 is smaller than the vertical distance between the top angle of the conductive layer 301 and the inclined surface 4021 .
  • the top angle of the transition layer 302 is in the section perpendicular to the substrate and perpendicular to the extension direction of the bit line structure 30 (in the section shown in FIG. 5 ), and the top of the transition layer 302 is close to the first vertex a of the inclined plane 4021 ; the transition layer 302
  • the vertical distance between the vertex angle and the inclined surface 4021 is the vertical distance d1 between the first vertex a and the inclined surface 4021 .
  • the top angle of the conductive layer 301 is in a cross-section perpendicular to the substrate and perpendicular to the extending direction of the bit line structure 30 (in the cross-section shown in FIG. 5 ), and the top of the conductive layer 301 is close to the second vertex b of the inclined plane 4021;
  • the distance between the top corner of the conductive layer 301 and the inclined surface 4021 is the vertical distance d2 from the second vertex b to the inclined surface 4021 .
  • the vertical distance d1 between the top angle of the transition layer 302 and the inclined surface 4021 is greater than the vertical distance d2 between the top angle of the conductive layer 301 and the inclined surface 4021 . In this way, when the transition layer 302 is a conductor, the resistance of the bit line structure 30 can be reduced, and the parasitic capacitance between the bit line structure 30 and the contact plug 40 can be further reduced.
  • the width of the transition layer 302 is 2/3-3/4 of the width of the conductive layer 301 , and this setting can reduce the influence of the cover layer 3031 on the conductive layer 301 , ensure the supporting force on the cover layer 3031 , and avoid transition The cover layer 3031 collapses due to the too small width of the layer 302 .
  • the material of the transition layer 302 provided in this embodiment may include metal-rich nitride (eg, tungsten nitride, molybdenum nitride, titanium nitride, etc.) or metal-rich silicide (eg, titanium silicide, tungsten silicide, etc.).
  • metal-rich nitride eg, tungsten nitride, molybdenum nitride, titanium nitride, etc.
  • metal-rich silicide eg, titanium silicide, tungsten silicide, etc.
  • metal-rich nitride refers to the molar ratio of metal atoms to nitrogen atoms greater than 1, such as 2, 3, 4, 5, 6, 7, etc.
  • metal-rich silicide refers to the mole ratio of metal atoms to silicon atoms The ratio is greater than 1, such as 2, 3, 4, 5, 6, 7, etc.
  • this embodiment further provides a semiconductor structure, which can be prepared by the method for preparing a semiconductor structure provided in any of the above embodiments, so that the bit line structure of the semiconductor structure includes a conductive layer 301 , a transition layer and a transition layer that are stacked in sequence. 302 and the cover layer 3031, the width of the transition layer 302 is smaller than the width of the conductive layer 301; The transition layer 302 and the air gap 305 can reduce the influence of the capping layer 3031 on the conductive layer 301 to prevent the resistance of the conductive layer 301 from increasing, thereby improving the performance of the semiconductor structure.
  • the semiconductor structure provided in this embodiment includes a substrate and a plurality of bit line structures spaced on the substrate.
  • the bit line structure includes a conductive layer 301, a transition layer 302 and a cover layer 3031 stacked in sequence, and the width of the transition layer 302 is smaller than that of the conductive layer. 301 width.
  • the material of the substrate may include silicon, germanium, silicon germanium, etc., and the material of the substrate is not limited in this embodiment.
  • Shallow trench isolation structures 10 and active region structures 20 may be formed at intervals on the substrate to facilitate the formation of transistor structures.
  • the conductive layer 301, the transition layer 302 and the cover layer 3031 are stacked, the transition layer 302 is located between the cover layer 3031 and the conductive layer 301, and the conductive layer 301 is disposed close to the substrate.
  • the conductive layer 301 may include a first conductive layer 3011 , a conductive contact layer 3012 and a second conductive layer 3013 that are sequentially stacked in a direction away from the substrate, wherein the conductive contact layer 3012 is located between the first conductive layer 3011 and the second conductive layer 3013 .
  • the conductive contact layer 3012 can prevent the materials constituting the first conductive layer 3011 and the second conductive layer 3013 from permeating.
  • the material of the first conductive layer 3011 may include polysilicon
  • the material of the second conductive layer 3013 may include tungsten
  • the material of the conductive contact layer 3012 may include titanium nitride.
  • bit line structures are spaced apart.
  • several bit line structures extend in a line shape along a direction parallel to the substrate, several bit line structures may be located in the same plane parallel to the substrate, and several bit line structures Arrangement of parallel and spaced structures.
  • the bit line structures in this embodiment may also be distributed on the substrate in other forms, which are not limited in this embodiment.
  • air gaps 305 are located on the top surface of conductive layer 301 and on the sides of transition layer 302 . That is to say, an air gap 305 is formed between the side surface of the transition layer 302 and the top surface of the conductive layer 301 .
  • the cladding layer 303 may include a cladding layer 3031 located on the upper portion of the transition layer 302, and an insulating sealing layer 3032 covering the sidewalls of the cladding layer 3031 and the sidewalls of the conductive layer 301; since the width of the transition layer 302 is smaller than that of the conductive layer 302 The width of the layer 301 can form grooves on both sides of the transition layer 302 ; after the insulating sealing layer is formed, the insulating sealing layer 3032 covers the grooves to form the air gap 305 .
  • the width of the capping layer 3031 is greater than the width of the conductive layer 301 .
  • the air gap 305 protrudes from the side surface of the conductive layer 301 , that is, the air gap 305 protrudes outward from the side surface of the conductive layer 301 .
  • This arrangement can increase the distance between the air gap 305 and the top surface of the conductive layer 301 .
  • the contact area can improve the protection effect on the top surface of the conductive layer 301; meanwhile, increasing the volume of the air gap 305 can further improve the parasitic capacitance between the bit line structure 30 and the surrounding structures (such as the conductive plug 40).
  • the semiconductor structure provided in this embodiment further includes conductive plugs 40 located between the bit line structures, the conductive plugs 40 are located between adjacent bit line structures 30 , and the conductive plugs 40 are used to connect the active Zone Structure 20.
  • the conductive plug 40 is also used to connect the capacitive storage structure.
  • the conductive plug 40 includes a first conductive portion 401 and a second conductive portion 402 that are sequentially stacked along a direction perpendicular to the substrate, that is, the second conductive portion 402 is located above the first conductive portion 401, wherein the first conductive portion 402
  • the conductive portion 401 is connected to the active region structure 20, and the second conductive portion 402 is used to connect the capacitive storage structure.
  • the material of the first conductive portion 401 may include polysilicon or the like, and the material of the second conductive portion 402 may include tungsten or the like.
  • a conductive barrier film is disposed between the conductive portion 401 and the second conductive portion 402, and the material of the conductive barrier film may include titanium nitride or the like.
  • the bottom of the second conductive portion 402 has a slope 4021 facing the bit line structure 30, and the bottom of the slope 4021 is higher than the top of the conductive layer 301 and lower than the top of the transition layer 302, so that the top of the transition layer 302 is located on the slope 4021 between the top and bottom.
  • the bottom of the second conductive portion further includes a bottom surface 4024, a first straight surface 4022, and a second straight surface 4023.
  • the bottom surface 4024 is in direct contact with the top surface of the first conductive portion 401, and two ends of the bottom surface 4024 are respectively connected to the first straight surface.
  • 4022 is connected to the second straight surface 4023; wherein, the first straight surface 4022 is also connected to the inclined surface 4021.
  • the vertical distance between the top angle of the transition layer 302 and the inclined surface 4021 is smaller than the vertical distance between the top angle of the conductive layer 301 and the inclined surface 4021 .
  • the top angle of the transition layer 302 is in a section perpendicular to the substrate and perpendicular to the extension direction of the bit line structure 30 (in the section shown in FIG. 5 ), and the top of the transition layer 302 is close to the first vertex a of the inclined plane 4021 ; the transition layer 302
  • the vertical distance between the vertex angle and the inclined surface 4021 is the vertical distance d1 between the first vertex a and the inclined surface 4021 .
  • the top angle of the conductive layer 301 is in a cross-section perpendicular to the substrate and perpendicular to the extending direction of the bit line structure 30 (in the cross-section shown in FIG. 5 ), and the top of the conductive layer 301 is close to the second vertex b of the inclined plane 4021;
  • the distance between the top angle of the conductive layer 301 and the inclined surface 4021 is the vertical distance d2 from the second vertex b to the inclined surface 4021 .
  • the vertical distance d1 between the top angle of the transition layer 302 and the inclined surface 4021 is greater than the vertical distance d2 between the top angle of the conductive layer 301 and the inclined surface 4021 . In this way, when the transition layer 302 is a conductor, the resistance of the bit line structure 30 can be reduced, and the parasitic capacitance between the bit line structure 30 and the contact plug 40 can be further reduced.
  • the width of the transition layer 302 is 2/3-3/4 of the width of the conductive layer 301 , and this setting can reduce the influence of the cover layer 3031 on the conductive layer 301 , ensure the supporting force on the cover layer 3031 , and avoid The cover layer 3031 collapses due to the too small width of the transition layer 302 .
  • the material of the transition layer 302 provided in this embodiment may include metal-rich nitride (eg, tungsten nitride, molybdenum nitride, titanium nitride, etc.) or metal-rich silicide (eg, titanium silicide, tungsten silicide, etc.).
  • metal-rich nitride eg, tungsten nitride, molybdenum nitride, titanium nitride, etc.
  • metal-rich silicide eg, titanium silicide, tungsten silicide, etc.
  • Such arrangement of metal-rich nitride and metal-rich silicide can trap nitrogen atoms migrated into the conductive layer 301 in the capping layer 3031 , so as to further reduce the influence of the conductive layer 301 on the capping layer 3031 and prevent the resistance of the conductive layer 301 from increasing.
  • the capping layer 3031 may include silicon nitride or the like.

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Abstract

本申请实施例属于半导体制作技术领域，涉及一种半导体结构的制备方法及半导体结构，用于提高半导体结构的性能。该半导体结构的制备方法包括：在基底上形成位线结构，位线结构包括依次层叠设置的导电层、过渡层和覆盖层，过渡层的宽度小于导电层的宽度；并且在导电层的顶面以及过渡层的侧面形成气隙。气隙既能减少覆盖层对导电层的影响以防止导电层的电阻增大，又能降低位线结构与其周边结构之间的寄生电容，从而提高了半导体结构的性能。

Description

半导体结构的制备方法及半导体结构
本申请要求于2021年03月12日提交中国专利局、申请号为202110269749.6、申请名称为“半导体结构的制备方法及半导体结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及半导体制造技术领域，尤其涉及一种半导体结构的制备方法及半导体结构。
背景技术
随着存储设备技术的逐渐发展，动态随机存储器(Dynamic Random Access Memory，简称DRAM)以其较高的密度以及较快的读写速度逐渐应用在各种电子设备中。动态随机存储器包括位线结构、电容结构和晶体管结构，位线结构、电容结构分别与晶体管结构连接，通过晶体管结构控制读取电容结构内存储的数据。
然而，目前动态随机存储器的性能仍然有待提高。
发明内容
第一方面，本申请实施例提供了一种半导体结构的制备方法，包括：
提供基底；
在所述基底上形成间隔分布的若干位线结构，所述位线结构包括依次叠设的导电层、过渡层和覆盖层，所述过渡层的宽度小于所述导电层的宽度；
在所述导电层的顶面以及所述过渡层的侧面形成气隙。
在一些实施中，所述覆盖层的宽度大于所述导电层的宽度；所述气隙凸出于所述导电层的侧面。
第二方面，本申请实施例还提供一种半导体结构，包括：
基底；
间隔分布于所述基底上的若干位线结构，所述位线结构包括依次叠设的导电层、过渡层和覆盖层，所述过渡层的宽度小于所述导电层的宽度；
气隙，所述气隙位于所述导电层的顶面以及所述过渡层的侧面。
本实施例提供的半导体结构的制备方法及半导体结构，基底上分布若干位线结构，位线结构包括依次层叠设置的导电层、过渡层和覆盖层，过渡层的宽度小于导电层的宽度；并且在导电层的顶面以及过渡层的侧面形成气隙。通过在导电层的顶面以及过渡层的侧面形成气隙，可以减少覆盖层对导电层之间的影响以防止导电层的电阻增大，又能降低位线结构与其周边结构之间的寄生电容，从而提高了半导体结构的性能。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是 本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的半导体结构的制备方法流程图；
图2为本申请实施例提供的半导体结构的制备方法中形成掩膜层后的结构示意图；
图3为本申请实施例提供的半导体结构的制备方法中形成凹槽后的结构示意图；
图4为本申请实施例提供的半导体结构的制备方法中形成绝缘密封层后的结构示意图；
图5为本申请实施例提供的半导体结构的结构示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本实施例提供一种半导体结构的制备方法及半导体结构，用于提高半导体结构的性能。
如图1所示，本实施例提供的半导体结构的制备方法，包括：
S101：提供基底。
其中，基底作为后续膜层的基础，可以对后续膜层起到支撑的作用。示例性的，基底的材质可以为半导体材料，示例的，包括硅、锗、硅锗等，本实施例对基底的材质不做限制。
请参照图2-图5，在基底(未示出)上可以形成有间隔设置的浅沟槽隔离结构10和有源区结构20，以便于形成晶体管结构。
本实施例提供的半导体结构的制备方法，在形成基底之后还包括：
S102：在基底上形成间隔分布的若干位线结构，位线结构包括依次叠设的导电层、过渡层和覆盖层，过渡层的宽度小于导电层的宽度。
继续参照图2-图5，导电层301、过渡层302和覆盖层3031层叠的设置，过渡层302位于覆盖层3031和导电层301之间，并且导电层301靠近基底设置。例如，导电层301可以与有源结构20相连，示例的，可以与有源结构20的源极或栅极相连。
形成导电层301的具体步骤可以包括：如图2所示，形成导电初始层311，示例的，沿远离基底的方向依次层叠形成第一导电初始层3111、导电接触初始层3112以及第二导电初始层3113，其中，导电接触初始层3112位于第一导电初始层3111和第二导电初始层3113之间，导电接触初始层3112可以阻止构成第一导电初始层3111和第二导电初始层3113的材质发生渗透，也可以降低第一导电初始层3111和第二导电初始层3113之间的接触电阻。示例性的，第一导电初始层3111的材质可以包括多晶硅，第二导电初始层3113的材质可以包括钨，导电接触初始层3112的材质可以包括氮化钛或氮化钨等。
在一些实施中，过渡层302的宽度小于导电层301的宽度(以图3所示方位为例， 宽度为水平方向的尺寸)；形成导电初始层311之后，形成层叠的过渡初始层312以及覆盖初始层313，并在覆盖初始层313上形成具有掩膜图案的掩膜层50；如图3所示，之后以掩膜层50为掩膜蚀刻覆盖初始层313、过渡初始层312以及导电初始层311，以形成覆盖层3031、过渡层302以及导电层301；此时覆盖层3031、过渡层302以及导电层301的宽度相等。在此之后，可以横向蚀刻过渡层302，以去除部分过渡层302，形成凹槽304，进而使得最终形成的过渡层302的宽度小于导电层301的宽度。示例的，可以利用湿法工艺去除部分过渡层302。在其他示例中，也可以在以掩膜层50为掩膜蚀刻覆盖初始层313、过渡初始层312和导电初始层311时同步刻蚀部分位于覆盖层3031下方的部分过渡初始层312，使得形成的过渡层302的宽度小于导电层301的宽度。示例的，在刻蚀到过渡初始层312时，可以选择过渡初始层312与导电初始层311以及覆盖初始层313具有较高的蚀刻选择比的气体进行刻蚀，以在沿宽度方向蚀刻位于覆盖层3031正下方的部分过渡初始层312，使得最终形成的过渡层302的宽度小于导电层301的宽度。
本实施例中，若干位线结构30间隔分部，示例性的，若干位线结构30沿平行于基底的方向延伸成线状，若干位线结构30可以位于同一平行于基底的平面内，并且若干位线结构30平行且间隔的设置。当然，本实施例中的位线结构30还可以呈其他的形式在基底上分布，本实施例对此不作限制。
本实施例提供的半导体结构的制备方法，在形成若干间隔分布的位线结构30之后还包括：
S104：在导电层的顶面以及过渡层的侧面形成气隙。
如图4-图5所示，示例的，位线结构30中过渡层302的宽度小于导电层301的宽度，使得位线结构30在过渡层302沿宽度方向的两侧形成凹槽304。为了形成气隙305，位线结构30可以包括覆盖导电层301的侧壁以及覆盖层3031侧壁上的绝缘密封层3032，此时绝缘密封层3032对凹槽304形成封闭，以形成位于过渡层302沿宽度方向两侧的气隙305。
示例的，可以采用CVD或ALD的方式形成绝缘密封层3032，同时避免绝缘密封层3032填满凹槽304，以使得绝缘密封层3032、导电层301、过渡层302以及覆盖层3031之间围设成气隙305。
示例性的，绝缘密封层3032的材质可以与覆盖层3031的材质相同，例如绝缘密封层3032和覆盖层3031的材质可以均为氮化硅、氧化硅等；绝缘密封层3032和覆盖层3031的材质相同，在形成绝缘密封层3032后，可以使覆盖层3031和绝缘密封层3032形成一体结构，以提高包覆层303的强度。
本实施例提供的半导体结构的制备方法，基底上分布若干位线结构30，位线结构30包括依次层叠设置的导电层301、过渡层302和覆盖层3031，过渡层302的宽度小于导电层301的宽度；并且在导电层301的顶面以及过渡层302的侧面形成气隙305。通过在导电层301的顶面和过渡层302的侧面形成气隙305，可以减少覆盖层3031对导电层301的影响，例如，覆盖层3031的材质为氮化硅时，导电层301的材质为钨时，气隙305的存在可以减少覆盖层3031中的氮迁移至导电层301将导电层301氮化形成氮化钨的程度，防止导电层301的电阻增大，同时，又能降低位线结构30与其周边结 构之间的寄生电容，从而提高了半导体结构的性能。
在一些实施中，覆盖层3031的宽度可以大于导电层301的宽度；形成的气隙305可以凸出于导电层301的侧面。如此设置，可以增大气隙305与导电层301顶面的接触面积，以提高对导电层301顶面的保护效果；同时，提高气隙305的体积，可以进一步改善位线结构30和周边结构(如导电插塞40)之间的寄生电容。
继续参照图5，本实施例提供的半导体结构的制备方法，还包括：在位线结构30之间的基底上形成导电插塞40，导电插塞40位于相邻的位线结构30之间，导电插塞40用于连接有源区结构20。在半导体结构为动态随机存储器的实现方式中，导电插塞40还用于连接电容存储结构。
示例的，导电插塞40包括沿垂直于基底方向依次层叠设置的第一导电部分401和第二导电部分402，也就是说，第二导电部分402位于第一导电部分401的上方，其中第一导电部分401与有源区结构20连接，第二导电部分402可以用于连接电容。示例性的，第一导电部分401的材质可以包括多晶硅等，第二导电部分402的材质可以包括钨等，为了阻止第一导电部分401和第二导电部分402的材质互相渗透，可以在第一导电部分401和第二导电部分402之间设置导电阻挡膜，导电阻挡膜的材质可以包括氮化钛等。
其中，第二导电部分402的底部具有面向位线结构30的斜面4021。
在一些实施中，斜面4021的底部高于导电层301的顶部，斜面4021的顶部低于过渡层302的顶部。以使得，过渡层302的顶部位于斜面4021的顶部和底部之间。此时形成的导电层301能够尽可能的高，具有较小的电阻。
示例的，第二导电部分402的底部还包括底面4024、第一直面4022和第二直面4023，底面4024与第一导电部分401的顶面直接接触，底面4024的两端分别与第一直面4022和第二直面4023连接；其中，第一直面4022还与斜面4021连接。
在上述实现方式中，过渡层302的顶角与斜面4021的垂直距离小于导电层301的顶角与斜面4021的垂直距离。其中过渡层302顶角为在垂直于基底且垂直于位线结构30延伸方向的截面中(如图5所示的截面中)，过渡层302顶端靠近斜面4021的第一顶点a；过渡层302顶角与斜面4021的垂直距离为第一顶点a到斜面4021之间的垂直距离d1。相应的，导电层301的顶角为在垂直于基底且垂直与位线结构30延伸方向的截面中(如图5所示的截面中)，导电层301顶端靠近斜面4021的第二顶点b；导电层301顶角与斜面4021之间的距离为第二顶点b到斜面4021的垂直距离d2。
在其他示例中，过渡层302的顶角与斜面4021的垂直距离d1大于导电层301的顶角与斜面4021的垂直距离d2。如此设置，在过渡层302为导体时，既能减少位线结构30的电阻，又能进一步降低位线结构30和接触插塞40之间的寄生电容。
本实施例中过渡层302的宽度为导电层301宽度的2/3-3/4，如此设置，可以在减少覆盖层3031对导电层301的影响，保证对覆盖层3031的支撑力，避免过渡层302的宽度过小导致的覆盖层3031塌陷。
本实施例提供的过渡层302的材质可以包括富金属氮化物(如氮化钨、氮化钼、氮化钛等)或者富金属硅化物(如硅化钛、硅化钨等)。如此设置，富金属氮化物和富金属硅化物可以捕获覆盖层3031中迁移至导电层301中的氮原子，以进一步避免导 电层301对覆盖层3031的影响，以防止导电层301的电阻变大。示例的，富金属氮化物指的是金属原子和氮原子的摩尔比大于1，例如为2，3，4，5，6，7等；富金属硅化物指的是金属原子和硅原子的摩尔比大于1，例如为2，3，4，5，6，7等。
继续参照图5，本实施例还提供一种半导体结构，可以通过上述任一实施例提供的半导体结构的制备方法制得，使得半导体结构的位线结构包括依次层叠设置的导电层301、过渡层302和覆盖层3031，过渡层302的宽度小于导电层301的宽度；并且在导电层301的顶面以及过渡层302的侧面形成气隙305。过渡层302以及气隙305可以减少覆盖层3031对导电层301的影响以避免导电层301的电阻增大，提高了半导体结构的性能。
本实施例提供的半导体结构包括基底以及间隔分部在基底上的若干位线结构，位线结构包括依次叠设的导电层301、过渡层302和覆盖层3031，过渡层302的宽度小于导电层301的宽度。
示例性的，基底的材质可以包括硅、锗、硅锗等，本实施例对基底的材质不做限制。在基底上可以形成有间隔设置的浅沟槽隔离结构10和有源区结构20，以便于形成晶体管结构。
导电层301、过渡层302和覆盖层3031层叠的设置，过渡层302位于覆盖层3031和导电层301之间，并且导电层301靠近基底设置。导电层301可以包括沿远离基底的方向依次层叠形成的第一导电层3011、导电接触层3012以及第二导电层3013，其中，导电接触层3012位于第一导电层3011和第二导电层3013之间，导电接触层3012可以阻止构成第一导电层3011和第二导电层3013的材质发生渗透。示例性的，第一导电层3011的材质可以包括多晶硅，第二导电层3013的材质可以包括钨，导电接触层3012的材质可以包括氮化钛。
本实施例中，若干位线结构间隔分部，示例性的，若干位线结构沿平行于基底的方向延伸成线状，若干位线结构可以位于同一平行于基底的平面内，并且若干位线结构平行且间隔的设置。当然，本实施例中的位线结构还可以呈其他的形式在基底上分布，本实施例对此不作限制。
继续参照图5，气隙305位于导电层301的顶面以及过渡层302的侧面。也就是说过渡层302的侧面和导电层301的顶面之间形成气隙305。
在一些实现方式中，包覆层303可以包括位于过渡层302上部的覆盖层3031，以及覆盖在覆盖层3031侧壁和导电层301侧壁的绝缘密封层3032；由于过渡层302的宽度小于导电层301的宽度，可以在过渡层302的两侧形成凹槽；在形成绝缘密封层之后，绝缘密封层3032覆盖在凹槽上以形成气隙305。
在一些实施中，覆盖层3031的宽度大于导电层301的宽度。
在一些实施中，气隙305凸出于导电层301的侧面，也就是说，气隙305由导电层301的侧面向外凸出，如此设置，可以增大气隙305与导电层301顶面的接触面积，以提高对导电层301顶面的保护效果；同时，提高气隙305的体积，可以进一步改善位线结构30和周边结构(如导电插塞40)之间的寄生电容。
继续参照图5，本实施例提供的半导体结构还包括位于位线结构之间的导电插塞 40，导电插塞40位于相邻的位线结构30之间，导电插塞40用于连接有源区结构20。在半导体结构为动态随机存储器的实现方式中，导电插塞40还用于连接电容存储结构。
示例的，导电插塞40包括沿垂直于基底方向依次层叠设置的第一导电部分401和第二导电部分402，也就是说，第二导电部分402位于第一导电部分401的上方，其中第一导电部分401与有源区结构20连接，第二导电部分402用于连接电容存储结构。示例性的，第一导电部分401的材质可以包括多晶硅等，第二导电部分402的材质可以包括钨等，为了阻止第一导电部分401和第二导电部分402的材质互相渗透，可以在第一导电部分401和第二导电部分402之间设置导电阻挡膜，导电阻挡膜的材质可以包括氮化钛等。
其中，第二导电部分402的底部,具有面向位线结构30的斜面4021，斜面4021的底部高于导电层301的顶部且低于过渡层302的顶部，以使得，过渡层302的顶部位于斜面4021的顶部和底部之间。
示例的，第二导电部分的底部还包括底面4024、第一直面4022和第二直面4023，底面4024与第一导电部分401的顶面直接接触，底面4024的两端分别与第一直面4022和第二直面4023连接；其中，第一直面4022还与斜面4021连接，通过设置第一直面4022和第二直面4023，可以进一步增大过渡层302和导电插塞40的第二导电部分402之间的距离，降低二者之间的寄生电容，同时减少短路缺陷，提高良率。
在上述实现方式中，过渡层302的顶角与斜面4021的垂直距离小于导电层301的顶角与斜面4021的垂直距离。其中过渡层302顶角为在垂直于基底且垂直与位线结构30延伸方向的截面中(如图5所示的截面中)，过渡层302顶端靠近斜面4021的第一顶点a；过渡层302顶角与斜面4021的垂直距离为第一顶点a到斜面4021之间的垂直距离d1。相应的，导电层301的顶角为在垂直于基底且垂直与位线结构30延伸方向的截面中(如图5所示的截面中)，导电层301顶端靠近斜面4021的第二顶点b；导电层301的顶角与斜面4021之间的距离为第二顶点b到斜面4021的垂直距离d2。
在其他示例中，过渡层302的顶角与斜面4021的垂直距离d1大于导电层301的顶角与斜面4021的垂直距离d2。如此设置，在过渡层302为导体时，既能减少位线结构30的电阻，又能进一步降低位线结构30和接触插塞40之间的寄生电容。
本实施例中，过渡层302的宽度为导电层301宽度的2/3-3/4，如此设置，可以在降低覆盖层3031对导电层301的影响，保证对覆盖层3031的支撑力，避免过渡层302的宽度过小导致的覆盖层3031塌陷。
本实施例提供的过渡层302的材质可以包括富金属氮化物(如氮化钨、氮化钼、氮化钛等)或者富金属硅化物(如硅化钛、硅化钨等)。如此设置富金属氮化物和富金属硅化物可以捕获覆盖层3031中迁移至导电层301中的氮原子，以进一步降低导电层301对覆盖层3031的影响，以避免导电层301的电阻变大。例如，覆盖层3031可以包括氮化硅等。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技 术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (15)

  1. 一种半导体结构的制备方法，包括：
    提供基底；
    在所述基底上形成间隔分布的若干位线结构，所述位线结构包括依次叠设的导电层、过渡层和覆盖层，所述过渡层的宽度小于所述导电层的宽度；
    在所述导电层的顶面以及所述过渡层的侧面形成气隙。
  2. 根据权利要求1所述的半导体结构的制备方法，其中，所述覆盖层的宽度大于所述导电层的宽度；所述气隙凸出于所述导电层的侧面。
  3. 根据权利要求1所述的半导体结构的制备方法，其中，还包括：
    在所述位线结构之间的所述基底上形成包括第一导电部分和第二导电部分的导电插塞，所述第二导电部分形成在所述第一导电部分的上方；
    其中，所述第二导电部分的底部具有面向所述位线结构的斜面。
  4. 根据权利要求3所述的半导体结构的制备方法，其中，
    所述第二导电部分的底部还包括底面、第一直面和第二直面，所述底面与所述第一导电部分的顶面直接接触，所述底面的两端分别与所述第一直面和所述第二直面连接；
    其中，所述第一直面还与所述斜面连接。
  5. 根据权利要求3所述的半导体结构的制备方法，其中，
    所述过渡层的顶角与所述斜面的垂直距离小于所述导电层的顶角与所述斜面的垂直距离。
  6. 根据权利要求5所述的半导体结构的制备方法，其中，所述斜面的底部高于所述导电层的顶部且低于所述过渡层的顶部。
  7. 一种半导体结构，包括：
    基底；
    间隔分布于所述基底上的若干位线结构，所述位线结构包括依次叠设的导电层、过渡层和覆盖层，所述过渡层的宽度小于所述导电层的宽度；
    气隙，所述气隙位于所述导电层的顶面以及所述过渡层的侧面。
  8. 根据权利要求7所述的半导体结构，其中，所述覆盖层的宽度大于所述导电层的宽度。
  9. 根据权利要求7所述的半导体结构，其中，所述气隙凸出于所述导电层的侧面。
  10. 根据权利要求7所述的半导体结构，其中，还包括：
    导电插塞，位于所述位线结构之间的所述基底上，所述导电插塞包括第一导电部分和位于所述第一导电部分上方的第二导电部分；
    其中，所述第二导电部分的底部具有面向所述位线结构的斜面。
  11. 根据权利要求10所述的半导体结构，其中，还包括：
    所述第二导电部分的底部还包括底面、第一直面和第二直面，所述底面与所述第一导电部分直接接触，所述底面的两端分别与所述第一直面和所述第二直面连接；
    其中，所述第一直面还与所述斜面连接。
  12. 根据权利要求10所述的半导体结构，其中，所述过渡层的顶角与所述斜面的 垂直距离小于所述导电层的顶角与所述斜面的垂直距离。
  13. 根据权利要求12所述的半导体结构，其中，所述斜面的底部高于所述导电层的顶部且低于所述过渡层的顶部。
  14. 根据权利要求12所述的半导体结构，其中，所述过渡层的宽度为所述导电层宽度的2/3-3/4。
  15. 根据权利要求7所述的半导体结构，其中，所述过渡层的材质包括富金属氮化物或富金属硅化物，所述覆盖层包括氮化硅。
PCT/CN2021/104158 2021-03-12 2021-07-02 半导体结构的制备方法及半导体结构 WO2022188311A1 (zh)

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US20140054537A1 (en) * 2012-08-24 2014-02-27 SK Hynix Inc. Resistive memory device capable of preventing disturbance and method for manufacturing the same
CN104103578A (zh) * 2013-04-08 2014-10-15 爱思开海力士有限公司 具有气隙的半导体器件及其制造方法
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