WO2023019481A1 - 半导体器件、其制备方法及半导体存储装置 - Google Patents

半导体器件、其制备方法及半导体存储装置 Download PDF

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Publication number
WO2023019481A1
WO2023019481A1 PCT/CN2021/113316 CN2021113316W WO2023019481A1 WO 2023019481 A1 WO2023019481 A1 WO 2023019481A1 CN 2021113316 W CN2021113316 W CN 2021113316W WO 2023019481 A1 WO2023019481 A1 WO 2023019481A1
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Prior art keywords
word line
line structure
trench
semiconductor substrate
structure part
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PCT/CN2021/113316
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English (en)
French (fr)
Inventor
梅晓波
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长鑫存储技术有限公司
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Priority to US17/647,632 priority Critical patent/US20230053178A1/en
Publication of WO2023019481A1 publication Critical patent/WO2023019481A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate

Definitions

  • the present disclosure relates to the field of semiconductor technology, in particular to a semiconductor device, a manufacturing method thereof, and a semiconductor storage device.
  • Dynamic Random Access Memory (Dynamic Random Access Memory, DRAM for short) is a semiconductor storage device commonly used in computers, consisting of many repeated semiconductor devices. Each semiconductor device usually includes a capacitor and a transistor; the gate of the transistor is connected to the word line structure, the drain is connected to the bit line, and the source is connected to the capacitor; the voltage signal on the word line structure can control the opening or closing of the transistor, and then through The bit line reads data information stored in the capacitor, or writes data information into the capacitor through the bit line for storage.
  • interference between word line structures affects the performance and reliability of semiconductor devices.
  • the first aspect of the embodiments of the present disclosure provides a semiconductor device, including:
  • a semiconductor substrate including: a shallow trench isolation region, and several active regions arranged at intervals defined by the shallow trench isolation region;
  • a plurality of word line trenches are formed in the semiconductor substrate, and the word line trenches are intersected with corresponding active regions; wherein, the word line trenches include a first word line trench and a second word line trench A word line trench; the orthographic projection of the first word line trench on the semiconductor substrate is located in the orthographic projection of the shallow trench isolation region located on the semiconductor substrate; the second word line trench is located in the orthographic projection of the semiconductor substrate the orthographic projection of the semiconductor substrate is within the orthographic projection of the active region on the semiconductor substrate;
  • a word line structure embedded in the word line trench wherein, the word line structure includes a first word line structure part and a second word line structure part connected to each other; the first word line structure part is formed in In the first word line trench, the second word line structure part is formed in the second word line trench;
  • the first word line structure part has an escape area, the top surface of the escape area is flush with the top surface of the second word line structure part, and an insulating substance is provided in the escape area.
  • the second aspect of the embodiments of the present disclosure provides a method for manufacturing a semiconductor device, including:
  • a shallow trench isolation region is formed in the semiconductor substrate, and several active regions arranged at intervals are defined by the shallow trench isolation region;
  • a plurality of word line trenches intersecting with corresponding active regions are formed in the semiconductor substrate; wherein, the word line trenches include a first word line trench and a second word line trench;
  • the orthographic projection of a word line trench on the semiconductor substrate is located within the orthographic projection of the shallow trench isolation region within the semiconductor substrate; the orthographic projection of the second word line trench on the semiconductor substrate located within an orthographic projection of the active region on the semiconductor substrate;
  • An embedded word line structure is formed in the word line trench; wherein, the word line structure includes a first word line structure part and a second word line structure part electrically connected to each other; the first word line structure part Formed in the first word line trench, the second word line structure part is formed in the second word line trench; the first word line structure part has an escape area, and the top of the escape area The surface is flush with the top surface of the second word line structure part, and an insulating substance is provided in the avoidance area.
  • a third aspect of the embodiments of the present disclosure provides a semiconductor storage device, including the above-mentioned semiconductor device.
  • FIG. 1 is a schematic top view of a semiconductor substrate in an embodiment of the disclosure
  • Fig. 2A is some cross-sectional structural schematic diagrams of the semiconductor substrate shown in Fig. 1 along the direction AA';
  • Fig. 2B is some cross-sectional structural schematic diagrams of the semiconductor substrate shown in Fig. 1 along the BB' direction;
  • FIG. 3A is a schematic diagram of some cross-sectional structures during the preparation process of a semiconductor device provided by an embodiment of the present disclosure
  • 3B is another schematic cross-sectional structure diagram during the preparation process of the semiconductor device provided by the embodiment of the present disclosure.
  • FIG. 3C is another schematic cross-sectional structure diagram during the manufacturing process of the semiconductor device provided by the embodiment of the present disclosure.
  • FIG. 3D is another schematic cross-sectional structure diagram during the manufacturing process of the semiconductor device provided by the embodiment of the present disclosure.
  • FIG. 3E is another schematic cross-sectional structure diagram during the manufacturing process of the semiconductor device provided by the embodiment of the present disclosure.
  • FIG. 3F is another schematic cross-sectional structure diagram during the manufacturing process of the semiconductor device provided by the embodiment of the present disclosure.
  • FIG. 3G is another schematic cross-sectional structure diagram during the manufacturing process of the semiconductor device provided by the embodiment of the present disclosure.
  • FIG. 3H is another schematic cross-sectional structure diagram during the manufacturing process of the semiconductor device provided by the embodiment of the present disclosure.
  • FIG. 3I is another schematic cross-sectional structure diagram during the preparation process of the semiconductor device provided by the embodiment of the present disclosure.
  • FIG. 3J is another schematic cross-sectional structure diagram during the manufacturing process of the semiconductor device provided by the embodiment of the present disclosure.
  • Fig. 4A is another cross-sectional structural schematic diagram of the semiconductor substrate shown in Fig. 1 along the direction AA';
  • Fig. 4B is another cross-sectional structural schematic view of the semiconductor substrate shown in Fig. 1 along the BB' direction;
  • Fig. 5 is another schematic cross-sectional structural diagrams of the semiconductor substrate shown in Fig. 1 along the direction AA';
  • Fig. 6 is another schematic cross-sectional structure diagram of the semiconductor substrate shown in Fig. 1 along the direction AA'.
  • FIG. 1 is a schematic top view structure diagram of a semiconductor device provided by an embodiment of the present disclosure.
  • Fig. 2A is a schematic cross-sectional structure diagram of the semiconductor device shown in Fig. 1 along the direction AA'.
  • Fig. 2B is a schematic cross-sectional structure diagram of the semiconductor device shown in Fig. 1 along the direction of BB'.
  • a semiconductor device provided by an embodiment of the present disclosure may include: a semiconductor substrate 10 .
  • the material of the semiconductor substrate 10 may include silicon, germanium or silicon-on-insulator (SOI) semiconductor, or germanium-silicon compound, silicon carbide or other known materials, such as group III and V compounds such as gallium arsenide. Certain dopant ions can also be implanted into the semiconductor substrate 10 according to design requirements to change electrical parameters.
  • the semiconductor substrate 10 may be a silicon substrate.
  • the semiconductor substrate 10 may have an array region and a peripheral region.
  • the array region may have memory cells, word line structures, and bit lines, and the memory cells may have transistors and columnar capacitors.
  • the peripheral area may have some control circuits, protection circuits (such as fuse devices), and the like.
  • the array region of the semiconductor substrate 10 may include: a shallow trench isolation region 300 (STI, Shallow Trench Isolation), and several trench isolation regions defined by the shallow trench isolation region 300 Active regions 100 arranged at intervals.
  • the shallow trench isolation region 300 may include a shallow trench and an insulating material filled in the shallow trench, which is used to isolate the shallow trench from leakage and reduce electrical coupling (Coupling).
  • the insulating material filled in the shallow trenches may be silicon oxide, silicon nitride and other materials.
  • the depth of the shallow trench can be set according to the needs of practical applications, so as to control the degree of transistor isolation.
  • the array region of the semiconductor substrate 10 may include: a plurality of word line structures 200 formed in the semiconductor substrate 10 and embedded in the word line trenches. .
  • the word line trench and the active area 100 of the corresponding word line trench are arranged intersecting, that is to say, the word line structure is also arranged intersecting with the corresponding active area 100 .
  • the word line trenches include a first word line trench 400A and a second word line trench 400B; the orthographic projection of the first word line trench 400A on the semiconductor substrate 10 is located in the shallow trench isolation region 300 and located in the semiconductor substrate 10 The orthographic projection of the second word line trench 400B on the semiconductor substrate 10 is located within the orthographic projection of the active region 100 on the semiconductor substrate 10 .
  • the word line structure 200 includes a first word line structure portion 200A and a second word line structure portion 200B electrically connected to each other; the first word line structure portion 200A is formed in the first word line trench 400A, and the second word line structure portion The portion 200B is formed in the second word line trench 400B.
  • the second word line structure part 200B directly in contact with the active region 100 can be used as the gate of the corresponding transistor in the memory cell, and during or after forming the word line structure, it can be In the active region 100, a source/drain region, such as the source/drain region 151 between the two word line structures, is used as the source of the corresponding transistor; and in another source/drain region, such as the word line structure and the shallow trench
  • the source/drain regions 152 and 153 between the channel isolation regions 300 can serve as the drains of the corresponding transistors.
  • the first word line structure part 200A has a avoidance region BR, and the top surface of the avoidance region BR is flush with the top surface of the second word line structure part 200B (that is, the avoidance region BR The top surface of the top surface of the second word line structure part 200B is flush with the plane S0), and there is an insulating material in the avoidance region BR.
  • the first word line structure part 200A and the second word line structure part 200B can realize the current flow, by setting the avoidance region BR in the first word line structure part 200A, the charge can be roughly concentrated on the first word line structure part 200A.
  • the charge in the non-avoiding region BRNBR of the word line structure part 200A and the avoiding region BR of the first word line structure part 200A is reduced, so that the charge in the avoiding region BR of the first word line structure part 200A is in contact with the second region of the adjacent word line structure.
  • the coupling electric field between the word line structure parts 200B is reduced, thereby reducing the interference between the word line structures, and improving the performance and reliability of the semiconductor device.
  • the depth of the first word line trench 400A is greater than the depth of the second word line trench 400B.
  • the top surface of the first word line trench 400A is flush with the top surface of the second word line trench 400B, that is, the top surface of the first word line trench 400A is aligned with the top surface of the second word line trench 400B. flush with plane S0.
  • the plane S0 may be the plane where the top surface of the active region 100 of the semiconductor substrate 10 is located.
  • the specific values of the depth of the first word line trench 400A and the depth of the second word line trench 400B can be designed according to the requirements of practical applications, which are not limited here.
  • the boundary of the first word line trench 400A coincides with the boundary of the second word line trench 400B.
  • the boundary of the first word line structure part 200A coincides with the boundary of the first word line structure part 200A.
  • the second word line structure part 200B is a solid structure. Also, in a direction perpendicular to the extending direction of the word line structure, the cross section of the first word line structure part 200A has a recessed area AC0. That is, the first word line structure portion 200A is grooved in a direction perpendicular to the semiconductor substrate 10 to form grooves in the first word line structure portion 200A.
  • the recessed area ACO may be the avoidance area BR.
  • digging grooves in the first word line structure part 200A can make the charge mainly concentrate on the bottom of the groove, and make the charge on the side walls of the groove less, so that the side walls of the groove of the first word line structure part 200A
  • the coupling electric field between the second word line structure part 200B and the adjacent word line structure is reduced, thereby reducing the interference between the word line structures, and improving the performance and reliability of the semiconductor device.
  • the top surface of the recessed region AC0 is flush with the top surface of the second word line structure part 200B, that is, the recessed region AC0
  • the top surface of the second word line structure portion 200B is flush with the plane S1.
  • the plane S1 is lower than the plane S0, or between the plane S1 and the bottom surface of the semiconductor substrate 10 (that is, the side of the semiconductor substrate 10 away from the side where the word line groove is provided)
  • the distance between them is smaller than the distance between the plane S0 and the bottom surface of the semiconductor substrate 10 (that is, the side of the semiconductor substrate 10 facing away from the side where the word line trenches are provided).
  • the bottom surface AXS1 of the recessed region AC0 is higher than the bottom surface ZS2 of the second word line structure part 200B, and the first word line structure
  • the bottom surface ZS1 of the portion 200A is lower than the bottom surface ZS2 of the second word line structure portion 200B.
  • the distance between the bottom surface AXS1 of the recessed region AC0 and the bottom surface of the semiconductor substrate 10 is greater than the distance between the bottom surface ZS2 of the second word line structure portion 200B and the bottom surface of the semiconductor substrate 10, and the first word line structure portion 200A
  • the distance between the bottom surface ZS1 of the second word line structure part 200B and the bottom surface of the semiconductor substrate 10 is smaller than the distance between the bottom surface ZS2 of the second word line structure part 200B and the bottom surface of the semiconductor substrate 10 .
  • the first word line structure part 200A and the second word line structure part 200B in the same word line structure can be better electrically connected for signal transmission.
  • the charge concentration point is located at the bottom of the groove of the first word line structure part 200A, and the opposite between the bottom of the groove of the first word line structure part 200A and the second word line structure part 200B of the adjacent word line structure.
  • the area is reduced as much as possible, so that the coupling electric field between the bottom of the groove of the first word line structure part 200A and the second word line structure part 200B of the adjacent word line structure can be reduced as much as possible, and the gap between the word line structures can be further reduced. The interference between them improves the performance and reliability of semiconductor devices.
  • the word line structure may include: a gate oxide layer 230 and a word line; wherein, the gate oxide layer 230 covers the sidewall of the word line trench; and the gate oxide layer Layer 230 is between the wordlines and the wordline trenches. And, exemplarily, the gate oxide layer 230 in contact with the second word line structure part 200B is in direct contact with the semiconductor substrate 10 . There is a shallow trench isolation layer 300 between the gate oxide layer 230 in contact with the first word line structure portion 200A and the semiconductor substrate 10 .
  • the recessed region AC0 may be located within the word line in the first word line structure portion 200A.
  • the word line includes a first conductive film layer 210 and a second conductive film layer 220; wherein, the first conductive film layer 210 is disposed on the sidewall of the word line trench, and the first conductive film layer 210 is located on the second conductive film layer 220. Between the film layer 220 and the gate oxide layer 230 .
  • the recessed area AC0 may be located in the second conductive film layer 220 in the first word line structure portion 200A.
  • the second conductive film layer 220 in the first word line structure part 200A may be vapor-phase etched to form a recessed region AC0 in the second conductive film layer 220 in the first word line structure part 200A. , as the avoidance area BR.
  • the insulating substance in the avoidance region BR may be air.
  • an air gap (Air Gap) process may be used to form an air gap in the first word line structure part 200A.
  • FIG. 3A to FIG. 3J are schematic cross-sectional structure diagrams during the manufacturing process of the semiconductor device provided by the embodiments of the present disclosure.
  • the material of the semiconductor substrate 10 may include silicon, germanium or silicon-on-insulator (SOI) semiconductor, or germanium-silicon compound, silicon carbide or other known materials, such as group III and V compounds such as gallium arsenide. Certain dopant ions can also be implanted into the semiconductor substrate 10 according to design requirements to change electrical parameters.
  • the semiconductor substrate 10 may be a silicon substrate.
  • step S20 may specifically include: first forming an STI mask on the semiconductor substrate 10 , and the area of the semiconductor substrate 10 covered by the STI mask is the active region 100 .
  • the STI mask is used as the etching mask, and the gas phase etching process is adopted.
  • the etching gas can be one or more of SF 6 , CF 4 , Cl 2 , CHF 3 , O 2 and Ar to achieve a certain etching.
  • the etching selectivity ratio is used to etch the exposed semiconductor substrate 10 to form shallow trench isolation trenches, so that the region of the semiconductor substrate 10 where the active region 100 will be formed is reserved.
  • the STI mask is removed to form a semiconductor substrate 10 with shallow trench isolation trenches ST0 as shown in FIG. 3A .
  • SiN is filled in the shallow trench isolation trench ST0 as the shallow trench isolation layer 300, thereby forming the shallow trench isolation region 300, and several intervals are defined in the semiconductor substrate 10 by the shallow trench isolation region 300.
  • the active area 100 is arranged.
  • step S30 may specifically be:
  • a first word line trench 400A may be formed in the shallow trench isolation region 300 by using a photolithography process and an etching process.
  • a photolithography process is used to form a mask of the first word line trench 400A, and the mask of the first word line trench 400A exposes a region in the shallow trench isolation region 300 where the first word line trench 400A will be formed.
  • the etching gas can be one or more of SF 6 , CF 4 , Cl 2 , CHF 3 , O 2 and Ar , to achieve a certain etching selectivity, etch the exposed SiN in the shallow trench isolation region 300 to form the first word line trench 400A in the SiN in the shallow trench isolation region 300 .
  • the mask of the first word line trench 400A is removed by vapor phase etching, thereby forming the structure of the semiconductor device shown in FIG. 3C , that is, the first word line trench 400A is formed in SiN in the shallow trench isolation region 300 .
  • a second word line trench 400B may be formed in the active region 100 by using a photolithography process and an etching process.
  • a photolithography process is used to form a mask for the second word line trench 400B, and the mask for the second word line trench 400B exposes a region in the active region 100 of the semiconductor substrate 10 where the second word line trench 400B will be formed.
  • the etching gas can be one or more of SF 6 , CF 4 , Cl 2 , CHF 3 , O 2 and Ar , to achieve a certain etching selectivity
  • the exposed active region 100 is etched to form the second word line trench 400B in the active region 100 .
  • the mask of the second word line trench 400B is removed by vapor phase etching, so as to form the structure of the semiconductor device shown in FIG. 3D , that is, the second word line trench 400B is formed in the active region 100 .
  • the first word line trenches 400A and the second word line trenches 400B in the same word line trench are arranged alternately.
  • step S40 may specifically be:
  • the gate oxide layer 230 may cover the sidewalls of the word line trenches.
  • a gate oxide layer 230 is formed on sidewalls of the word line trenches.
  • the material of the gate oxide layer 230 may include one or more of silicon oxide, silicon nitride, oxynitride, silicon nitride, oxide/nitride/oxide (ONO).
  • the gate oxide layer 230 may be formed by a wet or dry thermal oxidation process such as in an environment including oxide, water vapor, nitrogen monoxide, or combinations thereof, or by In situ steam generation (ISSG) process in the ambient environment, or by chemical vapor deposition (CVD) using tetraethyl orthosilicate (TEOS) and oxygen as precursors.
  • a wet or dry thermal oxidation process such as in an environment including oxide, water vapor, nitrogen monoxide, or combinations thereof, or by In situ steam generation (ISSG) process in the ambient environment, or by chemical vapor deposition (CVD) using tetraethyl orthosilicate (TEOS) and oxygen as precursors.
  • ISSG In situ steam generation
  • CVD chemical vapor deposition
  • TEOS tetraethyl orthosilicate
  • a conductive material may be filled in the word line trench formed with the gate oxide layer 230 to form an initial word line structure.
  • the material of the word line structure may include one or more of Ti, TiN, Ta, TaN, W, WN, TiSiN and WSiN.
  • the word line structure may adopt a single-layer structure. For example, one of Ti, TiN, Ta, TaN, W, WN, TiSiN, and WSiN is used.
  • the word line structure may also adopt a stacked structure. For example, referring to FIG.
  • a layer of TiN layer 210 is deposited on the sidewall of the word line trench with gate oxide layer 230 as the first conductive film layer 210 in the word line structure. .
  • a layer of W layer 220 is deposited in the word line trench with the TiN layer 210 as the second conductive film layer 220 in the word line structure.
  • the first conductive film layer 210 is located between the second conductive film layer 220 and the gate oxide layer 230 . In this way, the TiN layer 210 and the W layer 220 can be integrated to form an initial word line structure.
  • the initial word line structure is etched so that the top surface of the initial word line structure is lower than the top surface of the semiconductor substrate 10, so as to form the second word line structure part 200B and the first word line structure part 200B located in the first word line trench 400A.
  • An initial word line structure section Exemplarily, referring to FIG. 3H , a vapor phase etching process can be used, and the etching gas can be one or more of SF 6 , CF 4 , Cl 2 , CHF 3 , O 2 and Ar to achieve a certain etching selection.
  • the initial word line structure is etched so that the top surface S01 of the initial word line structure is lower than the top surface S02 of the semiconductor substrate 10 , so that the word line structure embedded in the semiconductor substrate 10 can be formed.
  • the first initial word line structure portion is etched to form a relief region BR to form the first word line structure portion 200A.
  • a photolithography process and an etching process may be used to etch the first initial word line structure part, so that the first initial word line structure part forms the escape region BR, so as to form the first word line structure part 200A.
  • a avoidance mask BRM is formed by a photolithography process, and the avoidance mask BRM exposes the part of the first initial word line structure part where the avoidance region BR is to be formed.
  • FIG. 3I a photolithography process and the avoidance mask BRM exposes the part of the first initial word line structure part where the avoidance region BR is to be formed.
  • a vapor phase etching process is adopted, and the etching gas can be one or more of SF 6 , CF 4 , Cl 2 , CHF 3 , O 2 and Ar.
  • vapor phase etching is performed on the W layer in the exposed first initial word line structure, so as to form a recessed area AC0 in the W layer of the first initial word line structure, as Avoid area BR.
  • an insulating barrier layer covering the entire semiconductor device may be formed, and the avoidance region BR is filled with an insulating substance.
  • an air gap forming process may be used to form an air gap in the avoidance region BR of the first word line structure part 200A while forming an insulating barrier layer covering the entire semiconductor device.
  • the material of the insulating barrier layer may include one or more of silicon oxide, silicon nitride, oxynitride, silicon nitride, oxide/nitride/oxide (ONO).
  • an air gap forming process may be used to form a SiN layer covering the entire semiconductor device as an insulating barrier layer, and simultaneously form an air gap in the avoidance region BR of the first word line structure portion 200A.
  • the above-mentioned flushness may not be completely flush, and there may be some deviations, so the above-mentioned flushing relationship only needs to be approximately It only needs to meet the above conditions, and all belong to the protection scope of the present disclosure.
  • the above-mentioned flushing may be the flushing allowed within the error tolerance range.
  • Embodiments of the present disclosure provide structural schematic diagrams of other semiconductor devices, as shown in FIG. 4A and FIG. 4B , which are modified for the implementation manners in the foregoing embodiments. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities will not be repeated here.
  • FIG. 4A is another schematic cross-sectional structure diagram of the semiconductor substrate shown in FIG. 1 along the AA' direction
  • FIG. 4B is another schematic diagram of the semiconductor substrate shown in FIG. 1 along the BB' direction Schematic diagram of the cross-sectional structure.
  • the first initial word line structure part is etched to form the first initial word line structure part into the avoidance region BR, so as to form the first word line structure part 200A.
  • the word line structure adopts, for example, a stacked structure of TiN layer 210 and W layer 220
  • the first word line trench After the W layer is formed in the word line trench with the TiN layer, the first word line trench
  • the W layer in the groove 400A is subjected to vapor phase etching, and a certain distance (can be designed and determined according to the actual application) of the W layer is removed, so that the W layer in the first word line trench 400A is a solid structure, so that the remaining W layer and the TiN layer form a recessed area ACO.
  • the W layer in the first word line trench 400A and the TiN layer below the W layer serve as the bottom of the recessed region AC0
  • the TiN layer on the sidewall of the word line trench serves as the sidewall of the recessed region AC0 .
  • the second conductive film layer 220 (such as the W layer) in the first word line structure portion 200A is a solid structure.
  • the top surface AXS2 of the second conductive film layer 220 (such as the W layer) is lower than the top surface AXS3 of the first conductive film layer 210 (such as the TiN layer), and the second conductive film layer 220 (such as W layer) serves as the bottom of the recessed region AC0, and the first conductive film layer 210 (such as TiN layer) disposed on the sidewall of the word line trench serves as the sidewall of the recessed region ACO.
  • Embodiments of the present disclosure provide structural schematic diagrams of other semiconductor devices, as shown in FIG. 5 , which is modified for the implementation manners in the foregoing embodiments. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities will not be repeated here.
  • FIG. 5 is a schematic diagram of some cross-sectional structures of the semiconductor substrate shown in FIG. 1 along the direction AA'.
  • the first initial word line structure part is etched to form the first initial word line structure part into the avoidance region BR, so as to form the first word line structure part 200A.
  • the word line structure adopts, for example, a stacked structure of TiN layer 210 and W layer 220
  • the first word line trench Both the W layer and the TiN layer in the groove 400A are subjected to vapor phase etching, and a certain distance (can be designed and determined according to the actual application) of the W layer and the TiN layer is removed, so that the W layer and the TiN layer in the first word line trench 400A A solid structure is formed as a whole, so that the remaining W layer, the TiN layer and the gate oxide layer 230 can form a recessed region ACO.
  • the W layer in the first word line trench 400A and the TiN layer below the W layer can serve as the bottom of the recessed region AC0, and the gate oxide layer 230 on the sidewall of the word line trench serves as the sidewall of the recessed sidewall.
  • the remaining steps of the manufacturing method of the semiconductor device in this embodiment are basically the same as the remaining steps of the above-mentioned manufacturing method, and will not be repeated here.
  • the top surface AXS2 of the W layer 220 in the first word line structure part 200A may be higher than the bottom surface of the TiN layer in the second word line structure part 200B, and the first The bottom surface of the TiN layer in the word line structure part 200A may be lower than the bottom surface of the TiN layer in the second word line structure part 200B.
  • the word lines in the first word line structure part 200A are solid structures. Moreover, in the first word line structure part 200A, the top surface AXS4 of the word line is lower than the top surface AXS5 of the gate oxide layer 230 (for example, it may be the S0 plane). And, in the first word line structure portion 200A, the word line serves as the bottom of the recessed region AC0 , and the gate oxide layer 230 disposed on the sidewall of the word line trench serves as the sidewall of the recessed region AC0 .
  • Embodiments of the present disclosure provide structural schematic diagrams of other semiconductor devices, as shown in FIG. 6 , which is modified for the implementation manners in the foregoing embodiments. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities will not be repeated here.
  • the insulating material in the avoidance region BR may also be an inorganic insulating material.
  • the inorganic insulating material may include one or more of silicon oxide, silicon nitride, oxynitride, silicon nitride, oxide/nitride/oxide (ONO).
  • FIG. 6 is a schematic diagram of some cross-sectional structures of the semiconductor substrate shown in FIG. 1 along the direction AA'.
  • a SiN layer is deposited on the entire semiconductor device as an insulating barrier layer, and at the same time, a filling layer is deposited in the avoidance region BR of the first word line structure part 200A. SiN layer.
  • the remaining steps of the manufacturing method of the semiconductor device in this embodiment are basically the same as the remaining steps of the above-mentioned manufacturing method, and will not be repeated here.
  • Embodiments of the present disclosure also provide some semiconductor storage devices.
  • the semiconductor storage device may include the above-mentioned semiconductor device provided by the embodiments of the present disclosure.
  • the problem-solving principle of the semiconductor storage device is similar to that of the semiconductor device described above, so the implementation of the semiconductor storage device can refer to the implementation of the semiconductor device described above, and repeated descriptions will not be repeated here.
  • the semiconductor device is, for example, a DRAM.
  • a semiconductor memory device may include a semiconductor device.
  • the semiconductor storage device may be a product or component having a storage function. The other essential components of the semiconductor storage device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as limitations on the present disclosure.

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Abstract

本公开实施例公开了半导体器件、其制备方法及半导体存储装置，包括：半导体衬底，多个字线沟槽，字线结构；字线沟槽包括第一字线沟槽和第二字线沟槽；第一字线沟槽在半导体衬底的正投影位于浅沟道隔离区位于半导体衬底的正投影内；第二字线沟槽在半导体衬底的正投影位于有源区在半导体衬底的正投影内；字线结构包括相互连接的第一字线结构部和第二字线结构部；第一字线结构部形成于第一字线沟槽中，第二字线结构部形成于第二字线沟槽中；其中，一字线结构部具有避让区域，避让区域的顶面与第二字线结构部的顶面齐平，并且避让区域中具有绝缘物质。

Description

半导体器件、其制备方法及半导体存储装置
相关申请的交叉引用
本申请要求在2021年08月16日提交中国专利局、申请号为202110934967.7、申请名称为“半导体器件、其制备方法及半导体存储装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及半导体技术领域，特别涉及半导体器件、其制备方法及半导体存储装置。
背景技术
动态随机存储器(Dynamic Random Access Memory，简称：DRAM)是计算机中常用的半导体存储器件，由许多重复的半导体器件组成。每一个半导体器件通常包括电容器和晶体管；晶体管的栅极与字线结构相连、漏极与位线相连、源极与电容器相连；字线结构上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。然而，字线结构之间的干扰，影响半导体器件的性能和可靠性。
发明内容
根据一些实施例，本公开实施例第一方面提供了半导体器件，包括：
半导体衬底，包括：浅沟道隔离区，以及由所述浅沟道隔离区界定出的若干个间隔排布的有源区；
多个字线沟槽，形成于所述半导体衬底中，并且所述字线沟槽与相应的有源区相交设置；其中，所述字线沟槽包括第一字线沟槽和第二字线沟槽；所述第一字线沟槽在所述半导体衬底的正投影位于所述浅沟道隔离区位于所 述半导体衬底的正投影内；所述第二字线沟槽在所述半导体衬底的正投影位于所述有源区在所述半导体衬底的正投影内；
字线结构，埋置于所述字线沟槽中；其中，所述字线结构包括相互连接的第一字线结构部和第二字线结构部；所述第一字线结构部形成于所述第一字线沟槽中，所述第二字线结构部形成于所述第二字线沟槽中；
其中，所述第一字线结构部具有避让区域，所述避让区域的顶面与所述第二字线结构部的顶面齐平，并且所述避让区域中具有绝缘物质。
根据一些实施例，本公开实施例第二方面提供了半导体器件的制备方法，包括：
提供半导体衬底；
在所述半导体衬底中形成浅沟道隔离区，以及由所述浅沟道隔离区界定出若干个间隔排布的有源区；
在所述半导体衬底中形成与相应的有源区相交设置的多个字线沟槽；其中，所述字线沟槽包括第一字线沟槽和第二字线沟槽；所述第一字线沟槽在所述半导体衬底的正投影位于所述浅沟道隔离区位于所述半导体衬底的正投影内；所述第二字线沟槽在所述半导体衬底的正投影位于所述有源区在所述半导体衬底的正投影内；
在所述字线沟槽中形成埋置的字线结构；其中，所述字线结构包括相互电连接的第一字线结构部和第二字线结构部；所述第一字线结构部形成于所述第一字线沟槽中，所述第二字线结构部形成于所述第二字线沟槽中；所述第一字线结构部具有避让区域，所述避让区域的顶面与所述第二字线结构部的顶面齐平，并且所述避让区域中具有绝缘物质。
根据一些实施例，本公开实施例第三方面提供了半导体存储装置，包括上述半导体器件。
附图说明
图1为本公开实施例中半导体衬底的俯视结构示意图；
图2A为图1所示的半导体衬底沿AA’方向上的一些剖视结构示意图；
图2B为图1所示的半导体衬底沿BB’方向上的一些剖视结构示意图；
图3A为本公开实施例提供的半导体器件的制备过程中的一些剖视结构示意图；
图3B为本公开实施例提供的半导体器件的制备过程中的另一些剖视结构示意图；
图3C为本公开实施例提供的半导体器件的制备过程中的又一些剖视结构示意图；
图3D为本公开实施例提供的半导体器件的制备过程中的又一些剖视结构示意图；
图3E为本公开实施例提供的半导体器件的制备过程中的又一些剖视结构示意图；
图3F为本公开实施例提供的半导体器件的制备过程中的又一些剖视结构示意图；
图3G为本公开实施例提供的半导体器件的制备过程中的又一些剖视结构示意图；
图3H为本公开实施例提供的半导体器件的制备过程中的又一些剖视结构示意图；
图3I为本公开实施例提供的半导体器件的制备过程中的又一些剖视结构示意图；
图3J为本公开实施例提供的半导体器件的制备过程中的又一些剖视结构示意图；
图4A为图1所示的半导体衬底沿AA’方向上的另一些剖视结构示意图；
图4B为图1所示的半导体衬底沿BB’方向上的另一些剖视结构示意图；
图5为图1所示的半导体衬底沿AA’方向上的又一些剖视结构示意图；
图6为图1所示的半导体衬底沿AA’方向上的又一些剖视结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
参见图1-图2B，图1为本公开实施例提供的半导体器件的俯视结构示意图。图2A为图1所示的半导体器件沿AA’方向上的剖视结构示意图。图2B为图1所示的半导体器件沿BB’方向上的剖视结构示意图。本公开实施例提供的半导体器件可以包括：半导体衬底10。示例性地，半导体衬底10的材质可以包括硅、锗或绝缘体上硅(SOI)的半导体，或者包括锗硅化合物、碳化硅或者其他已知材料，例如砷化镓等Ⅲ、Ⅴ族化合物。在半导体衬底10中还可以根据设计需求注入一定的掺杂离子以改变电学参数。示例性地，半导体衬底10可以为硅衬底。
在本公开实施例中，半导体衬底10可以具有阵列(Array)区与外围区。其中，阵列区可以具有存储单元、字线结构、位线，存储单元具有晶体管和 柱状电容器。并且，外围区可以具有一些控制电路、保护电路(例如熔断(fuse)器件)等。
在本公开实施例中，参考图1-图2B，半导体衬底10的阵列区中可以包括：浅沟道隔离区300(STI，Shallow Trench Isolation)，由浅沟道隔离区300界定出的若干个间隔排布的有源区100。本实施例中，浅沟道隔离区300可以包括浅沟槽以及填充于浅沟槽内的绝缘材料，其作用为隔离浅沟槽漏电以及减轻电耦合(Coupling)。并且，填充于浅沟槽中的绝缘材料可以为氧化硅、氮化硅等材料。并且，浅沟槽深度可以根据实际应用的需要设定，以控制晶体管隔离程度。
在本公开实施例中，参考图1-图2B，半导体衬底10的阵列区中可以包括：形成于半导体衬底10中的多个，以及埋置于字线沟槽中的字线结构200。其中，字线沟槽与相应字线沟槽的有源区100相交设置，也就是说，字线结构与相应的有源区100也相交设置。并且，字线沟槽包括第一字线沟槽400A和第二字线沟槽400B；第一字线沟槽400A在半导体衬底10的正投影位于浅沟道隔离区300位于半导体衬底10的正投影内；第二字线沟槽400B在半导体衬底10的正投影位于有源区100在半导体衬底10的正投影内。以及，字线结构200包括相互电连接的第一字线结构部200A和第二字线结构部200B；第一字线结构部200A形成于第一字线沟槽400A中，第二字线结构部200B形成于第二字线沟槽400B中。
需要说明的是，可以将与有源区100直接接触的第二字线结构部200B作为存储单元中相应的晶体管的栅极，并且在形成字线结构的过程中或者形成字线结构之后，可以在有源区100中一个源/漏区，如两字线结构之间的源/漏区151，作为相应的晶体管的源极；并在另一源/漏区，如字线结构和浅沟道隔离区300之间的源/漏区152、153，可作为相应的晶体管的漏极。
在本公开实施例中，参考图1-图2B，第一字线结构部200A具有避让区域BR，避让区域BR的顶面与第二字线结构部200B的顶面齐平(即避让区域BR的顶面与第二字线结构部200B的顶面与平面S0齐平)，并且避让区域 BR中具有绝缘物质。这样在可以使第一字线结构部200A和第二字线结构部200B能够实现电流流通的情况下，通过在第一字线结构部200A中设置避让区域BR，可以使电荷大致集中于第一字线结构部200A的非避让区域BRNBR，第一字线结构部200A的避让区域BR处的电荷降低，从而使得第一字线结构部200A的避让区域BR处与相邻字线结构的第二字线结构部200B之间的耦合电场降低，进而降低字线结构之间的干扰，提高半导体器件的性能和可靠性。
在本公开实施例中，参考图1-图2B，在垂直于半导体衬底10所在平面的方向F0上，第一字线沟槽400A的深度大于第二字线沟槽400B的深度。示例性地，第一字线沟槽400A的顶面与第二字线沟槽400B的顶面齐平，即第一字线沟槽400A的顶面与第二字线沟槽400B的顶面与平面S0齐平。其中，平面S0可以为半导体衬底10的有源区100的顶面所在的平面。在实际应用中，可以根据实际应用的需求设计第一字线沟槽400A的深度和第二字线沟槽400B的深度的具体数值，在此不作限定。
在本公开实施例中，参考图1-图2B，在字线结构的延伸方向上，同一字线沟槽中，第一字线沟槽400A的边界与第二字线沟槽400B的边界重合。并且，在字线结构的延伸方向上，同一字线结构中，第一字线结构部200A的边界与第一字线结构部200A的边界重合。
在本公开实施例中，参考图1-图2B，第二字线结构部200B为实心结构。并且，在垂直于字线结构的延伸方向上，第一字线结构部200A的截面具有凹陷区域AC0。也就是说，在垂直于半导体衬底10的方向上，对第一字线结构部200A进行了挖凹槽，以在第一字线结构部200A中形成了凹槽。示例性地，凹陷区域AC0可以为避让区域BR。这样在第一字线结构部200A中挖凹槽，可以使电荷主要集中于凹槽底部，而使凹槽侧壁上的电荷较少，从而使得第一字线结构部200A的凹槽侧壁处与相邻字线结构的第二字线结构部200B之间的耦合电场降低，进而降低字线结构之间的干扰，提高半导体器件的性能和可靠性。
在本公开实施例中，参考图1-图2B，在垂直于半导体衬底10的方向F0上，凹陷区域AC0的顶面与第二字线结构部200B的顶面齐平，即凹陷区域AC0的顶面与第二字线结构部200B的顶面均与平面S1齐平。即，在垂直于半导体衬底10的方向F0上，平面S1低于平面S0，或者，平面S1与半导体衬底10的底面(即半导体衬底10背离设置字线沟槽一侧的一面)之间的距离小于平面S0与半导体衬底10的底面(即半导体衬底10背离设置字线沟槽一侧的一面)之间的距离。
在本公开实施例中，参考图1-图2B，在垂直于半导体衬底10的方向F0上，凹陷区域AC0的底面AXS1高于第二字线结构部200B的底面ZS2，第一字线结构部200A的底面ZS1低于第二字线结构部200B的底面ZS2。即，凹陷区域AC0的底面AXS1与半导体衬底10的底面之间的距离大于第二字线结构部200B的底面ZS2与半导体衬底10的底面之间的距离，且第一字线结构部200A的底面ZS1与半导体衬底10的底面之间的距离小于第二字线结构部200B的底面ZS2与半导体衬底10的底面之间的距离。这样可以使同一字线结构中的第一字线结构部200A和第二字线结构部200B可以更好的电连接，以进行信号传输。并且，由于电荷集中处位于第一字线结构部200A的凹槽底部，且第一字线结构部200A的凹槽底部与相邻字线结构的第二字线结构部200B之间的正对面积尽可能的降低，从而可以使第一字线结构部200A的凹槽底部与相邻字线结构的第二字线结构部200B之间的耦合电场尽可能的降低，进一步降低字线结构之间的干扰，提高半导体器件的性能和可靠性。
在本公开实施例中，参考图1-图2B，字线结构可以包括：栅极氧化层230与字线；其中，栅极氧化层230覆盖于字线沟槽的侧壁；且栅极氧化层230位于字线和字线沟槽之间。并且，示例性地，与第二字线结构部200B接触的栅极氧化层230与半导体衬底10直接接触。与第一字线结构部200A接触的栅极氧化层230与半导体衬底10之间具有浅沟道隔离层300。
在本公开实施例中，参考图1-图2B，可以使凹陷区域AC0位于第一字线结构部200A中的字线内。示例性地，字线包括第一导电膜层210和第二导电 膜层220；其中，第一导电膜层210设置于字线沟槽的侧壁，且第一导电膜层210位于第二导电膜层220与栅极氧化层230之间。示例性地，凹陷区域AC0可以位于第一字线结构部200A中的第二导电膜层220内。例如，在制备时，可以对第一字线结构部200A中的第二导电膜层220进行气相刻蚀，以在第一字线结构部200A中的第二导电膜层220中形成凹陷区域AC0，以作为避让区域BR。
在本公开实施例中，参考图1-图2B，避让区域BR中的绝缘物质可以为空气。示例性地，可以采用空气隙(Air Gap)工艺在第一字线结构部200A形成空气隙。
以图1至图2B所示的半导体器件为例，参见图3A至图3J，图3A至图3J分别为本公开实施例提供的半导体器件的制备过程中的剖视结构示意图。
本公开实施例提供的制备方法可以包括如下步骤：
S10、提供半导体衬底10。
示例性地，半导体衬底10的材质可以包括硅、锗或绝缘体上硅(SOI)的半导体，或者包括锗硅化合物、碳化硅或者其他已知材料，例如砷化镓等Ⅲ、Ⅴ族化合物。在半导体衬底10中还可以根据设计需求注入一定的掺杂离子以改变电学参数。示例性地，半导体衬底10可以为硅衬底。
S20、在半导体衬底10中形成浅沟道隔离区300，以及由浅沟道隔离区300界定出若干个间隔排布的有源区100。
示例性地，步骤S20，例如，具体可以为：先在半导体衬底10上形成STI掩膜，STI掩膜覆盖的半导体衬底10的区域为有源区100。之后以STI掩膜为刻蚀掩膜，采用气相刻蚀工艺，刻蚀气体可以为SF 6、CF 4、Cl 2、CHF 3、O 2以及Ar中的一种或多种，以达到一定刻蚀选择比，对暴露出的半导体衬底10进行刻蚀，形成浅沟道隔离槽，使将要形成有源区100的半导体衬底10的区域保留下来。之后，去除STI掩膜，形成图3A所示的具有浅沟道隔离槽ST0的半导体衬底10。
之后，参见图3B，在浅沟道隔离槽ST0中填充SiN作为浅沟道隔离层300， 从而形成浅沟道隔离区300，以及由浅沟道隔离区300在半导体衬底10界定出若干个间隔排布的有源区100。
S30、在半导体衬底10中形成与相应的有源区100相交设置的多个字线沟槽。
在本公开实施例中，步骤S30、例如，具体可以为：
首先，可以采用光刻工艺和刻蚀工艺在浅沟道隔离区300中形成第一字线沟槽400A。例如，采用光刻工艺形成第一字线沟槽400A掩膜，第一字线沟槽400A掩膜暴露出浅沟道隔离区300中将要形成第一字线沟槽400A的区域。以第一字线沟槽400A掩膜为刻蚀掩膜，采用气相刻蚀工艺，刻蚀气体可以为SF 6、CF 4、Cl 2、CHF 3、O 2以及Ar中的一种或多种，以达到一定刻蚀选择比，对暴露出的浅沟道隔离区300中的SiN进行刻蚀，以在浅沟道隔离区300中的SiN中形成第一字线沟槽400A。之后，采用气相刻蚀去除第一字线沟槽400A掩膜，从而形成图3C所示的半导体器件的结构，即在浅沟道隔离区300中的SiN中形成第一字线沟槽400A。
之后，可以采用光刻工艺和刻蚀工艺在有源区100中形成第二字线沟槽400B。例如，采用光刻工艺形成第二字线沟槽400B掩膜，第二字线沟槽400B掩膜暴露出半导体衬底10的有源区100中将要形成第二字线沟槽400B的区域。以第二字线沟槽400B掩膜为刻蚀掩膜，采用气相刻蚀工艺，刻蚀气体可以为SF 6、CF 4、Cl 2、CHF 3、O 2以及Ar中的一种或多种，以达到一定刻蚀选择比，对暴露出的有源区100进行刻蚀，以在有源区100中形成第二字线沟槽400B。之后，采用气相刻蚀去除第二字线沟槽400B掩膜，从而形成图3D所示的半导体器件的结构，即有源区100中形成第二字线沟槽400B。
需要说明的是，在沿字线结构的延伸方向上，同一字线沟槽中的第一字线沟槽400A和第二字线沟槽400B交替排列。
S40、在字线沟槽中形成埋置的字线结构。
在本公开实施例中，步骤S40、例如，具体可以为：
首先，可以在字线沟槽的侧壁上覆盖栅极氧化层230。示例性地，参见图 3E，栅极氧化层230形成于字线沟槽的侧壁上。例如，栅极氧化层230的材质可包括氧化硅、氮化硅、氮氧化物、硅氮化物、氧化物/氮化物/氧化物(ONO)中的一种或多种。栅极氧化层230可以通过诸如在包括氧化物、水蒸气、一氧化氮或它们的组合的环境中的湿或干热氧化工艺形成，或者通过在氧气、水蒸气、一氧化氮或它们的组合的环境中的原位蒸汽生成(ISSG)工艺生成，或者通过使用正硅酸乙酯(TEOS)和氧气作为前驱体的化学汽相沉积(CVD)技术形成。
之后，可以在形成有栅极氧化层230的字线沟槽内填充导电材料，形成初始字线结构。示例性地，字线结构的材质可以包括Ti、TiN、Ta、TaN、W、WN、TiSiN以及WSiN中的一种或多种。示例性地，字线结构可以采用单层结构。例如，采用Ti、TiN、Ta、TaN、W、WN、TiSiN以及WSiN中的一种形成。或者，字线结构也可以采用叠层结构。例如，参见图3F，以设定的沉积速率，在具有栅极氧化层230的字线沟槽内的侧壁上沉积一层TiN层210，以作为字线结构中的第一导电膜层210。之后，参见图3G，以设定的沉积速率，在具有TiN层210的字线沟槽内沉积一层W层220，以作为字线结构中的第二导电膜层220。其中，第一导电膜层210位于第二导电膜层220与栅极氧化层230之间。这样可以使TiN层210和W层220作为一个整体，形成初始字线结构。需要说明的是，上述沉积方式的选择上本领域技术人员可以从化学气相沉积、物理气相沉积、原子层沉积、高密度等离子化学气相沉积、金属有机化学气相沉积、等离子体增强化学气相沉积或其他适合的沉积工艺中选择，本公开并不以此为限。并且，沉积速率可以根据实际应用的需求进行设计确定，在此不作限定。
之后，对初始字线结构进行刻蚀，使初始字线结构的顶面低于半导体衬底10的顶面，以形成第二字线结构部200B和位于第一字线沟槽400A中的第一初始字线结构部。示例性地，参见图3H，可以采用气相刻蚀工艺，刻蚀气体可以为SF 6、CF 4、Cl 2、CHF 3、O 2以及Ar中的一种或多种，以达到一定刻蚀选择比，对初始字线结构进行刻蚀，以使初始字线结构的顶面S01低于半 导体衬底10的顶面S02，从而可以形成埋置于半导体衬底10中的字线结构。
之后，对第一初始字线结构部进行刻蚀，使第一初始字线结构部形成避让区域BR，以形成第一字线结构部200A。示例性地，可以采用光刻工艺和刻蚀工艺对第一初始字线结构部进行刻蚀，使第一初始字线结构部形成避让区域BR，以形成第一字线结构部200A。例如，参见图3I，采用光刻工艺形成避让掩膜BRM，避让掩膜BRM暴露出第一初始字线结构部中要形成避让区域BR的部分。之后，参见图3J，以避让掩膜BRM为刻蚀掩膜，采用气相刻蚀工艺，刻蚀气体可以为SF 6、CF 4、Cl 2、CHF 3、O 2以及Ar中的一种或多种，以达到一定刻蚀选择比，对暴露出的第一初始字线结构部中的W层进行气相刻蚀，以在第一初始字线结构部的W层中形成凹陷区域AC0，以作为避让区域BR。
在步骤S40之后，可以形成覆盖整个半导体器件的绝缘阻挡层，并使避让区域BR中填充有绝缘物质。示例性地，参见图2A，可以采用形成空气隙工艺，在形成覆盖整个半导体器件的绝缘阻挡层的同时，在第一字线结构部200A的避让区域BR形成空气隙。示例性地，绝缘阻挡层的材料可包括氧化硅、氮化硅、氮氧化物、硅氮化物、氧化物/氮化物/氧化物(ONO)中的一种或多种。例如，可以采用形成空气隙工艺，在形成覆盖整个半导体器件的SiN层，作为绝缘阻挡层，并且同时在第一字线结构部200A的避让区域BR形成空气隙。
需要说明的是，在实际制备工艺中，由于工艺条件的限制或其他因素，上述所说的齐平可能并不会完全齐平，可能会有一些偏差，因此上述所说的齐平关系只要大致满足上述条件即可，均属于本公开的保护范围。例如，上述所说的齐平可以是在误差允许范围之内所允许的齐平。
本公开实施例提供了另一些半导体器件的结构示意图，如图4A与图4B所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
参见图4A与图4B，图4A为图1所示的半导体衬底沿AA’方向上的另一 些剖视结构示意图；图4B为图1所示的半导体衬底沿BB’方向上的另一些剖视结构示意图。在本公开实施例中，在制备方法中，对第一初始字线结构部进行刻蚀，使第一初始字线结构部形成避让区域BR，以形成第一字线结构部200A。示例性地，可以为在字线结构采用例如，TiN层210和W层220的叠层结构时，可以在具有TiN层的字线沟槽内形成W层之后，对形成于第一字线沟槽400A中的W层进行气相刻蚀，去除一定距离(可以根据实际应用进行设计确定)的W层，以使第一字线沟槽400A中的W层为实心结构，从而可以使剩余的W层与TiN层形成凹陷区域AC0。其中，第一字线沟槽400A中的W层以及W层下面的TiN层作为凹陷区域AC0的底部，字线沟槽侧壁上的TiN层作为凹陷区域AC0的侧壁。需要说明的是，本实施例中半导体器件的制备方法的其余步骤与上述制备方法中的其余步骤基本相同，在此不作赘述。
在本公开实施例中，如图4A与图4B所示，第一字线结构部200A中的第二导电膜层220(例如W层)为实心结构。并且，第一字线结构部200A中，第二导电膜层220(例如W层)的顶面AXS2低于第一导电膜层210(例如TiN层)的顶面AXS3，以及第二导电膜层220(例如W层)作为凹陷区域AC0的底部，设置于字线沟槽的侧壁的第一导电膜层210(例如TiN层)作为凹陷区域AC0的侧壁。
本公开实施例提供了另一些半导体器件的结构示意图，如图5所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
参见图5，图5为图1所示的半导体衬底沿AA’方向上的又一些剖视结构示意图。在本公开实施例中，在制备方法中，对第一初始字线结构部进行刻蚀，使第一初始字线结构部形成避让区域BR，以形成第一字线结构部200A。示例性地，可以为在字线结构采用例如，TiN层210和W层220的叠层结构时，可以在具有TiN层的字线沟槽内形成W层之后，对形成于第一字线沟槽400A中的W层和TiN层均进行气相刻蚀，去除一定距离(可以根据实际应 用进行设计确定)的W层和TiN层，以使第一字线沟槽400A中的W层和TiN层作为一个整体形成实心结构，从而可以使剩余的W层与TiN层和栅极氧化层230形成凹陷区域AC0。其中，第一字线沟槽400A中的W层以及W层下面的TiN层可以作为凹陷区域AC0的底部，字线沟槽侧壁上的栅极氧化层230作为凹陷侧壁的侧壁。需要说明的是，本实施例中半导体器件的制备方法的其余步骤与上述制备方法中的其余步骤基本相同，在此不作赘述。
在本公开实施例中，如图5所示，第一字线结构部200A中的W层220的顶面AXS2可以高于第二字线结构部200B中的TiN层的底面，并且，第一字线结构部200A中的TiN层的底面可以低于第二字线结构部200B中的TiN层的底面。
在本公开实施例中，如图5所示，第一字线结构部200A中的字线为实心结构。并且，第一字线结构部200A中，字线的顶面AXS4低于栅极氧化层230的顶面AXS5(例如可以为S0平面)。以及，第一字线结构部200A中，字线作为凹陷区域AC0的底部，且设置于字线沟槽的侧壁的栅极氧化层230作为凹陷区域AC0的侧壁。
本公开实施例提供了另一些半导体器件的结构示意图，如图6所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本公开实施例中，如图6所示，避让区域BR中绝缘物质也可以为无机绝缘材料。示例性地，无机绝缘材料可包括氧化硅、氮化硅、氮氧化物、硅氮化物、氧化物/氮化物/氧化物(ONO)中的一种或多种。
参见图6，图6为图1所示的半导体衬底沿AA’方向上的又一些剖视结构示意图。在本公开实施例中，在制备方法中，以设定的沉积速率，在整个半导体器件上沉积SiN层，作为绝缘阻挡层，并同时在第一字线结构部200A的避让区域BR中沉积填充SiN层。需要说明的是，本实施例中半导体器件的制备方法的其余步骤与上述制备方法中的其余步骤基本相同，在此不作赘述。
本公开实施例还提供了一些半导体存储装置。该半导体存储装置可以包 括本公开实施例提供的上述半导体器件。该半导体存储装置解决问题的原理与前述半导体器件相似，因此该半导体存储装置的实施可以参见前述半导体器件的实施，重复之处在此不再赘述。
在具体实施时，在本公开实施例中，半导体器件例如为DRAM。半导体存储装置可以包括半导体器件。并且，半导体存储装置可以为具有存储功能的产品或部件。对于该半导体存储装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (15)

  1. 一种半导体器件，包括：
    半导体衬底，包括：浅沟道隔离区，以及由所述浅沟道隔离区界定出的若干个间隔排布的有源区；
    多个字线沟槽，形成于所述半导体衬底中，并且所述字线沟槽与相应的有源区相交设置；其中，所述字线沟槽包括第一字线沟槽和第二字线沟槽；所述第一字线沟槽在所述半导体衬底的正投影位于所述浅沟道隔离区位于所述半导体衬底的正投影内；所述第二字线沟槽在所述半导体衬底的正投影位于所述有源区在所述半导体衬底的正投影内；
    字线结构，埋置于所述字线沟槽中；其中，所述字线结构包括相互连接的第一字线结构部和第二字线结构部；所述第一字线结构部形成于所述第一字线沟槽中，所述第二字线结构部形成于所述第二字线沟槽中；
    其中，所述第一字线结构部具有避让区域，所述避让区域的顶面与所述第二字线结构部的顶面齐平，并且所述避让区域中具有绝缘物质。
  2. 如权利要求1所述的半导体器件，其中，所述第二字线结构部为实心结构；在垂直于所述字线结构的延伸方向上，所述第一字线结构部的截面具有凹陷区域；
    所述避让区域包括所述凹陷区域。
  3. 如权利要求2所述的半导体器件，其中，在垂直于所述半导体衬底的方向上，所述凹陷区域的顶面与所述第二字线结构部的顶面齐平；
    并且，在垂直于所述半导体衬底的方向上，所述凹陷区域的底面高于所述第二字线结构部的底面，所述第一字线结构部的底面低于所述第二字线结构部的底面。
  4. 如权利要求3所述的半导体器件，其中，所述字线结构包括：栅极氧化层与字线；其中，所述栅极氧化层覆盖于所述字线沟槽的侧壁；且所述栅极氧化层位于所述字线和所述字线沟槽之间；
    所述凹陷区域位于所述第一字线结构部中的字线内。
  5. 如权利要求4所述的半导体器件，其中，所述字线包括第一导电膜层和第二导电膜层；其中，所述第一导电膜层设置于所述字线沟槽的侧壁，且所述第一导电膜层位于所述第二导电膜层与所述栅极氧化层之间；
    所述凹陷区域位于所述第一字线结构部中的第二导电膜层内；或者，
    所述第一字线结构部中的第二导电膜层为实心结构；且所述第一字线结构部中，所述第二导电膜层的顶面低于所述第一导电膜层的顶面，以及所述第二导电膜层作为所述凹陷区域的底部，设置于所述字线沟槽的侧壁的所述第一导电膜层作为所述凹陷区域的侧壁。
  6. 如权利要求3所述的半导体器件，其中，所述字线结构包括：栅极氧化层与字线；其中，所述栅极氧化层覆盖于所述字线沟槽的侧壁；且所述栅极氧化层位于所述字线和所述字线沟槽之间；
    所述第一字线结构部中的字线为实心结构；
    所述第一字线结构部中，所述字线的顶面低于所述栅极氧化层的顶面；
    所述第一字线结构部中，所述字线作为所述凹陷区域的底部，且设置于所述字线沟槽的侧壁的栅极氧化层作为所述凹陷区域的侧壁。
  7. 如权利要求4或6所述的半导体器件，其中，与所述第二字线结构部接触的栅极氧化层与所述半导体衬底直接接触；
    与所述第一字线结构部接触的栅极氧化层与所述半导体衬底之间具有浅沟道隔离层。
  8. 如权利要求1-6任一项所述的半导体器件，其中，所述绝缘物质包括空气和无机绝缘材料中的至少一种。
  9. 如权利要求1-6任一项所述的半导体器件，其中，在垂直于所述半导体衬底所在平面的方向上，所述第一字线沟槽的深度大于所述第二字线沟槽的深度。
  10. 一种如权利要求1-9任一项所述的半导体器件的制备方法，包括：
    提供半导体衬底；
    在所述半导体衬底中形成浅沟道隔离区，以及由所述浅沟道隔离区界定出若干个间隔排布的有源区；
    在所述半导体衬底中形成与相应的有源区相交设置的多个字线沟槽；其中，所述字线沟槽包括第一字线沟槽和第二字线沟槽；所述第一字线沟槽在所述半导体衬底的正投影位于所述浅沟道隔离区位于所述半导体衬底的正投影内；所述第二字线沟槽在所述半导体衬底的正投影位于所述有源区在所述半导体衬底的正投影内；
    在所述字线沟槽中形成埋置的字线结构；其中，所述字线结构包括相互电连接的第一字线结构部和第二字线结构部；所述第一字线结构部形成于所述第一字线沟槽中，所述第二字线结构部形成于所述第二字线沟槽中；所述第一字线结构部具有避让区域，所述避让区域的顶面与所述第二字线结构部的顶面齐平，并且所述避让区域中具有绝缘物质。
  11. 如权利要求10所述的制备方法，其中，所述在所述半导体衬底中形成与相应的有源区相交设置的多个字线沟槽，包括：
    在所述浅沟道隔离区中形成所述第一字线沟槽；
    在所述有源区中形成所述第二字线沟槽。
  12. 如权利要求11所述的制备方法，其中，所述在所述字线沟槽中形成埋置的字线结构，包括：
    在所述字线沟槽的侧壁上覆盖栅极氧化层；
    在形成有所述栅极氧化层的所述字线沟槽内填充导电材料，形成初始字线结构；
    对所述初始字线结构进行刻蚀，使所述初始字线结构的顶面低于所述半导体衬底的顶面，以形成第二字线结构部和位于所述第一字线沟槽中的第一初始字线结构部；
    对所述第一初始字线结构部进行刻蚀，使所述第一初始字线结构部形成避让区域，以形成第一字线结构部；
    在所述字线沟槽中形成埋置的字线结构之后，还包括：形成覆盖整个所 述半导体器件的绝缘阻挡层，并使所述避让区域中填充有绝缘物质。
  13. 如权利要求12所述的制备方法，其中，所述形成覆盖整个所述半导体器件的绝缘阻挡层，并使所述避让区域中填充有绝缘物质，包括：
    形成覆盖整个所述半导体器件的绝缘阻挡层，并在所述第一字线结构部的避让区域形成空气隙。
  14. 如权利要求12所述的制备方法，其中，所述形成覆盖整个所述半导体器件的绝缘阻挡层，并使所述避让区域中填充有绝缘物质，包括：
    形成覆盖整个所述半导体器件的绝缘阻挡层，并在所述第一字线结构部的避让区域填充所述绝缘阻挡层。
  15. 一种半导体存储装置，包括如权利要求1-9任一项所述的半导体器件。
PCT/CN2021/113316 2021-08-16 2021-08-18 半导体器件、其制备方法及半导体存储装置 WO2023019481A1 (zh)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110027988A1 (en) * 2009-07-31 2011-02-03 Sun-Hwan Hwang Method for forming buried word line in semiconductor device
CN106298673A (zh) * 2015-05-20 2017-01-04 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法
CN108695327A (zh) * 2017-04-12 2018-10-23 三星电子株式会社 半导体器件及其制造方法
CN210296374U (zh) * 2019-09-04 2020-04-10 福建省晋华集成电路有限公司 存储器
CN211555887U (zh) * 2020-04-14 2020-09-22 福建省晋华集成电路有限公司 存储器
CN112885833A (zh) * 2019-11-29 2021-06-01 长鑫存储技术有限公司 半导体器件及其制作方法
US20210242211A1 (en) * 2020-02-05 2021-08-05 Nanya Technology Corporation Semiconductor device having buried word line and method of manufacturing the same

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110027988A1 (en) * 2009-07-31 2011-02-03 Sun-Hwan Hwang Method for forming buried word line in semiconductor device
CN106298673A (zh) * 2015-05-20 2017-01-04 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法
CN108695327A (zh) * 2017-04-12 2018-10-23 三星电子株式会社 半导体器件及其制造方法
CN210296374U (zh) * 2019-09-04 2020-04-10 福建省晋华集成电路有限公司 存储器
CN112885833A (zh) * 2019-11-29 2021-06-01 长鑫存储技术有限公司 半导体器件及其制作方法
US20210242211A1 (en) * 2020-02-05 2021-08-05 Nanya Technology Corporation Semiconductor device having buried word line and method of manufacturing the same
CN211555887U (zh) * 2020-04-14 2020-09-22 福建省晋华集成电路有限公司 存储器

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