WO2022163052A1 - SiCエピタキシャルウェハの製造装置、及びSiCエピタキシャルウェハの製造方法 - Google Patents
SiCエピタキシャルウェハの製造装置、及びSiCエピタキシャルウェハの製造方法 Download PDFInfo
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- WO2022163052A1 WO2022163052A1 PCT/JP2021/040770 JP2021040770W WO2022163052A1 WO 2022163052 A1 WO2022163052 A1 WO 2022163052A1 JP 2021040770 W JP2021040770 W JP 2021040770W WO 2022163052 A1 WO2022163052 A1 WO 2022163052A1
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- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
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Definitions
- the present embodiment relates to a SiC epitaxial wafer manufacturing apparatus and a SiC epitaxial wafer manufacturing method.
- SiC silicon carbide
- SiC devices such as Schottky Barrier Diodes (SBDs), MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and IGBTs (Insulated Gate Bipolar Transistors) have been provided for power control applications.
- SBDs Schottky Barrier Diodes
- MOSFETs Metal Oxide Semiconductor Field Effect Transistors
- IGBTs Insulated Gate Bipolar Transistors
- Japanese Patent No. 6206786 U.S. Pat. No. 8,916,451 Japanese Patent No. 5910430 JP 2014-58411 A Japanese Patent Application Laid-Open No. 2005-109408 Japanese Patent Application Laid-Open No. 2019-210161
- the present embodiment provides a high-quality, low-cost SiC epitaxial wafer manufacturing apparatus and a SiC epitaxial wafer manufacturing method.
- a growth furnace a gas mixing preliminary chamber arranged outside the growth furnace for mixing and adjusting the pressure of a carrier gas and/or a material gas, and two substrates having SiC single crystals are provided.
- a wafer boat configured so that a plurality of SiC wafer pairs brought into contact with each other can be arranged at equal intervals with a gap therebetween, and a heating unit for heating the wafer boat installed in the growth furnace to an epitaxial growth temperature.
- the carrier gas and/or the material gas are preliminarily mixed and pressure-regulated in the gas mixing preliminary chamber and then introduced into the growth reactor to grow SiC layers on the surfaces of the plurality of SiC wafer pairs;
- An epitaxial wafer manufacturing apparatus is provided.
- the steps of installing a growth furnace, arranging a gas mixing preliminary chamber for mixing and adjusting the pressure of a carrier gas and/or a material gas outside the growth furnace, and growing a SiC single crystal a step of preparing a SiC wafer pair in which two provided substrates are in contact with each other back to back; a step of arranging the plurality of SiC wafer pairs in a wafer boat at equal intervals with a gap between each other; and placing the wafer boat in the growth furnace.
- FIG. 4C shows a structure of a wafer boat applied to the SiC epitaxial wafer manufacturing apparatus according to the embodiment, showing an enlarged view of the groove portion A.
- FIG. FIG. 5 shows a cross-sectional view of a SiC epitaxial wafer manufacturing apparatus according to another embodiment.
- FIG. 6A shows a front view of a state in which SiC epitaxial layers are adhesively transferred to both surfaces of a graphite substrate.
- FIG. 6B shows a side view of a state in which the SiC epitaxial layers are adhesively transferred onto both sides of the graphite substrate.
- FIG. 7 shows a process sequence of graphene etching, graphene growth, and SiC epitaxial growth in the SiC epitaxial wafer manufacturing apparatus according to the embodiment.
- FIG. 11 shows a schematic explanatory view of graphene etching, graphene growth at 1600° C., SiC epitaxial gas phase, and action of hydrogen and argon on the SiC surface in the manufacturing apparatus according to the embodiment.
- FIG. 12A is a method of manufacturing a SiC epitaxial wafer according to the first embodiment, and shows a cross-sectional view of a SiC single crystal substrate.
- FIG. 12B is a method of manufacturing a SiC epitaxial wafer according to the first embodiment, showing a cross-sectional view of a structure in which a graphene layer is formed on a SiC single crystal substrate.
- FIG. 12A is a method of manufacturing a SiC epitaxial wafer according to the first embodiment, and shows a cross-sectional view of a SiC single crystal substrate.
- FIG. 12B is a method of manufacturing a SiC epitaxial wafer according to the first embodiment, showing a cross-sectional view of a structure in which a graphene layer
- FIG. 12C is a method of manufacturing an SiC epitaxial wafer according to the first embodiment, showing a cross-sectional view of a structure in which a SiC epitaxial growth layer is formed on a graphene layer.
- FIG. 13A is a method of manufacturing a SiC epitaxial wafer according to the first embodiment, showing a cross-sectional view of a structure in which an amorphous Si layer is formed on a SiC epitaxial growth layer.
- FIG. 13B shows a cross-sectional view of a structure in which an amorphous SiC layer is formed on a SiC epitaxial growth layer in the method for manufacturing a SiC epitaxial wafer according to the first embodiment.
- FIG. 13A is a method of manufacturing a SiC epitaxial wafer according to the first embodiment, showing a cross-sectional view of a structure in which an amorphous Si layer is formed on a SiC epitaxial growth layer.
- FIG. 13B shows a cross-sectional view of
- FIG. 15A shows a method for manufacturing a SiC epitaxial wafer according to the first embodiment, in which a graphite substrate is bonded onto a polycrystalline Si layer/polycrystalline SiC layer via an adhesive layer, and a SiC epitaxial growth layer and a graphene layer are formed.
- FIG. 15B shows a method for manufacturing a SiC epitaxial wafer according to the first embodiment, in which a graphite substrate is bonded onto a polycrystalline Si layer/polycrystalline SiC layer via an adhesive layer, and a SiC epitaxial growth layer and a graphene layer are formed.
- FIG. 16 is a cross-sectional view of the method of manufacturing the SiC epitaxial wafer according to the first embodiment, in which the separation structure of FIG. 15A is attached to both sides of a graphite substrate, and a carbonized adhesion layer is formed by annealing. indicates FIG. 17 is a method of manufacturing an SiC epitaxial wafer according to the first embodiment, showing a cross-sectional view of a structure in which a SiC polycrystalline growth layer is formed by CVD and the outer periphery is ground.
- FIG. 16 is a cross-sectional view of the SiC single crystal substrate side of the structure separated at the interface of .
- FIG. 16 is a cross-sectional view of the method of manufacturing the SiC epitaxial wafer according to the first embodiment, in which the separation structure of FIG. 15A is attached to both sides of a graphite substrate, and a carbonized adhesion layer is formed by annealing. indicates FIG. 17 is a method of manufacturing an SiC epitaxial wafer according to
- FIG. 18 is a method of manufacturing an SiC epitaxial wafer according to the first embodiment, and shows a cross-sectional view of a structure in which a graphite substrate and a carbonized adhesion layer are sublimated by annealing.
- FIG. 19 shows a method of manufacturing a SiC epitaxial wafer according to the first embodiment, in which the SiC polycrystalline growth layer, the polycrystalline Si layer/polycrystalline SiC layer are removed, and the SiC epitaxial growth layer is formed on the SiC polycrystalline growth layer.
- 1 shows a cross-sectional view of a structure comprising FIG.
- FIG. 20 is a method of manufacturing an SiC epitaxial wafer according to the first embodiment, and shows a cross-sectional view of a structure having a heavily doped layer at the interface between the SiC polycrystalline growth layer and the SiC epitaxial growth layer.
- FIG. 21 shows a cross-sectional view of a structure in which a hydrogen ion-implanted layer and a phosphorus ion-implanted layer are formed on the C-plane of a SiC single crystal substrate in the first method of manufacturing an SiC epitaxial wafer according to the second embodiment.
- FIG. 22 is a first method for manufacturing an SiC epitaxial wafer according to the second embodiment, and shows a cross-sectional view of a structure in which a SiC polycrystalline growth layer is formed on the C-plane of the phosphorus ion-implanted layer by CVD.
- FIG. 23A shows a first method for manufacturing a SiC epitaxial wafer according to the second embodiment, in which the single-crystal SiC thinned layer is separated from the SiC single-crystal substrate via the separation surface, and SiC polycrystal growth is performed.
- 4 shows a cross-sectional view of a structure in which a SiC single crystal layer is formed on the layer and the SiC polycrystalline growth layer;
- FIG. 23B shows a cross-sectional view of the structure of the SiC single crystal substrate that has been peeled and separated.
- FIG. 24 is a first method for manufacturing an SiC epitaxial wafer according to the second embodiment, and shows a cross-sectional view of a structure in which the Si surface of the SiC single crystal layer is polished.
- FIG. 25 shows a cross-sectional view of a structure in which a SiC epitaxial growth layer is formed on a SiC thinned layer in the first method for manufacturing an SiC epitaxial wafer according to the second embodiment.
- FIG. 24 is a first method for manufacturing an SiC epitaxial wafer according to the second embodiment, and shows a cross-sectional view of a structure in which the Si surface of the SiC single crystal layer is polished.
- FIG. 25 shows a cross-sectional view of a structure in which a SiC epitaxial growth layer is formed on a SiC thinned layer in the first method for manufacturing an SiC epitaxial wafer according
- FIG. 26 shows a cross-sectional view of a structure in which a hydrogen ion-implanted layer is formed on the Si surface of a SiC single crystal substrate, in a second method for manufacturing an SiC epitaxial wafer according to the second embodiment.
- FIG. 27 shows a second method for manufacturing a SiC epitaxial wafer according to the second embodiment, in which the hydrogen ion-implanted layer is weakened by annealing to form a thin single-crystal SiC layer.
- 4 shows a cross-sectional view of a structure in which a SiC epitaxial growth layer is formed on the Si surface of a single-crystal SiC thin layer.
- FIG. 10 shows a cross-sectional view of a structure in which P ion implantation is performed to form a P ion implantation layer
- FIG. 30 shows a second method of manufacturing a SiC epitaxial wafer according to the second embodiment, in which the adhesive is removed to separate the laminate of the single-crystal SiC thinned layer and the SiC epitaxially grown layer from the graphite substrate. Then, the laminated body of the separated single-crystal SiC thinned layer and the SiC epitaxially grown layer is mounted so that the Si surface is in contact with the carbon tray, the C surface is exposed facing upward, and SiC polycrystal growth is performed on the same surface by the CVD method.
- FIG. 30 shows a second method of manufacturing a SiC epitaxial wafer according to the second embodiment, in which the adhesive is removed to separate the laminate of the single-crystal SiC thinned layer and the SiC epitaxially grown layer from the graphite substrate. Then, the laminated body
- FIG. 4 shows a cross-sectional view of a layered structure.
- FIG. 31 is a method of manufacturing an SiC epitaxial wafer according to the second embodiment, and shows a cross-sectional view of the structure from which the carbon tray is removed.
- FIG. 32 shows a schematic diagram of a sintered SiC substrate manufacturing apparatus applicable to the SiC epitaxial wafer manufacturing method according to the embodiment.
- FIG. 33 is a graphene layer applicable to the SiC epitaxial wafer manufacturing method according to the embodiment, showing a bird's-eye view of an example having a configuration in which multiple layers are laminated.
- FIG. 34 shows a cross-sectional view of a Schottky barrier diode fabricated using the SiC epitaxial wafer according to the first embodiment.
- FIG. 39B shows a structural diagram of the two-layer portion of the 4H—SiC crystal.
- FIG. 39C shows a configuration diagram of a four-layer portion of 4H—SiC crystal.
- FIG. 40 shows a configuration diagram of the unit cell of the 4H—SiC crystal shown in FIG. 37A viewed from directly above the (0001) plane.
- [C] indicates the C face of SiC
- [S] indicates the Si face of SiC
- FIG. 2 shows a cross-sectional view of a SiC epitaxial wafer 1A according to the second embodiment.
- a SiC epitaxial wafer 1A according to the second embodiment includes, as shown in FIG. , and a SiC polycrystalline growth layer 18PC arranged on the C plane facing the Si plane of the SiC single crystal layer 13I.
- FIG. 3 shows a schematic cross-sectional structural view of the SiC epitaxial wafer manufacturing apparatus 2 according to the embodiment.
- the SiC epitaxial wafer manufacturing apparatus 2 includes a growth reactor 100A and a gas mixing reserve disposed outside the growth reactor 100A for mixing and adjusting the pressure of carrier gas and/or material gas.
- a heating unit 101 for heating the wafer boat 210 to the epitaxial growth temperature TG.
- the growth furnace 100A includes an inner tube 102 and an outer tube 104, and has a structure of a double tubular furnace hot wall type low pressure (LP: Low Pressure)-CVD apparatus with a vertical structure.
- the inner tube 102 is made of graphite or the like.
- the outer tube 104 is made of quartz or the like.
- a heat insulating material 103 is arranged between the inner tube 102 and the outer tube 104 .
- the substrate may include a hexagonal SiC epitaxial growth layer 12RE, and the SiC layer may include a SiC polycrystalline growth layer 18PC formed on the C plane of the SiC epitaxial growth layer 12RE.
- the substrate includes a hexagonal SiC single crystal layer 13I and a SiC epitaxial growth layer 12E arranged on the Si surface of the SiC single crystal layer 13I.
- a SiC polycrystalline growth layer 18PC may be provided on the C plane facing the Si plane of the crystal layer 13I.
- the reaction chamber can be heated up to the epitaxial growth temperature TG by preheating in an argon (Ar) atmosphere of 0.1 Torr to 0.9 atm close to the atmospheric pressure.
- argon (Ar) atmosphere of 0.1 Torr to 0.9 atm close to the atmospheric pressure.
- Low-pressure CVD-SiC remote epitaxial growth can be realized by using the manufacturing apparatus 2 according to the first embodiment.
- a vacuum gas mixing preliminary chamber 107 is provided on the gas introduction side, and hydrogen gas and material gas are mixed in advance before epitaxial growth.
- the wafer boat 210 is made of SiC or SiC-coated graphite.
- a CH-based gas is introduced through a gas control valve 108
- a Si-based gas is introduced through a gas control valve 109
- H 2 /Ar as a carrier gas is introduced through a gas control valve 110.
- a system gas is introduced.
- the Si-based gas includes at least one of SiH 4 , SiH 3 F, SiH 2 F 2 , SiHF 3 and SiF 4 , for example.
- CH - based gases include, for example, C3H8 , C2H4 , C2H2 , CF4 , C2F6 , C3F8 , C4F6 , C4F8 , C5F8 , It has at least one of CHF 3 , CH 2 F 2 , CH 3 F, or C 2 HF 5 .
- At least one of N 2 , HCl, and F 2 can be applied as the carrier gas other than the H 2 /Ar-based gas.
- the carrier gas and/or the material gas is introduced from the bottom of the growth reactor 100A, and when a plurality of SiC wafer pairs 200WP are arranged in the heated wafer boat 210, the carrier gas and/or the material gas flow and rise on the surface of the SiC wafer pairs 200WP to grow.
- the direction of flow is reversed at the upper part of the furnace 100A and it descends, and is evacuated from the lower part of the growth furnace 100A.
- the flow of carrier gas and/or material gas and the substrate surface of the SiC wafer pairs 200WP are configured to be parallel.
- the mixed gas outlet valve 106 connected to the output side of the gas mixing pre-chamber 107 When the mixed gas outlet valve 106 connected to the output side of the gas mixing pre-chamber 107 is opened, the carrier gas and/or the carrier gas and/or carrier gas flow into the growth furnace 100A from the bottom of the growth furnace 100A as indicated by the flow direction GF of the mixed gas. Or material gas is introduced.
- the carrier gas and/or material gas flows upward over the surfaces of the plurality of SiC wafer pairs 200WP in the heated wafer boat 210 and reaches the top of the growth furnace 100A. to reverse the flow direction and descend.
- the carrier gas and/or material gas is evacuated from the bottom of the growth reactor 100A as indicated by the gas exhaust flow direction GFEX.
- the plurality of SiC wafer pairs 200WP are arranged so that the gas flow and the substrate surface are parallel.
- the method for manufacturing a SiC epitaxial wafer includes steps of installing a growth reactor 100A and arranging a gas mixing preliminary chamber 107 for mixing and adjusting the pressure of carrier gas and/or material gas outside the growth reactor 100A. , a step of preparing SiC wafer pairs 200WP in which two substrates having SiC single crystals are in contact with each other back to back, a step of arranging a plurality of SiC wafer pairs 200WP in a wafer boat 210 with a gap between them, and a growth furnace.
- a step of installing the wafer boat 210 in the 100A a step of heating the wafer boat 210 to the epitaxial growth temperature TG; a step of introducing the carrier gas and/or the material gas into the gas mixing preliminary chamber 107; a step of pre-mixing and adjusting the pressure of the carrier gas and/or the material gas; and a step of introducing the carrier gas and/or the material gas into the growth reactor 100A after mixing and adjusting the pressure of the carrier gas and/or the material gas. and growing SiC layers on the surfaces of the plurality of SiC wafer pairs 200WP.
- a carrier gas and/or material gas is introduced from the bottom of the growth furnace 100A, flows upward over the surfaces of the plurality of SiC wafer pairs 200WP in the heated wafer boat 210, and reverses the flow direction at the top of the growth furnace 100A. and descends, and is evacuated from the bottom of the growth furnace 100A.
- the carrier gas may be hydrogen and/or argon and/or nitrogen gas.
- the material gas supplied together with the carrier gas during the growth of the SiC layer may be silicon hydride or halide or halogen hydride gas and hydrocarbon gas.
- a step of suppressing variations in the thickness of the graphene layer may be included.
- a SiC single crystal substrate 10SB is placed as a substrate in the growth reactor 100A, a step of forming a graphene layer 11GR on the SiC single crystal substrate 10SB by a SiC surface pyrolysis method, and a SiC epitaxial growth layer 12RE on the graphene layer 11GR. , and the step of forming the graphene layer 11GR and the step of forming the SiC epitaxial growth layer 12E may be performed continuously within the same growth reactor 100A.
- material gases are C3H8 , C2H4 , C2H2 , CF4 , C2F6 , C3F8 , C4F6 , C4F8 , C5F8 , CHF 3 , CH2F2 , CH3F , or C2HF5 .
- At least one of H 2 , Ar, N 2 , HCl, and F 2 can be applied as the carrier gas.
- the SiC epitaxial wafer manufacturing apparatus since it is not necessary to place the gas pipe in a high-temperature atmosphere, the material gas is not thermally decomposed in the pipe, and clogging of the gas outlet and generation of particles are suppressed. It is possible. In addition, it is not necessary to use different pipes for different types of gas in order to suppress clogging of the gas outlet. Since the distance to the substrate can be secured, the distribution of each gas type can be made uniform on the substrate.
- the gas is flowed from the bottom to the top of the growth chamber. are arranged in parallel, many substrates can be processed at once.
- a wafer boat and substrates are set in the growth furnace 100A and preheated in vacuum. By this preheating, the inside of the growth furnace 100A can be degassed.
- a graphene layer is epitaxially grown by surface pyrolysis.
- the buffer layer BL+1 layer is targeted by time control.
- an n + drift layer of about 10 ⁇ m can be formed after forming an n ++ buffer layer of about 1 ⁇ m.
- remote epitaxial growth can be performed by adjusting the gas compositions defined respectively.
- the present embodiment aims to provide a SiC epitaxial wafer having a SiC epitaxial growth layer on a SiC polycrystalline growth layer, which has a quality equal to or higher than that of a SiC single crystal substrate grown by a sublimation method, and is less expensive. can be done.
- the present embodiment uses a vertical double-tube furnace hot-wall LP-CVD apparatus to provide a high-quality SiC epitaxial wafer manufacturing apparatus and a method for manufacturing SiC epitaxial wafers at a reduced cost. can.
- a vertical tubular furnace type CVD apparatus in which a plurality of SiC single crystal substrates 10SB are arranged with a gap in the growth chamber is used.
- the step of forming the graphene layer 11GR and the step of remotely epitaxially growing the single-crystal SiC epitaxial growth layer 12RE on the SiC single-crystal substrate 10SB via the graphene layer 11GR can be performed in situ as a series of processes. As a result, surface contamination of the graphene layer 11GR can be avoided.
- each dedicated reaction chamber (three chambers connected ). At that time, each reaction chamber is connected with a highly heat-resistant vacuum transfer chamber to enable in-situ processing in a vacuum.
- FIG. 4 shows the structure of a wafer boat 210 applied to the manufacturing apparatus according to the embodiment.
- 4A shows a side view in a first direction
- FIG. 4B shows a side view in a second direction
- FIG. 4C shows an enlarged view of groove A.
- FIG. 4A shows a side view in a first direction
- FIG. 4B shows a side view in a second direction
- FIG. 4C shows an enlarged view of groove A.
- SiC wafer pair 200WP are arranged with a certain gap between them.
- One pair SiC wafer pair 200WP is configured by arranging two single crystal SiC wafers back to back.
- a plurality of SiC wafer pairs 200WP are fitted into the grooves of the pillars of the wafer boat 210 and supported at three points by the edges of the SiC wafer pairs 200WP.
- the SiC wafer pair 200WP has a structural example in which SiC single crystal substrates 10SB1 and 10SB2 are attached to a graphite substrate 19GS via adhesive layers 17PI and 17P2. The Si surfaces of the SiC single crystal substrates 10SB1 and 10SB2 are exposed to the gas atmosphere.
- a SiC wafer pair 200WP shown in FIG. 4C corresponds to an example in which formation of a graphene layer and formation of a remote epitaxial growth layer are performed within the same growth reactor 100A.
- the graphite substrate 19GS which is one size larger than the SiC single crystal substrates 10SB1 and 10SB2, has the advantage of keeping the traces of the wafer boat support outside the substrate effective area when it is inserted into the wafer boat groove of a batch-type vertical CVD furnace and aligned.
- the SiC epitaxial wafer manufacturing apparatus 2A includes a growth furnace 100B and a gas mixing reserve disposed outside the growth furnace 100B for mixing and adjusting the pressure of carrier gas and/or material gas.
- a carrier gas and/or a material gas is introduced into the gas mixing preliminary chamber 107 by a gas input GFIN.
- An exhaust cooling device (cooling scavenger) 114 is arranged in the gas exhaust system, N 2 gas is introduced by gas exhaust valves 112 and 113, and gas exhaust EX is performed together with the N 2 gas.
- Other configurations and operation methods are the same as those of the SiC epitaxial wafer manufacturing apparatus 2 according to the embodiment shown in FIG.
- the carrier gas and/or the material gas is introduced from the bottom of the growth reactor 100A, and when a plurality of SiC wafer pairs 200WP are arranged in the heated wafer boat 210, the carrier gas and/or the material gas flow and rise on the surface of the SiC wafer pairs 200WP to grow.
- the direction of flow is reversed at the upper part of the furnace 100A and it descends, and is evacuated from the lower part of the growth furnace 100A.
- the flow of the carrier gas and/or material gas is perpendicular to the substrate surface of the SiC wafer pairs 200WP.
- FIG. 6A shows a front view of a state in which the SiC epitaxial layers 12RE1 and 12RE2 are adhesively transferred to the front and back surfaces of the graphite substrate 19GS, respectively.
- FIG. 6B shows a side view of a state in which the SiC epitaxial layers 12RE1 and 12RE2 are adhesively transferred to the front and back surfaces of the graphite substrate 19GS, respectively.
- FIGS. 6A and 6B show an embodiment in which a SiC wafer pair 200WP is installed when SiC polycrystalline growth layers 18PC1 and 18PC2 are directly grown on epitaxial growth layers 12RE1 and 12RE2 by CVD, respectively.
- the graphite substrate 19GS which is one size larger than the SiC epitaxial wafer on which the SiC epitaxial layers 12RE1 and 12RE2 are formed, is inserted into the wafer boat groove of a batch-type vertical CVD furnace and aligned, the traces of the wafer boat pillars are used as substrates. There are benefits to being outside the area.
- polishing damage on the substrate surface is removed by etching due to the reaction of high-temperature hydrogen and SiC before epitaxial growth.
- the conditions for this hydrogen etching are a substrate temperature of 1600° C., a growth pressure of 250 mbar, a hydrogen flow rate of 40 slm, and a hydrogen etching time of 3 minutes. The etching amount at this time is on the order of nm.
- SiH 4 and C 3 H 8 as material gases are introduced to carry out epitaxial growth.
- the temperature at which graphetization occurs on the SiC substrate is 1300°C or higher. However, the temperature at which Si sublimates from the SiC substrate changes depending on the pressure and surface conditions. Therefore, the graphetization temperature also changes depending on the pressure and surface conditions.
- FIG. 8 is an explanatory diagram of graphene etching and graphene growth in the manufacturing apparatus according to the embodiment, showing the relationship between the processing rate and the hydrogen/argon partial pressure ratio.
- FIG. 9 is an explanatory diagram of graphene etching and graphene growth in the manufacturing apparatus according to the embodiment, showing the temperature dependence of the graphene growth rate and graphene etching rate with pressure as a parameter.
- Graffetization proceeds at 1600 to 1650° C. or higher under an Ar flow of 1 atm and at 1150 to 1400° C. or higher under high vacuum. For example, graphetization proceeds at 1500-1600° C./0.5 Torr vacuum. Immediately before the start of remote epitaxial growth, graphene etching progresses with H 2 flow, and graphetization progresses with full Ar flow.
- H/H 2 enters the graphene buffer layer (GBL) from grain boundaries and defects, and intercalation cuts the bond with the SiC substrate to form graphene. After that, reaction/desorption occurs in the same manner as described above.
- GBL graphene buffer layer
- the C concentration on the SiC surface increases. Since C does not sublimate at this temperature and does not react with Ar, it stays on the SiC surface.
- SiC surface reaction before and after the event boundary -For full H2 or full Ar- It is assumed that when the total flow rate (partial pressure) of H 2 and Ar is constant, the Si sublimation rate from SiC is also constant.
- etching of the graphene layer predominantly proceeds with 100% H 2
- graphetization predominantly proceeds with 100% Ar.
- it grows up to about the buffer layer BL+graphene molecular layer G2-G3.
- a vertical tubular furnace type CVD apparatus in which a plurality of SiC single crystal substrates 10SB are arranged with a gap in the growth chamber is used to form graphene layers 11GR formed on the SiC single crystal substrates 10SB.
- a single crystal SiC epitaxial growth layer 12RE is remotely epitaxially grown through the graphene layer 11GR.
- a vertical tubular furnace type CVD apparatus in which substrates having a plurality of SiC epitaxial growth layers 12E are arranged with a gap in the growth chamber is used to form a SiC polycrystalline growth layer on the SiC epitaxial growth layer 12E.
- Grow 18PC the following effects are obtained.
- Graphene epitaxial growth caused by sublimation of Si from the surface of the SiC single crystal substrate 10SB (thermal decomposition of the SiC substrate surface) suppresses changes in the graphene layer thickness from the substrate temperature rise to immediately before the start of SiC remote epitaxial growth, The effect of controlling to 1 to 3 monolayers required for remote epitaxial growth of SiC is obtained.
- the SiC polycrystalline growth layer 18PC is uniformly grown to a predetermined thickness on the substrate provided with the plurality of SiC epitaxial growth layers 12E. The effect of reducing the manufacturing cost can be obtained.
- a SiC epitaxial wafer having a SiC epitaxial growth layer on a SiC polycrystalline growth layer a SiC epitaxial wafer having high quality equal to or higher than that of a SiC single crystal substrate grown by a sublimation method and capable of reducing costs can be obtained.
- a manufacturing apparatus and a method for manufacturing a SiC epitaxial wafer can be provided.
- the SiC epitaxial wafer 1 includes a SiC single crystal substrate (SiCSB) 10SB and a graphene layer ( GR) 11GR, a SiC epitaxial growth layer (SiC-epi) 12RE arranged above the SiC single crystal substrate 10SB via the graphene layer 11GR, and an amorphous layer arranged on the Si surface of the SiC epitaxial growth layer 12RE. .
- the amorphous layer includes an amorphous Si layer (a-Si) 13AS or an amorphous SiC layer (a-SiC) 13ASC.
- a microcrystalline layer of Si instead of the amorphous Si layer 13AS, a microcrystalline layer of Si may be provided.
- the Si microcrystalline layer can be obtained by subjecting the amorphous Si layer 13AS to a low-temperature annealing treatment at, for example, approximately 550.degree. C. to 700.degree.
- the SiC epitaxial wafer according to the first embodiment includes a SiC single crystal substrate 10SB, a graphene layer 11GR arranged on the Si surface of the SiC single crystal substrate 10SB, A SiC epitaxial growth layer 12RE arranged above the SiC single crystal substrate 10SB via the graphene layer 11GR and a polycrystalline layer arranged on the Si surface of the SiC epitaxial growth layer 12RE may be provided.
- the polycrystalline layer includes a polycrystalline Si layer (poly-Si) 15PS or a crystalline SiC layer (poly-SiC) 15PSC.
- the polycrystalline Si layer (poly-Si) 15PS is obtained by subjecting the amorphous Si layer 13AS to a medium temperature annealing treatment of about 700° C. to 900° C. or a high temperature annealing treatment of about 900° C. to 1100° C., for example. be done.
- the second ion-implanted layer is arranged between the single-crystal SiC thinned layer 10HE and the SiC polycrystalline growth layer 18PC.
- the Si plane of the SiC single crystal layer 13I is, for example, the [0001] oriented plane of 4H-SiC
- the C plane of the SiC single crystal layer 13I is the [000-1] oriented plane of 4H-SiC. is.
- the SiC single crystal substrate 10SB can be reused by separating it from the SiC epitaxial growth layer 12RE.
- the single-crystal SiC thinned layer 10HE is separated from the SiC single-crystal substrate 10SB via the separation plane BP, and SiC polycrystalline growth is performed.
- a cross-sectional view of the structure in which the SiC single crystal layer 13I is formed on the layer 18PC and the SiC polycrystalline growth layer 18PC is represented as shown in FIG. 23A.
- FIG. A cross-sectional view of a structure in which a SiC epitaxial growth layer 12E is formed on the Si surface of a SiC single crystal layer 13I in the first method for manufacturing an SiC epitaxial wafer according to the second embodiment is shown in FIG. is represented by
- an annealing process is performed to weaken the hydrogen ion-implanted layer 10HI to form a thin single-crystal SiC layer 10HE.
- the embrittled hydrogen ion-implanted layer 10HI becomes the single-crystal SiC thinned layer 10HE.
- the annealing treatment is embrittlement thermal annealing treatment. This is a process for generating hydrogen microbubbles after hydrogen ion implantation to facilitate breaking of the single-crystal SiC thin layer 10HE.
- a delamination surface BP is formed in the single crystal SiC thinned layer 10HE when a stress such as a shear stress is applied.
- a first method for manufacturing a SiC epitaxial wafer according to the second embodiment has the following steps. That is, a step of forming the hydrogen ion implanted layer 10HI on the C-plane of the SiC single-crystal substrate 10SB, a step of forming the SiC polycrystalline growth layer 18PC on the C-plane of the SiC single-crystal substrate 10SB, and a step of forming the SiC polycrystalline growth layer Along with the step of forming 18PC, the step of embrittlement of the hydrogen ion-implanted layer 10HI to form a thin single-crystal SiC layer 10HE, and the thin single-crystal SiC layer 10HE and the SiC polycrystalline growth layer from the SiC single-crystal substrate 10SB.
- a step of removing the first laminate of 18PC, a step of smoothing the surface of the separated single-crystal SiC thinned layer 10HE, and forming a SiC epitaxial growth layer 12E on the smoothed surface of the single-crystal SiC thinned layer 10HE. have a step of
- other ions such as P
- the depth of the phosphorus ion-implanted layer 10PI is, for example, approximately 0.1 ⁇ m to 0.5 ⁇ m.
- the acceleration energy is, for example, approximately 10 keV to 180 keV
- the dose amount is, for example, approximately 4.times.10.sup.15/ cm.sup.2 to 6.times.10.sup.16 / cm.sup.2 .
- the hydrogen ion-implanted layer 10HI can be embrittled at the same time as the high-temperature treatment during deposition of the SiC polycrystalline growth layer 18PC. At the same time, activation annealing for hydrogen ions, P ions, etc. is performed. The hydrogen ion-implanted layer 10HI is weakened at the same time as the heat treatment during the formation of the SiC polycrystalline growth layer 18PC, thereby forming the single crystal SiC thinned layer 10HE.
- a laminate (18PC, 10PI, 10HE) of a single-crystal SiC thinned layer 10HE, a phosphorus ion-implanted layer 10PI, and a SiC polycrystalline growth layer 18PC is formed from the SiC single-crystal substrate 10SB. exfoliate.
- the peeling step is performed on the peeled surface BP of the single-crystal SiC thinned layer 10HE subjected to the embrittlement treatment.
- the uneven structure of the thin single crystal SiC layer 10HE is exposed.
- the uneven structure of the thin single-crystal SiC layer 10HE is subjected to a mechanical polishing method and a mechanical-chemical polishing method in order to smooth the Si surface of the SiC single-crystal substrate 10SB.
- the Si surface of the SiC single crystal substrate 10SB has an average surface roughness Ra of, for example, about 1 nm or less due to the above process. As a result, the SiC single crystal substrate 10SB can be reused.
- the SiC single crystal substrate 10SB becomes reusable.
- the surface of the peeled SiC single-crystal thin layer 10E is smoothed by sequentially using a mechanical polishing method and a mechanical-chemical polishing method.
- the Si surface of the thinned SiC single crystal layer 10E has an average surface roughness Ra of, for example, about 1 nm or less due to the above process.
- the thinned SiC single crystal layer is formed by the ion implantation delamination method to the C plane of the hexagonal SiC single crystal substrate, and A SiC epitaxial wafer and a method for manufacturing the same are provided by combining the direct growth of a SiC polycrystalline layer on the C-plane of a SiC single crystal thinned layer without using a substrate bonding method for a single crystal SiC epitaxially grown layer and a SiC polycrystalline layer. can do.
- the thinned SiC single crystal layer is formed on the C plane of the SiC single crystal substrate by the ion implantation delamination method, and the thinned SiC single crystal is By directly depositing the SiC polycrystalline layer on the layer by the CVD method, the step of bonding the single-crystal SiC epitaxial growth layer and the SiC polycrystalline growth layer is eliminated, and the manufacturing process is simplified, thereby reducing the manufacturing cost. can.
- the single-crystal SiC epitaxial growth layer and the SiC multi-layer are formed by combining the ion implantation delamination method and the CVD direct deposition technology without bonding the substrates.
- a composite substrate of a laminate of crystal growth layers can be produced.
- a first method for manufacturing a SiC epitaxial wafer according to the second embodiment is a method for manufacturing a SiC composite substrate having a single-crystal SiC epitaxial growth layer on a SiC polycrystalline substrate, On the (000-1) C plane, by directly depositing a SiC polycrystalline growth layer by thermal CVD on the SiC single crystal thin layer obtained by thinning the surface of the SiC single crystal substrate using the ion implantation delamination method. 3.
- the substrate bonding between the single-crystal SiC epitaxial growth layer and the SiC polycrystalline growth layer is eliminated, the manufacturing process is simplified, and the manufacturing cost can be reduced.
- the following effects (1) to (6) are obtained.
- the first is hydrogen ion implantation for the ion implantation delamination method, and after the ion implantation, hydrogen microbubbles are generated to break the thinned layer.
- An embrittlement thermal anneal is required to facilitate
- the second ion implantation is P ion implantation for reducing the contact interface resistance (ohmic contact) between single crystal SiC and polycrystalline SiC. Annealing is required. Both of these annealings are simultaneously achieved by heating the substrate during deposition of the polycrystalline SiC support layer by CVD, so there is no need to perform these annealing steps separately, making it possible to reduce manufacturing costs.
- the hydrogen ion-implanted layer 10HI is annealed to weaken the hydrogen ion-implanted layer 10HI to form the thin single-crystal SiC layer 10HE.
- 27 shows a cross-sectional view of a structure in which a SiC epitaxial growth layer 12E is formed on the Si surface of a single-crystal SiC thinned layer 10HE.
- the adhesion layer 17PI is removed to separate the laminate of the single-crystal SiC thinned layer 10HE and the SiC epitaxial growth layer 12E from the graphite substrate 19GS. Then, the laminated body of the separated single crystal SiC thinned layer 10HE and the SiC epitaxial growth layer 12E is mounted so that the Si surface is in contact with the carbon tray 20CT, and the C surface is exposed with the C surface facing upward.
- a cross-sectional view of the structure in which the SiC polycrystalline growth layer 18PC is formed is represented as shown in FIG.
- FIG. 1 A cross-sectional view of the structure from which the carbon tray 20CT is removed in the SiC epitaxial wafer manufacturing method according to the second embodiment is shown in FIG.
- a second method for manufacturing a SiC epitaxial wafer according to the second embodiment has the following steps. That is, a step of forming a hydrogen ion implanted layer 10HI on the Si surface of the SiC single crystal substrate 10SB, a step of forming a SiC epitaxial growth layer 12E on the Si surface of the SiC single crystal substrate 10SB, and embrittlement of the hydrogen ion implanted layer 10HI.
- a step of forming a thin single-crystal SiC layer 10HE a step of attaching a temporary substrate to the Si surface of the SiC epitaxial growth layer 12E; , smoothing the surface of the single-crystal SiC thinned layer 10HE that has been stripped, and forming a SiC polycrystalline growth layer 18PC on the surface of the smoothed single-crystal SiC thinned layer 10HE.
- the hydrogen ion-implanted layer 10HI is subjected to high temperature treatment to embrittle the hydrogen ion-implanted layer 10HI.
- embrittlement thermal annealing is necessary to generate hydrogen microbubbles and make the thin single-crystal SiC layer 10HE easier to fracture.
- a single-crystal SiC epitaxial growth layer 12E is formed by homoepitaxial growth on the Si surface of the thin single-crystal SiC layer 10HE by CVD.
- P (phosphorous) ions are implanted into the smoothed surface to reduce the electric resistance value of the contact interface of the stack, forming a phosphorus ion-implanted layer 10PI.
- the depth of the phosphorus ion-implanted layer 10PI is, for example, approximately 0.1 ⁇ m to 0.5 ⁇ m.
- the acceleration energy is, for example, approximately 10 keV to 180 keV
- the dose amount is, for example, approximately 4.times.10.sup.15/ cm.sup.2 to 6.times.10.sup.16 / cm.sup.2 .
- the separated single-crystal SiC thinned layer 10HE and the single-crystal SiC epitaxially grown layer 12E are mounted so that the Si surface is in contact with the carbon tray 20CT, and the C surface is mounted. is exposed facing upward, a SiC polycrystalline growth layer 18PC is deposited on the same surface by CVD, and activation and crystal damage recovery annealing are performed at the same time.
- the laminate of the single-crystal SiC thin layer 10HE, the single-crystal SiC epitaxial growth layer 12E, and the SiC polycrystal growth layer 18PC is separated from the carbon tray 20CT, and the outer peripheral portion is formed. and both sides of the substrate are processed into a predetermined shape and surface condition.
- the CVD apparatus for forming 18PC may be the same CVD apparatus, or may be configured as separate dedicated apparatuses.
- the SiC epitaxial wafer manufacturing apparatus according to the present embodiment can be applied to the CVD apparatus used.
- the SiC epitaxial wafer 1 according to the second embodiment can be formed.
- the SiC single crystal substrate is thinned by ion implantation detachment to the Si surface of the hexagonal SiC single crystal substrate, and the polycrystalline SiC layer is formed by CVD.
- the SiC single crystal substrate is thinned by ion implantation detachment to the Si surface of the hexagonal SiC single crystal substrate, and the polycrystalline SiC layer is formed by CVD.
- a single-crystal SiC layer thinned to a single-crystal layer by ion implantation delamination is applied to the Si surface of a SiC single-crystal substrate by CVD.
- a second method for manufacturing a SiC epitaxial wafer according to the second embodiment is a method for manufacturing a SiC composite substrate having a single-crystal SiC epitaxial growth layer on a polycrystalline SiC substrate, comprising a hexagonal SiC single-crystal substrate (000 -1)
- a single crystal SiC layer is formed by directly depositing a polycrystalline SiC support layer by thermal CVD on a single crystal SiC layer obtained by thinning the surface of a SiC single crystal substrate using an ion implantation delamination method. It is possible to eliminate the substrate bonding between the layer and the polycrystalline SiC substrate, simplify the manufacturing process, and reduce the manufacturing cost.
- the interfacial contact resistance value can be reduced. We were able to reduce the driving voltage specific to composite substrates.
- the thermal CVD method enables high-concentration autodoping during the deposition of the polycrystalline SiC support layer, so that the bulk electrical resistance value can be reduced to a level comparable to that of a single-crystal substrate produced by the sublimation method. .
- the first is hydrogen ion implantation for the ion implantation separation method, and after the ion implantation, hydrogen microbubbles are generated to form a thin layer.
- An embrittlement thermal anneal is required to facilitate fracture of the .
- the second ion implantation is P ion implantation for reducing the contact interface resistance (ohmic contact) between monocrystalline SiC and polycrystalline SiC. Annealing is required. Both of these annealings are simultaneously achieved by heating the substrate during deposition of the polycrystalline SiC support layer by CVD, so there is no need to perform these annealing steps separately, making it possible to reduce manufacturing costs.
- a sintered SiC substrate manufacturing apparatus 500 applicable to the SiC epitaxial wafer manufacturing method according to the embodiment is schematically represented as shown in FIG.
- the inside 500A of the manufacturing apparatus 500 is filled with a vacuum atmosphere of about several Pa or replaced with Ar/N 2 gas.
- the manufacturing apparatus 500 employs a solid compression sintering method by hot press sintering (HP: Hot Press).
- a graphite sintering mold (graphite die) 900 filled with powder or solid SiC polycrystalline material is heated while being pressurized.
- Graphite die 900 houses a thermocouple or radiation thermometer 920 .
- the graphite die 900 is connected to the pressing shafts 600A and 600B via graphite bunches 800A and 800B and graphite spacers 700A and 700B.
- the heating temperature is, for example, about 1500° C. at maximum
- the pressurizing pressure P is, for example, about 280 MPa at maximum.
- HP hot press sintering
- SPS spark plasma sintering
- the graphene layers 11GR1, 11GR2, etc. applicable to the method for manufacturing the SiC epitaxial wafer 1 according to the embodiment may have a single-layer structure or may have a multi-layer structure.
- FIG. 33 shows a bird's-eye view of an example of a graphene layer applicable to the SiC epitaxial wafer manufacturing method according to the embodiment, which has a structure in which multiple layers are laminated.
- the graphene layer 11GF having a structure in which multiple layers are laminated has a laminated structure of graphite sheets GS1, GS2, GS3, . . . , GSn.
- the graphite sheets GS1, GS2, GS3, . GS1, GS2, GS3, . . . , GSn are coupled by van der Waals forces.
- the SiC epitaxial wafer according to the embodiment can be used, for example, for manufacturing various SiC semiconductor devices. Examples of a SiC-SBD, a SiC trench gate (T: Trench) type MOSFET, and a SiC planar gate type MOSFET using the SiC epitaxial wafer 1 according to the first embodiment will be described below. It should be noted that the same configuration is possible using the SiC epitaxial wafer 1A according to the second embodiment.
- the SiC-SBD 21 is, as shown in FIG.
- An epitaxial wafer 1 is provided.
- a high-concentration doped layer 12REN may be interposed between the SiC polycrystalline growth layer 18PC and the SiC epitaxial growth layer 12RE.
- the high-concentration doped layer 12REN suppresses the spread of the depletion layer in the SiC epitaxial growth layer 12RE and facilitates ohmic contact with the SiC polycrystalline growth layer 18PC formed on the C-plane of the SiC epitaxial growth layer 12RE. can be formed.
- the SiC epitaxial growth layer 12RE is a drift layer
- the heavily doped layer 12REN is a buffer layer
- the SiC polycrystalline growth layer 18PC is a substrate layer.
- the SiC polycrystalline growth layer 18PC is doped n + type (impurity density is, for example, about 1 ⁇ 10 18 cm ⁇ 3 to about 1 ⁇ 10 21 cm ⁇ 3 ), and the SiC epitaxial growth layer 12RE is n ⁇ type ( The impurity density is, for example, about 5 ⁇ 10 14 cm ⁇ 3 to about 5 ⁇ 10 16 cm ⁇ 3 ).
- the heavily doped layer 12REN is doped at a higher concentration than the SiC epitaxial growth layer 12RE.
- the SiC epitaxial growth layer 12RE may have a crystal structure of 4H-SiC, 6H-SiC, or 2H-SiC.
- n-type doping impurities for example, N (nitrogen), P (phosphorus), As (arsenic), etc. can be applied.
- p-type doping impurities for example, B (boron), Al (aluminum), TMA, etc. can be applied.
- the back surface ((000-1)C plane) of the SiC polycrystalline growth layer 18PC is provided with a cathode electrode 22 so as to cover the entire area thereof, and the cathode electrode 22 is connected to the cathode terminal K.
- a surface 100 (for example, (0001) Si plane) of the SiC epitaxial growth layer 12 has a contact hole 24 that exposes a part of the SiC epitaxial growth layer 12RE as an active region 23, and a field region 25 surrounding the active region 23 has a , a field insulating film 26 is formed.
- the field insulating film 26 is made of SiO 2 (silicon oxide), but may be made of other insulators such as silicon nitride (SiN).
- An anode electrode 27 is formed on the field insulating film 26, and the anode electrode 27 is connected to the anode terminal A. As shown in FIG.
- a p-type JTE (Junction Termination Extension) structure 28 is formed in the vicinity of the surface 100 (surface layer portion) of the SiC epitaxial growth layer 12 so as to be in contact with the anode electrode 27 .
- the JTE structure 28 is formed along the contour of the contact hole 24 so as to straddle the inside and outside of the contact hole 24 of the field insulating film 26 .
- a trench gate type MOSFET 31 is, as shown in FIG. 1.
- a high-concentration doped layer 12REN may be interposed between the SiC polycrystalline growth layer 18PC and the SiC epitaxial growth layer 12RE.
- the high-concentration doped layer 12REN suppresses the spread of the depletion layer in the SiC epitaxial growth layer 12RE and facilitates ohmic contact with the SiC polycrystalline growth layer 18PC formed on the C-plane of the SiC epitaxial growth layer 12RE. can be formed.
- the SiC epitaxial growth layer 12RE is a drift layer
- the heavily doped layer 12REN is a buffer layer
- the SiC polycrystalline growth layer 18PC is a substrate layer.
- the SiC polycrystalline growth layer 18PC is doped n + type (impurity density is, for example, about 1 ⁇ 10 18 cm ⁇ 3 to about 1 ⁇ 10 21 cm ⁇ 3 ), and the SiC epitaxial growth layer 12RE is n ⁇ type ( The impurity density is, for example, about 5 ⁇ 10 14 cm ⁇ 3 to about 5 ⁇ 10 16 cm ⁇ 3 ).
- the heavily doped layer 12REN is doped at a higher concentration than the SiC epitaxial growth layer 12RE.
- the SiC epitaxial growth layer 12RE may have a crystal structure of 4H-SiC, 6H-SiC, or 2H-SiC.
- n-type doping impurities for example, N (nitrogen), P (phosphorus), As (arsenic), etc. can be applied.
- p-type doping impurities for example, B (boron), Al (aluminum), TMA, etc. can be applied.
- the back surface ((000-1)C plane) of the SiC polycrystalline growth layer 18PC is provided with a drain electrode 32 so as to cover the entire area thereof, and the drain electrode 32 is connected to the drain terminal D.
- p-type (impurity density is, for example, about 1 ⁇ 10 16 cm ⁇ 3 to about 1 ⁇ 10 19 cm ⁇ 3 ).
- a body region 33 is formed.
- the portion on the side of the SiC polycrystalline growth layer 18PC with respect to the body region 33 is an n ⁇ -type drain region 34 (12RE), which is maintained as it is in the SiC epitaxial growth layer RE.
- a gate trench 35 is formed in the SiC epitaxial growth layer 12RE. Gate trench 35 penetrates body region 33 from surface 100 of SiC epitaxial growth layer 12RE, and its deepest portion reaches drain region 34 (12RE).
- a gate insulating film 36 is formed on the inner surface of the gate trench 35 and the surface 100 of the SiC epitaxial growth layer 12RE so as to cover the entire inner surface of the gate trench 35 .
- Gate electrode 37 is buried in gate trench 35 by filling the inside of gate insulating film 36 with, for example, polysilicon.
- a gate terminal G is connected to the gate electrode 37 .
- n + -type source region 38 forming part of the side surface of the gate trench 35 is formed in the surface layer portion of the body region 33 .
- p + -type (impurity density is, for example, about 1 ⁇ 10 18 cm ⁇ 3 to about 1 ⁇ 10 21 cm -3 ) of body contact region 39 is formed.
- An interlayer insulating film 40 made of SiO 2 is formed on the SiC epitaxial growth layer 12RE.
- a source electrode 42 is connected to the source region 38 and the body contact region 39 through a contact hole 41 formed in the interlayer insulating film 40 .
- a source terminal S is connected to the source electrode 42 .
- the gate electrode A channel can be formed near the interface with the gate insulating film 36 in the body region 33 by the electric field from 37 . Thereby, a current can flow between the source electrode 42 and the drain electrode 32, and the SiC-TMOSFET 31 can be turned on.
- a planar gate type MOSFET 51 is, as shown in FIG. 1.
- a high-concentration doped layer 12REN may be interposed between the SiC polycrystalline growth layer 18PC and the SiC epitaxial growth layer 12RE.
- the high-concentration doped layer 12REN suppresses the spread of the depletion layer in the SiC epitaxial growth layer 12RE and facilitates ohmic contact with the SiC polycrystalline growth layer 18PC formed on the C-plane of the SiC epitaxial growth layer 12RE. can be formed.
- the SiC epitaxial growth layer 12RE is a drift layer
- the heavily doped layer 12REN is a buffer layer
- the SiC polycrystalline growth layer 18PC is a substrate layer.
- the SiC polycrystalline growth layer 18PC is doped n + type (impurity density is, for example, about 1 ⁇ 10 18 cm ⁇ 3 to about 1 ⁇ 10 21 cm ⁇ 3 ), and the SiC epitaxial growth layer 12 is n ⁇ type ( The impurity density is, for example, about 5 ⁇ 10 14 cm ⁇ 3 to about 5 ⁇ 10 16 cm ⁇ 3 ).
- the SiC epitaxial growth layer 12 may have a crystal structure of either 4H-SiC, 6H-SiC, or 2H-SiC.
- n-type doping impurities for example, N (nitrogen), P (phosphorus), As (arsenic), etc. can be applied.
- p-type doping impurities for example, B (boron), Al (aluminum), TMA, etc. can be applied.
- a drain electrode 52 is formed on the back surface ((000-1) C plane) of the SiC single crystal substrate 10SB so as to cover the entire area, and a drain terminal D is connected to the drain electrode 52.
- p-type (impurity density is, for example, about 1 ⁇ 10 16 cm ⁇ 3 to about 1 ⁇ 10 19 cm ⁇ 3 ).
- a body region 53 is formed in a well shape.
- the portion on the SiC single crystal substrate 10SB side with respect to the body region 53 is an n ⁇ -type drain region 54 (12RE), which is maintained in the state after the epitaxial growth.
- n + -type source region 55 is formed in the surface layer portion of the body region 53 with a gap from the periphery of the body region 53 .
- a p + -type (impurity density is, for example, about 1 ⁇ 10 18 cm ⁇ 3 to about 1 ⁇ 10 21 cm ⁇ 3 ) body contact region 56 is formed inside the source region 55.
- Body contact region 56 penetrates source region 55 in the depth direction and is connected to body region 53 .
- a gate insulating film 57 is formed on the surface 100 of the SiC epitaxial growth layer 12RE.
- the gate insulating film 57 covers the portion of the body region 53 surrounding the source region 55 (periphery of the body region 53 ) and the outer periphery of the source region 55 .
- the gate electrode 58 faces the peripheral portion of the body region 53 with the gate insulating film 57 interposed therebetween.
- a gate terminal G is connected to the gate electrode 58 .
- An interlayer insulating film 59 made of SiO 2 is formed on the SiC epitaxial growth layer 12RE.
- a source electrode 61 is connected to the source region 55 and the body contact region 56 through a contact hole 60 formed in the interlayer insulating film 59 .
- a source terminal S is connected to the source electrode 61 .
- the [0001] axis and [000-1] axis are along the axial direction of the hexagonal prism, and the plane normal to the [0001] axis (the top surface of the hexagonal prism) is the (0001) plane (Si plane). On the other hand, the plane normal to the [000-1] axis (the lower surface of the hexagonal prism) is the (000-1) plane (C plane).
- SiC-MOSFET Semiconductor device DESCRIPTION OF SYMBOLS 100... Surface 100A of a SiC epitaxial growth layer, 100B... Growth furnace 101... Heating part 102... Inner tube 103... Heat insulating material 104... Outer tube 105... Gas diffusion plate 106... Mixed gas outlet valve 107... Gas mixing preliminary chamber 108, 109, 110... Gas control valves 112, 113... Gas exhaust valve 114...
- Exhaust cooling device (cooling scavenger) 200 SiC wafer 200WP SiC wafer pair 201 Primary orientation flat 202 Secondary orientation flat 210 Wafer boat 211, [S] Si surface 212, [C] C surface 500 Sintered SiC substrate manufacturing apparatuses GS1 and GS2 , GS3, .
- Direction of exhaust flow
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Abstract
Description
(第1の実施の形態)
図1は第1の実施の形態に係るSiCエピタキシャルウェハ1の断面図を示す。
図2は第2の実施の形態に係るSiCエピタキシャルウェハ1Aの断面図を示す。
図3は実施の形態に係るSiCエピタキシャルウェハの製造装置2の模式的断面構造図を示す。
実施の形態に係るSiCエピタキシャルウェハの製造方法は、成長炉100Aを設置する工程と、キャリアガス及び/又は材料ガスを混合及び調圧するガス混合予備室107を成長炉100Aの外部に配置する工程と、SiC単結晶を備える基板2枚を背合せに接触させたSiCウェハペア200WPを準備する工程と、複数のSiCウェハペア200WPを互いに隙間を空けてウェハボート210に等間隔に配置する工程と、成長炉100A内にウェハボート210を設置する工程と、ウェハボート210をエピタキシャル成長温度TGまで加熱する工程と、キャリアガス及び/又は材料ガスをガス混合予備室107に導入する工程と、ガス混合予備室107においてキャリアガス及び/又は材料ガスを事前に混合及び調圧する工程と、キャリアガス及び/又は材料ガスの混合及び調圧を行った後に、キャリアガス及び/又は材料ガスを成長炉100Aに導入する工程と、複数のSiCウェハペア200WPの表面にSiC層を成長させる工程とを有する。
第1の実施の形態に係る製造装置2を適用したプロセスステップを説明する。
図4は実施の形態に係る製造装置に適用されるウェハボート210の構造である。図4Aは第1の方向の側面図を示し、図4Bは第2の方向の側面図を示し、図4Cは溝部Aの拡大図を示す。
図5は実施の形態に係るSiCエピタキシャルウェハの製造装置2Aの断面図を示す。SiCエピタキシャルウェハ製造装置2Aにおいては、複数のSiCウェハペア200WPは、ガスの流れと基板面が略垂直となるように配置している。
図7は実施の形態に係る製造装置において、グラッフェンエッチング、グラッフェン成長及び、SiCエピタキシャル成長のプロセスシーケンスを示す。
以下に、グラッフェン層を介した遠隔エピタキシャル成長において、SiC単結晶基板上のグラッフェン層の厚さの制御について説明する。
グラッフェンエッチングとグラッフェタイゼーションには事象の境界がある。SiCホモエピタキシャル成長では、エピタキシャル成長の開始直前に、その場(in-situ)で水素エッチングを行うことが多い。このような高温H2雰囲気では、SiもCもエッチングされるため、グラッフェタイゼーションよりもエッチングが優勢に進行する。H2の代わりにArをフローすると、通常グラッフェタイゼーションが進行する。
図10は実施の形態に係る製造装置において、1600℃におけるグラッフェンエッチング、グラッフェン成長及び、SiCエピタキシャルの気相、SiC表面の水素とアルゴンの作用の説明図を示す。また、図11は実施の形態に係る製造装置において、1600℃におけるグラッフェンエッチング、グラッフェン成長及び、SiCエピタキシャルの気相、SiC表面の水素とアルゴンの作用の模式的説明図を示す。
SiC表面のステップからSiが選択的に昇華する。H2分圧により昇華速度は異なる。昇華したSiは、H/H2と反応して蒸気圧の高いSiH化合物になる。
多結晶グラッフェンは粒界端部にH/H2が吸着/反応しCH化合物となって脱離する。
SiC表面からSiが選択的に昇華する。Ar分圧により昇華速度は異なる。
―フルH2又はフルArの場合―
H2とArのトータル流量(分圧)が一定の場合、SiCからのSi昇華速度も一定と仮定する。
Bare-SiC基板の場合は、Si昇華と残留C生成とが化学平衡となるX%のH2であれば、グラッフェタイゼーションが進行しない。この場合、水素比によりグラッフェタイゼーション速度を制御することができる。但し、グラッフェン層形成後は水素を下記のY%にしないとグラッフェンエッチングが優勢になる。水素比率X>Yであり、例えばX=1.5Yの場合、0.5Yの差はSiと反応するH2分となる。
(SiCエピタキシャルウェハ)
第1の実施の形態に係るSiCエピタキシャルウェハ1は、図13A又は図13Bに示すように、SiC単結晶基板(SiCSB)10SBと、SiC単結晶基板10SBのSi面上に配置されたグラッフェン層(GR)11GRと、グラッフェン層11GRを介してSiC単結晶基板10SBの上方に配置されたSiCエピタキシャル成長層(SiC-epi)12REと、SiCエピタキシャル成長層12REのSi面上に配置されたアモルファス層とを備える。
第1の実施の形態に係るSiCエピタキシャルウェハの製造方法であって、SiC単結晶基板10SBの断面図は図12Aに示すように表され、SiC単結晶基板10SB上にグラッフェン層11GRを形成した構造の断面図は図12Bに示すように表され、グラッフェン層11GR上にSiCエピタキシャル成長層12REを形成した構造の断面図は、図12Cに示すように表される。
(SiCエピタキシャルウェハ)
第2の実施の形態に係るSiCエピタキシャルウェハ1Aは、図25に示すように、六方晶系のSiC単結晶層13Iと、SiC単結晶層13IのSi面上に配置されたSiCエピタキシャル成長層(SiC-epi)12Eと、SiC単結晶層13IのSi面と対向するC面上に配置されたSiC多結晶成長層(SiC-poly CVD)18PCとを備える。
第2の実施の形態に係るSiCエピタキシャルウェハの第1の製造方法であって、SiC単結晶基板(SiCSB)10SBのC面に水素イオン注入層10HI及びリンイオン注入層10PIを順次形成した構造の断面図は、図21に示すように表される。
第2の実施の形態に係るSiCエピタキシャルウェハの第1の製造方法においては、イオン注入剥離法を適用している。イオン注入剥離法により、SiC単結晶基板10SBの表面に単結晶SiC薄化層10HEを形成可能である。イオン注入剥離法は、以下の工程を有する。
(1)従来のイオン注入剥離法を用いた複合基板製造に必要な基板接合を用いないため、接合起因の接合欠陥やボイドによる歩留り低下を解消できた。また、工数削減及び不良起因の固定費と変動費損失の削減、並びに生産性と品質が向上した。
(2)接合性を確保するための精密な研磨加工が不要となり、それら工程で発生していた不良損失や加工コスト増加による高コスト化が解消し、安価なSiC複合基板の提供が可能となった。
(3)SiC多結晶成長層と単結晶SiCエピタキシャル成長層の接触面の片側に予めイオン注入を行い、もう一方には成膜時に高濃度ドーピング制御を行うことにより、界面接触抵抗値を低減できるため、複合基板特有の駆動電圧を低減できた。
(4)熱CVD法は多結晶SiC支持層堆積中に、高濃度オートドーピングが可能なため、バルクの電気抵抗値が、昇華法で作製した単結晶基板に匹敵する低抵抗化を可能にした。
(5)SiC単結晶基板C面への2回のイオン注入のうち、1回目はイオン注入剥離法のための水素イオン注入であり、イオン注入後には水素マイクロバブルを発生させ薄化層を破断しやすくするための脆化熱アニールが必要である。2回目のイオン注入は、単結晶SiCと多結晶SiCの接触界面抵抗低減(オーミックコンタクト)のためのPイオン注入であり、注入後にはPイオンを活性化しドナー密度を向上するための活性化熱アニールが必要である。この双方のアニールは、CVDによる多結晶SiC支持層堆積時の基板加熱により同時に達成されるので、これらアニール工程を別途行う必要が無く、製造コスト低減が可能となった。
(6)CVDによる多結晶SiC厚膜堆積前に、前記の脆化アニール効果による剥離現象が発生するため、単結晶SiCと多結晶SiCの熱膨張係数ミスマッチを緩和し、反りを抑制することができた。
第2の実施の形態に係るSiCエピタキシャルウェハの第2の製造方法であって、SiC単結晶基板10SBのSi面に水素イオン注入層10HIを形成した構造の断面図は、図26に示すように表される。
第2の実施の形態に係るSiCエピタキシャルウェハの第2の製造方法においては、イオン注入剥離法を適用している。イオン注入剥離法により、SiC単結晶基板10SBから単結晶SiC薄化層10HEを形成している。イオン注入剥離法は、以下の工程を有する。
(1)従来のイオン注入剥離法を用いた複合基板製造に必要な基板接合を用いないため、接合起因の接合欠陥やボイドによる歩留り低下を解消できた。また、工数削減及び不良起因の固定費と変動費損失の削減、並びに生産性と品質が向上した。
(2)接合性を確保するための精密な研磨加工が不要となり、それら工程で発生していた不良損失や加工コスト増加による高コスト化が解消し、安価なSiC複合基板の提供が可能となった。
(3)多結晶SiC層と単結晶SiCエピタキシャル成長層の接触面の片側に予めイオン注入を行い、もう一方には成膜時に高濃度ドーピング制御を行うことにより、界面接触抵抗値を低減できるため、複合基板特有の駆動電圧を低減できた。
(4)熱CVD法は多結晶SiC支持層堆積中に、高濃度オートドーピングが可能なため、バルクの電気抵抗値が、昇華法で作製した単結晶基板に匹敵する低抵抗化を可能にした。
(5)SiC単結晶基板10SBのC面への2回のイオン注入のうち、1回目はイオン注入剥離法のための水素イオン注入であり、イオン注入後には水素マイクロバブルを発生させ薄化層を破断しやすくするための脆化熱アニールが必要である。2回目のイオン注入は、単結晶SiCと多結晶SiCの接触界面抵抗低減(オーミックコンタクト)のためのPイオン注入であり、注入後にはPイオンを活性化しドナー密度を向上するための活性化熱アニールが必要である。この双方のアニールは、CVDによる多結晶SiC支持層堆積時の基板加熱により同時に達成されるので、これらアニール工程を別途行う必要が無く、製造コスト低減が可能となった。
(6)Si面をイオン注入剥離法で薄化する第2の実施の形態において、SiC多結晶成長層18PCの堆積の際にSiC単結晶基板10SB自体をCVD反応室に入れる必要がないため、SiC単結晶基板10SBの再利用回数を増加できるため、さらなるコスト低減が可能となった。
実施の形態に係るSiCエピタキシャルウェハの製造方法において、SiC多結晶基板16Pは、焼結SiC基板で形成可能である。
第1の実施の形態に係るSiCエピタキシャルウェハを用いて作製した半導体装置として、SiC-SBD21は、図34に示すように、SiC多結晶成長層(CVD)18PCとSiCエピタキシャル成長層12REとからなるSiCエピタキシャルウェハ1を備える。尚、SiC多結晶成長層18PCとSiCエピタキシャル成長層12REとの間に、高濃度ドープ層12RENを介在させても良い。ここで、高濃度ドープ層12RENにより、SiCエピタキシャル成長層12RE中に広がる空乏層の広がりを抑制し、かつSiCエピタキシャル成長層12REのC面に形成されるSiC多結晶成長層18PCとのオーミックコンタクトを容易に形成することができる。SiCエピタキシャル成長層12REはドリフト層、高濃度ドープ層12RENはバッファ層、SiC多結晶成長層18PCはサブストレート層となる。
第1の実施の形態に係るSiCエピタキシャルウェハを用いて作製した半導体装置として、トレンチゲート型MOSFET31は、図35に示すように、SiC多結晶成長層18PCとSiCエピタキシャル成長層12REとからなるSiCエピタキシャルウェハ1を備える。尚、SiC多結晶成長層18PCとSiCエピタキシャル成長層12REとの間に、高濃度ドープ層12RENを介在させても良い。ここで、高濃度ドープ層12RENにより、SiCエピタキシャル成長層12RE中に広がる空乏層の広がりを抑制し、かつSiCエピタキシャル成長層12REのC面に形成されるSiC多結晶成長層18PCとのオーミックコンタクトを容易に形成することができる。SiCエピタキシャル成長層12REはドリフト層、高濃度ドープ層12RENはバッファ層、SiC多結晶成長層18PCはサブストレート層となる。
第1の実施の形態に係るSiCエピタキシャルウェハを用いて作製した半導体装置として、プレーナゲート型MOSFET51は、図36に示すように、SiC多結晶成長層18PCとSiCエピタキシャル成長層12REとからなるSiCエピタキシャルウェハ1を備える。尚、SiC多結晶成長層18PCとSiCエピタキシャル成長層12REとの間に、高濃度ドープ層12RENを介在させても良い。ここで、高濃度ドープ層12RENにより、SiCエピタキシャル成長層12RE中に広がる空乏層の広がりを抑制し、かつSiCエピタキシャル成長層12REのC面に形成されるSiC多結晶成長層18PCとのオーミックコンタクトを容易に形成することができる。SiCエピタキシャル成長層12REはドリフト層、高濃度ドープ層12RENはバッファ層、SiC多結晶成長層18PCはサブストレート層となる。
図37は、SiCの結晶面を説明する図である。図37Aの平面図には1次オリフラ(orientation flat)201及び2次オリフラ202が形成されたSiCウェハ200のSi面211が示されている。図37Bの[-1100]の方位から見た側面図では、上面に[0001]の方位のSi面211が形成され、下面に[000-1]の方位のC面212が形成されている。
SiC多結晶成長層18PCと、SiCエピタキシャル成長層12REとを備える。
SiCエピタキシャル成長層12REに適用可能な4H-SiC結晶のユニットセルの模式的鳥瞰構成は、図39Aに示すように表され、4H-SiC結晶の2層部分の模式的構成は、図39Bに示すように表され、4H-SiC結晶の4層部分の模式的構成は、図39Cに示すように表される。
上記のように、いくつかの実施の形態について記載したが、開示の一部をなす論述及び図面は例示的なものであり、限定するものであると理解すべきではない。この開示から当業者には様々な代替実施の形態、実施例及び運用技術が明らかとなろう。
2、2A…製造装置(縦型管状LP-CVD装置)
10SB…SiC単結晶基板
10HI…水素イオン注入層
10HE…単結晶SiC薄化層
10PI…リンイオン注入層
11GR、11GF…グラッフェン層
12E、12RE、12RE1、12RE2…SiCエピタキシャル成長層
12REN…高濃度ドープ層
13I…SiC単結晶層
13AS…アモルファスSi層
13ASC…アモルファスSiC層
15PS、15PS1、15PS2…多結晶Si層
15PSC、15PSC1、15PSC2…多結晶SiC層
17PI、17PI1、17PI2…接着層
17PIC1、17PIC2…炭化した接着層
18PC…SiC多結晶成長層
19GS…黒鉛基板
20CT…カーボントレイ
21…半導体装置(SiC-SBD)
22…カソード電極
23…活性領域
24…コンタクトホール
25…フィールド領域
26…フィールド絶縁膜
27…アノード電極
28…JTE構造
31…半導体装置(SiC-TMOSFET)
32、52…ドレイン電極
33、53…ボディ領域
34、54…ドレイン領域
35…ゲートトレンチ
36、57…ゲート絶縁膜
37、58…ゲート電極
38、55…ソース領域
39、56…ボディコンタクト領域
40、59…層間絶縁膜
41、60…コンタクトホール
42、61…ソース電極
51…半導体装置(SiC-MOSFET)
100…SiCエピタキシャル成長層の表面
100A、100B…成長炉
101…加熱部
102…インナーチューブ
103…断熱材
104…アウターチューブ
105…ガス拡散板
106…混合ガス出口弁
107…ガス混合予備室
108、109、110…ガス制御弁
112、113…ガス排気弁
114…排気用冷却装置(クーリングスカベンジャー)
200…SiCウェハ
200WP…SiCウェハペア
201…1次オリフラ
202…2次オリフラ
210…ウェハボート
211、[S]…Si面
212、[C]…C面
500…焼結SiC基板の製造装置
GS1、GS2、GS3、…、GSn…グラファイトシート
S…ソース端子
D…ドレイン端子
G…ゲート端子
A…アノード端子
K…カソード端子
GF…混合ガスの流れの方向
GFL…装置内のガスの流れの方向
GFEX…ガス排気の流れの方向
Claims (17)
- 成長炉と、
前記成長炉の外部に配置され、キャリアガス及び/又は材料ガスを混合及び調圧するガス混合予備室と、
SiC単結晶を備える基板2枚を背合わせに接触させた複数のSiCウェハペアを互いに隙間を空けて等間隔に配置できるように構成されたウェハボートと、
前記成長炉内に設置した前記ウェハボートをエピタキシャル成長温度まで加熱する加熱部と
を備え、
前記キャリアガス及び/又は前記材料ガスは、前記ガス混合予備室において事前に混合及び調圧を行った後に前記成長炉に導入し、複数の前記SiCウェハペアの表面にSiC層を成長させる、SiCエピタキシャルウェハの製造装置。 - 前記キャリアガス及び/又は前記材料ガスは、前記成長炉の下部から導入し、加熱された前記ウェハボート内に複数の前記SiCウェハペアが配置された場合、前記SiCウェハペアの表面を流れて上昇し、前記成長炉の上部で流れの方向を反転して降下し、前記成長炉の下部から真空排気される、請求項1に記載のSiCエピタキシャルウェハの製造装置。
- 前記ウェハボート内に複数の前記SiCウェハペアが配置された場合、前記キャリアガス及び/又は前記材料ガスの流れと前記SiCウェハペアの基板面とが平行となるように構成された、請求項1又は2に記載のSiCエピタキシャルウェハの製造装置。
- 前記ウェハボート内に複数の前記SiCウェハペアが配置された場合、前記キャリアガス及び/又は前記材料ガスの流れと前記SiCウェハペアの基板面とが垂直となるように構成された、請求項1又は2に記載のSiCエピタキシャルウェハの製造装置。
- 前記成長炉は、縦型構造を備える、請求項1~4のいずれか1項に記載のSiCエピタキシャルウェハの製造装置。
- 前記加熱部は、高周波加熱用コイル、抵抗加熱用ヒータ、又は加熱用ランプのいずれかを備える、請求項1~5の少なくともいずれか1項に記載のSiCエピタキシャルウェハの製造装置。
- 成長炉を設置する工程と、
キャリアガス及び/又は材料ガスを混合及び調圧するガス混合予備室を前記成長炉の外部に配置する工程と、
SiC単結晶を備える基板2枚を背合わせに接触させたSiCウェハペアを準備する工程と、
複数の前記SiCウェハペアを互いに隙間を空けてウェハボートに等間隔に配置する工程と、
前記成長炉内に前記ウェハボートを設置する工程と、
前記ウェハボートをエピタキシャル成長温度まで加熱する工程と、
前記キャリアガス及び/又は前記材料ガスを前記ガス混合予備室に導入する工程と、
前記ガス混合予備室において前記キャリアガス及び/又は前記材料ガスを事前に混合及び調圧する工程と、
前記キャリアガス及び/又は前記材料ガスの混合及び調圧を行った後に、前記キャリアガス及び/又は前記材料ガスを前記成長炉に導入する工程と、
複数の前記SiCウェハペアの表面にSiC層を成長させる工程と
を有する、SiCエピタキシャルウェハの製造方法。 - 前記キャリアガス及び/又は前記材料ガスは、前記成長炉の下部から導入し、
加熱された前記ウェハボート内の複数の前記SiCウェハペアの表面を流れて上昇し、
前記成長炉の上部で流れの方向を反転して降下し、
前記成長炉の下部から真空排気される、請求項7に記載のSiCエピタキシャルウェハの製造方法。 - 加熱開始からエピタキシャル成長温度に到達し成長を開始するまでの間は、アルゴン及び/又は窒素ガスを流す工程を有する、請求項7又は8に記載のSiCエピタキシャルウェハの製造方法。
- 前記キャリアガス及び/又は前記材料ガスは、前記ガス混合予備室において、混合かつ成長圧力に調整する工程と、
前記SiC層が成長を開始するタイミングで、前記キャリアガス及び/又は前記材料ガスの混合されたガスを前記成長炉へ導入する工程と
を有する、請求項7~9のずれか1項に記載のSiCエピタキシャルウェハの製造方法。 - 前記キャリアガスは、水素、アルゴン及び窒素ガスの少なくともいずれか1種を含み、
前記SiC層の成長中に前記キャリアガスとともに供給する前記材料ガスは、シリコンの水素化物、ハロゲン化物、ハロゲン化水素化物ガス及び、炭化水素化物ガスの少なくともいずれか1種を含む、請求項7~10のいずれか1項に記載のSiCエピタキシャルウェハの製造方法。 - 前記キャリアガス及び/又は前記材料ガスの混合されたガスを前記成長炉へ導入する際に、エピタキシャル成長温度に応じて、成長圧力、及び/又は、前記キャリアガス、及び、前記材料ガスの分圧比を調節して、グラッフェン層の層厚の変動を抑制する工程を有する、請求項7~11のいずれか1項に記載のSiCエピタキシャルウェハの製造方法。
- 前記成長炉内に、前記基板としてSiC単結晶基板を設置し、SiC表面熱分解法により前記SiC単結晶基板の上にグラッフェン層を形成する工程と、
前記グラッフェン層の上にSiCエピタキシャル成長層を形成する工程と
を有し、前記グラッフェン層を形成する工程と前記SiCエピタキシャル成長層を形成する工程は、前記成長炉内で連続して行う、請求項7~12のいずれか1項に記載のSiCエピタキシャルウェハの製造方法。 - 前記材料ガスは、SiH4、SiH3F、SiH2F2、SiHF3若しくはSiF4の少なくともいずれか1種のSi系ガスを有する、請求項7~13のいずれか1項に記載のSiCエピタキシャルウェハの製造方法。
- 前記材料ガスは、C3H8、C2H4、C2H2、CF4、C2F6、C3F8、C4F6、C4F8、C5F8、CHF3、CH2F2、CH3F、若しくはC2HF5の少なくともいずれか1種のCH系ガスを有する、請求項7~13のいずれか1項に記載のSiCエピタキシャルウェハの製造方法。
- 前記キャリアガスは、H2、Ar、N2、HCl、F2の少なくともいずれか1種を有するである、請求項8~15のいずれか1項に記載のSiCエピタキシャルウェハの製造方法。
- 前記SiC層はドーパントを有し、
前記ドーパントの原料は、n型ドーピング不純物としては、N(窒素)、P(リン)及び、As(ひ素)の内の少なくともいずれか1種、p型ドーピング不純物としては、B(ボロン)、Al(アルミニウム)、TMA(トリメチルアルミニウム)の内の少なくともいずれか1種を有する、請求項8~16のいずれか1項に記載のSiCエピタキシャルウェハの製造方法。
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