WO2018107616A1 - 复合衬底及其制造方法 - Google Patents

复合衬底及其制造方法 Download PDF

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WO2018107616A1
WO2018107616A1 PCT/CN2017/079048 CN2017079048W WO2018107616A1 WO 2018107616 A1 WO2018107616 A1 WO 2018107616A1 CN 2017079048 W CN2017079048 W CN 2017079048W WO 2018107616 A1 WO2018107616 A1 WO 2018107616A1
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substrate
gan
single crystal
amorphous
crystal layer
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French (fr)
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陈龙
李成
袁理
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上海新微技术研发中心有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02694—Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties

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  • the present invention relates to the field of semiconductor materials, and in particular to a composite substrate and a method of fabricating the same.
  • III-N materials represented by GaN are widely used in many applications, such as wide direct band gap, superior anti-radiation, high avalanche breakdown electric field, good thermal conductivity, and high electron drift rate under strong field. Various occasions.
  • the epitaxial film of the GaN-based LED is usually grown on a sapphire substrate, SiC, Si or the like due to the lack of a GaN substrate. So far, the epitaxial growth technology of GaN material systems is basically based on heterogeneous heteroepitaxial technology with large mismatch.
  • the main problems of the heteroepitaxial technology of sapphire substrate are: 1. Due to the large lattice mismatch and thermal stress mismatch between GaN and sapphire, it causes extremely high misfit dislocations, which seriously affects the crystal. Quality, reduce the reliability of the device; 2. Sapphire is an insulator, the resistivity is greater than 1011 ⁇ cm at room temperature, so that it is impossible to fabricate a vertical structure device. Usually, N-type and P-type electrodes can be fabricated on the upper surface of the epitaxial layer, which increases device preparation. The lithography and etching processes also reduce the material utilization rate; 3. The sapphire has poor thermal conductivity, and the thermal conductivity at 100 ° C is about 0.25 W/cmK. In large-area high-power devices, heat dissipation problems Very prominent; 4. Sapphire is very hard, difficult to handle later, usually requires laser stripping.
  • SiC substrate Although its crystal constant is the closest to GaN lattice constant and lattice mismatch is small, there are still misfit dislocations and thermal misfit dislocations, and thermal mismatch will further The microcracks of the epitaxial film during the cooling process are more important; more importantly, the SiC substrate is extremely expensive to manufacture and has significant difficulties in commercial applications.
  • the main problems of heteroepitaxial technology of Si substrate are: 1. 17% large lattice mismatch between GaN and silicon, resulting in high defect density; a large mismatch of thermal expansion coefficient of 2.54% leads to epitaxial film Cracks occur during the cooling process; 3. Metal Ga directly reacts with the silicon substrate to have a chemical remelting reaction.
  • GaN single crystal substrates directly limits its commercial applications in various device fields.
  • a 2-inch GaN single crystal substrate can reach a price of 2,000 US dollars, and a large-sized GaN single crystal substrate is technically more difficult to obtain, so such a
  • the huge cost completely limits the application of GaN single crystal substrates.
  • the technical problem to be solved by the present invention is to provide a composite substrate for epitaxial growth and a method of manufacturing the same.
  • the present invention provides a composite substrate comprising a support layer and a single crystal layer on the surface of the support layer, the support layer and the single crystal layer being a group III compound semiconductor, and the The material of the support layer is a polycrystalline or amorphous material.
  • the material of the support layer is selected from any one of polycrystalline AlN, amorphous AlN, polycrystalline GaN, and amorphous GaN.
  • the support layer has a thickness of between 150 um and 725 um.
  • the material of the single crystal layer is selected from any one of GaN, AlN, AlGaN/GaN stack, AlN/AlGaN/GaN stack, GaN/AlGaN/AlN stack, and GaN/AlGaN stack.
  • the material of the single crystal layer is selected from any one of GaN, AlN, AlGaN/GaN stack, AlN/AlGaN/GaN stack, GaN/AlGaN/AlN stack, and GaN/AlGaN stack.
  • the material of the single crystal layer is selected from any one of GaN, AlN, AlGaN/GaN stack, AlN/AlGaN/GaN stack, GaN/AlGaN/AlN stack, and GaN/AlGaN stack.
  • GaN/AlGaN stack GaN/AlGaN stack
  • the thickness of the single crystal layer ranges from 200 nm to 1000 nm.
  • a method of fabricating a composite substrate comprising the steps of: providing a first substrate having a surface of a single crystal layer and a second substrate having a surface of an amorphous or polycrystalline material, an amorphous or polycrystalline material and said single Each of the crystal layers is a group III compound semiconductor; implanting a bubble ion to the first substrate; and an intermediate layer of the surface of the single crystal layer of the first substrate and the surface of the amorphous or polycrystalline material of the second substrate Bonding the first substrate and the second substrate together; thermally bonding the bonded substrate, causing the first substrate to be peeled off at the bubble ion implantation to form a composite substrate, the composite liner
  • the bottom includes a single crystal layer disposed on the surface of the amorphous or polycrystalline material.
  • the foaming ions are selected from one or a combination of hydrogen ions and barium ions.
  • the material of the first substrate is single crystal silicon.
  • the amorphous or polycrystalline material is selected from any one of polycrystalline AlN, amorphous AlN, polycrystalline GaN, and amorphous GaN.
  • the material of the single crystal layer is selected from any one of GaN, AlN, AlGaN/GaN stack, AlN/AlGaN/GaN stack, GaN/AlGaN/AlN stack, and GaN/AlGaN stack. And formed on the surface of the first substrate in an epitaxial manner.
  • the thickness of the single crystal layer ranges from 200 nm to 1000 nm.
  • the surface of the composite substrate is a single crystal layer, and the homoepitaxial growth on the single crystal layer does not cause lattice mismatch or thermal expansion mismatch, and a material having high crystal quality can be obtained.
  • the support layer under the composite substrate is amorphous or polycrystalline layer with the same element, which is cheaper and has a thermal expansion coefficient matching with the single crystal layer, and the curvature of the substrate does not change due to the temperature rise and fall during the growth process. This avoids epitaxial film microcracking caused by thermal expansion mismatch. Therefore, the composite substrate provided by the present embodiment has better material properties than a heterogeneous substrate, and has a lower cost than a homogeneous substrate which is entirely a single crystal layer.
  • FIG. 1 is a schematic view showing the implementation steps of a specific embodiment of the method of the present invention.
  • FIGS. 2A through 2E are process flow diagrams showing an embodiment of the method of the present invention.
  • step S10 providing a first substrate having a surface of a single crystal layer and a second surface having an amorphous or polycrystalline material surface Substrate; step S11, injecting bubbling ions into the first substrate; and step S12, using the surface of the single crystal layer of the first substrate and the surface of the amorphous or polycrystalline material of the second substrate as an intermediate layer, The first substrate and the second substrate are bonded together; in step S13, the bonded substrate is heat-treated to cause the first substrate to peel off at the bubble ion implantation.
  • a first substrate 21 and a second substrate 22 are provided.
  • a surface of the first substrate 21 is provided with a single crystal layer 211 to obtain a first substrate 21 having a surface of a single crystal layer; and the second substrate 22 is entirely amorphous or multi-layered.
  • the single crystal layer 211 and the second substrate 22 are both group III compound semiconductors.
  • the thickness of the single crystal layer 211 ranges from 200 nm to 1000 nm.
  • a support layer may be disposed on the surface of the second substrate 22 to obtain a second substrate having a surface of an amorphous or polycrystalline material, the support layer being polycrystalline or amorphous.
  • the material is formed by means of epitaxy or bonding.
  • the single crystal layer 211 on the surface of the first substrate 21 may be formed by means of epitaxy or bonding.
  • the single crystal layer 211 may be formed by homoepitaxial or heteroepitaxial growth.
  • the second substrate 22 and the single crystal layer 211 are both group III compound semiconductors, and thus have a matching or close thermal expansion coefficient.
  • the material of the second substrate 22 is selected from any one of polycrystalline AlN, amorphous AlN, polycrystalline GaN, and amorphous GaN;
  • the material of the single crystal layer 211 is selected from GaN, AlN, AlGaN/GaN. Any of a laminate, an AlN/AlGaN/GaN stack, a GaN/AlGaN/AlN stack, and a GaN/AlGaN stack.
  • the material of the second substrate 22 may be selected from any one of polycrystalline Si, amorphous Si, polycrystalline GeSi, and amorphous GeSi; the material of the single crystal layer 211 is selected from Si, GeSi, and Any of the GeSi/Si stacks.
  • foaming ions are implanted into the first substrate 21.
  • the foaming ions are selected from one or a combination of hydrogen ions and barium ions.
  • the surface of the first substrate 21 has a single crystal layer 211, and the foaming ions are preferably implanted into other regions than the single crystal layer 211 of the first substrate 21, and the single crystal layer 211 The distance is from 100 nm to 400 nm to ensure the lattice integrity of the single crystal layer 211.
  • the surface of the single crystal layer of the first substrate 21 and the surface of the amorphous or polycrystalline material of the second substrate 22 are intermediate layers, and the first substrate and the first substrate are The two substrates are bonded together.
  • the bonding surface can be treated with nitrogen plasma prior to bonding, and bonded at a high temperature of 200 ° C to 500 ° C. The above method can enhance the bonding strength.
  • the bonded substrate is heat-treated to cause the first substrate 21 to be peeled off at the bubble ion implantation.
  • the heat treatment is preferably carried out in two steps, and the first step temperature is as low as 400 ° C to 850 ° C, and the main action is to form bubbles of the foaming ions and further peel off the first substrate.
  • the second step temperature is 850 ° C ⁇ 1380 ° C, the role is to strengthen the bonding strength of the bonding interface to form a covalent bond.
  • the stripped first substrate can also continue to be used for surface growth of the single crystal layer for recycling.
  • the single crystal layer 211 is separately provided on the surface of the first substrate 21, it is necessary to remove the first substrate 21 remaining on the surface of the single crystal layer 211.
  • One or a combination of processes such as grinding, polishing, dry etching, and wet etching may be selected to remove the remaining first substrate 21 to form a composite substrate.
  • the composite substrate includes a single crystal layer disposed on a surface of an amorphous or polycrystalline material.
  • the above-described step of removing the residual first substrate 21 can be omitted. If you want a smoother surface, you can Grinding and polishing are selected to achieve planarization.
  • the composite substrate obtained comprises a single crystal layer disposed on the surface of an amorphous or polycrystalline material.
  • the amorphous or polycrystalline material is provided by a second substrate 22 provided by a single crystal layer 211 of the first substrate 21.
  • the material of the second substrate 22 is selected from any one of polycrystalline AlN, amorphous AlN, polycrystalline GaN, and amorphous GaN;
  • the material of the single crystal layer 211 is selected from GaN, AlN, AlGaN/GaN. Any of a laminate, an AlN/AlGaN/GaN stack, a GaN/AlGaN/AlN stack, and a GaN/AlGaN stack.
  • the material of the second substrate 22 may be selected from any one of polycrystalline Si, amorphous Si, polycrystalline GeSi, and amorphous GeSi; the material of the single crystal layer 211 is selected from Si, GeSi, and Any of the GeSi/Si stacks.
  • the thickness of the single crystal layer 211 ranges from 200 nm to 1000 nm.
  • the surface of the composite substrate is a single crystal layer, and the homoepitaxial growth on the single crystal layer does not cause lattice mismatch or thermal expansion mismatch, and a material having high crystal quality can be obtained.
  • the support layer under the composite substrate is amorphous or polycrystalline layer with the same element, which is cheaper and has a thermal expansion coefficient matching with the single crystal layer, and the curvature of the substrate does not change due to the temperature rise and fall during the growth process. This avoids epitaxial film microcracking caused by thermal expansion mismatch. Therefore, the composite substrate provided by the present embodiment has better material properties than a heterogeneous substrate, and has a lower cost than a homogeneous substrate which is entirely a single crystal layer.
  • a structure of GaN/HT-AlN/LT-AlN/Si (111) is formed by epitaxial layer of a single crystal GaN-based thin film on a P-type Si (111) substrate by MOCVD. Specific steps are as follows:
  • a 400 nm single crystal GaN layer was grown at 1050 ° C under 200 mbar.
  • H+500 keV and 5E16 cm-3 were implanted into the Si substrate at a distance of 200 nm from the interface between Si and single crystal GaN.
  • the bonding surface was treated with nitrogen plasma and vacuum bonded.
  • the bonding atmosphere pressure was 0.01 Pa
  • the temperature was 250 ° C
  • the bonding was carried out for 10 min.
  • the support substrate is made of polycrystalline GaN, 450 um thick, and has a thermal expansion coefficient close to that of single crystal GaN.
  • High temperature annealing The annealing environment is nitrogen, the temperature is 450 ° C, lasting 60 minutes, and the environment is atmospheric pressure. Again The temperature was raised to 1200 ° C, the annealing environment was nitrogen for 120 minutes, and the environment was atmospheric pressure.
  • the LT-AlN/HT-AlN/single-crystal GaN/polycrystalline GaN structure was formed by etching with a 15% TMAH etching solution at 75 ° C for 5 minutes to remove residual silicon. Further, CMP polishing was performed to the single crystal GaN layer to form a composite substrate of single crystal GaN and polycrystalline GaN having a thickness of 300 nm.

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Abstract

一种复合衬底的制造方法，包括如下步骤：提供一具有单晶层（211）表面第一衬底（21）和一具有非晶或多晶材料表面的第二衬底（22），非晶或多晶材料与单晶层均为III族化合物半导体；注入起泡离子至第一衬底；以第一衬底的单晶层表面和第二衬底的非晶或多晶材料表面为中间层，将第一衬底和第二衬底键合在一起；热处理键合后衬底，使第一衬底在起泡离子注入处发生剥离而形成复合衬底，复合衬底包括设置在非晶或多晶材料表面的单晶层。

Description

复合衬底及其制造方法 技术领域
本发明涉及半导体材料领域，尤其涉及一种复合衬底及其制造方法。
背景技术
以GaN为代表的III-N族材料具有宽直接带隙、优越的抗辐噪性、高雪崩击穿电场、良好的热传导率以及强场下高电子漂移速率等众多优良特性，被广泛应用于各种场合。
对于现在的GaN基半导体材料器件来讲，由于缺少GaN衬底，通常GaN基LED的外延膜主要是生长在蓝宝石衬底、SiC、Si等衬底上。到目前为止，GaN材料体系的外延生长技术，基本是基于大失配的异质外延技术。
蓝宝石衬底的异质外延技术，其主要问题是：1.由于GaN和蓝宝石之间有较大的晶格失配和热应力失配，由此造成极高的失配位错，严重影响晶体质量，降低器件的可靠性；2.蓝宝石是绝缘体，常温下电阻率大于1011Ωcm，这样就无法制作垂直结构的器件，通常只能在外延层上表面制作N型和P型电极，增加了器件制备中的光刻和刻蚀工艺过程，也降低了材料的利用率；3.蓝宝石的导热性能不好，在100℃热导率约为0.25W/cmK，在大面积大功率器件中，散热问题非常突出；4.蓝宝石硬度很高，后续难以处理，通常需要激光剥离。
SiC衬底的异质外延技术：虽然其晶体常数与GaN晶格常数最为相近，晶格失配较小，但仍然存在失配位错及热失配位错，热失配则更进一步地会造成外延膜在降温过程中的微裂纹；更为重要的是，SiC衬底造价极其昂贵，在商用领域应用中存在明显困难。
Si衬底的异质外延技术，其主要问题是：1.GaN与硅之间的17％大晶格失配，造成很高的缺陷密度；2.54％的热膨胀系数的巨大失配导致外延膜在降温过程中产生裂纹；3.金属Ga直接与硅衬底接触时会有化学回融反应。
因此，对于晶体外延而言，同质外延能够获得完全匹配的晶格、和同样的热膨胀系数，是外延的最佳选择。然而，GaN单晶衬底高昂的价格直接制约了其在各类器件领域的商业应用。目前，一片2英寸GaN单晶衬底价格可以达到2000美金，大尺寸的GaN单晶衬底在技术上更是难以获得，所以，这样的 巨大成本完全限制了GaN单晶衬底的应用。
发明内容
本发明所要解决的技术问题是，提供一种用于外延生长的复合衬底及其制造方法。
为了解决上述问题，本发明提供了一种复合衬底，包括一支撑层和所述支撑层表面的单晶层，所述支撑层与所述单晶层均为III族化合物半导体，且所述支撑层的材料为多晶或非晶材料。
可选的，所述支撑层的材料选自于多晶AlN、非晶AlN、多晶GaN和非晶GaN中的任意一种。
可选的，所述支撑层厚度介于150um-725um。
可选的，所述单晶层的材料选自于GaN、AlN、AlGaN/GaN叠层、AlN/AlGaN/GaN叠层、GaN/AlGaN/AlN叠层、和GaN/AlGaN叠层中的任意一种。
可选的，所述单晶层的厚度范围是200nm至1000nm。
一种复合衬底的制造方法，包括如下步骤：提供一具有单晶层表面第一衬底和一具有非晶或多晶材料表面的第二衬底，非晶或多晶材料与所述单晶层均为III族化合物半导体；；注入起泡离子至所述第一衬底；以所述第一衬底的单晶层表面和第二衬底的非晶或多晶材料表面为中间层，将所述第一衬底和第二衬底键合在一起；热处理键合后衬底，使所述第一衬底在起泡离子注入处发生剥离而形成复合衬底，所述复合衬底包括设置在非晶或多晶材料表面的单晶层。
可选的，所述起泡离子选自于氢离子和氦离子中的一种或者两者的组合。
可选的，所述第一衬底的材料是单晶硅。
可选的，所述非晶或多晶材料选自于多晶AlN、非晶AlN、多晶GaN和非晶GaN中的任意一种。
可选的，所述单晶层的材料选自于GaN、AlN、AlGaN/GaN叠层、AlN/AlGaN/GaN叠层、GaN/AlGaN/AlN叠层、和GaN/AlGaN叠层中的任意一种，并以外延的方式形成于所述第一衬底表面。
可选的，所述单晶层的厚度范围是200nm至1000nm。
上述复合衬底表面为单晶层，在该单晶层上继续同质外延不会造成晶格失配或热膨胀失配，可以获得高晶体质量的材料。而复合衬底下的支撑层由于是采用相同元素的非晶或多晶层，成比低廉且具有与单晶层相匹配热膨胀系数，在生长过程中不会由于升降温导致衬底曲率发生变化，这就避免了热膨胀失配引起的外延膜微裂纹。故本具体实施方式提供的复合衬底相比异质衬底具有更好的材料性能，相比全部为单晶层的同质衬底具有更低的成本。
附图说明
附图1所示是本发明所述方法的一具体实施方式的实施步骤示意图。
附图2A至附图2E所示是本发明所述方法的一具体实施方式的工艺流程图。
具体实施方式
下面结合附图对本发明提供的复合衬底及其制造方法的具体实施方式做详细说明。
附图1所示是本发明所述方法的一具体实施方式的实施步骤示意图，包括：步骤S10，提供一具有单晶层表面第一衬底和一具有非晶或多晶材料表面的第二衬底；步骤S11，注入起泡离子至所述第一衬底；步骤S12，以所述第一衬底的单晶层表面和第二衬底的非晶或多晶材料表面为中间层，将所述第一衬底和第二衬底键合在一起；步骤S13，热处理键合后衬底，使所述第一衬底在起泡离子注入处发生剥离。
附图2A所示，参考步骤S10，提供一第一衬底21和一第二衬底22。在本具体实施方式中，所述第一衬底21的表面设置一单晶层211以获得具有单晶层表面第一衬底21；所述第二衬底22则整体是一非晶或者多晶衬底。单晶层211和第二衬底22均为III族化合物半导体。所述单晶层211的厚度范围是200nm至1000nm。在另一具体实施方式中，也可以是所述第二衬底22的表面设置一支撑层以获得具有非晶或多晶材料表面的第二衬底，所述支撑层为多晶或非晶材料，并是通过外延或者键合等手段形成。所述第一衬底21表面的单晶层211可以是通过外延或者键合等手段形成的。对于通过外延形成单晶层 211的具体实施方式，可以是同质外延或者异质外延形成单晶层211。
所述第二衬底22与所述单晶层211均为III族化合物半导体，因此具有匹配或接近的热膨胀系数。例如所述第二衬底22的材料选自于多晶AlN、非晶AlN、多晶GaN和非晶GaN中的任意一种；单晶层211的材料选自于GaN、AlN、AlGaN/GaN叠层、AlN/AlGaN/GaN叠层、GaN/AlGaN/AlN叠层、和GaN/AlGaN叠层中的任意一种。也可以是所述第二衬底22的材料选自于多晶Si、非晶Si、多晶GeSi和非晶GeSi中的任意一种；单晶层211的材料选自于Si、GeSi、以及GeSi/Si叠层中的任意一种。
附图2B所示，参考步骤S11，注入起泡离子至所述第一衬底21。所述起泡离子选自于氢离子和氦离子中的一种或者两者的组合。本具体实施方式中，所述第一衬底21的表面具有单晶层211，所述起泡离子优选注入至第一衬底21的单晶层211以外的其他区域，并与单晶层211距离100nm至400nm，以保证单晶层211的晶格完整性。
附图2C所示，参考步骤S12，以所述第一衬底21的单晶层表面和第二衬底22的非晶或多晶材料表面为中间层，将所述第一衬底和第二衬底键合在一起。在键合前可以采用氮等离子体处理键合表面，并采用200℃～500℃高温键合，以上方法可以加强键合强度。
附图2D所示，参考步骤S13，热处理键合后衬底，使所述第一衬底21在起泡离子注入处发生剥离。热处理优选为两步实施，第一步温度较低，为400℃到850℃，主要作用形成使起泡离子形成气泡，并进一步使第一衬底发生剥离。第二步温度为850℃～1380℃，作用是加强键合界面的键合强度，形成共价键。剥离后的第一衬底还可以继续用于表面生长单晶层，做到循环利用。
继续参考附图2E所示，对于在所述第一衬底21的表面单独设置单晶层211的具体实施方式，还需要将单晶层211表面残留的第一衬底21除去。可以选择研磨、抛光、干法刻蚀、和湿法腐蚀等工艺中的一种或者几种的组合，以去除残留的第一衬底21，进而形成复合衬底。所述复合衬底包括设置在非晶或多晶材料表面的单晶层。对于第一衬底21整体是一单晶衬底的具体实施方式，上述去除残余第一衬底21的步骤可省略。若希望获得更为平整的表面，可以 选择实施研磨和抛光以实现平坦化。
所获得的复合衬底包括设置在非晶或多晶材料表面的单晶层。所述非晶或多晶材料由第二衬底22提供，单晶层由第一衬底21的单晶层211提供。例如所述第二衬底22的材料选自于多晶AlN、非晶AlN、多晶GaN和非晶GaN中的任意一种；单晶层211的材料选自于GaN、AlN、AlGaN/GaN叠层、AlN/AlGaN/GaN叠层、GaN/AlGaN/AlN叠层、和GaN/AlGaN叠层中的任意一种。也可以是所述第二衬底22的材料选自于多晶Si、非晶Si、多晶GeSi和非晶GeSi中的任意一种；单晶层211的材料选自于Si、GeSi、以及GeSi/Si叠层中的任意一种。所述单晶层211的厚度范围是200nm至1000nm。
上述复合衬底表面为单晶层，在该单晶层上继续同质外延不会造成晶格失配或热膨胀失配，可以获得高晶体质量的材料。而复合衬底下的支撑层由于是采用相同元素的非晶或多晶层，成比低廉且具有与单晶层相匹配热膨胀系数，在生长过程中不会由于升降温导致衬底曲率发生变化，这就避免了热膨胀失配引起的外延膜微裂纹。故本具体实施方式提供的复合衬底相比异质衬底具有更好的材料性能，相比全部为单晶层的同质衬底具有更低的成本。
以下给出一实施例对上述具体实施方式做具体说明。实施例的工艺参数仅用于举例说明，不用于限定本发明的任何内容。
在一P型Si(111)衬底上采用MOCVD外延单晶GaN基薄膜外延层，形成GaN/HT-AlN/LT-AlN/Si(111)的结构。具体步骤如下：
1.在750℃，60mbar条件下，生长20nm的LT-AlN成核层；
2.在1080℃，50mbar条件下，生长160nm的HT-AlN缓冲层；
3.在1050℃，200mbar条件下，生长400nm的单晶GaN层。
采用H+500keV,5E16cm-3注入到Si衬底中，与Si与单晶GaN界面距离200nm处。
氮等离子体处理键合表面，并真空键合。键合环境气压为0.01Pa，温度250℃，键合10min。支撑衬底采用多晶GaN，厚450um，热膨胀系数与单晶GaN接近。
高温退火。退火环境为氮气，温度450℃，持续60分钟，环境为常压。再 升温到1200℃，退火环境为氮气，持续120分钟，环境为常压。
采用15％TMAH腐蚀液，在75℃环境下腐蚀5分钟以去除残余的硅，形成LT-AlN/HT-AlN/单晶GaN/多晶GaN结构。再使用CMP抛光至单晶GaN层，形成300nm厚度的单晶GaN与多晶GaN形成的复合衬底。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (10)

  1. 一种复合衬底，包括一支撑层和所述支撑层表面的单晶层，其特征在于，所述支撑层与所述单晶层均为III族化合物半导体，且所述支撑层的材料为多晶或非晶材料。
  2. 根据权利要求1所述的复合衬底，其特征在于，所述支撑层的材料选自于多晶AlN、非晶AlN、多晶GaN和非晶GaN中的任意一种。
  3. 根据权利要求1所述的复合衬底，其特征在于，所述单晶层的材料选自于GaN、AlN、AlGaN/GaN叠层、AlN/AlGaN/GaN叠层、GaN/AlGaN/AlN叠层、和GaN/AlGaN叠层中的任意一种。
  4. 根据权利要求1所述的复合衬底，其特征在于，所述单晶层的厚度范围是200nm至1000nm。
  5. 一种复合衬底的制造方法，其特征在于，包括如下步骤：
    提供一具有单晶层表面第一衬底和一具有非晶或多晶材料表面的第二衬底，非晶或多晶材料与所述单晶层均为III族化合物半导体；
    注入起泡离子至所述第一衬底；
    以所述第一衬底的单晶层表面和第二衬底的非晶或多晶材料表面为中间层，将所述第一衬底和第二衬底键合在一起；
    热处理键合后衬底，使所述第一衬底在起泡离子注入处发生剥离而形成复合衬底，所述复合衬底包括设置在非晶或多晶材料表面的单晶层。
  6. 根据权利要求5所述的方法，其特征在于，所述起泡离子选自于氢离子和氦离子中的一种或者两者的组合。
  7. 根据权利要求5所述的方法，其特征在于，所述第一衬底的材料是单晶硅。
  8. 根据权利要求5所述的方法，其特征在于，所述非晶或多晶材料选自于多晶AlN、非晶AlN、多晶GaN和非晶GaN中的任意一种。
  9. 根据权利要求5所述的方法，其特征在于，所述单晶层的材料选自于GaN、AlN、AlGaN/GaN叠层、AlN/AlGaN/GaN叠层、GaN/AlGaN/AlN叠层、和GaN/AlGaN叠层中的任意一种，并以外延的方式形成于所述第一衬底表面。
  10. 根据权利要求5所述的方法，其特征在于，所述单晶层的厚度范围是200nm 至1000nm。
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