WO2022161248A1 - 一种晶圆级系统封装结构及封装方法 - Google Patents

一种晶圆级系统封装结构及封装方法 Download PDF

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Publication number
WO2022161248A1
WO2022161248A1 PCT/CN2022/072998 CN2022072998W WO2022161248A1 WO 2022161248 A1 WO2022161248 A1 WO 2022161248A1 CN 2022072998 W CN2022072998 W CN 2022072998W WO 2022161248 A1 WO2022161248 A1 WO 2022161248A1
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WO
WIPO (PCT)
Prior art keywords
wafer
device wafer
chip
opening
level system
Prior art date
Application number
PCT/CN2022/072998
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English (en)
French (fr)
Inventor
黄河
向阳辉
刘孟彬
Original Assignee
中芯集成电路（宁波）有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Priority claimed from CN202110130763.8A external-priority patent/CN114823390A/zh
Priority claimed from CN202110130767.6A external-priority patent/CN114823393A/zh
Priority claimed from CN202110129191.1A external-priority patent/CN114823382A/zh
Priority claimed from CN202110130771.2A external-priority patent/CN114823394A/zh
Priority claimed from CN202110129171.4A external-priority patent/CN114823379A/zh
Priority claimed from CN202110130764.2A external-priority patent/CN114823391A/zh
Priority claimed from CN202110129133.9A external-priority patent/CN114823377A/zh
Priority claimed from CN202110129150.2A external-priority patent/CN114823378A/zh
Priority claimed from CN202110129185.6A external-priority patent/CN114823381A/zh
Application filed by 中芯集成电路（宁波）有限公司 filed Critical 中芯集成电路（宁波）有限公司
Publication of WO2022161248A1 publication Critical patent/WO2022161248A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

Definitions

  • the invention relates to the field of semiconductor packaging, in particular to a wafer-level system packaging structure and packaging method.
  • System-level packaging uses any combination to combine multiple active components/devices, passive components/devices, MEMS devices, discrete KGD (Known Good Die) with different functions and prepared by different processes, such as optoelectronic chips, biochips, etc., It is integrated and assembled in three dimensions (X direction, Y direction and Z direction) into a single standard package with a multi-layer device structure and can provide multiple functions to form a system or subsystem.
  • KGD known Good Die
  • the system-in-package method includes: providing a PCB circuit board, wherein solder balls arranged according to certain requirements are formed on the PCB circuit board (formed by a ball mounting process); dipping flux on the circuit board, and then flip-chip mounting the chip The chip is placed on the circuit board; the pads on the chip are electrically connected to the solder balls on the circuit board by the reflow process; after that, the bottom of the chip and the circuit board are filled with glue to increase the overall structure mechanical strength.
  • the existing system-level packaging method has the following disadvantages: 1. The process is complicated, resulting in low packaging efficiency; 2. Each chip needs to be welded on the solder balls in sequence, and the packaging efficiency is low; 3. The chip needs to be realized by a welding process The electrical connection with the PCB board is not compatible with the process in the front section of the package; 4. When a large pressure is applied accidentally during the process of dipping the flux, it is easy to cause the circuit board to crack.
  • the invention discloses a wafer-level system packaging structure and packaging method, which can solve the problem of low packaging efficiency.
  • the present invention provides a wafer-level system packaging method, including: providing a first device wafer or a plurality of first chips, the lower surface of the first device wafer or the first chips There are a plurality of exposed first pads, the first device wafer has a plurality of first device modules inside, the first pads are electrically connected to the first device modules; a second device wafer is provided, the A plurality of second device modules are formed inside the second device wafer, the second device wafer includes opposite upper and lower surfaces, and the upper surface exposes a plurality of second device modules that are electrically connected to the second device modules.
  • an adhesive layer is formed on the upper surface of the second device wafer, the lower surface of the first device module or the lower surface of the first chip, and the first device is bonded to the first device through the adhesive layer
  • the wafer or the first chip is bonded to the second device wafer, and the first pad and the second pad are relatively surrounded to form a gap; an electroplating process is used to form conductive bumps in the gap block to electrically connect the first pad and the second pad.
  • the present invention also provides a wafer-level system packaging structure, comprising: a first device wafer or a plurality of first chips, the lower surface of the first device wafer or the first chip has a plurality of bonding pads, A plurality of first device modules are formed inside the first device wafer, and the first pads are electrically connected to the first device modules; and a second device wafer is formed inside the second device wafer.
  • the second device wafer includes opposing upper and lower surfaces, the upper surface has a plurality of second pads electrically connected to the second device module, the first device wafer Or the first chip is bonded to the upper surface of the second device wafer through an adhesive layer; conductive bumps are formed between the oppositely disposed first pads and the second pads by an electroplating process. between.
  • the beneficial effect of the present invention is that the present invention forms the conductive bumps through the electroplating process, so as to realize the electrical connection between the first bonding pad and the second bonding pad.
  • the process of the present invention is simple and the packaging efficiency is high; second, when the first device wafer is provided, a plurality of first device modules are located in the first device. In the wafer, a plurality of second device modules are located in the second device wafer.
  • the electroplating process is compatible with the process in the front-end of the packaging, and the traditional chip manufacturing process can be used to realize the wafer-level system packaging.
  • forming the cavity through the adhesive layer can save process steps (otherwise the cavity needs to be formed when the device module and/or the first chip is fabricated).
  • the second opening formed on the second device wafer is used to satisfy the cavity environment in which the first device module or the first chip works, so that while the system integration is completed, it is compatible with the cavity of the first device module or the first chip. Cavity requirements are reduced, the packaging height of the system is reduced, and additional capping is avoided, which saves process steps and reduces costs.
  • the physical connection between the first chip or the first device wafer and the second device wafer is realized by a photolithographic bonding material, using the second opening formed on the second device wafer and the second opening formed in the adhesive layer.
  • the first opening satisfies the cavity environment in which the first device module or the first chip works, and can realize both patterning to form the first cavity and bonding, simplifying the process, and covering the first cavity with photolithographic bonding materials.
  • a region around the cavity directly enhances the mechanical strength of the entire structure.
  • the connection between the first chip and the second device wafer is realized, the height of device integration is reduced, and the space is increased. utilization, improve the integration of the device.
  • the physical connection between the first device wafer or the first chip and the second device wafer is realized by a photolithographic bonding material, and the photolithographic bonding material covers the peripheral area of the conductive bump, which directly strengthens the The mechanical strength of the entire structure is improved, and the filling and gluing process of the prior art can be omitted.
  • the plastic packaging material does not need to fill the gap between the first device module or the first chip and the second device wafer, thereby saving time in the plastic packaging process.
  • the photolithographic bonding material of the dry film material due to its relatively small elastic modulus, can be easily deformed without being damaged when subjected to thermal stress, thereby reducing the size of the first device wafer or the first chip and the second device. Bond stress between wafers.
  • the photolithographic bonding material can limit the positions of the conductive bumps to prevent lateral overflow of the conductive bumps in the electroplating process.
  • first bonding pad and the second bonding pad adopt a dislocation design in the direction perpendicular to the surface of the second device wafer, the area of the overlapping area is greater than half of the area of the first bonding pad or the second bonding pad, and the dislocation design can prevent electroplating.
  • the conductive bumps do not fill the voids.
  • the dislocation design ensures a certain bonding strength on the basis of ensuring that the conductive bumps fill the gaps.
  • the height of the void is 5-200 microns, it not only satisfies that the electroplating solution can easily enter the void for electroplating, but also avoids the problem that the height of the void is too high and leads to a long electroplating time, thus taking into account the electroplating efficiency and electroplating yield. .
  • the photolithographic bonding material when its projection is centered on the center of the first device module or the first chip, and the coverage area is greater than 10% of the area of the first device module or the first chip, preferably covering the first device.
  • the entire lower surface of the module or the first chip except the area where the first pad is located), so that when the plastic packaging layer is formed in the subsequent process, it is ensured that there is no gap under the first device module or the first chip, which improves the bonding strength and improves the yield. .
  • FIG. 1 to 4 are schematic structural diagrams corresponding to different steps of a wafer-level system packaging method according to Embodiment 1 of the present invention.
  • FIG. 5-7 are schematic structural diagrams corresponding to different steps of a wafer-level system packaging method according to Embodiment 2 of the present invention.
  • FIGS. 8-11 are schematic structural diagrams corresponding to different steps of a wafer-level system packaging method according to Embodiment 3 of the present invention.
  • FIGS. 12-13 are schematic structural diagrams corresponding to different steps of a wafer-level system packaging method according to Embodiment 4 of the present invention.
  • FIGS. 14-18 are schematic structural diagrams corresponding to different steps of a wafer-level system packaging method according to Embodiment 5 of the present invention.
  • FIG. 19 shows a schematic structural diagram corresponding to different steps of a wafer-level system packaging method according to Embodiment 6 of the present invention.
  • FIG. 20 shows a schematic structural diagram corresponding to different steps of a wafer-level system packaging method according to Embodiment 7 of the present invention.
  • FIG. 21 shows a schematic structural diagram corresponding to different steps of a wafer-level system packaging method according to Embodiment 8 of the present invention.
  • 22-24 are schematic structural diagrams corresponding to different steps of a wafer-level system packaging method according to Embodiment 9 of the present invention.
  • This embodiment provides a wafer-level system packaging method, including the following steps: S101 : providing a first device wafer 20 or a plurality of first chips 201 ′, and the lower part of the first device wafer 20 or the first chips 201 ′ is provided.
  • the surface has a plurality of exposed first bonding pads 21
  • the first device wafer 20 has a plurality of first device modules 201 inside, and the first bonding pads 21 are electrically connected to the first device modules 201
  • S102 providing the second device wafer 10 , a plurality of second device modules 101 are formed inside the second device wafer 10 , the second device wafer 10 includes opposite upper and lower surfaces, and the upper surface exposes a plurality of second solder joints electrically connected to the second device modules 101 Pad 11
  • S103 forming an adhesive layer on the upper surface of the second device wafer 10, the lower surface of the first device module 201 or the lower surface of the first chip 201', and the first device wafer 20 or the first device wafer 20 or The first chip 201 ′ is bonded to the second device wafer 10 , and the first bonding pad 21 and the second bonding pad 11 are relatively surrounded by a gap
  • S104 use an electroplating process to form conductive bumps 30 in the gap for electrical connection
  • FIGS. 1 to 4 are schematic structural diagrams corresponding to different steps of the wafer-level system packaging method of the present embodiment. Please refer to FIGS. 1 to 4 .
  • the packaging of the first device wafer and the second device wafer is taken as an example for details. Each step is explained.
  • a first device wafer 20 is provided.
  • the first device wafer 20 is a wafer to be packaged after device fabrication is completed.
  • the first device wafer 20 can be fabricated by an integrated circuit fabrication technology, such as on a semiconductor substrate.
  • NMOS devices, PMOS devices, resistors, diodes or triodes are formed through deposition, etching and other processes, and structures such as a dielectric layer, a metal interconnection structure, and a pad electrically connected to the metal interconnection structure are formed on the device, so that the first A plurality of first device modules 201 are integrated in the device wafer 20 .
  • the first pad 21 is an electrical lead-out structure of the first device module 201 , which may be a pad or other conductive blocks with an electrical connection function.
  • a dielectric layer 12 exposing the first pads 21 is formed on the front surface of the first device wafer 20 .
  • the dielectric layer 12 has a certain thickness so that the first pads 21 are recessed on the surface of the first device wafer 20 .
  • the semiconductor substrate can be silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, etc., and the semiconductor substrate can also be other types of substrates, such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. .
  • the semiconductor substrate may be a material suitable for process requirements or ease of integration.
  • the first device module 201 includes a bare chip, a chip with a plastic encapsulation layer, a chip with a shielding layer on the top surface, and a chip with an electrical terminal on the top surface, for example, the first device wafer is a thinned bare chip wafer, or The non-pad surface of the wafer is covered with a plastic encapsulation layer or a shielding layer, or a typical lead-out terminal such as an electrical connection structure or a plug connected to the electrical connection structure is provided on the non-pad surface of the wafer.
  • the first device module 201 includes at least one of a logic chip, a memory chip, a central processing unit chip, a microprocessor chip, and an analog-to-digital conversion chip, or the first device module includes a microphone, a pressure sensor, a gyroscope, a speed sensor, an acceleration sensor At least one MEMS chip in the sensor, a sensor chip for sensing one of radio frequency signals, infrared radiation signals, visible light signals, acoustic wave signals, and electromagnetic wave signals, the chip has a cavity or does not contain a cavity, or the first device
  • the module includes a PN junction device with at least one of CMOS, CIS, diode, and triode, or the first device module includes a passive device at least one of inductor, capacitor, filter, MLCC, and connector.
  • the types of the plurality of first device modules 201 may be the same or different.
  • the sensor chip can be a radio frequency module chip used in 5G equipment, but is not limited to a 5G radio frequency sensor module chip, and can also be other types of radio frequency module chips.
  • the module chip that receives the infrared radiation signal may be an infrared sensor module chip that utilizes the infrared radiation signal, such as a thermal imager, a forehead temperature gun, and other types of temperature measurement or imaging.
  • the sensor module chip can also be a camera module chip, such as a module chip including a photosensitive chip and a filter, which can receive visible light for imaging.
  • the sensor module chip can also be a microphone module chip, which can receive sound waves to transmit sound signals.
  • the sensor module chips in the present invention are not limited to the types listed here, and can be various types of sensor module chips that can achieve certain functions in the art.
  • the MEMS chip includes at least one of a microphone, a pressure sensor, a gyroscope, a speed sensor, an acceleration sensor, and a thermopile sensor.
  • the filter chip includes at least one of a surface acoustic wave resonator and a bulk acoustic wave resonator.
  • MLCC chips include: NP0, C0G, Y5V, Z5U, X7R, X5R and other capacitors.
  • the second device wafer 10 is a wafer to be packaged after the device fabrication is completed.
  • the second device wafer 10 can be fabricated by using integrated circuit fabrication technology.
  • the structure type is also referred to the first device module 201 , which is not repeated here.
  • an adhesive layer is formed by using a photolithographic bonding material 40 to bond the first device wafer 20 to the upper surface of the second device wafer 10 , so that the first bonding pads 21 A gap is formed relative to the second pad 11 .
  • the photolithographic bonding material 40 can be formed on the surface of the first device wafer 20 , can also be formed on the surface of the second device wafer 10 , and can also be formed on the first device wafer 20 and the second device wafer 10 .
  • the photolithographic bonding material 40 is each formed.
  • the photolithographic bonding material 40 includes a film-like dry film or a liquid dry film, and may also include other photosensitive adhesive materials.
  • the film-like dry film is to coat the solvent-free photoresist on the polyester film base, and then cover it with polyethylene film; when using, remove the polyethylene film, and press the solvent-free photoresist on the first device.
  • a pattern can be formed in the dry film.
  • Liquid dry film means that the components in the film-like dry film exist in liquid form.
  • dry film is a permanently bonded film with high bond strength.
  • the film-like dry film may be formed on the first device wafer 20 and/or the second device wafer 10 by means of film sticking, and the liquid dry film may be coated on the first device wafer 20 and/or the second device wafer 10 by a spin coating process On the wafer 10, the liquid dry film is then cured.
  • the bonding material can also be a die attach film (Die attach film), a film-like material with double-sided adhesiveness, which can be patterned by etching or laser ablation; it can also be a dielectric layer, such as silicon oxide A compound or nitride that connects the first device wafer and the second device wafer by fusion bonding; or a polymer material. It can also be a combination of materials, such as metal and polymer arranged side by side. In other embodiments, the bonded material can also be a photosensitive material, so that patterning can be achieved through a photolithography process, so that the counter electrode or external interconnection can be reduced. damage to the line.
  • Die attach film die attach film
  • a film-like material with double-sided adhesiveness which can be patterned by etching or laser ablation
  • it can also be a dielectric layer, such as silicon oxide A compound or nitride that connects the first device wafer and the second device wafer by fusion bonding
  • a polymer material can also be
  • the dry film needs to be subjected to a patterning process to expose the first pads 21 of the first device wafer 20 and the second pads 11 of the second device wafer 10, through the dry film
  • the first device wafer 20 and the second device wafer 10 are bonded.
  • the dry film is a photolithographic material, which can form a desired pattern through a semiconductor process. The process is simple and compatible with the semiconductor process, and can be mass-produced. Moreover, the elastic modulus of the dry film is relatively small, which can be easily deformed without being damaged when subjected to thermal stress, thereby reducing the bonding stress between the first device wafer 20 and the second device wafer 10 .
  • the thickness of the photolithographic bonding material 40 is 5-200 ⁇ m, such as 15 ⁇ m, 30 ⁇ m, 80 ⁇ m, 150 ⁇ m, and the like. It not only satisfies that the electroplating solution can easily enter the gap for electroplating, but also avoids the problem that the height of the gap is too high and leads to a long electroplating time, thus taking into account the electroplating efficiency and the electroplating yield.
  • the projection of the photolithographic bonding material 40 on the surface direction of the second device wafer 10 is centered on the center of the first device module 201 and covers at least 10% of the area of the first device module 201 .
  • the photoetchable bonding material 40 of this solution not only plays a role of bonding, but also plays a role of sealing in advance.
  • the photoetchable bonding material 40 and the plastic sealing layer in the subsequent process jointly play the role of sealing the first device module. effect.
  • the photolithographic bonding material 40 covers the entire lower surface of the first device module (except the area where the first pad and the second pad are located), so that when the plastic encapsulation layer is formed in the subsequent process, the first There is no gap under the device module, which improves the bonding strength and improves the yield.
  • the photoetchable bonding material 40 is provided with fluid channels communicating with the voids.
  • the lithographic bonding material 40 surrounds the first bonding pad 21 or the second bonding pad 11 , but a fluid channel is left to connect the gap to the edge of the chip.
  • the fluid channel may pass through the lithographic bonding material 40 or not. or the lithographic bonding material 40 does not surround or completely surround the first pad 21 or the second pad 11 , and the unsurrounded part communicates with the outside world as a fluid channel.
  • the gap communicates with the outside, and can also be used as a fluid channel; optionally, a channel is left in the photolithographic bonding material 40 between the adjacent device modules of the first device wafer 20, and the channel communicates with the outside. , the channel extends to the gap formed by the first pad 21 and the second pad 11 , so that the external plating solution flows to the gap through the channel to form the conductive bump 30 .
  • the photoetchable bonding material 40 covers the peripheral area of the subsequently formed conductive bump, that is, defines the formation position of the conductive bump, that is to say, the photoetchable bonding material 40 encloses a gap
  • the boundary of the subsequent conductive bumps 30 cannot exceed the boundary, which facilitates the control of the electroplating process and prevents the formed conductive bumps 30 from overflowing laterally. Because the physical connection between the first device wafer 20 and the second device wafer 10 is achieved through the photolithographic bonding material 40, and the photolithographic bonding material 40 covers the peripheral area of the conductive bump 30, the entire The mechanical strength of the structure can save the filling and gluing process of the prior art. If the plastic encapsulation process is subsequently performed, the plastic encapsulation material does not need to fill the gap between the first device module 201 and the second device module 101 , thereby saving the time of the plastic encapsulation process.
  • the projections of the first bonding pad 21 and the second bonding pad 11 in the direction perpendicular to the surface of the second device wafer 10 are staggered, and the area of the projected overlapping area is larger than that of the first bonding pad 11 .
  • Half of the area of the pad 21 or the second pad 11, so that the conductive bumps 30 formed later can fill the gap as completely as possible, and avoid the contact area of the conductive bumps 30 formed with the first pad 21 and the second pad 11.
  • the staggered parts can be more easily contacted with the electroplating solution, which can avoid the problem that the electroplating solution is not easy to flow into the gap due to the small gap, resulting in the inability to form relatively intact conductive bumps.
  • the first bonding pad 21 is recessed on the lower surface of the first device wafer 20 or the first chip 201 ′, or the surface of the first bonding pad 21 and the surface of the first device wafer 20 or the first chip 201 ′
  • the lower surface is flush
  • the second bonding pad 11 is recessed on the upper surface of the second device wafer 10 , or the surface of the second bonding pad 11 is flush with the upper surface of the second device wafer 10 .
  • the first bonding pads 21 are recessed on the lower surface of the first device wafer 20 or the first chip 201 ′, and the second bonding pads 11 are recessed on the upper surface of the second device wafer 10 , so as to improve the formation of conductive bumps
  • the contact area of the block increases the electrical conductivity.
  • conductive bumps 30 are formed in the voids using an electroplating process to electrically connect the first pads 21 and the second pads 11 .
  • the electroplating process includes electroless plating.
  • the plating solution used in the electroless plating is determined according to the materials of the conductive bumps 30 and the materials of the first bonding pads 21 and the second bonding pads 11 to be formed in practice.
  • the materials of the first pad 21 and the second pad 11 are selected from any one of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium or any combination thereof.
  • the material of the conductive bumps 30 includes any one of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium or any combination thereof.
  • the height of the conductive bumps 30 is 5-200 ⁇ m, such as 10 ⁇ m, 50 ⁇ m, 100 ⁇ m, and/or the cross-sectional area of the conductive bumps 30 is greater than 10 square ⁇ m.
  • the height of the conductive bump 30, that is, the gap is 5-200 ⁇ m, it not only satisfies that the electroplating solution can easily enter the gap for electroplating, but also avoids the problem that the height of the gap is too high and leads to a long electroplating time, so that both the electroplating efficiency and the good electroplating Rate.
  • Electroless plating includes: electroless palladium immersion gold, in which the time for chemical nickel is 30-50 minutes, the time for chemical gold is 4-40 minutes, and the time for chemical palladium is 7-minute; The time is 30-50 minutes, and the time for chemical gold is 4-40 minutes; or, for chemical nickel, the time for chemical nickel is 30-50 minutes.
  • electroplating process chooses electroless palladium immersion gold (ENEPIG) or electroless nickel gold (ENIG), the process parameters can refer to Table 1 below.
  • the present invention forms the conductive bumps 30 through an electroplating process, so as to realize the electrical connection between the first pad 21 and the second pad 11 .
  • the present invention has a simple process flow and high packaging efficiency; second, a plurality of first device modules 201 are located in the first device wafer 20, and a plurality of first device modules 201 The two device modules 101 are located in the second device wafer 10.
  • the electroplating process is compatible with the process in the front-end of packaging, and the traditional chip manufacturing process can be used to realize wafer-level system packaging.
  • the surface of the pad Before electroless plating, in order to better complete the electroplating process, the surface of the pad can be cleaned first to remove the natural oxide layer on the surface of the pad and improve the surface wettability of the pad; after that, activation can be performed process to promote the nucleation and growth of the coating metal on the metal to be plated.
  • the settings of the first pad 21 and the second pad 11 also need to meet certain requirements, for example, the exposed area of the first pad 21 is 5-200 Square micrometers, within this range, the pads can be in sufficient contact with the plating solution to avoid insufficient contact between the pads and the plating solution and affect the contact between the conductive bumps 30 and the pads, such as the contact area is too small to affect the resistance, or, Inability to make contact results in poor electrical contact; moreover, it can also ensure that the contact area will not be too large to reduce the plating efficiency and will not occupy too much surface.
  • the cross-sectional area of the formed conductive bumps is greater than 10 square micrometers, which can not only ensure that the area occupied by the conductive bumps 30 is not too large, but also ensure the bonding strength between the conductive bumps 30 and the bonding pads.
  • the material of the conductive bumps 30 is the same as the material of the first bonding pads 21 , which makes it easier to form the conductive bumps 30 .
  • the material of the first pad 21 may be different from the material of the conductive bump 30.
  • a material layer may be formed on the first pad 21 first, and the material of the material layer is the same as that of the conductive bump 30.
  • the material of the block 30 is the same, and the method of forming the material layer may be a deposition process.
  • the method further includes: cutting the first device wafer 20 with the second device wafer 10 and/or the temporary carrier as a support, and/or using the first device wafer 20 And/or a temporary carrier for supporting the dicing of the second device wafer 10 .
  • the backside of the first device wafer 20 is first thinned to an appropriate thickness by a thinning process, which not only ensures the performance of the first device module 201 but also reduces the package thickness.
  • the first device wafer 20 is cut along the dicing lines, and the first device wafer 20 is divided into a plurality of pieces, each of which includes at least one first device module 201 . Refer to FIG. 4 for the structure after cutting.
  • the second device wafer 10 When cutting the first device wafer 20 , the second device wafer 10 may be used as a carrier. Then, the cut side is temporarily bonded to the temporary carrier board, and the second device wafer 10 is cut with the temporary carrier board as a support. First, the backside of the second device wafer 10 is thinned to a suitable thickness by a thinning process. That is, the performance of the second device module 101 is guaranteed, and the package thickness can be reduced.
  • the second device wafer 10 is cut along the dicing lines, and the second device wafer 10 is divided into a plurality of pieces, each of which includes at least one second device module 101 . In this embodiment, the first device wafer 20 is cut first and then the second device wafer 10 is cut.
  • the second device wafer 10 can also be cut first and then the first device wafer 20 is cut.
  • two dicing can be selected, and the dicing must have sufficient support to prevent debris.
  • the packaging method of the first chip 201 ′ and the second device wafer 10 is the same as the above-mentioned first chip 201 ′.
  • the method steps of the device wafer 20 and the second device wafer 10 are basically the same, and the difference is that a plurality of first chips 201 ′ need to be bonded to the second device wafer 10 one by one.
  • the surface of the first chip 201 ′ has a plurality of exposed first bonding pads 21 , specifically, the first bonding pad 21 is embedded in the surface of the first chip 201 ′, and only the surface of the first bonding pad 21 is exposed to the air or, part of the first pad 21 is located in the first chip 201', and the other part is exposed to the air; alternatively, a dielectric layer 12 is formed on the surface of the first chip 201', and the dielectric layer 12 is etched to form an opening, The first bonding pad 21 is formed on the first chip 201 ′ through the opening and exposes part of the first bonding pad 21 .
  • the first chip 201' is a fabricated chip, and is bonded to the second device wafer 10 through a photolithographic bonding material 40.
  • the surface of the first chip 201' on which the first bonding pads 21 are formed is the first surface of the first chip 201', the second surface of the first chip 201' is opposite to the first surface, and the first surface may be the first chip 201'
  • the front side of the first chip 201 ′ may also be the back side of the first chip 201 ′.
  • the first chip 201 ′ may contain through silicon vias (TSVs for short), and the first pads 21 are electrically connected to the through silicon vias.
  • the first chip 201' is bonded to the second device wafer 10, and the first bonding pads 21 and the second bonding pads 11 are opposite to form a gap.
  • the gap is prepared for the subsequent electroplating work, and the first conductive bump 30 will be formed in the gap later to realize the electrical connection between the first pad 21 and the first pad 21 .
  • a conductive bump connecting the first pad 21 and the second pad 11 is formed in the gap through an electroplating process to realize the electrical connection between the first chip 201 ′ and the second device module 101 , and finally only the second device
  • the wafer 10 can be cut, and the structure of the package is completed with reference to FIG. 4 .
  • the number of the first chips 201 ′ is multiple, and the multiple first chips 201 ′ may be chips with the same function; or the multiple first chips 201 ′ may include at least two different types of chips.
  • a functional chip a variety of chips with different functions are integrated together to achieve a certain function.
  • the type of the first chip 201' may refer to the chip type of the first device module 201.
  • this embodiment has a first opening formed in the adhesive layer, and the cavity formed by the first opening serves as the The working cavity of the first device module 201 or the first chip 201 ′, and/or the working cavity of the second device module 101 .
  • the types of the first device wafer 20 and the second device wafer 10 refer to Embodiment 1.
  • An adhesive layer is formed on the lower surface of the first device wafer 20 or the upper surface of the second device wafer 10 by a photolithographic bonding material 40.
  • the patterning can be photolithographic In the bonding material 40 , a first opening 41 is formed in the photolithographic bonding material 40 , and the depth of the first opening 41 is equal to or less than the thickness of the photolithographic bonding material 40 .
  • the first opening 41 is covered to form a cavity, and the cavity serves as the first device module 201 and/or the second device module 101 working chamber.
  • the first device module 201 or the second device module 101 needs to form a cavity, by forming the first opening 41 in the photolithographic bonding material 40, process steps can be saved (otherwise it is Cavities are formed when two-device modules are used).
  • the first opening 41 is formed by patterning a photolithographic bonding material, and the patterning process can be performed on the photolithographic bonding material to expose the first pads 21 of the first device wafer 20
  • the selection and patterning process of the photolithographic bonding material 40 used for the adhesive layer refer to Embodiment 1.
  • the first opening 41 is used for heat insulation, so the depth of the first opening 41 is not limited.
  • the thickness of the bonding material 40 is the same) or only a part of the thickness of the photolithographic bonding material 40 (the depth of the opening is smaller than the thickness of the photolithographic bonding material 40 ).
  • a suitable thickness is formed when the photolithographic bonding material 40 is formed.
  • fbar cavity-type bulk acoustic wave resonators
  • SAW surface acoustic wave resonators
  • a lower cavity is provided below the main resonance area, a cover is formed above, and an upper cavity is formed between the cover and the main resonance area.
  • the cavity in the embodiment can be used as an upper cavity or a lower cavity.
  • SMR solidly mounted bulk acoustic resonator
  • an upper cavity is formed above and between the covers, and the cavity in this embodiment can be used as the upper cavity.
  • thermopile sensor a thermal insulation cavity for thermal insulation is provided below the functional area, and the cavity formed in this embodiment can be used as a thermal insulation cavity.
  • the membrane-shaped vibrating part is suspended in the air, the upper surface is used to receive ultrasonic waves, and the lower surface covers the cavity.
  • the cavity in this embodiment can be used as the lower cavity of the ultrasonic sensor.
  • the cavity needs to communicate with the outside (such as a microphone chip, due to the working requirements of the microphone chip, the cavity needs to communicate with the outside)
  • the first device wafer 20 is cut in the later process.
  • the first device module 201 or the second device module 101 does not completely cover the cavity, so that the cavity is communicated with the outside, if the cavity is small, the cut first device module 201 or The second device module 101 seals the cavity, and further includes forming a through hole in the non-functional area of the device, and communicating the cavity with the outside through the through hole.
  • the subsequent encapsulation steps such as electroplating and cutting refer to Embodiment 1, which will not be repeated here.
  • the encapsulation structure after electroplating is completed is shown in FIG. 6 .
  • the packaging method for providing a plurality of first chips 201 ′ and the second device wafer 10 is basically the same as the above-mentioned packaging method for the first device wafer 20 and the second device wafer 10 , here Without further elaboration, the package structure after the first chip 201 ′ is bonded to the second device wafer 10 and electroplating is completed as shown in FIG. 7 .
  • the difference between this embodiment and Embodiment 1 is that the second device wafer 10 provided in this embodiment has a second opening 14 formed on the surface, and the second pad 11 is located in the second opening. 14 outer periphery; the second opening 14 serves as the working cavity of the first device module 201 or the first chip 201'.
  • first, the first device wafer 20 and the second device wafer 10 having the second opening 14 on the upper surface are provided.
  • the second pad 11 is located at the outer periphery of the second opening 14 .
  • the first device wafer 20 and the second device wafer 10 are bonded together through an adhesive layer, the second opening 14 is used as a working cavity of the first device module 201 in the first device wafer 20 above, and the second device wafer 20
  • the pads 11 are opposite to the first pads 21 to enclose a gap, and then conductive bumps 30 are formed in the gaps through an electroplating process, and the conductive bumps 30 are electrically connected to the first pads 21 and the second pads 11 .
  • Example 1 for the electroplating method which will not be repeated here.
  • Subsequent encapsulation steps such as cutting are the same as those in Embodiment 1, which will not be repeated here.
  • the encapsulation structure after electroplating is completed is shown in FIG. 10 .
  • the method for forming the second opening 14 includes: providing the second device wafer 10; etching the second device wafer 101 to form the second opening 14; or, as shown in FIG. 9, the second device wafer 101 includes a dielectric layer 12 , and the second opening 14 is formed by etching the dielectric layer 12 .
  • the material of the dielectric layer 12 includes: silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride or ethyl silicate; or, when forming the second device wafer 10, a sacrificial block is formed to form the second device wafer After 10, the sacrificial block is removed to form the second opening 14 .
  • the second device wafer 10 has opposite front and back surfaces.
  • the second pads 11 and the second openings 14 are formed on the front of the second device wafer 10 .
  • the second pads 11 and the second opening 14 may also be formed on the backside of the second device wafer 10 .
  • external connection pads 16 are also formed. 16 is located at the periphery of the second bonding pad 11 so as to electrically connect the second device wafer 10 to the outside.
  • a TSV hole is formed on the side of the second device wafer 10 away from the second opening 14, and a plug is formed in the TSV hole, so as to The second device wafer 101 is electrically connected to the outside.
  • the side of the second chip 50 facing away from the second device wafer 10 is exposed with TSV holes. plug for electrical connection to the outside.
  • the second opening 14 may be located on the second device wafer 10 and extend into the substrate of the second device wafer 10, and the second opening 14 may avoid the devices, such as between adjacent devices, such as As shown in Figure 8, it can also be included in the device and can be designed according to requirements.
  • the second opening 14 is located on a structure layer on the surface of the second device wafer 10 , such as the dielectric layer 12 , and the device is located under the structure layer, as shown in FIG. 9 .
  • the second pad 11 is located at the outer periphery of the second opening 14 , specifically, the second pad 11 is embedded in the second device wafer 10 , and only the surface of the second pad 11 is exposed to the air; or, the second pad 11 A part is inside the second device wafer 10, and the other part is exposed to the air.
  • the packaging method of providing a plurality of first chips 201 ′ and the second device wafer 10 is basically the same as the packaging method of the first device wafer 20 and the second device wafer 10 described above.
  • the second opening 14 can be used as a working cavity for the first chip 201 ′ above.
  • electroplating and cutting method steps refer to Embodiment 1 and Embodiment 1 2. It is not repeated here.
  • the package structure after the first chip 201 ′ is bonded to the second device wafer 10 and the electroplating is completed is shown in FIG. 11 .
  • a first opening 41 is formed in the photolithographic bonding material 40 of the adhesive layer, and the second device crystallizes
  • a second opening 14 is formed on the surface of the circle 10, and the second pad 11 is located at the outer periphery of the second opening 14; ,
  • the second opening 14 encloses a first cavity, and the first cavity serves as a working cavity of the first device module 201 or the first chip 201'.
  • first provide the first device wafer 20 and the second device wafer 10 with the second opening 14 on the upper surface, wherein the second solder
  • the pad 11 is located on the outer periphery of the second opening 14;
  • the formation method and structure of the second opening 14 refer to Embodiment 3;
  • a photolithographic bonding material 40 adhesive layer
  • the first opening 41 is formed in the adhesive layer through a patterning process.
  • the method for forming the first opening 41 refers to Embodiment 2; after that, referring to FIG.
  • the first device wafer 20 is bonded on the On the two device wafers 10 , after bonding, the first opening 41 and the second opening 14 communicate with each other and enclose the working cavity of the first device module 201 ; the first pad 21 and the second pad 11 relatively enclose a gap.
  • the conductive bumps 30 connecting the first bonding pads 21 and the second bonding pads 11 are formed in the gaps through an electroplating process, so as to realize the electrical connection between the first device module 201 and the second device module 101 .
  • the first device wafer 20 and the second device wafer 10 may be diced through a dicing process.
  • the first device wafer 20 and the second device wafer 10 are connected by a photolithographic bonding material 40 (adhesive layer), and the first opening 41 formed in the photolithographic bonding material 40 and the The second openings 14 on the second device wafer 10 together form a working cavity to meet the cavity environment in which the first chip 201' or the first device module 201 works, so as to avoid additional capping and save process steps; in addition,
  • the working cavity is formed by the photolithographic bonding material 40 and the second opening 14 , which can reduce the technological difficulty of forming the working cavity; wherein the photolithographic bonding material 406 needs to avoid the bonding pads.
  • the packaging method of providing a plurality of first chips 201 ′ and the second device wafer 10 is basically the same as the packaging method of the first device wafer 20 and the second device wafer 10 described above.
  • the cavity formed by the second opening 14 and the first opening 41 can be used as the working cavity of the first chip 201 ′ above.
  • electroplating and cutting The method steps refer to Embodiment 1 and Embodiment 2, which will not be repeated here.
  • the package structure after the first chip 201 ′ is bonded to the second device wafer 10 and electroplating is completed as shown in FIG. 13 .
  • Embodiment 1 the difference between this embodiment and Embodiment 1 is that, on the basis of Embodiment 1, in this embodiment, a plurality of grooves 15 are formed on the upper surface of the second device wafer 10 , at least Part of the second bonding pads 11 are located at the bottom of the groove 15 ; the first chip 201 ′ is embedded in the groove 15 and bonded to the second device wafer 10 .
  • grooves 15 are formed on the surface of the second device wafer 10 , and the second pads 11 are located under the grooves 15 .
  • the groove 15 may be located on the second device wafer 10 and extend into the device wafer substrate, the groove 15 may be located on a structural layer on the surface of the second device wafer 10, such as the dielectric layer 12, the device is located on the structural layer.
  • the groove 15 can avoid the device, such as between adjacent devices, and can also be in the device, which can be designed according to requirements.
  • the present invention realizes the connection between the first chip 201' and the second device wafer 10 by forming the groove 15 on the second device wafer 10, and subsequently embedding the first chip 201' into the groove 15 through a bonding process, thereby reducing the The height of device integration is increased, the space utilization rate is improved, and the integration degree of the device is improved.
  • the second bonding pad 11 is located below the groove 15 , specifically, the second bonding pad 11 is embedded in the device wafer, and only the surface of the second bonding pad 11 is exposed in the groove 15 ; or, the second bonding pad 11 is partially located In the second device wafer 10 , another part is exposed in the groove 15 .
  • the method for forming the groove 15 includes: the first method: after the second device wafer 10 is formed, the groove 15 is formed by etching on the second device wafer 10 , as shown in FIG. 14 .
  • the second device wafer 10 includes a dielectric layer 12 , and the grooves 15 are formed by etching the dielectric layer 12 .
  • the material of the dielectric layer 12 includes: silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride or ethyl silicate, as shown in FIG. 15 .
  • the third type forming a sacrificial block when the second device wafer 10 is formed, and removing the sacrificial block to form the groove 15 after the device wafer is formed.
  • a first chip 201 ′ is provided, the surface of the first chip 201 ′ has a plurality of exposed first bonding pads 21 , the first chip 201 ′ is embedded in the groove 15 and connected with the second device wafer 10 bonding connection, the first pad 21 is opposite to the second pad 11 to enclose a gap.
  • an adhesive layer is preferably formed on the lower surface of the first chip 201 ′, and the material of the adhesive layer is a photolithographic bonding material 40 , the type of the first chip 201 ′, and the structure of the first pad 21 .
  • the material selection of the photoresistable material and the formation method thereof may refer to Embodiment 1.
  • the groove 15 is formed on the second device wafer 10 , and the first chip 201 ′ is bonded to the bottom of the groove 15 through a photolithographic bonding material 40 through a bonding process, so that the first chip 201 ′ and the The connection of the second device wafer 10 reduces the height of device integration, improves space utilization, and improves device integration.
  • the difference between this embodiment and Embodiment 5 is that, on the basis of Embodiment 5, in this embodiment, a first opening is formed in the adhesive layer, and the cavity formed by the first opening serves as the first opening.
  • the working cavity of the chip 201 ′ or the second device module 101 is formed in this embodiment.
  • the adhesive layer in this embodiment is formed of the photolithographic bonding material 40 , and the method for forming the first opening 41 in the adhesive layer can be referred to in Embodiment 2, which will not be repeated here.
  • the groove 15 is formed on the second device wafer 10, and the first chip 201' is bonded to the bottom of the groove 15 through a connecting layer through a bonding process, so as to realize the first chip 201' and the second device wafer.
  • 10 connection reduces the height of device integration, improves space utilization and device integration; and by forming the first opening 41 in the adhesive layer as the working cavity of the first chip 201 ′, the working cavity can be the first opening 41 ′.
  • the chip 201' provides a working cavity environment, and no additional capping is required, which simplifies the process.
  • the difference between this embodiment and Embodiment 1 is that the backside of the first device module 201 (or the first chip 201 ′) has a first electrical connection structure 22 .
  • the The second chip 50 or the third device wafer is electrically connected to the first electrical connection structure 22 .
  • the first electrical connection structure 22 is formed on the back of the first device module 201.
  • the second chip 50 is provided; Bonded with the first device module 201 .
  • the second chip 50 may be electrically connected to one first device module 201 , or may be electrically connected to two or more first device modules 201 .
  • the figure shows a situation in which the second chip 50 is electrically connected to a first device module 201 .
  • to electrically connect the second chip 50 and the first device module 201 refer to the first bonding of the second chip 50 and the first device module 201 in Embodiment 1, forming a gap and electroplating to form a conductive block.
  • a ball mounting process may be used to electrically connect the second chip 50 and the first device module.
  • the second chip 50 is electrically connected to the first device module 201 after the first device wafer 10 is cut.
  • the second chip 50 may be electrically connected to the first device module 201 before the first device wafer 20 is diced.
  • a third device wafer is directly provided, the third device wafer includes a plurality of second chips 50 inside, the third device wafer is bonded to the back of the first device wafer 20, and the second chip 50 and the first device wafer 50 are bonded together.
  • a device module 201 is electrically connected.
  • the difference between this embodiment and Embodiment 2 is that the lower surface of the second device module 101 has a second electrical connection structure 13 , and the method further includes: providing a third chip 51 or a fourth device wafer 100 , and placing the first The three chips 51 or the fourth device wafer 100 are electrically connected to the second electrical connection structure 13 .
  • the lower surface of the second device module 101 has a second electrical connection structure 13
  • the fourth device wafer 100 includes a plurality of third chips 51
  • the second electrical connection structure 13 is electrically connected to the third chips 51 .
  • the lower surface of the second device wafer 10 is thinned to expose the second electrical connection structure 13 , and then the fourth device wafer 100 is bonded on the second device wafer 10 , and the third chip 51 and the
  • the implementation method can refer to Embodiment 7, and the bumps can be formed by electroplating or the solder balls can be formed by a ball-mounting process.
  • a separate third chip 51 may also be provided, and each second chip is electrically connected to the second electrical connection structure 13 one by one.
  • this embodiment provides a method for electrically extracting devices on the basis of Embodiment 1.
  • the upper surface of the first device wafer 20 is provided with an electrical connection structure, and the electrical connection structure For example, it is electrically connected to the first device module 201 or the second device module 101 through a plug.
  • the method further includes: forming a plastic encapsulation layer 60 , and the plastic encapsulation layer 60 covers the first device module 201 ; forming a conductive structure 61 penetrating the plastic sealing layer 60 , one end of the conductive structure 61 is connected to the electrical connection structure of the second device module, and the other end is located on the upper surface of the plastic sealing layer 60 .
  • the external electrical connections are drawn from the back of the second device wafer 10, and the electrical properties of the second device module 101 or the first device module 201 are led to the electrical properties of the second device module 101 or the first device module 201 through a conductive structure 61, such as a plug.
  • the backside of the second device wafer 10 is used for electrical connection with external circuits such as a PCB board.
  • the wafer-level system packaging structure includes: a first device wafer 20 or a plurality of first chips 201 ′, a first device wafer 20 or a first device wafer 20 or a first chip 201 ′.
  • the lower surface of a chip 201 ′ has a plurality of bonding pads, wherein a plurality of first device modules 201 are formed inside the first device wafer 20 , and the first bonding pads 21 are electrically connected to the first device modules 201 ; the second device wafer 10 , a plurality of second device modules 101 are formed inside the second device wafer 10 , the second device wafer 10 includes opposite upper and lower surfaces, and the upper surface has a plurality of second pads electrically connected to the second device modules 101 11.
  • the first device wafer 20 or the first chip 201' is bonded to the upper surface of the second device wafer 10 through an adhesive layer; the conductive bumps 30 are formed on the oppositely disposed first pads 21 and 10 through an electroplating process. between the second pads 11 .
  • the structures of the first device wafer 20, the first chip 201', and the second device wafer 10, and the types of the first device module 201 and the second device module 101 refer to Embodiment 1.
  • the material of the adhesive layer is the photolithographic bonding material 40 , the optional material, the thickness of the photolithographic bonding material 40 and the smeared area refer to Embodiment 1.
  • the projections of the first bonding pads 21 and the second bonding pads 11 in the direction perpendicular to the surface of the first device wafer 20 are staggered, and the area of the projected overlapping area is larger than that of the first bonding pads 21 or the second bonding pads 11 half of the area.
  • the height of the conductive bumps 30 is 5-200 micrometers, and/or the cross-sectional area of the conductive bumps 30 is greater than 10 square micrometers.
  • a first opening 41 is formed in the adhesive layer, and a cavity formed by the first opening 41 serves as the first device module 201 or the first chip 201 ′.
  • the working chamber, and/or as the working chamber of the second device module 101 are the difference between this embodiment and Embodiment 11 .
  • a second opening 14 is formed on the surface of the second device wafer 10 , the second pad 11 is located on the outer periphery of the second opening 14 ; the second opening 14 serves as a The working cavity of the first device module 201 or the first chip 201'.
  • a first opening 41 is formed in the adhesive layer, a second opening 14 is formed on the surface of the second device wafer 10 , and a second bonding pad is formed.
  • 11 is located on the periphery of the second opening 14; the first device module 201 or the first chip 201', the adhesive layer and the second device wafer 10 enclose the first opening 41 and the second opening 14 to form a first cavity, and the first cavity The cavity serves as a working cavity of the first device module 201 or the first chip 201'.
  • the difference between this embodiment and Embodiment 11 is that a plurality of grooves 15 are formed on the upper surface of the second device wafer 10 , and at least part of the second pads 11 are located at the bottom of the grooves 15 ; A chip 201 ′ is embedded in the groove 15 and bonded to the second device wafer 10 .

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Abstract

本发明提供一种晶圆级系统封装方法及封装结构，方法包括：提供第一器件晶圆或多个第一芯片，第一器件晶圆或第一芯片的下表面具有多个裸露的第一焊垫，第一器件晶圆内部具有多个第一器件模块，第一焊垫电连接第一器件模块；提供第二器件晶圆，第二器件晶圆内部形成有多个第二器件模块，第二器件晶圆包括相对的上表面和下表面，上表面暴露出电连接第二器件模块的多个第二焊垫；在第二器件晶圆的上表面、第一器件模块的下表面或第一芯片的下表面形成粘合层，通过粘合层将第一器件晶圆或第一芯片与第二器件晶圆键合，并使第一焊垫和第二焊垫相对围成空隙；采用电镀工艺在空隙中形成导电凸块，以电连接第一焊垫和第二焊垫。

Description

一种晶圆级系统封装结构及封装方法 技术领域
本发明涉及半导体封装领域，尤其涉及一种晶圆级系统封装结构及封装方法。
 背景技术
统级封装采用任何组合，将多个具有不同功能和采用不同工艺制备的有源元/器件、无源元/器件、MEMS器件、分立的KGD（Known Good Die）诸如光电芯片、生物芯片等，在三维（X方向、Y方向和Z方向）集成组装成为具有多层器件结构，并且可以提供多种功能的单个标准封装件，形成一个系统或者子系统。
倒装芯片（FC，Flip-Chip）焊接为目前比较常用的一种系统级封装方法。该系统级封装的方法包括：提供PCB电路板，其中PCB电路板上形成有按一定要求排列的焊球（利用植球工艺形成）；在电路板上浸蘸助焊剂，然后将芯片倒装贴片在电路板上；利用回流焊工艺将芯片上的焊垫（pad）与电路板上的焊球进行焊接后电连接；之后，在芯片底部和电路板之间充填灌胶，以增加整个结构的机械强度。
 技术问题
但是，现有的系统级封装的方法，存在以下缺点：1、工艺复杂，造成封装效率低；2、需要将各个芯片依次焊接在焊球上，封装效率低；3、需要利用焊接工艺实现芯片与PCB板的电连接，无法与封装前段的工艺兼容； 4、浸蘸助焊剂过程中稍有不慎施以较大压力时容易造成电路板压裂。
因此，期待一种新的晶圆级系统封装结构及封装方法。可以提高封装效率。
 技术解决方案
本发明揭示了一种晶圆级系统封装结构及封装方法，能够解决封装效率低的问题。
为解决上述技术问题，本发明提供了一种晶圆级系统封装方法，包括：提供第一器件晶圆或多个第一芯片，所述第一器件晶圆或所述第一芯片的下表面具有多个裸露的第一焊垫，所述第一器件晶圆内部具有多个第一器件模块，所述第一焊垫电连接所述第一器件模块；提供第二器件晶圆，所述第二器件晶圆内部形成有多个第二器件模块，所述第二器件晶圆包括相对的上表面和下表面，所述上表面暴露出电连接所述第二器件模块的多个第二焊垫；在所述第二器件晶圆的上表面、所述第一器件模块的下表面或所述第一芯片的下表面形成粘合层，通过所述粘合层将所述第一器件晶圆或所述第一芯片与所述第二器件晶圆键合，并使所述第一焊垫和所述第二焊垫相对围成空隙；采用电镀工艺在所述空隙中形成导电凸块，以电连接所述第一焊垫和所述第二焊垫。
本发明还提供了一种晶圆级系统封装结构，包括：第一器件晶圆或多个第一芯片，所述第一器件晶圆或所述第一芯片的下表面具有多个焊垫，其中所述第一器件晶圆内部形成有多个第一器件模块，所述第一焊垫电连接所述第一器件模块；第二器件晶圆，所述第二器件晶圆内部形成有多个第二器件模块，所述第二器件晶圆包括相对的上表面和下表面，所述上表面具有电连接所述第二器件模块的多个第二焊垫，所述第一器件晶圆或所述第一芯片通过粘合层键合于所述第二器件晶圆的上表面；导电凸块，通过电镀工艺形成于相对设置的所述第一焊垫和所述第二焊垫之间。
 有益效果
本发明的有益效果在于：本发明通过电镀工艺形成导电凸块，以实现第一焊垫与第二焊垫的电连接。第一、相对于传统的通过植球工艺形成导电凸快的方法，本发明工艺流程简单，封装效率高；第二、当提供第一器件晶圆时，多个第一器件模块位于第一器件晶圆中，多个第二器件模块位于第二器件晶圆中，通过键合第一器件晶圆与第二器件晶圆，实现了相较于传统的每个第一器件模块与第二器件模块单独粘合相比，极大的提高了封装效率。第三、电镀工艺与封装前段的工艺兼容，可以利用传统的芯片制造工艺实现晶圆级的系统封装。
进一步地，当器件模块和/或第一芯片工作需要空腔环境时，通过粘合层形成空腔，可以节省工艺步骤（否则需要在制造器件模块和/或第一芯片时形成空腔）。
进一步地，利用第二器件晶圆上形成的第二开口，满足第一器件模块或第一芯片工作的空腔环境，这样在完成系统集成的同时，兼容第一器件模块或第一芯片的空腔需求，降低了系统的封装高度，且避免另外做封盖，节省了工艺步骤，降低成本。
进一步地，第一芯片或第一器件晶圆与第二器件晶圆之间通过可光刻键合材料实现物理连接，利用第二器件晶圆上形成的第二开口以及粘合层中形成的第一开口，满足第一器件模块或第一芯片工作的空腔环境，既可以实现图形化形成第一空腔，又能实现键合，工艺简化，而且可光刻键合材料覆盖所述第一空腔外围的区域，直接增强了整个结构的机械强度。
进一步地，通过在第二器件晶圆上形成凹槽，通过键合工艺将第一芯片嵌入凹槽中，实现第一芯片与第二器件晶圆的连接，降低了器件集成的高度，提高空间利用率，提高器件的集成度。
进一步地，第一器件晶圆或第一芯片与第二器件晶圆之间通过可光刻键合材料实现物理连接，而且可光刻键合材料覆盖所述导电凸块外围的区域，直接增强了整个结构的机械强度，可以省去现有技术的充填灌胶工艺。在后续进行塑封工艺时，塑封材料无需填充第一器件模块或第一芯片与第二器件晶圆之间的间隙，从而节省了塑封工艺的时间。另外，干膜材料的可光刻键合材料，由于弹性模量比较小，在受到热应力时可以很容易变形而不至于破损，从而减小第一器件晶圆或第一芯片与第二器件晶圆之间的结合应力。
进一步的，可光刻键合材料可以限制导电凸块的位置，防止电镀工艺中导电凸块横向外溢。
进一步地，第一焊垫与第二焊垫在垂直于第二器件晶圆表面方向上采用错位设计，重叠区域的面积大于第一焊垫或第二焊垫面积的一半，错位设计可以防止电镀导电凸块时，导电凸块填充不满空隙。错位设计在保证导电凸块填满空隙的基础上，同时保证一定的结合强度。
进一步地，当空隙的高度为5-200微米时，既满足了电镀液容易进入空隙进行电镀，也避免了空隙高度太高而导致电镀时间长的问题，从而兼顾了电镀效率与电镀的良率。
进一步地，形成可光刻的键合材料时，其投影以第一器件模块或第一芯片的中心为中心，覆盖面积大于第一器件模块或第一芯片面积的10%，优选覆盖第一器件模块或第一芯片的全部下表面（除第一焊垫所在的区域），这样，在后续工艺形成塑封层时，保证第一器件模块或第一芯片下方没有空隙，提高结合强度，提高成品率。
 附图说明
通过结合附图对本发明示例性实施例进行更详细的描述，本发明的上述以及其它目的、特征和优势将变得更加明显，在本发明示例性实施例中，相同的参考标号通常代表相同部件。
图1至图4示出了本发明实施例1的一种晶圆级系统封装方法的不同步骤对应的结构示意图。
图5-图7示出了本发明实施例2的一种晶圆级系统封装方法的不同步骤对应的结构示意图。
图8-图11示出了本发明实施例3的一种晶圆级系统封装方法的不同步骤对应的结构示意图。
图12-图13示出了本发明实施例4的一种晶圆级系统封装方法的不同步骤对应的结构示意图。
图14-图18示出了本发明实施例5的一种晶圆级系统封装方法的不同步骤对应的结构示意图。
图19示出了本发明实施例6的一种晶圆级系统封装方法的不同步骤对应的结构示意图。
图20示出了本发明实施例7的一种晶圆级系统封装方法的不同步骤对应的结构示意图。
图21示出了本发明实施例8的一种晶圆级系统封装方法的不同步骤对应的结构示意图。
图22-图24示出了本发明实施例9的一种晶圆级系统封装方法的不同步骤对应的结构示意图。
 本发明的实施方式
以下结合附图和具体实施例对本发明作进一步详细说明。根据下面的说明和附图，本发明的优点和特征将更清楚，然而，需说明的是，本发明技术方案的构思可按照多种不同的形式实施，并不局限于在此阐述的特定实施例。附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
实施例 1
本实施例提供了一种晶圆级系统封装方法，包括以下步骤：S101：提供第一器件晶圆20或多个第一芯片201’，第一器件晶圆20或第一芯片201’的下表面具有多个裸露的第一焊垫21，第一器件晶圆20内部具有多个第一器件模块201，第一焊垫21电连接第一器件模块201；S102：提供第二器件晶圆10，第二器件晶圆10内部形成有多个第二器件模块101，第二器件晶圆10包括相对的上表面和下表面，上表面暴露出电连接第二器件模块101的多个第二焊垫11；S103：在第二器件晶圆10的上表面、第一器件模块201的下表面或第一芯片201’的下表面形成粘合层，通过粘合层将第一器件晶圆20或第一芯片201’与第二器件晶圆10键合，并使第一焊垫21和第二焊垫11相对围成空隙；S104：采用电镀工艺在空隙中形成导电凸块30，以电连接第一焊垫21和第二焊垫11。
需要说明的是，本说明书中的S0N不代表制造工艺的先后顺序。
图1至图4示出了本实施例的晶圆级系统封装方法的不同步骤对应的结构示意图，请参考图1至图4，以封装第一器件晶圆和第二器件晶圆为例详细说明各步骤。
参考图1，提供第一器件晶圆20，第一器件晶圆20为完成器件制作的待封装晶圆，第一器件晶圆20可以采用集成电路制作技术所制成，例如在半导体衬底上通过沉积、刻蚀等工艺形成NMOS器件、PMOS器件、电阻、二极管或三极管等，在器件上形成介质层、金属互连结构以及与金属互连结构电连接的焊盘等结构，从而使第一器件晶圆20中集成多个第一器件模块201。第一焊垫21为第一器件模块201的电性引出结构，可以是焊盘（Pad），也可以是其他具有电连接功能的导电块。本实施例中，第一器件晶圆20的正面形成有露出第一焊垫21的介质层12。介质层12具有一定的厚度，使第一焊垫21凹陷于第一器件晶圆20的表面。
半导体衬底可以为硅、锗、锗化硅、碳化硅、砷化镓或镓化铟等，半导体衬底还能够为绝缘体上的硅衬底或者绝缘体上的锗衬底等其他类型的衬底。半导体衬底可以是适宜于工艺需要或易于集成的材料。
第一器件模块201包括裸芯片，具有塑封层的芯片，顶面具有屏蔽层的芯片，顶面具有电性引出端的芯片，如在第一器件晶圆为减薄后的裸芯片晶圆，或者晶圆非焊盘面覆盖有塑封层或者屏蔽层，或者在晶圆非焊盘面设置典型引出端，如电连接结构，或者还有连接电连接结构的插塞。或者第一器件模块201包括逻辑芯片、存储芯片、中央处理器芯片、微处理器芯片、模数转换芯片的至少之一，或者第一器件模块包括麦克风、压力传感器、陀螺仪、速度传感器、加速度传感器中的至少一种MEMS芯片，感测传感射频信号、红外辐射信号、可见光信号、声波信号、电磁波信号其中之一的传感器芯片，芯片中有空腔或者未含空腔，或者第一器件模块包括具有CMOS、CIS、二极管、三极管至少之一的PN结器件，或者第一器件模块包括电感、电容、滤光片、MLCC、连接件至少之一的无源器件。多个第一器件模块201的种类可以相同也可以不同。
传感器芯片可以是应用在5G设备中的射频模组芯片，但不限于5G射频传感器模组芯片，还可以是其他类型的射频模组芯片。接收红外辐射信号的模组芯片可以是热像仪、额温枪、其他类型中的测温或成像等利用红外辐射信号的红外传感器模组芯片。传感器模组芯片还可以是摄像头模组芯片，比如包括感光芯片以及滤光片的模组芯片，可以接收可见光用来成像。传感器模组芯片还可以是麦克风模组芯片，可以接收声波用来传递声音信号。本发明中的传感器模组芯片不限于在此列举的类型，可以为本领域可以实现一定功能的各种类型的传感器模组芯片。MEMS芯片包括麦克风、压力传感器、陀螺仪、速度传感器、加速度传感器、热电堆传感器中的至少一种。滤波器芯片包括：表面声波谐振器、体声波谐振器至少其中之一。MLCC芯片包括：NP0、C0G、Y5V、Z5U、X7R、X5R等电容器。
第二器件晶圆10为完成器件制作的待封装晶圆，第二器件晶圆10可以采用集成电路制作技术所制成，具体可参照第一器件晶圆20的描述，第二器件模块101的结构种类也参照第一器件模块201，此处不再赘述。
参考图2，本实施例中，通过可光刻的键合材料40形成粘合层，以将第一器件晶圆20键合在第二器件晶圆10的上表面，使第一焊垫21和第二焊垫11相对围成空隙。可光刻的键合材料40可以形成在第一器件晶圆20的表面，也可以形成在第二器件晶圆10的表面，还可以在第一器件晶圆20以及第二器件晶圆10上均形成可光刻键合材料40。
可光刻的键合材料40包括膜状干膜或液态干膜，也可以包括其他光敏粘合材料。膜状干膜是将无溶剂型光致抗蚀剂涂在涤纶片基上，再覆上聚乙烯薄膜；使用时揭去聚乙烯薄膜，把无溶剂型光致抗蚀剂压于第一器件晶圆20和/或第二器件晶圆10上，经曝光显影处理，即可在干膜内形成图形。液态干膜指的是膜状干膜中的成分以液态的形式存在。另外，干膜是一种永久键合膜，粘结强度较高。膜状干膜可以通过贴膜的方式形成在第一器件晶圆20和/或第二器件晶圆10上，液态干膜通过旋涂工艺涂布在第一器件晶圆20和/或第二器件晶圆10上，之后对液态干膜进行固化处理。
键合的材料还可以为芯片粘结膜DAF膜（Die attach film），有双面粘性的膜状材料，可以利用刻蚀或者激光烧蚀进行图形化；还可以是介质层，如硅的氧化物或氮化物，通过熔融键合连接第一器件晶圆和第二器件晶圆；或聚合物材料。还可以是材料的组合，如金属和聚合物并排设置，在其他实施例中，键合的材料还可以为光敏材料，从而能够通过光刻工艺实现图形化，从而能够降低对电极或外接互连线的损伤。
应当注意，在进行固化处理之后，需要对干膜进行图形化工艺，以暴露第一器件晶圆20的第一焊垫21和第二器件晶圆10上的第二焊垫11，通过干膜键合第一器件晶圆20和第二器件晶圆10，一方面干膜是可光刻材料，可以通过半导体工艺形成所需的图案样式，工艺简单且与半导体工艺兼容，可批量化生产。而且干膜的弹性模量比较小，在受到热应力时可以很容易变形而不至于破损，减小第一器件晶圆20与第二器件晶圆10的结合应力。
可光刻键合材料40的厚度为5-200μm，如15μm、30μm、80μm、150μm等。既满足了电镀液容易进入空隙进行电镀，也避免了空隙高度太高而导致电镀时间长的问题，从而兼顾了电镀效率与电镀的良率。另外，可光刻键合材料40在第二器件晶圆10表面方向上的投影以第一器件模块201的中心为中心，并至少覆盖第一器件模块201面积的10%。形成较大面积的可光刻键合材料40，尤其将可光刻键合材料40形成在后期工艺中塑封层不容易填充的位置（可选方案中，后期工艺切割第一器件晶圆20，分离第一器件模块后形成塑封层）。本方案的可光刻的键合材料40不但起到粘合的作用，还起到了提前密封的作用，可光刻的键合材料40和后续工艺中的塑封层共同起到密封第一器件模块的作用。可选方案中，可光刻的键合材料40覆盖第一器件模块的全部下表面（除第一焊垫、第二焊垫所在的区域），这样，在后续工艺形成塑封层时，保证第一器件模块下方没有空隙，提高结合强度，提高成品率。
为便于后续电镀时外部电镀液体流入空隙，可光刻键合材料40留有连通空隙流体通道。如光刻键合材料40包围第一焊垫21或第二焊垫11，但留有流体通道将空隙连通到芯片边缘，流体通道可以贯穿光刻键合材料40，也可以不贯穿光刻键合材料40；或者光刻键合材料40未包围或未完全包围第一焊垫21或第二焊垫11，未包围的部分与外界连通作为流体通道。其他实施例中，空隙连通外部，也可以作为一种流体通道；可选的在第一器件晶圆20的相邻器件模块之间的可光刻键合材料40中留有通道，通道连通外部，该通道延伸至第一焊垫21和第二焊垫11形成的空隙，这样使得外部镀液通过通道流至空隙，形成导电凸块30。在一种可能的实现方式中，可光刻键合材料40覆盖后续形成的导电凸块外围的区域，即定义导电凸块的形成位置，也就是说可光刻键合材料40围成了空隙的边界，后续导电凸块30不能超越该边界，方便进行电镀工艺的控制，防止形成的导电凸块30横向外溢。由于，第一器件晶圆20与第二器件晶圆10之间通过可光刻键合材料40实现物理连接，而且可光刻键合材料40覆盖导电凸块30外围的区域，直接增强了整个结构的机械强度，可以省去现有技术的充填灌胶工艺。若后续还进行塑封工艺，塑封材料无需填充第一器件模块201与第二器件模块101之间的间隙，从而节省了塑封工艺的时间。
本实施例中，为了可以更好进行电镀工艺，第一焊垫21和第二焊垫11在垂直于第二器件晶圆10表面方向上的投影相互交错，投影重叠区域的面积大于第一焊垫21或第二焊垫11面积的一半，以便于后续形成的导电凸30块尽可能完整的填充空隙内，避免形成的导电凸块30与第一焊垫21、第二焊垫11接触面积过小而导致电阻增大；另一方面，错开的部分可以更容易与电镀液接触，这样可以避免由于空隙小而导致电镀液不容易流入空隙而导致无法形成比较完好的导电凸块的问题。
本实施例中，第一焊垫21凹陷于第一器件晶圆20或第一芯片201’的下表面，或者第一焊垫21的表面与第一器件晶圆20或第一芯片201’的下表面齐平；第二焊垫11凹陷于第二器件晶圆10的上表面，或者第二焊垫11的表面与第二器件晶圆10的上表面齐平。优选地，第一焊垫21凹陷于第一器件晶圆20或第一芯片201’的下表面，第二焊垫11凹陷于第二器件晶圆10的上表面，以此能够提高形成导电突块的接触面积，增加导电性能。
参考图3，采用电镀工艺在空隙中形成导电凸块30，以电连接第一焊垫21和第二焊垫11。本发明中，电镀工艺包括化学镀。其中，化学镀采用的镀液根据实际中需要形成的导电凸块30的材料以及第一焊垫21、第二焊垫11的材料确定。第一焊垫21、第二焊垫11的材料选自铜、钛、铝、金、镍、铁、锡、银、锌或铬中的任意一种或它们的任意组合。导电凸块30的材料包括：铜、钛、铝、金、镍、铁、锡、银、锌或铬中的任意一种或它们的任意组合。可选实施例中，导电凸块30的高度为5-200μm，如10μm、50μm、100μm，和/或导电凸块30的横截面积大于10平方微米。当导电凸块30即空隙的高度为5-200μm时，既满足了电镀液容易进入空隙进行电镀，也避免了空隙高度太高而导致电镀时间长的问题，从而兼顾了电镀效率与电镀的良率。
化学镀包括：化学镀钯浸金，其中化学镍的时间为30-50分钟，化学金的时间为4-40分钟，化学钯的时间为7-分钟；或者，化学镍金，其中化学镍的时间为30-50分钟，化学金的时间为4-40分钟；或者，化学镍，其中化学镍的时间为30-50分钟。
电镀工艺选择化学镀钯浸金（ENEPIG）或化学镍金（ENIG）时，工艺参数可以参照下表1。
表1
Figure dest_path_image001
本发明通过电镀工艺形成导电凸块30，以实现第一焊垫21与第二焊垫11的电连接。第一、相对于传统的通过植球工艺形成导电凸快的方法，本发明工艺流程简单，封装效率高；第二、多个第一器件模块201位于第一器件晶圆20中，多个第二器件模块101位于第二器件晶圆10中，通过键合第一器件晶圆20与第二器件晶圆10，实现了相较于传统的每个第一器件模块201与第二器件模块101单独粘合相比，极大的提高了封装效率。第三、电镀工艺与封装前段的工艺兼容，可以利用传统的芯片制造工艺实现晶圆级的系统封装。
在进行化学镀之前，为了更好的完成电镀工艺，可以先对焊垫的表面进行清洁，以去除焊垫表面的自然氧化层、提高焊垫的表面湿润度（wetabilities）；之后，可以进行活化工艺，促进镀层金属在待镀金属上的形核生长。
为了更好的实现电镀，形成比较完善的导电凸块30，第一焊垫21、第二焊垫11的设置也需要满足一定的要求，比如：第一焊垫21暴露出面积为5-200平方微米，在该范围内，焊垫可以与电镀液较充分的接触，避免焊垫与镀液不充分接触而影响导电凸块30与焊垫的接触，比如接触面积过小影响电阻，或者，无法接触造成电接触不良；而且，也可以保证接触面积不会过大而降低电镀效率及不会占用过多的面。
形成的导电凸块的横截面积大于10平方微米，既可以保证导电凸块30占用的面积不会太大，也可以保证导电凸块30与焊垫之间的结合强度。
可选方案中，导电凸块30的材料与第一焊垫21的材料相同，这样更容易形成导电凸块30。当然，第一焊垫21的材料可以与导电凸块30的材料不同，为了后续更容易形成导电凸块30，可以在第一焊垫21上先形成材料层，该材料层的材料与导电凸块30的材料相同，形成材料层的方法可以为沉积工艺。
本实施例中，在形成导电凸块30后，方法还包括：以第二器件晶圆10和/或临时载板为支撑切割第一器件晶圆20，和/或以第一器件晶圆20和/或临时载板为支撑切割第二器件晶圆10。本实施例中，先对第一器件晶圆20的背面进行减薄工艺，减薄到合适厚度，即保证第一器件模块201的性能，又能减少封装厚度。沿切割道切割第一器件晶圆20，将第一器件晶圆20分割成多块，每块包括至少一个第一器件模块201，切割后的结构参考图4。切割第一器件晶圆20时，可以以第二器件晶圆10为承载。之后将切割后的一面临时键合在临时载板上，以临时载板为支撑切割第二器件晶圆10，首先对第二器件晶圆10的背面进行减薄工艺，减薄到合适厚度，即保证第二器件模块101的性能，又能减少封装厚度。沿切割道切割第二器件晶圆10，将第二器件晶圆10分割成多块，每块包括至少一个第二器件模块101。本实施例，先切割第一器件晶圆20后第二器件晶圆10，在另一个实施例中，也可以先切割第二器件晶圆10后切割第一器件晶圆20。本实施例中，不同于单晶圆的切割，由于两片器件晶圆厚度累加，且晶圆材质可能有差异，可以选用两次切割，切割需有足够的支撑，防止碎片。
继续参考图4，在其他实施例中，若提供的是第一芯片201’与第二器件晶圆10键合，则第一芯片201’与第二器件晶圆10的封装方法与上述第一器件晶圆20与第二器件晶圆10的方法步骤基本一致，区别在于需要首先将多个第一芯片201’逐个键合于与第二器件晶圆10上。
需要说明的是，第一芯片201’的表面具有多个裸露的第一焊垫21，具体为第一焊垫21内嵌第一芯片201’表面，仅第一焊垫21的表面暴露于空气中；或者，第一焊垫21部分位于第一芯片201’内，另一部分暴露于空气中；还或者，第一芯片201’的表面形成有介质层12，刻蚀介质层12，形成开口，第一焊垫21通过开口形成于第一芯片201’上并暴露部分第一焊垫21。
在本实施例中，第一芯片201’是制作好的芯片，通过可光刻键合材料40粘接在第二器件晶圆10上。第一芯片201’形成有第一焊垫21的面为第一芯片201’的第一表面，第一芯片201’的第二表面和第一表面相对，第一表面可以是第一芯片201’的正面也可以是第一芯片201’的背面，第一芯片201’中可以含有穿硅通孔(Through Silicon Via，简称TSV)，第一焊垫21与该穿硅通孔电连接。
将第一芯片201’与第二器件晶圆10键合，第一焊垫21与第二焊垫11相对围成空隙。该空隙为后续的电镀工作做准备，后续会在该空隙中形成第一导电凸块30，以实现第一焊垫21和第一焊垫21的电连接。
之后再通过电镀工艺在空隙中形成连接第一焊垫21和第二焊垫11的导电突块，实现第一芯片201’与第二器件模块101之间的电连接，最后仅对第二器件晶圆10进行切割即可，完成封装的结构参考图4。
需要说明的是，本实施例中第一芯片201’的数量为多个，多个第一芯片201’可以为具有同功能的芯片；也可以是多个第一芯片201’至少包括两种不同功能的芯片，多种不同功能的芯片集成在一起实现一定的功能。第一芯片201’的类型可参考第一器件模块201的芯片类型。
实施例 2
如图5-图7所示，本实施例与实施例1的区别在于，在实施例1的基础上，本实施例在粘合层中形成有第一开口，第一开口形成的空腔作为第一器件模块201或第一芯片201’的工作腔，和/或，作为第二器件模块101的工作腔。
以提供第一器件晶圆20与第二器件晶圆10进行封装为例，第一器件晶圆20和第二器件晶圆10的类型参考实施例1。
在第一器件晶圆20下表面或第二器件晶圆10上表面通过可光刻的键合材料40形成粘合层，如图5所示，在形成粘合层之后，图形化可光刻的键合材料40，在可光刻的键合材料40中形成第一开口41，第一开口41的深度等于或小于可光刻的键合材料40的厚度。
之后，通过粘合层键合第一器件晶圆20和第二器件晶圆10后，第一开口41被覆盖形成空腔，此空腔作为第一器件模块201和/或第二器件模块101的工作腔。
当第一器件模块201或第二器件模块101需要形成空腔时，通过在可光刻的键合材料40中形成第一开口41，可以节省工艺步骤（否则需要在制造第一器件模块或第二器件模块时形成空腔）。
本实施例中，第一开口41通过图形化可光刻的键合材料形成，可以在对可光刻的键合材料进行图形化工艺，以暴露第一器件晶圆20的第一焊垫21和第二器件晶圆10上的第二焊垫11的步骤中，同时形成第一开口41，粘合层采用的可光刻的键合材料40的选择及图形化工艺参考实施例1。
本实施例中，第一开口41用于隔热，因此对于第一开口41的深度并不做限定，第一开口41可以贯穿可光刻的键合材料40（开口深度与可光刻的键合材料40厚度相同）也可以只贯穿可光刻的键合材料40的一部分厚度（开口深度小于可光刻的键合材料40的厚度）。
在其他实施例中，如果需要对开口的深度进行限定，则在形成可光刻的键合材料40时，形成合适的厚度。对于空腔型体声波谐振器（fbar）和表声波谐振器（SAW）在主体谐振区下方设置有下空腔，上方形成有封盖，封盖和主体谐振区之间形成了上空腔，本实施例中的空腔即可以作为上空腔也可以作为下空腔。对于牢固安置型体声波谐振器（SMR），其上方也封盖之间形成有上空腔，本实施例中的空腔可以作为上空腔。对于红外热电堆传感器，其功能区下方设置有用于隔热的隔热空腔，本实施例形成的空腔可以作为隔热空腔。对于超声波传感器，膜状的振动部悬空设置，上表面用于接收超声波，下表面遮盖空腔，本实施例的空腔可以作为超声波传感器的下空腔。
当空腔需要与外部连通时（如麦克风芯片，由于麦克风芯片的工作需求，空腔需与外部连通），在形成空腔时，可以形成较大的空腔，后期工艺切割第一器件晶圆20或第二器件晶圆10后，第一器件模块201或第二器件模块101并未完全遮盖空腔，以使空腔与外部连通，如果空腔较小，切割后的第一器件模块201或第二器件模块101将空腔密封，还包括在器件非功能区形成通孔，通过通孔将空腔与外部连通。
本实施例中，后续的电镀、切割等封装步骤参考实施例1，此处不再赘述，完成电镀后的封装结构如图6所示。
在其他实施例中，对于提供多个第一芯片201’与第二器件晶圆10的封装方法，与上述第一器件晶圆20与第二器件晶圆10的封装方法步骤基本一致，此处不再赘述，第一芯片201’与第二器件晶圆10键合并完成电镀后的封装结构如图7所示。
实施例 3
如图8-图11所示，本实施例与实施例1的区别在于，本实施例中提供的第二器件晶圆10的表面形成有第二开口14，第二焊垫11位于第二开口14外周；第二开口14作为第一器件模块201或第一芯片201’的工作腔。
以提供第一器件晶圆20与第二器件晶圆10进行封装为例，如图8所示，首先，提供第一器件晶圆20和上表面具有第二开口14的第二器件晶圆10，其中，第二焊垫11位于第二开口14外周。
然后，通过粘合层将第一器件晶圆20和第二器件晶圆10键合在一起，第二开口14作为上方第一器件晶圆20中第一器件模块201的工作腔，第二焊垫11与第一焊垫21相对以围成空隙，然后通过电镀工艺在空隙内形成导电凸块30，导电凸块30电连第一焊垫21和第二焊垫11。电镀方法参考实施例1，此处不做赘述。后续的切割等封装步骤与实施例1相同，此处不再赘述，完成电镀后的封装结构如图10所示。
在本实施例中，第二开口14的形成方法包括：提供第二器件晶圆10；刻蚀第二器件晶圆101形成第二开口14；或者，如图9所示，第二器件晶圆101包括介质层12，刻蚀介质层12形成第二开口14。其中，介质层12的材料包括:氧化硅、氮化硅、氮氧化硅、碳氮化硅或硅酸乙酯；或者，形成第二器件晶圆10时形成牺牲块，形成第二器件晶圆10后去掉牺牲块形成第二开口14。
第二器件晶圆10具有相对的正面和背面，在本实施例中，第二焊垫11和第二开口14形成于第二器件晶圆10的正面，在其它实施例中，第二焊垫11和第二开口14也可以形成于第二器件晶圆10的背面。
另外，参考图8和图9，为了便于第二器件晶圆10与外部电连，在形成第二器件晶圆10的第二焊垫11时，还形成外连焊垫16，外连焊垫16位于第二焊垫11外围，以便于将第二器件晶圆10与外部电连。在其他实施例中，为了便于将第二器件晶圆10与外部电连接，还以在第二器件晶圆10背离第二开口14的一面形成TSV孔，并在TSV孔中形成插塞，以实现第二器件晶圆101与外部电连接。在其他实施例中，若后续形成的第二芯片50的键合于第二器件晶圆10后，其背离第二器件晶圆10的一面暴露有TSV孔，也可以通过在TSV孔内形成插塞以与外部电连接。
本实施例中，第二开口14可以位于第二器件晶圆10上并延伸至第二器件晶圆10衬底中，该第二开口14可以避开器件，如位于相邻器件之间，如图8所示，还可在器件中，可以根据需求设计。或者第二开口14位于第二器件晶圆10表面的结构层上，如介质层12，器件位于结构层的下面，如图9所示。
第二焊垫11位于第二开口14的外周，具体为第二焊垫11内嵌第二器件晶圆10内，仅第二焊垫11的表面暴露于空气中；或者，第二焊垫11部分位于第二器件晶圆10内，另一部分暴露于空气中。
本实施例中，对于提供多个第一芯片201’与第二器件晶圆10的进行封装的实施方式，与上述第一器件晶圆20与第二器件晶圆10的封装方法基本一致，将第一芯片201’与第二器件晶圆10键合后，第二开口14可作为上方第一芯片201’的工作腔，对于后续的键合、电镀及切割的方法步骤参考实施1和实施例2，此处不再赘述，第一芯片201’与第二器件晶圆10键合并完成电镀后的封装结构如图11所示。
实施例 4
如图12-图13所示，本实施例在实施例2和实施例3的基础上，在粘合层的可光刻的键合材料40中形成有第一开口41，且第二器件晶圆10的表面形成有第二开口14，第二焊垫11位于第二开口14外周；第一器件模块201或第一芯片201’、粘合层和第二器件晶圆10将第一开口41、第二开口14围成第一空腔，第一空腔作为第一器件模块201或第一芯片201’的工作腔。
以提供第一器件晶圆20与第二器件晶圆10进行封装为例，首先，提供第一器件晶圆20和上表面具有第二开口14的第二器件晶圆10，其中，第二焊垫11位于第二开口14外周；第二开口14的形成方法及结构参考实施例3；然后，在第一器件晶圆20或第二器件晶圆10上形成可光刻的键合材料40（粘合层），并通过图形化工艺在粘合层中形成第一开口41，第一开口41的形成方法参考实施例2；之后，参考图12，将第一器件晶圆20键合在第二器件晶圆10上，键合之后第一开口41和第二开口14相通并围成第一器件模块201的工作腔；第一焊垫21和第二焊垫11相对围成空隙。
然后，通过电镀工艺在空隙中形成连接第一焊垫21和第二焊垫11的导电凸块30，实现第一器件模块201和第二器件模块101的电连接。
之后，参考实施例3，可通过切割工艺对第一器件晶圆20和第二器件晶圆10进行切割。
本实施例的第一器件晶圆20与第二器件晶圆10之间通过可光刻键合材料40（粘合层）连接，且可光刻键合材料40中形成的第一开口41和第二器件晶圆10上的第二开口14共同形成工作腔，以满足第一芯片201’或第一器件模块201工作的空腔环境，以避免另外做封盖，节省了工艺步骤；另外，通过可光刻的键合材料40和第二开口14形成工作腔，可以降低形成工作腔的工艺难度；其中可光刻键合材料406需要避开焊垫设置。
本实施例中，对于提供多个第一芯片201’与第二器件晶圆10的进行封装的实施方式，与上述第一器件晶圆20与第二器件晶圆10的封装方法基本一致，将第一芯片201’与第二器件晶圆10键合后，第二开口14和第一开口41形成的空腔可作为上方第一芯片201’的工作腔，对于后续的键合、电镀及切割的方法步骤参考实施1和实施例2，此处不再赘述，第一芯片201’与第二器件晶圆10键合并完成电镀后的封装结构如图13所示。
实施例 5
如图14-图18所示，本实施例与实施例1的区别在于，在实施例1的基础上，本实施例中第二器件晶圆10的上表面形成有多个凹槽15，至少部分第二焊垫11位于凹槽15的底部；第一芯片201’嵌入凹槽15并与第二器件晶圆10键合连接。
参考图14和图15，本实施例中，第二器件晶圆10的表面形成凹槽15，第二焊垫11位于凹槽15的下方。凹槽15可以位于第二器件晶圆10上并延伸至器件晶圆衬底中，该凹槽15可以位于第二器件晶圆10表面的结构层上，如介质层12，器件位于结构层的下面，如图15所示；或者，该凹槽15可以避开器件，如位于相邻器件之间，还可在器件中，可以根据需求设计。本发明通过在第二器件晶圆10上形成凹槽15，后续通过键合工艺将第一芯片201’嵌入凹槽15中，实现第一芯片201’与第二器件晶圆10的连接，降低了器件集成的高度，提高空间利用率，提高器件的集成度。第二焊垫11位于凹槽15的下方，具体为第二焊垫11内嵌器件晶圆内，仅第二焊垫11的表面暴露于凹槽15中；或者，第二焊垫11部分位于第二器件晶圆10内，另一部分暴露于凹槽15中。
凹槽15的形成方法包括：第1种：形成第二器件晶圆10后，在第二器件晶圆10上刻蚀形成凹槽15，如图14所示。
第2种：第二器件晶圆10包括介质层12，刻蚀介质层12形成凹槽15。其中，介质层12的材料包括:氧化硅、氮化硅、氮氧化硅、碳氮化硅或硅酸乙酯，如图15所示。
第3种：形成第二器件晶圆10时形成牺牲块，形成器件晶圆后去掉牺牲块形成凹槽15。
本实施例中，关于第二器件晶圆10的材料及结构等特征可以参考实施例1，此处不做赘述。   
参考图16和图17，提供第一芯片201’，第一芯片201’的表面具有多个裸露的第一焊垫21，将第一芯片201’嵌入凹槽15内并与第二器件晶圆10键合连接，第一焊垫21与第二焊垫11相对以围成空隙。
本实施例中，优选在第一芯片201’的下表面形成粘合层，粘合层的材料为可光刻的键合材料40，第一芯片201’的类型、第一焊垫21的结构、可光刻材料的材料选择以及其形成方法可参考实施例1。
本实施例通过在第二器件晶圆10上形成凹槽15，通过键合工艺将第一芯片201’通过可光刻键合材料40键合至凹槽15底部，实现第一芯片201’与第二器件晶圆10的连接，降低了器件集成的高度，提高空间利用率，提高器件的集成度。
实施例 6
如图19所示，本实施例与实施例5的区别在于，在实施例5的基础上，本实施例中在粘合层中形成有第一开口，第一开口形成的空腔作为第一芯片201’或第二器件模块101的工作腔。
本实施例中的粘合层为可光刻键合材料40形成，在粘合层中形成第一开口41的方法参考实施例2，此处不再赘述。
本实施例通过在第二器件晶圆10上形成凹槽15，通过键合工艺将第一芯片201’通过连接层键合在凹槽15底部，实现第一芯片201’与第二器件晶圆10的连接，降低了器件集成的高度，提高空间利用率和器件的集成度；并且通过在粘合层中形成第一开口41作为第一芯片201’的工作腔，该工作腔能够为第一芯片201’提供工作的空腔环境，不需再另外做封盖，简化了工艺。
实施例 7
参考图20，本实施例与实施例1不同的是：第一器件模块201（或第一芯片201’）的背面具有第一电连接结构22，切割第一器件晶圆20前或后，提供第二芯片50或第三器件晶圆，将第二芯片50或第三器件晶圆与第一电连接结构22电连接。
在本实施例中，第一器件模块201背面形成有第一电连接结构22，在实施例1中切割完第一器件晶圆10的步骤之后，提供第二芯片50；再将第二芯片50与第一器件模块201键合。第二芯片50可以与一个第一器件模块201电连接，也可以和两个或者多个第一器件模块201电连接。图中示出了第二芯片50与一个第一器件模块201电连接的情况。需要说明的是，电连接第二芯片50和第一器件模块201可参照实施例1中的先键合第二芯片50和第一器件模块201，形成空隙并电镀形成导电块。在其他实施例中，可以采用植球工艺电连接第二芯片50和第一器件模块。
需要说明的是，本实施例中，第二芯片50是在切割完第一器件晶圆10后与第一器件模块201电性连接。在另一个实施例中，第二芯片50可以在第一器件晶圆20切割前与第一器件模块201实现电性连接。或者，直接提供第三器件晶圆，第三器件晶圆内部包括多个第二芯片50，将第三器件晶圆键合在第一器件晶圆20的背面，并实现第二芯片50与第一器件模块201电性连接。
需要说明的是，本实施例的方案同样适用于上述实施例2-6。
实施例 8
参考图21，本实施例与实施例2不同的是：第二器件模块101的下表面具有第二电连接结构13，方法还包括：提供第三芯片51或第四器件晶圆100，将第三芯片51或第四器件晶圆100与第二电连接结构13电连接。
第二器件模块101的下表面具有第二电连接结构13，第四器件晶圆100包括多个第三芯片51，第二电连接结构13电连接第三芯片51。首先对第二器件晶圆10的下表面进行减薄，暴露出第二电连接结构13，之后将第四器件晶圆100键合在第二器件晶圆10上，并实现第三芯片51与第二电连接结构13的电性连接，实现方法可参照实施例7，可以通过电镀形成凸块或者通过植球工艺形成焊球。需要说明的是，本实施例中，也可以提供单独的第三芯片51，将每个第二芯片一一电连接在第二电连接结构13上。
需要说明的是，本实施例的方案同样适用于上述实施例2-6。
实施例 9
参考图22-图24，本实施例在实施例1的基础上提供了一种将器件电性引出的方法，参考图22，第一器件晶圆20上表面设有电连接结构，电连接结构如通过插塞与第一器件模块201或第二器件模块101电连接。
另外其他实施例，参考图23，第二器件模块101上表面设有电连接结构后，切割完第一器件晶圆10后，方法还包括：形成塑封层60，塑封层60覆盖第一器件模块201；形成贯穿塑封层60的导电结构61，导电结构61一端连接于第二器件模块的电连接结构，另一端位于塑封层60的上表面。
参考图24，在另一个实施例中，外部电连接从第二器件晶圆10背部引出，通过导电结构61，如插塞，将第二器件模块101或第一器件模块201的电性引到第二器件晶圆10背部，以便于和外部电路如PCB板电连。
需要说明的是，本实施例的方案同样适用于上述实施例2-6。
实施例 10
本实施例提供了一种晶圆级系统封装结构，参照图4，该晶圆级系统封装结构包括：第一器件晶圆20或多个第一芯片201’，第一器件晶圆20或第一芯片201’的下表面具有多个焊垫，其中第一器件晶圆20内部形成有多个第一器件模块201，第一焊垫21电连接第一器件模块201；第二器件晶圆10，第二器件晶圆10内部形成有多个第二器件模块101，第二器件晶圆10包括相对的上表面和下表面，上表面具有电连接第二器件模块101的多个第二焊垫11，第一器件晶圆20或第一芯片201’通过粘合层键合于第二器件晶圆10的上表面；导电凸块30，通过电镀工艺形成于相对设置的第一焊垫21和第二焊垫11之间。
本实施例中，第一器件晶圆20、第一芯片201’、第二器件晶圆10的结构，第一器件模块201、第二器件模块101的类型参照实施例1。粘合层的材料为可光刻的键合材料40，可选材料，可光刻键合材料40的厚度、涂抹的区域参照实施例1。
本实施例中第一焊垫21与第二焊垫11在垂直于第一器件晶圆20表面方向上的投影相互交错，且投影重叠区域的面积大于第一焊垫21或第二焊垫11面积的一半。导电凸块30的高度为5-200微米，和/或导电凸块30的横截面积大于10平方微米。
实施例 11
参照图6和图7，本实施例与实施例11的区别在于，粘合层中形成有第一开口41，第一开口41形成的空腔作为第一器件模块201或第一芯片201’的工作腔，和/或，作为第二器件模块101的工作腔。
实施例 12
参照图10和图11，本实施例与实施例11的区别在于，第二器件晶圆10的表面形成有第二开口14，第二焊垫11位于第二开口14外周；第二开口14作为第一器件模块201或第一芯片201’的工作腔。
实施例 13
参照图12和图13，本实施例与实施例12的区别在于，，粘合层中形成有第一开口41，且第二器件晶圆10的表面形成有第二开口14，第二焊垫11位于第二开口14外周；第一器件模块201或第一芯片201’、粘合层和第二器件晶圆10将第一开口41、第二开口14围成第一空腔，第一空腔作为第一器件模块201或第一芯片201’的工作腔。
实施例 14
参照图17和图18，本实施例与实施例11的区别在于，第二器件晶圆10的上表面形成有多个凹槽15，至少部分第二焊垫11位于凹槽15的底部；第一芯片201’嵌入凹槽15并与第二器件晶圆10键合连接。
需要说明的是，本说明书中的各个实施例均采用相关的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于结构实施例而言，由于其基本相似于方法实施例，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。
上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于权利要求书的保护范围。

Claims (23)

  1. 一种晶圆级系统封装方法，其特征在于，包括： 提供第一器件晶圆或多个第一芯片，所述第一器件晶圆或所述第一芯片的下表面具有多个裸露的第一焊垫，所述第一器件晶圆内部具有多个第一器件模块，所述第一焊垫电连接所述第一器件模块；提供第二器件晶圆，所述第二器件晶圆内部形成有多个第二器件模块，所述第二器件晶圆包括相对的上表面和下表面，所述上表面暴露出电连接所述第二器件模块的多个第二焊垫；在所述第二器件晶圆的上表面、所述第一器件模块的下表面或所述第一芯片的下表面形成粘合层，通过所述粘合层将所述第一器件晶圆或所述第一芯片与所述第二器件晶圆键合，并使所述第一焊垫和所述第二焊垫相对围成空隙；采用电镀工艺在所述空隙中形成导电凸块，以电连接所述第一焊垫和所述第二焊垫。
  2. 如权利要求1所述的晶圆级系统封装方法，其特征在于，所述粘合层中形成有第一开口，所述第一开口形成的空腔作为所述第一器件模块或所述第一芯片的工作腔，和/或，作为所述第二器件模块的工作腔。
  3. 如权利要求1所述的晶圆级系统封装方法，其特征在于，所述第二器件晶圆的表面形成有第二开口，所述第二焊垫位于所述第二开口外周；所述第二开口作为所述第一器件模块或所述第一芯片的工作腔。
  4. 如权利要求1所述的晶圆级系统封装方法，其特征在于，所述粘合层中形成有第一开口，且所述第二器件晶圆的表面形成有第二开口，所述第二焊垫位于所述第二开口外周；所述第一器件模块或所述第一芯片、所述粘合层和所述第二器件晶圆将所述第一开口、所述第二开口围成第一空腔，所述第一空腔作为所述第一器件模块或所述第一芯片的工作腔。
  5. 如权利要求1或2所述的晶圆级系统封装方法，其特征在于，所述第二器件晶圆的上表面形成有多个凹槽，至少部分所述第二焊垫位于所述凹槽的底部；
    所述第一芯片嵌入所述凹槽并与所述第二器件晶圆键合连接。
  6. 如权利要求1所述的晶圆级系统封装方法，其特征在于，所述粘合层的材料为可光刻的键合材料，所述可光刻键合材料为芯片粘结膜，金属，介质层，或聚合物材料之一或组合。
  7. 如权利要求6所述的晶圆级系统封装方法，其特征在于，所述可光刻的键合材料的厚度为5-200μm。
  8. 如权利要求6所述的晶圆级系统封装方法，其特征在于，所述可光刻的键合材料在所述第二器件晶圆表面方向上的投影以所述第一器件模块或所述第一芯片的中心为中心，并至少覆盖所述第一器件模块或所述第一芯片面积的10%。
  9. 如权利要求2所述的晶圆级系统封装方法，其特征在于，所述可光刻键合材料覆盖所述导电凸块外围的区域，所述可光刻键合材料留有连通所述空隙的流体通道，以使外部电镀液体流入所述空隙。
  10. 如权利要求1所述的晶圆级系统封装方法，其特征在于，所述第一器件模块或所述第一芯片的上表面具有第一电连接结构，所述方法还包括：
    提供第二芯片或第三器件晶圆，将所述第二芯片或第三器件晶圆与所述第一电连接结构电连接。
  11. 如权利要求1或6所述的晶圆级系统封装方法，其特征在于，所述第二器件模块的下表面具有第二电连接结构，所述方法还包括：
    提供第三芯片或第四器件晶圆，将所述第三芯片或第四器件晶圆与所述第二电连接结构电连接。
  12. 如权利要求1所述的晶圆级系统封装方法，其特征在于，所述第一焊垫与所述第二焊垫在垂直于所述第二器件晶圆表面方向上的投影相互交错，且所述投影重叠区域的面积大于所述第一焊垫或所述第二焊垫面积的一半。
  13. 13、如权利要求1所述的晶圆级系统封装方法，其特征在于，所述空隙的高度为5-200微米，和/或所述导电凸块的横截面积大于10平方微米。
  14. 如权利要求1所述的晶圆级系统封装方法，其特征在于，所述第一焊垫凹陷于所述第一器件晶圆或所述第一芯片的下表面，或者所述第一焊垫的表面与所述第一器件晶圆或所述第一芯片的下表面齐平；
    所述第二焊垫凹陷于所述第二器件晶圆的上表面，或者所述第二焊垫的表面与所述第二器件晶圆的上表面齐平。
  15. 一种晶圆级系统封装结构，其特征在于，包括：第一器件晶圆或多个第一芯片，所述第一器件晶圆或所述第一芯片的下表面具有多个焊垫，其中所述第一器件晶圆内部形成有多个第一器件模块，所述第一焊垫电连接所述第一器件模块；第二器件晶圆，所述第二器件晶圆内部形成有多个第二器件模块，所述第二器件晶圆包括相对的上表面和下表面，所述上表面具有电连接所述第二器件模块的多个第二焊垫，所述第一器件晶圆或所述第一芯片通过粘合层键合于所述第二器件晶圆的上表面；导电凸块，通过电镀工艺形成于相对设置的所述第一焊垫和所述第二焊垫之间。
  16. 如权利要求15所述的晶圆级系统封装方法，其特征在于，所述粘合层中形成有第一开口，所述第一开口形成的空腔作为所述第一器件模块或所述第一芯片的工作腔，和/或，作为所述第二器件模块的工作腔。
  17. 如权利要求15所述的晶圆级系统封装方法，其特征在于，所述第二器件晶圆的表面形成有第二开口，所述第二焊垫位于所述第二开口外周；所述第二开口作为所述第一器件模块或所述第一芯片的工作腔。
  18. 如权利要求15所述的晶圆级系统封装方法，其特征在于，所述粘合层中形成有第一开口，且所述第二器件晶圆的表面形成有第二开口，所述第二焊垫位于所述第二开口外周；所述第一器件模块或所述第一芯片、所述粘合层和所述第二器件晶圆将所述第一开口、所述第二开口围成第一空腔，所述第一空腔作为所述第一器件模块或所述第一芯片的工作腔。
  19. 如权利要求15或16所述的晶圆级系统封装方法，其特征在于，所述第二器件晶圆的上表面形成有多个凹槽，至少部分所述第二焊垫位于所述凹槽的底部；所述第一芯片嵌入所述凹槽并与所述第二器件晶圆键合连接。
  20. 如权利要求15所述的晶圆级系统封装结构，其特征在于，所述粘合层的材料为可光刻的键合材料；所述可光刻键合材料的厚度为5-200μm。
  21. 如权利要求20所述的晶圆级系统封装结构，其特征在于，所述可光刻的键合材料在所述第二器件晶圆表面方向上的投影以所述第一器件模块或所述第一芯片的中心为中心，并至少覆盖所述第一器件模块或所述第一芯片面积的10%。
  22. 如权利要求13所述的晶圆级系统封装结构，其特征在于，所述第一焊垫与所述第二焊垫在垂直于所述第一器件晶圆表面方向上的投影相互交错，且所述投影重叠区域的面积大于所述第一焊垫或所述第二焊垫面积的一半。
  23. 如权利要求13所述的晶圆级系统封装结构，其特征在于，所述导电凸块的高度为5-200微米，和/或所述导电凸块的横截面积大于10平方微米。
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