WO2020134585A1 - Mems封装结构及其制作方法 - Google Patents

Mems封装结构及其制作方法 Download PDF

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Publication number
WO2020134585A1
WO2020134585A1 PCT/CN2019/115606 CN2019115606W WO2020134585A1 WO 2020134585 A1 WO2020134585 A1 WO 2020134585A1 CN 2019115606 W CN2019115606 W CN 2019115606W WO 2020134585 A1 WO2020134585 A1 WO 2020134585A1
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Prior art keywords
mems
device wafer
contact pad
layer
electrically connected
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PCT/CN2019/115606
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English (en)
French (fr)
Inventor
秦晓珊
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中芯集成电路（宁波）有限公司上海分公司
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Priority to KR1020217014375A priority Critical patent/KR20210072815A/ko
Priority to US17/419,199 priority patent/US20220063988A1/en
Publication of WO2020134585A1 publication Critical patent/WO2020134585A1/zh

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0006—Interconnects
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/007—Interconnections between the MEMS and external electrical signals
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00269—Bonding of solid lids or wafers to the substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C3/00—Assembling of devices or systems from individually processed components
    • B81C3/001—Bonding of two components
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/02—Sensors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/02—Sensors
    • B81B2201/0214—Biosensors; Chemical sensors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/02—Sensors
    • B81B2201/0228—Inertial sensors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/02—Sensors
    • B81B2201/0228—Inertial sensors
    • B81B2201/0235—Accelerometers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/02—Sensors
    • B81B2201/0228—Inertial sensors
    • B81B2201/0242—Gyroscopes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/02—Sensors
    • B81B2201/0257—Microphones or microspeakers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/02—Sensors
    • B81B2201/0264—Pressure sensors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/03—Microengines and actuators
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/04—Optical MEMS
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/05—Microfluidics
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/10—Microfilters, e.g. for gas or fluids
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/01—Microstructural systems or auxiliary parts thereof comprising a micromechanical device connected to control or processing electronics, i.e. Smart-MEMS
    • B81B2207/012—Microstructural systems or auxiliary parts thereof comprising a micromechanical device connected to control or processing electronics, i.e. Smart-MEMS the micromechanical device and the control or processing electronics being separate parts in the same package
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/07—Interconnects
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/01—Packaging MEMS
    • B81C2203/0154—Moulding a cap over the MEMS device
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/07—Integrating an electronic processing unit with a micromechanical structure
    • B81C2203/0785—Transfer and j oin technology, i.e. forming the electronic processing unit and the micromechanical structure on separate substrates and joining the substrates
    • B81C2203/0792—Forming interconnections between the electronic processing unit and the micromechanical structure

Definitions

  • the invention relates to the semiconductor field, in particular to a MEMS packaging structure and a manufacturing method thereof.
  • MEMS micro-electromechanical system
  • the MEMS chip is usually fabricated on one wafer, and the control circuit is fabricated on another wafer, and then integrated.
  • the MEMS chip wafer and the control circuit wafer there are two main integration methods: one is to join the MEMS chip wafer and the control circuit wafer to the same package substrate, and use the leads to connect the MEMS chip wafer and the control circuit wafer to the package substrate.
  • the pads are bonded to electrically connect the control circuit and the MEMS chip; the other is to directly join the wafer with the MEMS chip and the control circuit wafer, and electrically connect their corresponding pads, thereby achieving the control circuit and Electrical connection of MEMS chip.
  • the pad area needs to be reserved on the packaging substrate, and the size is usually large, which is not conducive to the reduction of the overall device.
  • the manufacturing process of MEMS chips with different functions (or structures) is quite different, only one function (or structure) MEMS chip can usually be manufactured on the same wafer, and it is difficult to use the latter integration method in the same crystal
  • the semiconductor process is used to form MEMS chips with multiple functions, and if MEMS chip wafers with different functions are integrated on different control wafers multiple times and then interconnected, the process is complicated, the cost is high, and the obtained microelectromechanical The device size is still large. Therefore, the existing methods for integrating MEMS chips and the resulting MEMS packaging structure still cannot meet the requirements for size and functional integration capability in practical applications.
  • the present invention provides a MEMS packaging structure and a manufacturing method thereof. Another object of the present invention is to improve the functional integration capability of the MEMS packaging structure.
  • a MEMS packaging structure including:
  • a device wafer having opposite first and second surfaces the device wafer is provided with a control unit and a first interconnect structure and a second interconnect structure electrically connected to the control unit; a first contact pad , Provided on the first surface, the first contact pad is electrically connected to the first interconnect structure; a MEMS chip, bonded to the first surface, the MEMS chip has a micro cavity, used to connect external electrical A second contact pad of the signal and a bonding surface opposite to the first surface, the micro cavity of the MEMS chip has a through hole communicating with the outside of the chip, the first contact pad is electrically connected to the corresponding second contact pad Connection; a bonding layer between the first surface and the bonding surface to bond the device wafer and the MEMS chip, the bonding layer has an opening; and a rewiring layer is provided on the second On the surface, the rewiring layer is electrically connected to the second interconnect structure.
  • the redistribution layer includes input and output connectors.
  • a plurality of the MEMS chips are bonded to the first surface, and the plurality of MEMS chips belong to the same or different categories according to the manufacturing process.
  • a plurality of the MEMS chips are bonded to the first surface, and the microcavities of the plurality of MEMS chips all have through holes communicating with the outside or at least one of the MEMS chips has a closed microcavity.
  • the closed microcavity is filled with damping gas or vacuum.
  • a plurality of the MEMS chips are bonded to the first surface, and the plurality of MEMS chips include a gyroscope, an accelerometer, an inertial sensor, a pressure sensor, a displacement sensor, a humidity sensor, an optical sensor, a gas sensor, and a catalyst At least two of sensors, microwave filters, DNA amplification microsystems, MEMS microphones, and microactuators.
  • control unit includes one or more MOS transistors.
  • the first interconnection structure includes a first conductive plug, the first conductive plug penetrates at least a part of the thickness of the device wafer and is electrically connected to the control unit, and the first conductive plug One end of the plug is exposed on the first surface to be electrically connected to the corresponding first contact pad;
  • the second interconnection structure includes a second conductive plug, the second conductive plug at least penetrates a portion of the thickness of the The device wafer is electrically connected to the control unit, and one end of the second conductive plug is exposed on the second surface to be electrically connected to the rewiring layer.
  • the device wafer is a thinned wafer.
  • the first contact pad and the corresponding second contact pad are electrically connected by an electrical connection block, and the electrical connection block is located between the first contact pad and the corresponding second contact pad Area, the opening exposes the electrical connection block.
  • the MEMS packaging structure further includes:
  • An encapsulation layer is located on the first bonding surface.
  • the encapsulation layer covers the plurality of MEMS chips and fills the opening in the bonding layer.
  • the encapsulation layer exposes the through hole.
  • the bonding layer includes an adhesive material.
  • the adhesive material includes a dry film.
  • a method for manufacturing a MEMS packaging structure including the following steps:
  • a MEMS chip and a device wafer for controlling the MEMS chip, the device wafer having a first surface for bonding the MEMS chip, a control unit formed in the device wafer and electrically connected to the control unit A first interconnection structure; a first contact pad is formed on the first surface, the first contact pad is electrically connected to the first interconnection structure, the MEMS chip has a microcavity for connecting an external electrical signal Second contact pad and bonding surface, the micro cavity of the MEMS chip has a through hole communicating with the outside of the chip; the bonding layer is used to bond the MEMS chip and the device wafer, the bonding layer is located on the first surface And the bonding surface, the bonding layer has an opening that exposes the first contact pad and the corresponding second contact pad; between the first contact pad and the corresponding second Forming an electrical connection between the contact pads; forming a second interconnect structure in the device wafer, the second interconnect structure being electrically connected to the control unit; and in the device wafer and the first A rewiring layer is formed on
  • the first interconnection structure includes a first conductive plug, the first conductive plug penetrates at least a portion of the thickness of the device wafer and is electrically connected to the control unit, and the first contact pad Electrically connected to the first conductive plug.
  • the second interconnection structure includes a second conductive plug, the second conductive plug penetrates at least a part of the thickness of the device wafer and is electrically connected to the control unit, and the rewiring layer is The second conductive plug is electrically connected.
  • the step of forming an electrical connection between the first contact pad and the corresponding second contact pad includes: using an electroless plating process in the opening of the first contact pad and the corresponding The area between the second contact pads forms an electrical connection block, and the opening exposes the electrical connection block.
  • the manufacturing method of the MEMS packaging structure further includes:
  • a sacrificial layer is formed, the sacrificial layer covering the through hole.
  • the manufacturing method of the MEMS package structure further includes:
  • the MEMS packaging structure provided by the present invention includes a device wafer and a MEMS chip.
  • the device wafer is provided with a control unit, a first interconnect structure and a second interconnect structure electrically connected to the control unit, and the first The first contact pad electrically connected to the interconnect structure is provided on the first surface of the device wafer for electrical connection with the MEMS chip.
  • the MEMS chip has a microcavity, a second contact pad for connecting an external electrical signal, and a bonding surface.
  • the micro cavity of the MEMS chip has a through hole communicating with the outside of the chip, and the rewiring layer is disposed on the second surface of the device wafer and is electrically connected to the second interconnection structure, wherein the first contact pad is connected with the opening of the bonding layer
  • the second contact pads of the MEMS chip are electrically connected.
  • the MEMS packaging structure realizes the electrical interconnection of the MEMS chip and the device wafer, which can reduce the size of the packaging structure relative to the existing integration process. Further, the MEMS packaging structure may include a plurality of MEMS chips having the same or different functions and structures, which helps to improve the functional integration capability of the MEMS packaging structure while reducing the size.
  • disposing the rewiring layer and the MEMS chip on both sides of the device wafer is helpful to reduce the size of the MEMS package structure, and can reduce the design difficulty of the rewiring and interconnection structure, and improve the reliability of the MEMS package structure.
  • the manufacturing method of the MEMS packaging structure provided by the present invention can form the above MEMS packaging structure, and thus has the same or similar advantages as the above MEMS packaging structure.
  • FIG. 1 is a schematic cross-sectional view of a device wafer and a plurality of MEMS chips provided by a method for manufacturing a MEMS packaging structure according to an embodiment of the invention.
  • FIG. 2 is a schematic cross-sectional view of a method for manufacturing a MEMS package structure according to an embodiment of the present invention after forming a plurality of first contact pads on a first surface.
  • FIG. 3 is a schematic cross-sectional view of a method for manufacturing a MEMS package structure according to an embodiment of the present invention after a plurality of MEMS chips and device wafers are joined using a bonding layer.
  • FIG. 4 is a schematic cross-sectional view of a method for manufacturing a MEMS package structure after forming a sacrificial layer according to an embodiment of the invention.
  • FIG. 5 is a schematic cross-sectional view after forming an electrical connection block according to a method of manufacturing a MEMS package structure according to an embodiment of the invention.
  • FIG. 6 is a schematic cross-sectional view of a method for manufacturing a MEMS package structure after forming a package layer according to an embodiment of the invention.
  • FIG. 7 is a schematic cross-sectional view of a method for manufacturing a MEMS package structure after forming a second interconnect structure according to an embodiment of the invention.
  • FIG. 8 is a schematic cross-sectional view of a method for manufacturing a MEMS package structure after forming a rewiring layer according to an embodiment of the invention.
  • FIG. 9 is a schematic cross-sectional view of a method for manufacturing a MEMS package structure after exposing a through hole of a second microcavity according to an embodiment of the present invention.
  • FIG. 10 is a schematic cross-sectional view of a MEMS package structure according to an embodiment of the invention.
  • FIG. 11 is a schematic cross-sectional view of a MEMS package structure according to another embodiment of the invention.
  • Device wafer 100a-first surface; 100b-second surface; 101-substrate; 102-isolation structure; 103-first dielectric layer; 104-second dielectric layer; 210-first MEMS chip; 211-th A microcavity; 220-second MEMS chip; 221-second microcavity; 221a-through hole; 410-first contact pad; 201-second contact pad; 220a-bonding surface; 230-sacrificial layer; 300-inter Connection structure; 310-first interconnect structure; 311-first conductive plug; 320-second interconnect structure; 321-second conductive plug; 500-bonding layer; 510-opening; 501-encapsulation layer; 600 -Electrical connection block; 700- Rerouting layer.
  • the MEMS packaging structure of the embodiment of the present invention includes:
  • the device wafer 100 has opposing first and second surfaces 100a and 100b.
  • the device wafer 100 is provided with a control unit and an interconnection structure 300 electrically connected to the control unit; the first contact pad 410 is provided on On the first surface 100a, the first contact pad 410 is electrically connected to the interconnect structure 300; a MEMS chip (such as the second MEMS chip 220 in FIG. 9) is bonded to the first surface 100a, the MEMS The chip has a microcavity (as in the second MEMS chip 220 in FIG.
  • each of the MEMS chips has a second contact pad 201 for connecting an external electrical signal and an opposite to the first surface 100a
  • the micro cavity of the MEMS chip has a through hole communicating with the outside of the chip (as shown in FIG. 9 the second micro cavity 221 of the second MEMS chip 220 has a through hole 221a), the first contact pad 410 and the corresponding
  • the second contact pad 201 is electrically connected;
  • a bonding layer 500 is located between the first surface 100a and the bonding surface 200a to bond the device wafer 100 and the MEMS chip, the bonding layer 500 has An opening 510; and a rewiring layer 700 disposed on the second surface 100b.
  • the rewiring layer 700 is electrically connected to the interconnect structure 300.
  • the above MEMS packaging structure may include a plurality of the MEMS chips, and the device wafer 100 is used to control the plurality of MEMS chips, wherein a plurality of control units corresponding to the plurality of MEMS chips are provided for driving and bonding on the first surface thereof, respectively Multiple MEMS chips of 100a work.
  • the device wafer 100 may be formed using a general semiconductor process.
  • the above-mentioned multiple control units may be fabricated on a substrate 101 (eg, a silicon substrate) to form the device wafer 100.
  • the substrate 101 is, for example, a silicon substrate or a silicon-on-insulator (SOI) substrate.
  • the material of the substrate 101 may also include germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium or other III , Group V compounds.
  • the substrate 101 is preferably a substrate that can be easily processed or integrated in a semiconductor process.
  • the above-mentioned multiple control units may be formed based on the substrate 101.
  • Each of the control units may include one or more MOS transistors, and adjacent MOS transistors may be isolated by an isolation structure 102 provided in the device wafer 100 (or substrate 101) and an insulating material covering the substrate 101
  • the isolation structure 102 is, for example, a shallow trench isolation structure (STI) and/or a deep trench isolation structure (DTI).
  • STI shallow trench isolation structure
  • DTI deep trench isolation structure
  • the control unit outputs a control electrical signal through one source/drain of one of the MOS transistors to control the corresponding MEMS chip 200.
  • the device wafer 100 further includes a first dielectric layer 103 formed on one side surface of the substrate 101, and a source/drain (as an electrical connection terminal) for outputting a control electrical signal of the control unit is provided In the first dielectric layer 103, a second dielectric layer 104 is formed on the other side surface of the substrate 101, and materials of the first dielectric layer 103 and the second dielectric layer 104 may include silicon oxide, silicon nitride, and silicon carbide And at least one of insulating materials such as silicon oxynitride.
  • the surface of the first dielectric layer 103 away from the substrate 101 can be used as the first surface 100a of the device wafer 100, and the surface of the second dielectric layer 104 away from the substrate 101 can be used as the second surface of the device wafer 100.
  • Surface 100b the surface of the first dielectric layer 103 away from the substrate 101.
  • an interconnection structure 300 is provided in the device wafer 100, the interconnection structure 300 and the first on the first bonding surface 100a
  • the contact pad 410, the redistribution layer 700, and the control unit in the device wafer 100 are all electrically connected.
  • the interconnection structure 300 may include a first interconnection structure 310 for interconnecting the control unit in the device wafer 100 and the first contact pad 410 on the first surface 100 a, and The second interconnection structure 310 for interconnecting between the control unit in the device wafer 100 and the rewiring layer 700 on the second surface 100b.
  • the first interconnect structure 310 and the second interconnect structure 310 may include more than one electrical contact formed in the device wafer 100, electrical connections, and electrical connection lines formed between them.
  • the first interconnection structure 310 may include a first conductive plug 311 that penetrates at least a part of the thickness of the device wafer 100 and corresponds to the control The cells are electrically connected, the first contact pad 410 on the first surface 100a is electrically connected to the corresponding first conductive plug 311;
  • the second interconnection structure 320 may include a second conductive plug 321, the second conductive plug The plug 321 penetrates at least a part of the thickness of the device wafer 100 and is electrically connected to the corresponding control unit, and the rewiring of the rewiring layer 700 on the second surface 100a is electrically connected to the corresponding second conductive plug 321 .
  • the electrical signals of the control unit are led out to the first surface 100a and the second surface 100b through the first interconnect structure 310 and the second interconnect structure 320, respectively, the purpose is to set the connection and re-wiring of the device wafer 100 and the MEMS chip separately On both sides of the device wafer 100, it is advantageous to reduce the size of the MEMS package structure, and can reduce the design difficulty of the rewiring and interconnection structure, and improve the reliability of the MEMS package structure.
  • the first conductive plug 311 and the second conductive plug 321 are preferably designed in the isolation material region in the device wafer 100, as shown in FIG. 9, the first conductive plug The plug 311 preferably passes through a part of the thickness of the first dielectric layer 103 to the first surface 100a, and one end of the first conductive plug 311 is exposed to the first surface 100a to be electrically connected to the corresponding first contact pad 410 ; And the second conductive plug 321 preferably passes through the partial thickness of the first dielectric layer 103 and the isolation structure 102, one end of the second conductive plug 321 is exposed to the second surface 100b to re-wiring Layer 700 is electrically connected.
  • the device wafer 100 is preferably a thinned wafer to facilitate the fabrication of the second conductive plug 321 and to reduce the thickness of the final formed MEMS package structure.
  • the re-wiring layer 700 provided on the second surface 100 b of the device wafer 100 is electrically connected to the second interconnect structure 320.
  • the re-wiring layer 700 may use a conductive material. Specifically, as shown in FIG. 9, the redistribution layer 700 may be electrically connected to the second interconnect structure 320 through a portion covering the second conductive plug 321.
  • the re-wiring layer 700 may include re-wiring and input-output connectors, wherein the re-wiring is used to electrically connect with the second interconnect structure 320, and the input-output connectors are used to connect the MEMS package structure with external signals or devices. To process or control the circuit signals connected to it. Further, the input and output connectors are electrically connected to the rewiring, so that the input and output connectors can process or control the input and output signals of the MEMS chip through the rewiring, the second interconnection structure 320, and the control unit .
  • the multiple MEMS chips can be selected from MEMS chips with the same or different functions, uses, and structures.
  • the manufacturing processes of MEMS chips known in the art can be used to fabricate such as gyroscopes on different substrates (such as silicon wafers). Accelerometer, inertial sensor, pressure sensor, humidity sensor, displacement sensor, gas sensor, catalytic sensor, microwave filter, optical sensor (such as MEMS scanning mirror, ToF image sensor, photodetector, vertical cavity surface emitting laser (VCSEL), (Diffractive optical element (DOE)), DNA amplification microsystem, MEMS microphone, microactuator (such as micromotor, microresonator, microrelay, microlight/RF switch, light projection display, smart skin, micropump/ Valve) and other MEMS devices, and then separate independent chip dies and select at least two types as the MEMS chips in this embodiment.
  • MEMS microphone such as MEMS microphone, microactuator (such as micromotor, microresonator, microrelay, microlight/RF switch, light projection display, smart skin
  • a certain number or multiple types of MEMS chips may be selected and arranged on the first surface 100 a of the device wafer 100 according to the needs of design and application.
  • one or more sensing performance MEMS chips may be bonded on the first surface 100 a of the device wafer 100.
  • Each of the plurality of MEMS chips 200 may have an opening communicating with the outside, or at least one of the MEMS chips may have a closed micro cavity.
  • this embodiment focuses on the MEMS package structure including the device wafer 100 and the MEMS chip provided on the first surface 100a thereof, but this does not mean that the MEMS package structure of this embodiment includes only the above-mentioned components and the device wafer 100 can also be provided with/bonded with other chips (such as memory chips, communication chips, processor chips, etc.), or provided with other devices (such as power devices, bipolar devices, resistors, capacitors, etc.), which are well known in the art The device and connection relationship can also be included.
  • the MEMS chips bonded on the device wafer 100 are not limited to one, and may be two or more than three, and the structure and/or types of the multiple MEMS chips may be changed accordingly according to needs.
  • multiple MEMS chips belong to the same or different categories according to the manufacturing process.
  • the manufacturing processes of the two types of MEMS chips are not completely the same or the functions (uses) are not completely the same.
  • a plurality of MEMS chips may include a first MEMS chip 210 and a second MEMS chip 220 arranged side by side on the first surface 100 a of the device wafer 100, the first MEMS chip 210 has a first Microcavity 211, the second MEMS chip 220 has a second microcavity 221, wherein the first microcavity 211 enclosed by the first MEMS chip 210, the first microcavity 211 may be filled with damping gas or in a vacuum state
  • the second MEMS chip 220 is, for example, an air inlet MEMS chip (air inlet MEMS), where the second microcavity 221 is non-closed, and has a through hole 221a communicating with the outside of the chip.
  • the two MEMS chips 210 shown in FIG. 9 may be a gyroscope and an air intake type MEMS chip, respectively, where the through hole 210a communicates In the atmosphere, the through hole 210 a may face away from the first surface 100 a of the device wafer 100.
  • the multiple MEMS chips may include gyroscopes, accelerometers, inertial sensors, pressure sensors, displacement sensors, humidity sensors, optical sensors, gas sensors, catalytic sensors, microwave filters, DNA amplification microsystems, At least two of MEMS microphones and microactuators.
  • the air intake MEMS chip may specifically be a pressure sensor (see FIG. 10) or an optical sensor (see FIG. 11), where the pressure sensor may include a closed microcavity and a The microcavity communicating with the outside, for the optical sensor, further includes a transparent member disposed on the microcavity to receive external light signals.
  • this embodiment focuses on the MEMS package structure including the device wafer 100 and the MEMS chip provided on the first surface 100a thereof, but this does not mean that the MEMS package structure of this embodiment includes only the above-mentioned components and the device wafer 100 can also be provided with/bonded with other chips (such as memory chips, communication chips, processor chips, etc.), or provided with other devices (such as power devices, bipolar devices, resistors, capacitors, etc.), which are well known in the art
  • the device and connection relationship can also be included.
  • the first contact pad 410 and the second contact pad 220 described in this embodiment may be solder pads, or may be other connection components that function as electrical connections.
  • the MEMS chips are bonded to the first surface 100a of the device wafer 100 through the bonding layer 500 (if there are multiple MEMS chips, the multiple MEMS chips are arranged side by side on the first bonding surface 100a) .
  • each of the MEMS chips further has a second contact pad 201 for connecting an external electrical signal and a bonding surface 200a opposite to the first surface 100a, and the first surface 100a of the device wafer 100
  • a contact pad 410 is electrically connected to the second contact pad 201 of the corresponding MEMS chip, for example, through an electrical connection block 600 located in an area between the first contact pad 410 and the corresponding second contact pad 220.
  • the bonding layer 500 is used to bond and fix the plurality of MEMS chips and the device wafer 100. Specifically, the bonding layer 500 is located between the first surface 100a of the device wafer 100 and the bonding surface 200a of the MEMS chip.
  • the bonding layer 500 has an opening 510 that exposes the plurality of electrical connection blocks 600, such as As shown in FIG. 7, the opening 510 faces the gap or both sides of the plurality of MEMS chips, and part of the side surface of the electrical connection block 600 is exposed in the opening 510.
  • the material of the bonding layer 500 may include oxide or other suitable materials.
  • the bonding layer 500 may be a bonding material, and the bonding surface 200a of the plurality of MEMS chips and the first surface 100a of the device wafer 100 are bonded together by fusing bonding or vacuum bonding.
  • the bonding layer 500 may further include an adhesive material, for example, including an adhesive film (Die Attach Film, DAF) or a dry film (dry film) to bond the MEMS chip and the device wafer 100 together by means of bonding.
  • a dry film is preferably used for the bonding layer 500.
  • the dry film is a photoresist film with viscosity, which can undergo polymerization reaction after ultraviolet irradiation to form a stable substance attached to the adhesive surface and has a barrier plating
  • the advantages of etching by first attaching the dry film to the bonding surface 200a of the MEMS chip, the second contact pad 201 can be exposed from the dry film, which facilitates the subsequent matching of the second contact pad 220 to the device wafer 100
  • the first contact pad 410 is electrically connected.
  • each MEMS chip 200 may be located on the bonding surface 200a of the corresponding MEMS chip, for example, near the edge of the bonding surface 200a, so that the bonding layer 500 may be in the area of the edge of the MEMS chip or multiple MEMS chips 200 The area between them forms an opening 510 to expose the second contact pad 201.
  • the MEMS packaging structure of this embodiment may further include a packaging layer 501 on the first surface 100 a of the device wafer 100, the packaging layer 501 covers the MEMS chip and fills the bonding layer 500. With the opening 510, the encapsulation layer 501 may also cover the remaining area of the first surface 100a. At the through hole 221a of the second microcavity 221, the encapsulation layer 501 exposes the through hole 221a, so as to facilitate the operation of the air intake type MEMS chip.
  • the encapsulation layer 501 can make the MEMS chip more stable on the device wafer 100 and prevent the MEMS chip from being damaged externally.
  • the encapsulation layer 501 is, for example, a layer of plastic encapsulation material.
  • an injection molding process can be used to fill gaps between multiple MEMS chips and fix the MEMS chips on the bonding layer 500.
  • the encapsulation layer 501 can be made of a material that can be softened or flowed during the molding process, that is, has plasticity to form a certain shape.
  • the material of the encapsulation layer 501 can also undergo chemical reaction to crosslink and solidify.
  • the The material of the encapsulation layer 501 may include at least one of thermosetting resins such as phenolic resin, urea-formaldehyde resin, formaldehyde resin, epoxy resin, polyurethane, etc.
  • thermosetting resins such as phenolic resin, urea-formaldehyde resin, formaldehyde resin, epoxy resin, polyurethane, etc.
  • epoxy resin is preferably used as the material of the encapsulation layer 501, wherein the epoxy resin It can include filler materials, and can also include various additives (such as curing agent, modifier, release agent, thermochromic agent, flame retardant, etc.), such as phenol resin as a curing agent, and solid particles of silicon fine powder as filler.
  • the above MEMS packaging structure realizes the electrical interconnection of the MEMS chip and the device wafer 100, and the size of the packaging structure can be reduced relative to the existing integration process.
  • multiple MEMS chips can be integrated on the same device wafer 100, and the multiple MEMS chips can correspond to the same or different functions (uses) and structures, which helps to improve the functional integration capability of the MEMS packaging structure while reducing the size.
  • This embodiment also includes a method for manufacturing a MEMS package structure, which can be used to manufacture the MEMS package structure described above.
  • the manufacturing method of the MEMS packaging structure includes the following steps:
  • First step providing a MEMS chip and a device wafer for controlling the MEMS chip, the device wafer having a first surface for bonding the MEMS chip, a control unit formed in the device wafer and A first interconnect structure electrically connected to the control unit;
  • Second step forming a first contact pad on the first surface, the first contact pad is electrically connected to the first interconnect structure, the MEMS chip has a microcavity, a second for connecting an external electrical signal Contact pads and bonding surfaces, the micro cavity of the MEMS chip has a through hole communicating with the outside of the chip;
  • the third step bonding the MEMS chip and the device wafer with a bonding layer, the bonding layer is located between the first surface and the bonding surface, the bonding layer has an opening, and the opening is exposed The first contact pad and the corresponding second contact pad;
  • the fourth step forming an electrical connection between the first contact pad and the corresponding second contact pad;
  • Sixth step forming a rewiring layer on a surface of the device wafer opposite to the first surface, the rewiring layer is electrically connected to the second interconnect structure.
  • FIG. 1 is a schematic cross-sectional view of a device wafer and a plurality of MEMS chips provided by a method for manufacturing a MEMS packaging structure according to an embodiment of the invention.
  • a first step is first performed to provide a MEMS chip and a device wafer 100 for controlling the MEMS chip, the device wafer 100 having a first surface 100a for bonding the MEMS chip, the device wafer A control unit and a first interconnect structure 310 electrically connected to the control unit are formed in 100.
  • the MEMS chip has a microcavity, a second contact pad 201 for connecting an external electrical signal, and a bonding surface 200a.
  • the microcavity of the MEMS chip has a through hole communicating with the outside of the chip (referring to the outside of the MEMS chip).
  • MEMS chip there may be more than one MEMS chip to be integrated on the same device wafer 100, but multiple MEMS chips are provided (such as the first MEMS chip 210 and the second MEMS chip 220 in FIG. 1, wherein the second MEMS chip
  • the chip 220 has a second microcavity 221 which has a through hole 221 a) communicating with the outside and is integrated with the device wafer 100.
  • the device wafer 100 of this embodiment may include a substrate 101, such as a silicon substrate or a silicon-on-insulator (SOI) substrate.
  • a substrate 101 such as a silicon substrate or a silicon-on-insulator (SOI) substrate.
  • a mature semiconductor manufacturing process may be used to form a plurality of control units based on the substrate 101 to facilitate subsequent control of the aforementioned plurality of MEMS chips.
  • Each control unit may be a group of CMOS control circuits.
  • each control unit may include one or more MOS transistors, and adjacent MOS transistors may be provided in the substrate 101 (or device wafer 100).
  • the isolation structure 102 and the insulating material deposited on the substrate 101 are isolated.
  • the isolation structure 102 is, for example, a shallow trench isolation structure (STI) and/or a deep trench isolation structure (DTI).
  • the device wafer 100 may further include a first dielectric layer 103 formed on one side surface of the substrate 101.
  • the connection terminal of each control unit for outputting control electrical signals may be provided in the first dielectric layer 103, which may be The surface of the first dielectric layer 103 far away from the substrate 101 is used as the surface of the device wafer 100 for bonding the MEMS chip, that is, the first surface 100a, but it is not limited to this.
  • the device crystal The other surface of the circle 100 serves as a surface to which the MEMS chip is bonded.
  • the device wafer 100 can be manufactured using methods disclosed in the art.
  • the first interconnect structure 310 may include more than one electrical contact formed in the device wafer 100, electrical connections, and electrical connection lines formed between them.
  • the first interconnect structure 310 in the device wafer 100 includes a first conductive plug 311 (when multiple MEMS chips are integrated, there are multiple first conductive plugs 311), each of the first The conductive plug 311 penetrates at least a part of the thickness of the device wafer 100 and is electrically connected to the corresponding control unit in the device wafer 100.
  • the material of the first conductive plug 311 can be selected from metals or alloys containing elements such as cobalt, molybdenum, aluminum, copper, tungsten, etc.
  • the conductive material can also be selected from metal silicides (such as titanium silicide, tungsten silicide, cobalt silicide, etc.), Metal nitride (such as titanium nitride) or doped polysilicon, etc.
  • metal silicides such as titanium silicide, tungsten silicide, cobalt silicide, etc.
  • Metal nitride such as titanium nitride
  • doped polysilicon etc.
  • the material of the first conductive plug 311 is copper, and the end of the first conductive plug 311 facing the first surface 100 a of the device wafer 100 is flush with the first surface 100 a by a copper CMP process.
  • the multiple MEMS chips may be selected from MEMS chips having the same or different functions, uses and structures.
  • the multiple MEMS chips to be integrated are preferably selected from two types Or more than two categories, and, for example, multiple MEMS chips 200 may be selected from gyroscopes, accelerometers, inertial sensors, pressure sensors, flow sensors, displacement sensors, humidity sensors, optical sensors, gas sensors, catalytic sensors, microwave filters At least two of the device, DNA amplification microsystem, MEMS microphone, microactuator.
  • each MEMS chip may be an independent chip (or die), and has a micro cavity as a sensing component and a second for connecting an external electrical signal (for controlling the operation of the MEMS chip) Contact pad 201.
  • the microcavities 210 of the MEMS chip 200 may be all in communication with the outside (such as the atmosphere), or part of the microcavities of the MEMS chip may be in communication with the outside of the chip and some of the microcavities of the MEMS chip may be closed. As shown in FIG.
  • the first MEMS chip 210 and the second MEMS chip 220, the first MEMS chip 210 has a first micro cavity 211, the second MEMS chip 220 has a second micro cavity 221, in this embodiment, the first micro cavity 211 is a closed micro cavity ,
  • the first microcavity 210 may be a high vacuum or low vacuum environment, or may be filled with damping gas, and the second microcavity 221 is an unclosed microcavity, and the second microcavity 221 has communication with the outside of the chip ⁇ 221a.
  • the second contact pad 201 is exposed on the surface of the corresponding MEMS chip.
  • the second contact pad 201 may be located on the bonding surface 200a of the multiple MEMS chips, for example, near the edge of the bonding surface 200a, so that the subsequent bonding layer 500 forms an opening 510 in the area between the multiple MEMS chips to contact the second The pad 220 is exposed, but not limited to this. According to the circuit condition of the MEMS chip, the second contact pad 220 may also be formed in other areas on the surface of the MEMS chip.
  • the through hole 221a of the second microcavity 221 for communicating with the outside may face the side of the second MEMS chip 220 away from the bonding surface 200a, so as to facilitate the communication between the second microcavity 221 and the outside after the packaging structure is completed.
  • MEMS chips can be manufactured using methods disclosed in the art.
  • FIG. 2 is a schematic cross-sectional view of a method for manufacturing a MEMS package structure according to an embodiment of the present invention after forming a plurality of first contact pads on a first surface.
  • a second step is then performed to form a first contact pad 410 on the first surface 100 a.
  • the first contact pad 410 is electrically connected to the first interconnect structure 310.
  • first contact pads 410 When integrating multiple MEMS chips, there may be multiple first contact pads 410, which are formed using the same film-forming and patterning process.
  • the forming process is, for example, first depositing a metal layer, metal on the first surface 100a of the device wafer 100
  • the layer may be made of the same material as the first conductive plug 311, and formed using a physical vapor deposition (PVD) process, an atomic layer deposition (ALD), or a chemical vapor deposition (CVD) process, and then subjected to a patterning process to form a first contact ⁇ 410.
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • the first contact pad 410 is electrically connected to the first interconnect structure 310 to extract the electrical signal of the control unit.
  • corresponding multiple first contact pads 410 may also be electrically connected on the first surface 100a.
  • FIG. 3 is a schematic cross-sectional view of a method for manufacturing a MEMS package structure according to an embodiment of the present invention after bonding the plurality of MEMS chips and the device wafer using a bonding layer.
  • a third step is then performed.
  • the MEMS chip and the device wafer 100 are bonded using a bonding layer 500, the bonding layer 500 is located between the first surface 100a and the bonding surface 200a.
  • the bonding layer 500 has an opening 510 that exposes the first contact pad 410 and the corresponding second contact pad 201.
  • a bonding method such as fusion bonding or vacuum bonding may be used to bond the device wafer 100 to the plurality of MEMS chips, where the material of the bonding layer 500 is bonding Material (such as silicon oxide); in another embodiment, the device wafer 100 and the plurality of MEMS chips may be bonded together by bonding and light (or thermal) curing.
  • the bonding layer 500 may include an adhesive material, specifically, an adhesive film or a dry film may be used. Multiple MEMS chips can be bonded one by one, or they can be bonded to a carrier board by part or all of them, and then bonded to the device wafer 100 in batches or at the same time.
  • the first contact pad 410 and the corresponding second contact pad 201 may be exposed by forming a bonding material only in a partial area when bonding each MEMS chip to the device wafer 100, thereby bonding An opening 510 is formed in layer 500.
  • the bonding material when bonding each MEMS chip to the device wafer 100, the bonding material may cover the first surface 100a of the device wafer 100 and the bonding surface 200a of the MEMS chip, and then be dry-etched, for example The etching process forms an opening 510 to expose the first contact pad 410 and the corresponding second contact pad 201.
  • the purpose of forming the opening 510 in the bonding layer 500 is to connect the first contact pad 410 connected to the control unit in the device wafer 100 and the second contact pad 201 of the MEMS chip between the first surface 100a and the bonding surface 200a .
  • FIG. 4 is a schematic cross-sectional view of a method for manufacturing a MEMS package structure after forming a sacrificial layer according to an embodiment of the invention.
  • a sacrificial layer 230 is formed at 221a, and the sacrificial layer 230 covers the through hole 221a to protect the second microcavity 221.
  • the material of the sacrificial layer 230 may include one or more of photoresist, silicon carbide, and amorphous carbon.
  • the sacrificial layer 230 can be formed into a film using a chemical vapor deposition process and manufactured through a photomask process and an etching process.
  • FIG. 5 is a schematic cross-sectional view after forming an electrical connection block according to a method of manufacturing a MEMS package structure according to an embodiment of the invention. Referring to FIG. 5, a fourth step is then performed to form an electrical connection between the first contact pad 410 and the corresponding second contact pad 220.
  • the opening 510 in the bonding layer 500 exposes the first contact pad 410 and the corresponding second contact pad 220 so that it can pass between the first contact pad 410 and the corresponding second contact pad 220
  • the area forming the electrical connection block 600 connects the first contact pad 410 to the corresponding second contact pad 220.
  • the other parts of the opening 510 are still underfilled, and the opening 510 exposes the electrical connection block 600.
  • the electrical connection block 600 may be formed using an electroless plating process including, for example, a process of placing a device wafer 100 to which a plurality of MEMS chips are bonded and an opening 510 is formed in the bonding layer 500 to a solution containing metal ions (For example, solutions of electroless silver plating, nickel plating, copper plating, etc.), the metal ions are reduced to metal by using a strong reducing agent and deposited on the first contact pad 410 and the corresponding second contact pad exposed by the opening 510 On 201, after a lapse of a reaction time, the metal material connects the first contact pad 410 with the corresponding second contact pad 201, thereby forming an electrical connection block 600.
  • an electroless plating process including, for example, a process of placing a device wafer 100 to which a plurality of MEMS chips are bonded and an opening 510 is formed in the bonding layer 500 to a solution containing metal ions (For example, solutions of electroless silver plating, nickel plating, copper plating, etc
  • the material of the electrical connection block 600 includes one or more of copper, nickel, zinc, tin, silver, gold, tungsten, and magnesium.
  • the above electroless plating process may also include a step of depositing a seed layer in the area where the electrical connection block 600 is to be formed in the opening 510 before being placed in the solution containing the metal ions.
  • the first contact pad 410 is electrically connected to the corresponding second contact pad 201 by forming an electrical connection block 600 between the first surface 100a and the bonding surface 200a, which does not require wire bonding, which is beneficial for reducing the packaging structure
  • the size of the device does not affect the inside of the device wafer 100, which can improve the reliability of the MEMS packaging structure.
  • FIG. 6 is a schematic cross-sectional view of a method for manufacturing a MEMS package structure after forming a package layer according to an embodiment of the invention.
  • the manufacturing method of the MEMS packaging structure of this embodiment may further include the following steps: forming a packaging layer 501 on the first bonding surface, the packaging layer 501 covering the MEMS chip and filling the opening 510.
  • the encapsulation layer 501 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, etc., and may also include materials such as polycarbonate, polyethylene terephthalate, polyethersulfone, polyphenylene oxide,
  • Thermoplastic resins such as polyamide, polyetherimide, methacrylic resin, or cyclic polyolefin resin, may also include resins such as epoxy resin, phenolic resin, urea-formaldehyde resin, formaldehyde resin, polyurethane, acrylic resin, vinyl ester resin, acyl
  • Thermosetting resins such as imine resins, urea resins or melamine resins may also include organic insulating materials such as polystyrene and polyacrylonitrile.
  • the encapsulation layer 501 may be formed by, for example, a chemical vapor deposition process or an injection molding process.
  • a step of planarizing the device wafer 100 on the side where the bonding layer 500 is formed may further include a sacrificial layer 230 covering the opening 210a Exposed from the encapsulation layer 501 so as to directly remove the sacrificial layer 230 to open the through hole 221a of the covered second microcavity 221, and, after being flattened, may be subsequently on the side opposite to the first surface 100a
  • the encapsulation layer 501 is used as a supporting surface.
  • FIG. 7 is a schematic cross-sectional view of a method for manufacturing a MEMS package structure after forming a second interconnect structure according to an embodiment of the invention.
  • a fifth step is then performed to form a second interconnect structure 320 in the device wafer 100, and the second interconnect structure 320 is electrically connected to the control unit.
  • the method of fabricating the MEMS package structure of this embodiment may be thinned in the thickness direction on the side of the device wafer 100 opposite to the first surface 100a before forming the second interconnect structure Device wafer 100.
  • the device wafer 100 may be thinned using a back grinding process, a wet etching process, or a hydrogen ion implantation process.
  • the substrate 101 may be thinned from the side opposite to the first surface 100a. The thinned position of the substrate 101 may be flush with the bottom of the isolation structure 102 in the substrate 101.
  • a dielectric material may be deposited on the thinned surface of the device wafer 100 to form As shown in FIG. 6, the second dielectric layer 104 covers the thinned surface of the device wafer 100.
  • a side surface of the second dielectric layer 104 away from the first surface 100 a of the device wafer 100 may be used as the second surface 100 b of the device wafer 100.
  • the device wafer 100 is not shown as the orientation after flipping, but in this embodiment, the device wafer 100 is thinned and the subsequent process can also use the encapsulation layer 501 away from the first surface
  • One side surface of 100a serves as a supporting surface, and the device wafer 100 is turned over.
  • the second interconnection structure 320 may include more than one electrical contacts, electrical connectors, and electrical connection lines connecting any two of them formed in the device wafer 100.
  • the second interconnection structure 320 is included in Second conductive plugs 321 formed in the device wafer 100 (when multiple MEMS chips are integrated, there are multiple second conductive plugs 321).
  • the second conductive plug 321 penetrates at least a part of the thickness of the device wafer 100 and is electrically connected to one of the control units, and one end of the second conductive plug 320 is exposed to the second surface 100b, so as to facilitate subsequent Wiring layer connection.
  • the second interconnect structure 320 preferably passes through the isolation structure 102 region in the device wafer 100 to avoid the influence on the control unit.
  • the first conductive plug 310 and the second conductive plug 320 may be manufactured according to methods disclosed in the art, and will not be repeated here.
  • the interconnect structure 300 in the device wafer 100 may include the first interconnect structure 310 and the second interconnect structure 320 described above.
  • FIG. 8 is a schematic cross-sectional view of a method for manufacturing a MEMS package structure after forming a rewiring layer according to an embodiment of the invention.
  • a sixth step is then performed to form a surface on the side of the device wafer 100 opposite to the first surface 100 a (here, the second surface 100 b formed after the device wafer 100 is thinned)
  • the wiring layer 700 is electrically connected to the second interconnection structure 320.
  • the rewiring layer 700 may cover the second dielectric layer 104 and be in contact with the second conductive plug 320 to be electrically connected to the second interconnect structure 320.
  • the formation process of the redistribution layer 700 is, for example, first depositing a metal layer on the second surface 100b of the device wafer 100.
  • the metal layer may use a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) or a chemical vapor deposition (CVD) process After forming, a patterning process is performed to form the redistribution layer 700.
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • the rewiring layer 700 may include rewiring to draw out electrical contacts of each MEMS chip, so as to form electrical interconnections between multiple MEMS chips and the device wafer 100 and between multiple MEMS chips.
  • the redistribution layer 700 may further include input-output connectors (not shown). The input-output connectors are used to connect the MEMS package structure with external signals or devices to process or control the connected circuit signals.
  • FIG. 9 is a schematic cross-sectional view of a method for manufacturing a MEMS package structure after exposing a through hole of a second microcavity according to an embodiment of the present invention.
  • the manufacturing method of the MEMS package structure of this embodiment may further include the following steps: removing the sacrificial layer 230 to expose the through hole 221 a where the second microcavity 221 communicates with the outside.
  • the sacrificial layer 230 After the sacrificial layer 230 is exposed from the encapsulation layer 501, it may be removed by, for example, an ashing process, so that the through hole 221a on the second microcavity 221 in the second MEMS chip 220 is exposed (or opened), so that The second microcavity 210 communicates with the outside of the chip to facilitate the normal operation of the chip.
  • the formed MEMS packaging structure is shown in FIG. 9.
  • other MEMS chips can also be integrated on the device wafer and packaged.
  • the MEMS packaging structure shown in FIG. 10 and FIG. 11 can be obtained, which will not be repeated here.
  • multiple MEMS chips are integrated on the same device wafer 100 (at least one of the microcavities has a through hole communicating with the outside), and the device wafer 100 is opposite to the MEMS chip A rewiring layer 700 is formed on one side of the device, which can reduce the size of the package structure relative to existing integration methods.
  • multiple MEMS chips with the same or different functions (uses) and structures can be packaged and integrated with the same device wafer, which is conducive to improving the functional integration capability of the MEMS packaging structure while reducing the size.
  • forming the rewiring layer and the MEMS chip on both sides of the device wafer is conducive to reducing the size of the MEMS package structure, and can reduce the design difficulty of the rewiring and interconnection structure, and improve the reliability of the MEMS package structure. Therefore, it helps to meet the requirements for the integration, portability and high performance of MEMS packaging structures including MEMS chips in practical applications.

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Abstract

一种MEMS封装结构及其制作方法。其中MEMS封装结构包括MEMS芯片(210、220)及器件晶圆(100)，器件晶圆(100)中设置有控制单元和互连结构(300)，并在第一表面(100a)设有第一接触垫(410)，MEMS芯片(210、220)具有微腔(211、221)、用于连接外部电信号的第二接触垫(201)以及接合面(200a、220a)， MEMS芯片(100)的微腔(221)具有与芯片外部连通的通孔(221a)，MEMS芯片(210、220)通过接合层(500)排布于第一表面(100a)，接合层(500)中具有开口(510)，第一接触垫(410)和第二接触垫(201)电连接，再布线层(700)设置于与第一表面(100a)相对的第二表面(100b)。MEMS封装结构实现了MEMS芯片与器件晶圆的电性互连，相对于现有集成工艺可以缩小尺寸，并且同一器件晶圆上可集成相同或不同的结构和功能的MEMS芯片。

Description

MEMS封装结构及其制作方法 技术领域
本发明涉及半导体领域，特别涉及一种MEMS封装结构及其制作方法。
背景技术
随着超大规模集成电路的发展趋势，集成电路特征尺寸持续减小，人们对集成电路的封装技术的要求相应也不断提高。在传感器类MEMS封装结构的市场上，微机电系统(MEMS)芯片在诸如智能手机、健身手环、打印机、汽车、无人机以及VR/AR头戴式设备等产品领域得到了广泛的应用。常用的MEMS芯片有压力传感器、加速度计、陀螺仪、MEMS麦克风、光传感器、催化传感器等等。MEMS芯片与其他芯片通常是利用系统级封装(system in package，SIP)进行集成以形成微机电装置。具体而言，通常是在一个晶圆上制作MEMS芯片，而在另一个晶圆上制作控制电路，然后进行集成。目前常用的集成方法主要有两种：一种是将MEMS芯片晶圆和控制电路晶圆分别接合在同一个封装基底上，并利用引线将MEMS芯片晶圆和控制电路晶圆与封装基底上的焊盘键合，从而将控制电路与MEMS芯片电连接；另一种是直接将制作有MEMS芯片晶圆和控制电路晶圆接合，并使它们对应的焊盘形成电连接，进而实现控制电路与MEMS芯片的电连接。
但是，利用上述前一种集成方法制备得到的微机电装置，封装基底上需要预留出焊盘区，通常尺寸较大，不利于整体装置缩小。此外，由于不同功能(或结构)的MEMS芯片制造工艺差别较大，在同一个晶圆上通常仅能制作一种功能(或结构)的MEMS芯片，利用上述后一种集成方法难以在同一晶圆上利用半导体工艺形成多种功能的MEMS芯片，而如果将不同功能的MEMS芯片晶圆分多次集成在不同的控制晶圆上再进行互连，工序复杂，成本高，并且得到的微机电装置尺寸仍然较大。因此，现有集成MEMS芯片的方法和所得到的MEMS封装结构仍不能满足实际应用中对尺寸和功能集成能力的要求。
发明内容
为了缩小MEMS封装结构的尺寸，本发明提供了一种MEMS封装结构及其制作方法。本发明的另一目的是提高MEMS封装结构的功能集成能力。
根据本发明的一个方面，提供了一种MEMS封装结构，包括：
器件晶圆，具有相对的第一表面和第二表面，所述器件晶圆中设置有控制 单元以及与所述控制单元电连接的第一互连结构和第二互连结构；第一接触垫，设置于所述第一表面，所述第一接触垫与所述第一互连结构电连接；MEMS芯片，接合于所述第一表面，所述MEMS芯片具有微腔、用于连接外部电信号的第二接触垫以及与所述第一表面相对的接合面，所述MEMS芯片的微腔具有与芯片外部连通的通孔，所述第一接触垫与相应的所述第二接触垫电连接；接合层，位于所述第一表面和所述接合面之间以接合所述器件晶圆和所述MEMS芯片，所述接合层中具有开口；以及再布线层，设置于所述第二表面，所述再布线层与所述第二互连结构电连接。
可选的，所述再布线层包括输入输出连接件。
可选的，多个所述MEMS芯片接合于所述第一表面，且多个所述MEMS芯片根据制作工艺区分属于相同或不同的类别。
可选的，多个所述MEMS芯片接合于所述第一表面，且多个所述MEMS芯片的微腔均具有与外部连通的通孔或者至少一个所述MEMS芯片具有封闭的微腔。
可选的，所述封闭的微腔内填充有阻尼气体或者为真空。
可选的，多个所述MEMS芯片接合于所述第一表面，多个所述MEMS芯片包括陀螺仪、加速度计、惯性传感器、压力传感器、位移传感器、湿度传感器、光学传感器、气体传感器、催化传感器、微波滤波器、DNA扩增微系统、MEMS麦克风和微致动器中的至少两种。
可选的，所述控制单元包括一个或多个MOS晶体管。
可选的，所述第一互连结构包括第一导电插塞，所述第一导电插塞至少贯穿部分厚度的所述器件晶圆并与所述控制单元电连接，所述第一导电插塞的一端暴露于所述第一表面以与对应的所述第一接触垫电连接；所述第二互连结构包括第二导电插塞，所述第二导电插塞至少贯穿部分厚度的所述器件晶圆并与所述控制单元电连接，所述第二导电插塞的一端暴露于所述第二表面以与所述再布线层电连接。
可选的，所述器件晶圆为减薄晶圆。
可选的，所述第一接触垫与相应的所述第二接触垫通过电连接块电连接，所述电连接块位于所述第一接触垫与相应的所述第二接触垫之间的区域，所述开口露出所述电连接块。
可选的，所述MEMS封装结构还包括：
封装层，位于所述第一接合面上，所述封装层覆盖所述多个MEMS芯片并填充所述接合层中的开口，所述封装层露出所述通孔。
可选的，所述接合层包括胶黏材料。
可选的，所述胶黏材料包括干膜。
根据本发明的另一方面，提供了一种MEMS封装结构的制作方法，包括以下步骤：
提供MEMS芯片和用于控制所述MEMS芯片的器件晶圆，所述器件晶圆具有用于接合MEMS芯片的第一表面，所述器件晶圆中形成有控制单元以及与所述控制单元电连接的第一互连结构；在所述第一表面形成第一接触垫，所述第一接触垫与所述第一互连结构电连接，所述MEMS芯片具有微腔、用于连接外部电信号的第二接触垫以及接合面，所述MEMS芯片的微腔具有与芯片外部连通的通孔；利用接合层接合所述MEMS芯片与所述器件晶圆，所述接合层位于所述第一表面和所述接合面之间，所述接合层中具有开口，所述开口露出所述第一接触垫与相应的所述第二接触垫；在所述第一接触垫与相应的所述第二接触垫之间形成电连接；在所述器件晶圆中形成第二互连结构，所述第二互连结构与所述控制单元电连接；以及在所述器件晶圆的与所述第一表面相对的一侧表面形成再布线层，所述再布线层与所述第二互连结构电连接。
可选的，所述第一互连结构包括第一导电插塞，所述第一导电插塞至少贯穿部分厚度的所述器件晶圆并与所述控制单元电连接，所述第一接触垫与所述第一导电插塞电连接。
可选的，所述第二互连结构包括第二导电插塞，所述第二导电插塞至少贯穿部分厚度的所述器件晶圆并与所述控制单元电连接，所述再布线层与所述第二导电插塞电连接。
可选的，在所述第一接触垫与相应的所述第二接触垫之间形成电连接的步骤包括：利用化学镀工艺在所述开口中的所述第一接触垫与相应的所述第二接触垫之间的区域形成电连接块，所述开口露出所述电连接块。
可选的，在形成所述电连接块之前，所述MEMS封装结构的制作方法还包括：
形成牺牲层，所述牺牲层覆盖所述通孔。
可选的，在形成所述电连接块之后、形成所述第二互连结构之前，所述MEMS封装结构的制作方法还包括：
在所述第一接合面上形成封装层，所述封装层覆盖所述MEMS芯片并填充所述开口，所述封装层露出所述牺牲层；以及去除所述牺牲层，以露出所述通孔。
本发明提供的MEMS封装结构，包括器件晶圆及MEMS芯片，器件晶圆中设置有控制单元以及与所述控制单元电连接的第一互连结构和第二互连结构，与所述第一互连结构电连接的第一接触垫设置于器件晶圆的第一表面用于与MEMS芯片电连接，MEMS芯片具有微腔、用于连接外部电信号的第二接触垫以及与接合面，所述MEMS芯片的微腔具有与芯片外部连通的通孔，再布线层设置于器件晶圆的第二表面与所述第二互连结构电连接，其中第一接触垫在接合层的开口中与MEMS芯片的第二接触垫电连接，所述MEMS封装结构实现了MEMS芯片与器件晶圆的电性互连，相对于现有集成工艺可以缩小封装结构的尺寸。进一步的，所述MEMS封装结构可以包括多个具有相同或不同的功能及结构的MEMS芯片，在缩小尺寸的同时有利于提高所述MEMS封装结构的功能集成能力。此外，将再布线层和MEMS芯片分别设置于器件晶圆的两侧，有利于缩小MEMS封装结构的尺寸，并且可以减小再布线和互连结构的设计难度，提高MEMS封装结构的可靠性。
本发明提供的MEMS封装结构的制作方法，可形成上述MEMS封装结构，因而具有与上述MEMS封装结构相同或类似的优点。
附图说明
图1是依照本发明一实施例的MEMS封装结构的制作方法提供的器件晶圆和多个MEMS芯片的剖面示意图。
图2是依照本发明一实施例的MEMS封装结构的制作方法在第一表面形成多个第一接触垫后的剖面示意图。
图3是依照本发明一实施例的MEMS封装结构的制作方法利用接合层接合多个MEMS芯片与器件晶圆后的剖面示意图。
图4是依照本发明一实施例的MEMS封装结构的制作方法在形成牺牲层后的剖面示意图。
图5是依照本发明一实施例的MEMS封装结构的制作方法形成电连接块后的剖面示意图。
图6是依照本发明一实施例的MEMS封装结构的制作方法在形成封装层后的剖面示意图。
图7是依照本发明一实施例的MEMS封装结构的制作方法在形成第二互连结构后的剖面示意图。
图8是依照本发明一实施例的MEMS封装结构的制作方法在形成再布线层后的剖面示意图。
图9是依照本发明一实施例的MEMS封装结构的制作方法在暴露出第二微腔的通孔后的剖面示意图。
图10是依照本发明一实施例的MEMS封装结构的剖面示意图。
图11是依照本发明另一实施例的MEMS封装结构的剖面示意图。
附图标记说明：
器件晶圆；100a-第一表面；100b-第二表面；101-衬底；102-隔离结构；103-第一介质层；104-第二介质层；210-第一MEMS芯片；211-第一微腔；220-第二MEMS芯片；221-第二微腔；221a-通孔；410-第一接触垫；201-第二接触垫；220a-接合面；230-牺牲层；300-互连结构；310-第一互连结构；311-第一导电插塞；320-第二互连结构；321-第二导电插塞；500-接合层；510-开口；501-封装层；600-电连接块；700-再布线层。
具体实施方式
以下结合附图和具体实施例对本发明的MEMS封装结构及其制作方法作进一步详细说明。根据下面的说明，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
下文中的术语“第一”、“第二”等用于在类似要素之间进行区分，且未必是用于描述特定次序或时间顺序。要理解，在适当情况下，如此使用的这些术语可替换，例如可使得本文所述的本发明实施例能够不同于本文所述的或所示的其他顺序来操作。类似的，如果本文所述的方法包括一系列步骤，且本文所呈现的这些步骤的顺序并非必须是可执行这些步骤的唯一顺序，且一些所述的步骤可被省略和/或一些本文未描述的其他步骤可被添加到该方法。若某附图中的构件与其他附图中的构件相同，虽然在所有附图中都可轻易辨认出这些构件，但为了使附图的说明更为清楚，本说明书不会将所有相同构件的标号标于每一图中。
参考图9，本发明实施例的MEMS封装结构包括：
器件晶圆100，具有相对的第一表面100a和第二表面100b，所述器件晶圆 100中设置有控制单元以及与所述控制单元电连接的互连结构300；第一接触垫410设置于所述第一表面100a，所述第一接触垫410与所述互连结构300电连接；MEMS芯片(如图9中的第二MEMS芯片220)接合于所述第一表面100a，所述MEMS芯片具有微腔(如图9中第二MEMS芯片220具有第二微腔221)，所述MEMS芯片均具有用于连接外部电信号的第二接触垫201以及与所述第一表面100a相对的接合面200a，所述MEMS芯片的微腔具有与芯片外部连通的通孔(如图9中第二MEMS芯片220的第二微腔221具有通孔221a)，所述第一接触垫410与相应的所述第二接触垫201电连接；接合层500位于所述第一表面100a和所述接合面200a之间以接合所述器件晶圆100和所述MEMS芯片，所述接合层500中具有开口510；以及再布线层700，设置于所述第二表面100b，所述再布线层700与所述互连结构300电连接。
上述MEMS封装结构可包括多个所述MEMS芯片，器件晶圆100用于控制上述多个MEMS芯片，其中设置了对应控制多个MEMS芯片的多个控制单元，以分别驱动接合在其第一表面100a的多个MEMS芯片工作。器件晶圆100可以利用通用的半导体工艺形成，例如，可以在一衬底101(例如是硅衬底)上制作上述多个控制单元以形成器件晶圆100。所述衬底101例如是硅衬底或绝缘体上硅(SOI)衬底等，所述衬底101的材料还可以包括锗、锗化硅、碳化硅、砷化镓、镓化铟或其他Ⅲ、Ⅴ族化合物。所述衬底101优选是易于进行半导体工艺处理或集成的衬底。上述多个控制单元可基于衬底101形成。每个所述控制单元可包括一个或多个MOS晶体管，相邻的MOS晶体管可通过在器件晶圆100(或衬底101)中设置的隔离结构102以及在衬底101上覆盖的绝缘材料隔离，所述隔离结构102例如是浅沟槽隔离结构(STI)和/或深沟槽隔离结构(DTI)。作为示例，控制单元通过其中一个MOS晶体管的一个源/漏极将控制电信号输出，以控制对应的MEMS芯片200。本实施例中，器件晶圆100还包括在衬底101的一侧表面上形成的第一介质层103，控制单元的用于输出控制电信号的一个源/漏极(作为电连接端)设置于第一介质层103中，在衬底101的另一侧表面上形成有第二介质层104，第一介质层103和第二介质层104的材料可包括氧化硅、氮化硅、碳化硅和氮氧化硅等绝缘材料中的至少一种。本实施例中，可将第一介质层103远离衬底101的表面作为器件晶圆100的第一表面100a，而将第二介质层104远离衬底101的表面作为器件晶圆100的第二表面100b。
为了将MEMS芯片与器件晶圆100中的控制单元形成电气互连，本实施例 中，在器件晶圆100中设置了互连结构300，互连结构300与第一接合面100a上的第一接触垫410、再布线层700和器件晶圆100中的控制单元均电连接。具体的，参照图9，所述互连结构300可包括用于在器件晶圆100中的控制单元和第一表面100a上的第一接触垫410进行互连的第一互连结构310，以及用于在器件晶圆100中的控制单元和第二表面100b上的再布线层700之间进行互连的第二互连结构310。
第一互连结构310和第二互连结构310可包括在器件晶圆100中形成的一个以上的电接触、电连接件以及在它们之间形成的电连接线。参照图9，本实施例中，第一互连结构310可包括第一导电插塞311，所述第一导电插塞311至少贯穿部分厚度的所述器件晶圆100并与对应的所述控制单元电连接，第一表面100a上的第一接触垫410与相应的所述第一导电插塞311电连接；第二互连结构320可包括第二导电插塞321，所述第二导电插塞321至少贯穿部分厚度的所述器件晶圆100并与对应的所述控制单元电连接，第二表面100a上的再布线层700的再布线与相应的所述第二导电插塞321电连接。
分别通过第一互连结构310和第二互连结构320将控制单元的电信号引出至第一表面100a和第二表面100b，目的是将器件晶圆100与MEMS芯片的连接和再布线分别设在器件晶圆100的两侧，有利于缩小MEMS封装结构的尺寸，并且可以减小再布线和互连结构的设计难度，提高MEMS封装结构的可靠性。
为了避免对器件晶圆100中控制单元的影响，上述第一导电插塞311和第二导电插塞321优选设计在器件晶圆100中的隔离材料区域，如图9所示，第一导电插塞311优选穿过部分厚度的第一介质层103至第一表面100a，所述第一导电插塞311的一端暴露于所述第一表面100a以与对应的所述第一接触垫410电连接；而第二导电插塞321优选从部分厚度的第一介质层103以及隔离结构102中穿过，所述第二导电插塞321的一端暴露于所述第二表面100b以与所述再布线层700电连接。器件晶圆100优选是减薄晶圆，以方便第二导电插塞321的制作以及减小最终形成的MEMS封装结构的厚度。
在器件晶圆100的第二表面100b设置的再布线层700与第二互连结构320电连接，再布线层700可采用导电材料。具体的，如图9所示，再布线层700可通过覆盖第二导电插塞321的部分与第二互连结构320电连接。
优选的，所述再布线层700可包括再布线以及输入输出连接件，其中再布线用于与第二互连结构320电连接，输入输出连接件用于MEMS封装结构与外 部信号或装置连接，以对其连接的电路信号进行处理或控制。进一步的，所述输入输出连接件与所述再布线电连接，从而所述输入输出连接件可通过再布线、第二互连结构320以及控制单元进而对MEMS芯片的输入输出信号进行处理或控制。
多个MEMS芯片可以选自具有相同或不同的功能、用途及结构的MEMS芯片，可以分别利用本领域公知的MEMS芯片的制造工艺在不同的衬底(例如硅晶圆)上制作诸如陀螺仪、加速度计、惯性传感器、压力传感器、湿度传感器、位移传感器、气体传感器、催化传感器、微波滤波器、光学传感器(例如MEMS扫描镜、ToF图像传感器、光电探测器、垂直腔面发射激光器(VCSEL)、衍射光学元件(DOE))、DNA扩增微系统、MEMS麦克风、微致动器(例如微型马达、微型谐振器、微继电器、微型光/RF开关、光投影显示器、灵巧蒙皮、微型泵/阀)等MEMS器件，然后分割出独立的芯片晶粒并选择至少两类作为本实施例中的MEMS芯片。具体实施时，可以根据设计及用途的需要，选择一定数量或多个种类的MEMS芯片设置在器件晶圆100的第一表面100a。例如，可在器件晶圆100的第一表面100a上接合一种或者多种传感性能的MEMS芯片。多个MEMS芯片200可均具有与外部连通的开口，或者至少一个所述MEMS芯片具有封闭的微腔。可以理解，本实施例重点说明的是包括器件晶圆100及在其第一表面100a设置了MEMS芯片的MEMS封装结构，但并不表示本实施例的MEMS封装结构仅包括上述部件，器件晶圆100上也可以设置/接合有其他芯片(例如存储芯片、通讯芯片、处理器芯片等等)，或者设置有其他器件(例如功率器件、双极型器件、电阻、电容等等)，本领域公知的器件和连接关系也可包含在其中。并且，器件晶圆100上所接合的MEMS芯片并不局限于一个，也可以是两个或三个以上，且多个MEMS芯片的结构和/或种类也可以根据需要作相应变化。为了提高MEMS封装结构的功能集成能力，优选的，多个MEMS芯片根据制作工艺区分属于相同或不同的类别，此处两类MEMS芯片的制作工艺不完全相同或者功能(用途)不完全相同。
如图9所示，作为示例，多个MEMS芯片可包括在器件晶圆100的第一表面100a上并列排布的第一MEMS芯片210和第二MEMS芯片220，第一MEMS芯片210具有第一微腔211，第二MEMS芯片220具有第二微腔221，其中，第一MEMS芯片210封闭的第一微腔211，第一微腔211内可填充有阻尼气体(damping gas)或者为真空状态，第二MEMS芯片220例如是进气型MEMS 芯片(air inlet MEMS)，其中第二微腔221是非封闭的，其具有与芯片外部连通的通孔221a，可以理解，对于具有通孔的微腔，通常选择通孔221a所在表面以外的表面作为对应的MEMS芯片的接合面220a，例如，图9所示的两个MEMS芯片210可分别是陀螺仪和进气型MEMS芯片，其中通孔210a连通大气，通孔210a可朝向远离器件晶圆100的第一表面100a的方向。在又一实施例中，多个MEMS芯片可包括陀螺仪、加速度计、惯性传感器、压力传感器、位移传感器、湿度传感器、光学传感器、气体传感器、催化传感器、微波滤波器、DNA扩增微系统、MEMS麦克风、微致动器中的至少两种。参照图10和图11，在另外的实施例中，进气型MEMS芯片具体可以是压力传感器(如图10)或者光学传感器(如图11)，其中压力传感器可包括一个封闭的微腔和一个与外部连通的微腔，对于光学传感器，还包括设置于微腔上的透明部件以接收外部的光信号。
可以理解，本实施例重点说明的是包括器件晶圆100及在其第一表面100a设置了MEMS芯片的MEMS封装结构，但并不表示本实施例的MEMS封装结构仅包括上述部件，器件晶圆100上也可以设置/接合有其他芯片(例如存储芯片、通讯芯片、处理器芯片等等)，或者设置有其他器件(例如功率器件、双极型器件、电阻、电容等等)，本领域公知的器件和连接关系也可包含在其中。此外，本实施例所描述的第一接触垫410和第二接触垫220可以是焊垫，也可以是其它起电连接作用的连接部件。
本实施例中，上述MEMS芯片通过接合层500接合于器件晶圆100的第一表面100a上(如果是多个MEMS芯片，则多个MEMS芯片在所述第一接合面100a上并列排布)。具体的，每个所述MEMS芯片还具有用于连接外部电信号的第二接触垫201以及与所述第一表面100a相对的接合面200a，并且器件晶圆100的第一表面100a上的第一接触垫410与相应的MEMS芯片的第二接触垫201电连接，例如通过位于所述第一接触垫410与相应的所述第二接触垫220之间的区域的电连接块600连接。电连接块600可以是多个，以连接每个MEMS芯片的第二接触垫201和器件晶圆100上对应的第一接触垫410。
接合层500用于将上述多个MEMS芯片与器件晶圆100接合固定。具体的，接合层500位于器件晶圆100的第一表面100a和MEMS芯片的接合面200a之间，所述接合层500中具有开口510，所述开口510露出上述多个电连接块600，如图7所示，开口510朝向多个MEMS芯片之间的间隙或两侧，电连接块600的部分侧表面在开口510中被露出。
接合层500的材料可包括氧化物或其他合适的材料。例如，接合层500可以是键合材料，以通过熔融键合(fusing bonding)或真空键合等方式将上述多个MEMS芯片的接合面200a与器件晶圆100的第一表面100a键合在一起。接合层500还可以包括胶黏材料，例如包括粘片膜(Die Attach Film，DAF)或干膜(dry film)，以通过粘接方式将上述MEMS芯片与器件晶圆100接合在一起。本实施例中接合层500优选采用干膜，干膜是一种具有粘性的光致抗蚀膜，通过紫外线的照射后能够发生聚合反应形成一种稳定的物质附着于粘着面上，具有阻挡电镀和蚀刻的优点，通过将干膜先附着在MEMS芯片的接合面200a上，可以将第二接触垫201暴露与干膜之外，便于后续使第二接触垫220与器件晶圆100上相应的第一接触垫410电连接。每个MEMS芯片200的第二接触垫201可以位于对应的MEMS芯片的接合面200a上，例如靠近所述接合面200a的边缘，从而接合层500可在MEMS芯片边缘的区域或者多个MEMS芯片200之间的区域形成开口510将第二接触垫201暴露出来。
本实施例的MEMS封装结构还可包括封装层501，所述封装层501位于器件晶圆100的第一表面100a上，所述封装层501覆盖所述MEMS芯片并填充所述接合层500中的开口510，所述封装层501也可以覆盖在第一表面100a的其余区域。在第二微腔221的通孔221a处，封装层501将通孔221a露出，以便于进气型MEMS芯片的工作。
封装层501可以使所述MEMS芯片在器件晶圆100上更加稳固，并避免所述MEMS芯片受到外部损伤。所述封装层501例如是塑封材料层，例如可通过注塑工艺将多个MEMS芯片之间的间隙填满并将上述MEMS芯片固定在接合层500上。所述封装层501可采用在成型过程中能软化或流动、即具有可塑性的材料，以制成一定形状，所述封装层501的材料还可发生化学反应而交联固化，作为示例，所述封装层501的材料可以包括酚醛树脂、脲醛树脂、甲醛树脂、环氧树脂、聚氨酯等热固性树脂中的至少一种，其中，较佳地使用环氧树脂作为封装层501的材料，其中环氧树脂中可包括填料物质，还可包括各种添加剂(例如固化剂、改性剂、脱模剂、热色剂、阻燃剂等)，例如以酚醛树脂作为固化剂，以硅微粉的固体颗粒作为填料。
上述MEMS封装结构实现了MEMS芯片与器件晶圆100的电性互连，相对于现有集成工艺可以缩小封装结构的尺寸。此外，同一器件晶圆100上可集成多个MEMS芯片，多个MEMS芯片可以对应于相同或不同的功能(用途)及结 构，在缩小尺寸的同时有利于提高MEMS封装结构的功能集成能力。
本实施例还包括一种MEMS封装结构的制作方法，可以用于制作上述MEMS封装结构。所述MEMS封装结构的制作方法包括以下步骤：
第一步骤：提供MEMS芯片和用于控制所述MEMS芯片的器件晶圆，所述器件晶圆具有用于接合MEMS芯片的第一表面，所述器件晶圆中形成有控制单元以及与所述控制单元电连接的第一互连结构；
第二步骤：在所述第一表面形成第一接触垫，所述第一接触垫与所述第一互连结构电连接，所述MEMS芯片具有微腔、用于连接外部电信号的第二接触垫以及接合面，述MEMS芯片的微腔具有与芯片外部连通的通孔；
第三步骤：利用接合层接合所述MEMS芯片与所述器件晶圆，所述接合层位于所述第一表面和所述接合面之间，所述接合层中具有开口，所述开口露出所述第一接触垫与相应的所述第二接触垫；
第四步骤：在所述第一接触垫与相应的所述第二接触垫之间形成电连接；
第五步骤：在所述器件晶圆中形成第二互连结构，所述第二互连结构与所述控制单元电连接；
第六步骤：在所述器件晶圆的与所述第一表面相对的一侧表面形成再布线层，所述再布线层与所述第二互连结构电连接。
以下结合图1至图9对本发明实施例的MEMS封装结构的制作方法进行详细说明。
图1是依照本发明一实施例的MEMS封装结构的制作方法提供的器件晶圆和多个MEMS芯片的剖面示意图。参照图1，首先执行第一步骤，提供MEMS芯片和用于控制所述MEMS芯片的器件晶圆100，所述器件晶圆100具有用于接合MEMS芯片的第一表面100a，所述器件晶圆100中形成有控制单元以及与所述控制单元电连接的第一互连结构310。其中，所述MEMS芯片具有微腔、用于连接外部电信号的第二接触垫201以及接合面200a，所述MEMS芯片的微腔具有与芯片外部(指MEMS芯片的外部)连通的通孔。
本实施例中，同一器件晶圆100上要集成的MEMS芯片可以不止一个，而是提供了多个MEMS芯片(如图1中的第一MEMS芯片210和第二MEMS芯片220，其中第二MEMS芯片220具有第二微腔221，第二微腔221具有与外部连通的通孔221a)与器件晶圆100集成。
具体的，本实施例的器件晶圆100可包括衬底101，所述衬底101例如是硅 衬底或绝缘体上硅(SOI)衬底等。本实施例中，器件晶圆100中的控制单元也可不止一个。可以利用成熟的半导体制程，基于衬底101形成多个控制单元，以便于后续控制上述多个MEMS芯片。每个所述控制单元可以是一组CMOS控制电路，例如，每个控制单元可包括一个或多个MOS晶体管，相邻的MOS晶体管可通过在衬底101(或器件晶圆100)中设置的隔离结构102以及在衬底101上沉积的绝缘材料隔离，所述隔离结构102例如是浅沟槽隔离结构(STI)和/或深沟槽隔离结构(DTI)。器件晶圆100还可包括在衬底101的一侧表面上形成的第一介质层103，每个控制单元的用于输出控制电信号的连接端可设置于第一介质层103中，可将第一介质层103的远离所述衬底101的表面作为器件晶圆100用于接合MEMS芯片的面，即第一表面100a，但不限于此，在另一实施例中，也可以将器件晶圆100的其他表面作为接合MEMS芯片的面。器件晶圆100可利用本领域公开的方法制作。
第一互连结构310可包括在器件晶圆100中形成的一个以上的电接触、电连接件以及在它们之间形成的电连接线。本实施例中，器件晶圆100中的第一互连结构310包括第一导电插塞311(在集成多个MEMS芯片时，第一导电插塞311为多个)，每个所述第一导电插塞311至少贯穿部分厚度的所述器件晶圆100并与器件晶圆100中对应的所述控制单元电连接。第一导电插塞311的材料可选择含有钴、钼、铝、铜、钨等元素的金属或合金，所述导电材料还可以选择金属硅化物(如硅化钛、硅化钨、硅化钴等)、金属氮化物(如氮化钛)或者掺杂多晶硅等等。本实施例中，第一导电插塞311的材料为铜，第一导电插塞311的朝向器件晶圆100的第一表面100a的一端利用铜CMP工艺从而与所述第一表面100a齐平。
多个MEMS芯片可以选自具有相同或不同的功能、用途及结构的MEMS芯片，本实施例中，为了使MEMS封装结构具备多种用途或功能，待集成的多个MEMS芯片优选选自两种或两种以上的类别，并且，例如多个MEMS芯片200可选自陀螺仪、加速度计、惯性传感器、压力传感器、流量传感器、位移传感器、湿度传感器、光学传感器、气体传感器、催化传感器、微波滤波器、DNA扩增微系统、MEMS麦克风、微致动器中的至少两种。本实施例中，每个MEMS芯片可以是一独立的芯片(或晶粒)，并具有作为传感部件的微腔以及用于接入外部电信号(用于控制使MEMS芯片工作)的第二接触垫201。MEMS芯片200的微腔210可以全部与外部(如大气)连通，也可以是部分MEMS芯片的微腔 与芯片外部连通而部分MEMS芯片的微腔封闭，如图1所示，多个MEMS芯片包括第一MEMS芯片210和第二MEMS芯片220，第一MEMS芯片210具有第一微腔211，第二MEMS芯片220具有第二微腔221，本实施例中，第一微腔211为封闭微腔，第一微腔210内可以是高真空或低真空的环境，或者也可填充有阻尼气体(damping gas)，而第二微腔221是非封闭微腔，第二微腔221具有与芯片外部连通的通孔221a。第二接触垫201在对应的MEMS芯片表面被暴露出来。所述第二接触垫201可位于多个MEMS芯片的接合面200a，例如靠近所述接合面200a的边缘，以方便后续接合层500在多个MEMS芯片之间的区域形成开口510将第二接触垫220暴露出来，但不限于此，根据MEMS芯片的线路情况，第二接触垫220也可形成在MEMS芯片表面的其它区域。第二微腔221的用于与外部连通的通孔221a可朝向第二MEMS芯片220远离所述接合面200a的一侧，以便于在封装结构制作完成后使第二微腔221与外部连通。MEMS芯片可利用本领域公开的方法制作。
图2是依照本发明一实施例的MEMS封装结构的制作方法在第一表面形成多个第一接触垫后的剖面示意图。参照图2，接着执行第二步骤，在所述第一表面100a形成第一接触垫410，所述第一接触垫410与所述第一互连结构310电连接。
在集成多个MEMS芯片时，第一接触垫410可以是多个，并利用同一成膜及图案化工艺形成，其形成过程例如是先在器件晶圆100的第一表面100a沉积金属层，金属层可采用与第一导电插塞311相同的材料，并利用物理气相沉积(PVD)工艺、原子层沉积(ALD)或者化学气相沉积(CVD)工艺形成，然后进行图形化处理以形成第一接触垫410。所述第一接触垫410与所述第一互连结构310电连接以将控制单元的电信号引出。根据设计要求，对于集成多个MEMS芯片的情形，对应的多个第一接触垫410之间在第一表面100a上也可以进行电连接。
图3是依照本发明一实施例的MEMS封装结构的制作方法利用接合层接合所述多个MEMS芯片与所述器件晶圆后的剖面示意图。参照图3，接着执行第三步骤，利用接合层500接合所述MEMS芯片与所述器件晶圆100，所述接合层500位于所述第一表面100a和所述接合面200a之间，所述接合层500中具有开口510，所述开口510露出所述第一接触垫410与相应的所述第二接触垫201。
可选实施方式中，可以采用键合方式诸如熔融键合、真空键合的方法使器 件晶圆100与所述多个MEMS芯片键合在一起，此处所述接合层500的材料为键合材料(例如氧化硅)；在另一种实施方式中，可以采用接合且光(或热)固化的方式使器件晶圆100与所述多个MEMS芯片粘接在一起，此处所述接合层500可包括胶黏材料，具体可选用粘片膜或干膜。多个MEMS芯片可以逐个进行接合，也可以通过部分或全部先贴合在一载板上，再分批或同时与器件晶圆100接合。
可选实施方式中，可以通过在接合每个MEMS芯片至器件晶圆100上时仅在部分区域形成接合材料的方法使第一接触垫410与相应的第二接触垫201暴露出来，从而在接合层500中形成开口510。在另一种实施方式中，在接合每个MEMS芯片至器件晶圆100上时，接合材料可以覆盖器件晶圆100的第一表面100a和MEMS芯片的接合面200a，然后再通过例如干法刻蚀工艺形成开口510，以暴露出第一接触垫410与相应的第二接触垫201。在接合层500中形成开口510的目的是将连接至器件晶圆100中的控制单元的第一接触垫410和MEMS芯片的第二接触垫201在第一表面100a和接合面200a之间连接起来。
图4是依照本发明一实施例的MEMS封装结构的制作方法在形成牺牲层后的剖面示意图。参照图4，为了避免后续工艺对与外部连通的第二微腔221的影响，在将所述MEMS芯片接合于器件晶圆100的第一表面100a之后，优选在第二微腔221的通孔221a处形成了牺牲层230，牺牲层230覆盖通孔221a以保护第二微腔221。牺牲层230的材料可包括光刻胶、碳化硅和无定型碳中的一种或多种。牺牲层230可利用化学气相沉积工艺成膜并经过光罩工艺及蚀刻工艺制作。
图5是依照本发明一实施例的MEMS封装结构的制作方法形成电连接块后的剖面示意图。参照图5，接着执行第四步骤，在第一接触垫410与相应的所述第二接触垫220之间形成电连接。
本实施例中，接合层500中的开口510将上述第一接触垫410与相应的第二接触垫220露了出来，从而可以通过在第一接触垫410与相应的第二接触垫220之间的区域形成电连接块600将第一接触垫410与相应的第二接触垫220连接，所述开口510的其它部分仍为未填满状态，所述开口510露出所述电连接块600。
电连接块600可以利用化学镀工艺形成，所述化学镀工艺例如包括以下过程：将接合有多个MEMS芯片并在接合层500中形成有开口510的器件晶圆100 放置到含有金属离子的溶液(例如化学镀银、镀镍、镀铜等溶液)中，利用强还原剂使所述金属离子还原成金属而沉积在开口510所暴露的第一接触垫410与相应的所述第二接触垫201上，经过一段反应时间之后，金属材料将第一接触垫410与相应的所述第二接触垫201连接，从而形成电连接块600。电连接块600的材料包括铜、镍、锌、锡、银、金、钨和镁中的一种或多种。上述化学镀工艺也可以包括在放置到含有所述金属离子的溶液之前，先在开口510中要形成电连接块600的区域沉积种子层(seed layer)的步骤。
通过在第一表面100a和接合面200a之间形成电连接块600的方法将第一接触垫410与相应的所述第二接触垫201电连接，不需要进行引线键合，有利于缩小封装结构的尺寸，并且对器件晶圆100内部不会造成影响，可以提高MEMS封装结构的可靠性。
图6是依照本发明一实施例的MEMS封装结构的制作方法在形成封装层后的剖面示意图。参照图6，为了避免接合在器件晶圆100上的MEMS芯片受到外部因素(例如水汽、氧气、振动和撞击等等)的影响，以及使MEMS芯片更稳固，在形成上述电连接块600之后，本实施例的MEMS封装结构的制作方法还可包括以下步骤：在所述第一接合面上形成封装层501，所述封装层501覆盖所述MEMS芯片并填充所述开口510。
封装层501可包括诸如氧化硅、氮化硅、碳化硅、氮氧化硅等无机绝缘材料，也可包括诸如聚碳酸脂、聚对苯二甲酸乙二醇酯、聚醚砜、聚苯醚、聚酰胺、聚醚酰亚胺、甲基丙烯酸树脂或环聚烯烃系树脂等热塑性树脂，也可包括诸如环氧树脂、酚醛树脂、脲醛树脂、甲醛树脂、聚氨酯、亚克力树脂、乙烯酯树脂、酰亚胺类树脂、尿素树脂或三聚氰胺树脂等热固性树脂，也可包括诸如聚苯乙烯、聚丙烯腈等有机绝缘材料。封装层501可通过例如化学气相沉积工艺或者注塑工艺形成。优选地，在制作所述封装层501的过程中，还可包括在器件晶圆100的形成有所述接合层500的一侧进行平坦化处理的步骤，使得覆盖在开口210a上的牺牲层230从封装层501中露出来，以便后续直接去除牺牲层230以打开所覆盖的第二微腔221的通孔221a，并且，经平坦处理之后，可以在后续在与第一表面100a相对的一侧形成第二互连结构以及再布线层的过程中利用封装层501作为支撑面。
图7是依照本发明一实施例的MEMS封装结构的制作方法在形成第二互连结构后的剖面示意图。参照图7，接着执行第五步骤，在所述器件晶圆100中形 成第二互连结构320，所述第二互连结构320与所述控制单元电连接。
为了减小MEMS封装结构的尺寸，本实施例的MEMS封装结构的制作方法在形成第二互连结构之前，可以先在器件晶圆100的与第一表面100a相对的一侧沿厚度方向减薄器件晶圆100。具体可采用背部研磨工艺、湿法刻蚀工艺或氢离子注入等工艺减薄器件晶圆100。本实施例中，可以通过从与第一表面100a相对的一侧减薄衬底101，衬底101减薄的位置可与隔离结构102在衬底101中的底部齐平。
为了优化减薄后的表面，提高后续形成的再布线层的附着力以及减少表面缺陷，在减薄衬底101之后，可在器件晶圆100的减薄后的表面上沉积介质材料，以形成如图6所示的第二介质层104，第二介质层104覆盖器件晶圆100的经减薄后的表面。方便起见，可将第二介质层104远离器件晶圆100的第一表面100a的一侧表面作为器件晶圆100的第二表面100b。可以理解，为了体现与上述步骤的关联，器件晶圆100并没有示意为翻转之后的方位，但本实施例对器件晶圆100进行减薄及后续工艺也可利用封装层501的远离第一表面100a的一侧表面作为支撑面，将器件晶圆100翻转之后进行。
第二互连结构320可包括在器件晶圆100中形成的一个以上的电接触、电连接件以及连接它们中任意两个的电连接线，本实施例中，第二互连结构320包括在所述器件晶圆100中形成的第二导电插塞321(在集成多个MEMS芯片时，第二导电插塞321为多个)。所述第二导电插塞321至少贯穿部分厚度的所述器件晶圆100并与一个所述控制单元电连接，所述第二导电插塞320的一端露出第二表面100b，以便于后续与再布线层连接。第二互连结构320优选从器件晶圆100中的隔离结构102区域穿过，以避免对控制单元的影响。第一导电插塞310和第二导电插塞320可以依据本领域公开的方法制作，此处不再赘述。器件晶圆100中的互连结构300可包括上述第一互连结构310和第二互连结构320。
图8是依照本发明一实施例的MEMS封装结构的制作方法在形成再布线层后的剖面示意图。参照图8，接着执行第六步骤，在所述器件晶圆100的与所述第一表面100a相对的一侧表面(此处即器件晶圆100减薄后形成的第二表面100b)形成再布线层700，所述再布线层700与所述第二互连结构320电连接。
具体的，上述再布线层700可覆盖于所述第二介质层104上，并与上述第二导电插塞320接触，从而与第二互连结构320电连接。再布线层700的形成 过程例如是先在器件晶圆100的第二表面100b沉积金属层，金属层可以利用物理气相沉积(PVD)工艺、原子层沉积(ALD)或者化学气相沉积(CVD)工艺形成，然后进行图形化处理以形成再布线层700。根据设计需要，再布线层700可包括再布线，以将每个MEMS芯片的电接触引出，以便于多个MEMS芯片和器件晶圆100之间以及多个MEMS芯片之间形成电气互连。再布线层700还可包括输入输出连接件(未示出)，输入输出连接件用于MEMS封装结构与外部信号或装置连接，以对其连接的电路信号进行处理或控制。
图9是依照本发明一实施例的MEMS封装结构的制作方法在暴露出第二微腔的通孔后的剖面示意图。参照图9，本实施例的MEMS封装结构的制作方法还可包括以下步骤：去除所述牺牲层230，以露出第二微腔221与外部连通的通孔221a。在牺牲层230从封装层501中露出来之后，可以利用例如灰化工艺将其去除，使得第二MEMS芯片220中的第二微腔221上的通孔221a被暴露(或打开)，从而使第二微腔210与芯片外部连通，以便于该芯片的正常工作。
经过上述步骤，所形成MEMS封装结构如图9所示。利用类似的制作方法，也可以在器件晶圆上集成其它MEMS芯片并进行封装，例如可得到如图10和图11所示的MEMS封装结构，此处不再赘述。
本实施例的MEMS封装结构的制作方法，在同一器件晶圆100上集成了多个MEMS芯片(其中至少一个的微腔具有与外部连通的通孔)，在器件晶圆100的与MEMS芯片相对的一侧形成了再布线层700，相对于现有集成方法可以缩小封装结构的尺寸。此外，可将多个具有相同或不同的功能(用途)及结构的所述MEMS芯片与同一器件晶圆进行封装集成，在缩小尺寸的同时有利于提高所述MEMS封装结构的功能集成能力。此外，将再布线层和MEMS芯片分别形成于器件晶圆的两侧，有利于缩小MEMS封装结构的尺寸，并且可以减小再布线和互连结构的设计难度，提高MEMS封装结构的可靠性，从而有助于满足实际应用中对包括MEMS芯片的MEMS封装结构的集成度、便携性和高性能的要求。
上述描述仅是对本发明较佳实施例的描述，并非对本发明权利范围的任何限定，任何本领域技术人员在不脱离本发明的精神和范围内，都可以利用上述揭示的方法和技术内容对本发明技术方案做出可能的变动和修改，因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化及修饰，均属于本发明技术方案的保护范围。

Claims (19)

  1. 一种MEMS封装结构，其特征在于，包括：
    器件晶圆，具有相对的第一表面和第二表面，所述器件晶圆中设置有控制单元以及与所述控制单元电连接的第一互连结构和第二互连结构；
    第一接触垫，设置于所述第一表面，所述第一接触垫与所述第一互连结构电连接；
    MEMS芯片，接合于所述第一表面，所述MEMS芯片具有微腔、用于连接外部电信号的第二接触垫以及与所述第一表面相对的接合面，所述MEMS芯片的微腔具有与芯片外部连通的通孔，所述第一接触垫与相应的所述第二接触垫电连接；
    接合层，位于所述第一表面和所述接合面之间以接合所述器件晶圆和所述MEMS芯片，所述接合层中具有开口；以及
    再布线层，设置于所述第二表面，所述再布线层与所述第二互连结构电连接。
  2. 如权利要求1所述的MEMS封装结构，其特征在于，所述再布线层包括输入输出连接件。
  3. 如权利要求1所述的MEMS封装结构，其特征在于，多个所述MEMS芯片接合于所述第一表面，且多个所述MEMS芯片根据制作工艺区分属于相同或不同的类别。
  4. 如权利要求1所述的MEMS封装结构，其特征在于，多个所述MEMS芯片接合于所述第一表面，且多个所述MEMS芯片的微腔均具有与外部连通的通孔或者至少一个所述MEMS芯片具有封闭的微腔。
  5. 如权利要求4所述的MEMS封装结构，其特征在于，所述封闭的微腔内填充有阻尼气体或者为真空。
  6. 如权利要求1所述的MEMS封装结构，其特征在于，多个所述MEMS芯片接合于所述第一表面，且多个所述MEMS芯片包括陀螺仪、加速度计、惯性传感器、压力传感器、位移传感器、湿度传感器、光学传感器、气体传感器、催化传感器、微波滤波器、DNA扩增微系统、MEMS麦克风和微致动器中的至少两种。
  7. 如权利要求1所述的MEMS封装结构，其特征在于，所述控制单元包 括一个或多个MOS晶体管。
  8. 如权利要求1所述的MEMS封装结构，其特征在于，所述第一互连结构包括第一导电插塞，所述第一导电插塞至少贯穿部分厚度的所述器件晶圆并与所述控制单元电连接，所述第一导电插塞的一端暴露于所述第一表面以与对应的所述第一接触垫电连接；所述第二互连结构包括第二导电插塞，所述第二导电插塞至少贯穿部分厚度的所述器件晶圆并与所述控制单元电连接，所述第二导电插塞的一端暴露于所述第二表面以与所述再布线层电连接。
  9. 如权利要求1所述的MEMS封装结构，其特征在于，所述器件晶圆为减薄晶圆。
  10. 如权利要求1所述的MEMS封装结构，其特征在于，所述第一接触垫与相应的所述第二接触垫通过电连接块电连接，所述电连接块位于所述第一接触垫与相应的所述第二接触垫之间的区域，所述开口露出所述电连接块。
  11. 如权利要求1所述的MEMS封装结构，其特征在于，还包括：
    封装层，位于所述第一接合面上，所述封装层覆盖多个所述MEMS芯片并填充所述接合层中的开口，所述封装层露出所述通孔。
  12. 如权利要求1所述的MEMS封装结构，其特征在于，所述接合层包括胶黏材料。
  13. 如权利要求12所述的MEMS封装结构，其特征在于，所述胶黏材料包括干膜。
  14. 一种MEMS封装结构的制作方法，其特征在于，包括：
    提供MEMS芯片和用于控制所述MEMS芯片的器件晶圆，所述器件晶圆具有用于接合MEMS芯片的第一表面，所述器件晶圆中形成有控制单元以及与所述控制单元电连接的第一互连结构；
    在所述第一表面形成第一接触垫，所述第一接触垫与所述第一互连结构电连接，所述MEMS芯片具有微腔、用于连接外部电信号的第二接触垫以及接合面，所述MEMS芯片的微腔具有与芯片外部连通的通孔；
    利用接合层接合所述MEMS芯片与所述器件晶圆，所述接合层位于所述第一表面和所述接合面之间，所述接合层中具有开口，所述开口露出所述第一接触垫与相应的所述第二接触垫；
    在所述第一接触垫与相应的所述第二接触垫之间形成电连接；
    在所述器件晶圆中形成第二互连结构，所述第二互连结构与所述控制单元电连接；以及
    在所述器件晶圆的与所述第一表面相对的一侧表面形成再布线层，所述再布线层与所述第二互连结构电连接。
  15. 如权利要求14所述的MEMS封装结构的制作方法，其特征在于，所述第一互连结构包括第一导电插塞，所述第一导电插塞至少贯穿部分厚度的所述器件晶圆并与所述控制单元电连接，所述第一接触垫与所述第一导电插塞电连接。
  16. 如权利要求14所述的MEMS封装结构的制作方法，其特征在于，所述第二互连结构包括第二导电插塞，所述第二导电插塞至少贯穿部分厚度的所述器件晶圆并与所述控制单元电连接，所述再布线层与所述第二导电插塞电连接。
  17. 如权利要求14所述的MEMS封装结构的制作方法，其特征在于，在所述第一接触垫与相应的所述第二接触垫之间形成电连接的步骤包括：利用化学镀工艺在所述开口中的所述第一接触垫与相应的所述第二接触垫之间的区域形成电连接块，所述开口露出所述电连接块。
  18. 如权利要求17所述的MEMS封装结构的制作方法，其特征在于，在形成所述电连接块之前，还包括：
    形成牺牲层，所述牺牲层覆盖所述通孔。
  19. 如权利要求18所述的MEMS封装结构的制作方法，其特征在于，在形成所述电连接块之后、形成所述第二互连结构之前，还包括：
    在所述第一接合面上形成封装层，所述封装层覆盖所述MEMS芯片并填充所述开口，所述封装层露出所述牺牲层；以及
    去除所述牺牲层，以露出所述通孔。
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