WO2020134590A1 - Mems封装结构及其制作方法 - Google Patents

Mems封装结构及其制作方法 Download PDF

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Publication number
WO2020134590A1
WO2020134590A1 PCT/CN2019/115616 CN2019115616W WO2020134590A1 WO 2020134590 A1 WO2020134590 A1 WO 2020134590A1 CN 2019115616 W CN2019115616 W CN 2019115616W WO 2020134590 A1 WO2020134590 A1 WO 2020134590A1
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Prior art keywords
mems
device wafer
mems chip
layer
conductive plug
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PCT/CN2019/115616
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English (en)
French (fr)
Inventor
秦晓珊
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中芯集成电路（宁波）有限公司上海分公司
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Priority to KR1020217014346A priority Critical patent/KR20210072811A/ko
Priority to US17/418,919 priority patent/US20220112076A1/en
Publication of WO2020134590A1 publication Critical patent/WO2020134590A1/zh

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
    • B81C1/0023—Packaging together an electronic processing unit die and a micromechanical structure die
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/007—Interconnections between the MEMS and external electrical signals
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0006—Interconnects
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00269—Bonding of solid lids or wafers to the substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C3/00—Assembling of devices or systems from individually processed components
    • B81C3/001—Bonding of two components
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/02—Sensors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/03—Microengines and actuators
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/01—Microstructural systems or auxiliary parts thereof comprising a micromechanical device connected to control or processing electronics, i.e. Smart-MEMS
    • B81B2207/012—Microstructural systems or auxiliary parts thereof comprising a micromechanical device connected to control or processing electronics, i.e. Smart-MEMS the micromechanical device and the control or processing electronics being separate parts in the same package
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/07—Interconnects
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/09—Packages
    • B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
    • B81B2207/094—Feed-through, via
    • B81B2207/096—Feed-through, via through the substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/01—Packaging MEMS
    • B81C2203/0154—Moulding a cap over the MEMS device
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/07—Integrating an electronic processing unit with a micromechanical structure
    • B81C2203/0785—Transfer and j oin technology, i.e. forming the electronic processing unit and the micromechanical structure on separate substrates and joining the substrates
    • B81C2203/0792—Forming interconnections between the electronic processing unit and the micromechanical structure

Definitions

  • the invention relates to the semiconductor field, in particular to a MEMS packaging structure and a manufacturing method thereof.
  • MEMS micro-electromechanical system
  • the MEMS chip is usually fabricated on one wafer, and the control circuit is fabricated on another wafer, and then integrated.
  • the MEMS chip wafer and the control circuit wafer there are two main integration methods: one is to join the MEMS chip wafer and the control circuit wafer to the same package substrate, and use the leads to connect the MEMS chip wafer and the control circuit wafer to the package substrate.
  • the pads are bonded to electrically connect the control circuit and the MEMS chip; the other is to directly join the wafer with the MEMS chip and the control circuit wafer, and electrically connect their corresponding pads, thereby achieving the control circuit and Electrical connection of MEMS chip.
  • the pad area needs to be reserved on the packaging substrate, and the size is usually large, which is not conducive to the reduction of the overall device.
  • the manufacturing process of MEMS chips with different functions (or structures) is quite different, only one function (or structure) MEMS chip can usually be manufactured on the same wafer, and it is difficult to use the latter integration method in the same crystal
  • the semiconductor process is used to form MEMS chips with multiple functions, and if MEMS chip wafers with different functions are integrated on different control wafers multiple times and then interconnected, the process is complicated, the cost is high, and the obtained microelectromechanical The device size is still large. Therefore, the existing methods for integrating MEMS chips and the resulting MEMS packaging structure still cannot meet the requirements for size and functional integration capability in practical applications.
  • the present invention provides a MEMS packaging structure and a manufacturing method thereof. Another object of the present invention is to improve the functional integration capability of the MEMS packaging structure.
  • a MEMS packaging structure including:
  • MEMS chip having a microcavity and a contact pad for connecting an external electrical signal, the microcavity of the MEMS chip has an opening communicating with the outside; a device wafer, the device wafer has first A surface and a second surface, the MEMS chip is bonded to the first surface, a control unit corresponding to the MEMS chip is provided in the device wafer; an interconnection structure is located in the device wafer, the The interconnection structure is electrically connected to both the contact pad and the control unit; and a rewiring layer is provided on the second surface, and the rewiring layer is electrically connected to the interconnection structure.
  • a plurality of the MEMS chips are bonded to the first surface, and the plurality of MEMS chips belong to the same or different categories according to the manufacturing process.
  • a plurality of the MEMS chips are bonded to the first surface, and the microcavities of the plurality of MEMS chips all have openings that communicate with the outside or at least one of the MEMS chips has a closed microcavity.
  • the closed microcavity is filled with damping gas or vacuum.
  • a plurality of the MEMS chips are bonded to the first surface, and the plurality of MEMS chips include a gyroscope, an accelerometer, an inertial sensor, a pressure sensor, a displacement sensor, a humidity sensor, an optical sensor, a gas sensor, At least two of catalytic sensors, microwave filters, DNA amplification microsystems, MEMS microphones, and microactuators.
  • control unit includes one or more MOS transistors.
  • the interconnect structure includes:
  • a first conductive plug and a second conductive plug the first conductive plug penetrates at least part of the device wafer and is electrically connected to the control unit, and the second conductive plug penetrates the device wafer and It is electrically connected to the contact pad, wherein the rewiring layer is electrically connected to both the first conductive plug and the second conductive plug.
  • an isolation structure is further provided in the device wafer, the isolation structure is located between adjacent MOS transistors, and the first conductive plug and the second conductive plug both penetrate the isolation structure .
  • the MEMS packaging structure further includes:
  • a bonding layer covering the first surface, and the MEMS chip is bonded to the first surface through the bonding layer; and a packaging layer covering the MEMS chip and the bonding layer, And expose the opening to make the corresponding microcavity communicate with the outside.
  • the bonding layer includes an adhesive material.
  • the adhesive material includes a dry film.
  • the surface on which the contact pad is located is opposite to the first surface, and the opening of the microcavity communicating with the outside faces a direction away from the first surface.
  • the rewiring layer includes rewiring and a pad electrically connected to the rewiring.
  • a method for manufacturing a MEMS packaging structure including the following steps:
  • a MEMS chip and a device wafer for controlling the MEMS chip are provided, the MEMS chip has a microcavity and a contact pad for connecting an external electrical signal, the microcavity of the MEMS chip has an opening communicating with the outside, the
  • the device wafer has a first surface, a control unit is formed in the device wafer; the MEMS chip is bonded to the first surface; an interconnect structure is formed in the device wafer, the interconnect structure is The contact pad and the control unit are electrically connected; and a rewiring layer is formed on a surface of the device wafer opposite to the first surface, the rewiring layer is electrically connected to the interconnect structure .
  • the step of bonding the MEMS chip to the first surface includes:
  • the method further includes:
  • the sacrificial layer is removed to expose the opening.
  • the step of forming the interconnect structure in the device wafer includes:
  • a first conductive plug and a second conductive plug are formed in the device wafer, the first conductive plug penetrates at least part of the device wafer and is electrically connected to the control unit, and the second conductive plug The plug penetrates the device wafer and is electrically connected to the contact pad, wherein one ends of the first conductive plug and the second conductive plug are opposite to the first surface of the device wafer One side surface is exposed.
  • the method before forming the interconnection structure in the device wafer, the method further includes:
  • the device wafer is thinned in the thickness direction from the side of the device wafer opposite to the first surface.
  • the MEMS packaging structure provided by the present invention includes a MEMS chip and a device wafer.
  • the MEMS chip has a microcavity and a contact pad for connecting an external electrical signal.
  • the microcavity of the MEMS chip has an opening communicating with the outside.
  • the device wafer has a first surface and a second surface opposite to each other, the MEMS chip is bonded to the first surface, and the device wafer is provided with an interconnect structure electrically connected to both the contact pad and the control unit
  • a rewiring layer is provided on the second surface of the device wafer, and the rewiring layer is electrically connected to the interconnection structure.
  • the above-mentioned MEMS packaging structure realizes the electrical interconnection of the MEMS chip and the device wafer, and the MEMS chip and the rewiring layer are respectively provided on the two surfaces of the device wafer, which is conducive to reducing the size of the MEMS packaging structure.
  • the MEMS packaging structure may include a plurality of the MEMS chips having the same or different functions and structures, which helps to improve the functional integration capability of the MEMS packaging structure while reducing the size.
  • the method for forming a MEMS package structure bonds a plurality of MEMS chips to the first surface of a device wafer, and forms contact pads with the MEMS chip in the device wafer and the control unit in the device wafer A connected interconnection structure, and a rewiring layer is formed on a surface of the device wafer opposite to the first surface, wherein each of the MEMS chips has a microcavity and contact pads for connecting external electrical signals, and At least one micro cavity of the MEMS chip has an opening communicating with the outside.
  • FIG. 1 is a schematic cross-sectional view of a device wafer and a plurality of MEMS chips provided by a method for manufacturing a MEMS packaging structure according to an embodiment of the invention.
  • FIG. 2 is a schematic cross-sectional view of a method for manufacturing a MEMS packaging structure according to an embodiment of the present invention after a plurality of MEMS chips and device wafers are joined by using a bonding layer.
  • FIG. 3 is a schematic cross-sectional view of a method for manufacturing a MEMS package structure after forming a sacrificial layer according to an embodiment of the invention.
  • FIG. 4 is a schematic cross-sectional view of a method for manufacturing a MEMS package structure after forming a packaging layer according to an embodiment of the invention.
  • FIG. 5 is a schematic cross-sectional view of a method for manufacturing a MEMS package structure after thinning a substrate according to an embodiment of the present invention.
  • FIG. 6 is a schematic cross-sectional view of a method for manufacturing a MEMS package structure after forming an interconnect structure according to an embodiment of the invention.
  • FIG. 7 is a schematic cross-sectional view of a method for manufacturing a MEMS package structure after forming a rewiring layer according to an embodiment of the invention.
  • FIG. 8 is a schematic cross-sectional view of the method for manufacturing an integrated circuit device after exposing the opening of the microcavity according to an embodiment of the invention.
  • FIG. 9 is a schematic cross-sectional view of a MEMS package structure according to an embodiment of the invention.
  • FIG. 10 is a schematic cross-sectional view of a MEMS package structure according to another embodiment of the invention.
  • 100-device wafer 100a-first surface; 100b-second surface; 101-substrate; 102-isolation structure; 103-first dielectric layer; 104-second dielectric layer; 210-first MEMS chip; 211 -First microcavity; 212-First contact pad; 220-Second MEMS chip; 221-Second microcavity; 221a-Opening; 222-Second contact pad; 300-Interconnect structure; 310-First conductive plug Plug; 320-second conductive plug; 400-rerouting layer; 500-bonding layer; 223-sacrificial layer; 501-encapsulation layer.
  • the MEMS package structure of this embodiment includes a MEMS chip (such as the second MEMS chip 220 in FIG. 6) and a device wafer 100, the MEMS chip has a microcavity and a contact pad for connecting an external electrical signal,
  • the micro cavity of the MEMS chip has an opening communicating with the outside (as in FIG. 8, the second MEMS chip 220 has a second micro cavity 221 and a second contact pad 222, and the second micro cavity 221 has an opening 221a communicating with the outside)
  • the device wafer 100 includes a first surface 100a and a second surface 100b opposite to the first surface 100b.
  • the device wafer 100 is provided with a control unit corresponding to the MEMS chip and an interconnect structure 300.
  • connection structure 400 is electrically connected to the contact pads of the MEMS chip and the control unit in the device wafer, and a rewiring layer 400 is provided on the second surface 100b of the device wafer 100.
  • the rewiring layer 400 is electrically connected to the interconnection structure 300 connection.
  • the above MEMS packaging structure may include a plurality of the MEMS chips, and the device wafer 100 is used to control the plurality of MEMS chips, wherein a plurality of control units are provided to respectively drive a plurality of MEMS chips bonded to the first surface 100a thereof to work .
  • the device wafer 100 can be formed using a general semiconductor process.
  • the above-mentioned multiple control units can be fabricated on a substrate (eg, a silicon substrate) to form the device wafer 100.
  • the device wafer 100 may include a substrate 101, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, etc., the substrate 101
  • the material may also include germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium or other Group III and V compounds.
  • the substrate 101 is preferably a substrate that can be easily processed or integrated in a semiconductor process. The above-mentioned multiple control units may be formed based on the substrate 101.
  • Each of the control units may include one or more MOS transistors, and adjacent MOS transistors may be isolated by an isolation structure 102 provided in the device wafer 100 (or substrate 101) and an insulating material covering the substrate 101
  • the isolation structure 102 is, for example, a shallow trench isolation structure (STI) and/or a deep trench isolation structure (DTI).
  • the control unit outputs a control electrical signal through one source/drain of one of the MOS transistors to control the MEMS chip.
  • the device wafer 100 further includes a first dielectric layer 103 formed on one side surface of the substrate 101, and a source/drain (as an electrical connection terminal) for outputting a control electrical signal of the control unit is provided In the first dielectric layer 103, a second dielectric layer 104 is formed on the other side surface of the substrate 101, and materials of the first dielectric layer 103 and the second dielectric layer 104 may include silicon oxide, silicon nitride, and silicon carbide And at least one of insulating materials such as silicon oxynitride.
  • the surface of the first dielectric layer 103 away from the substrate 101 may be used as the first surface 100a of the device wafer 100, and the surface of the second dielectric layer 104 away from the substrate 101 may be used as the second surface 100b of the device wafer 100.
  • the substrate 101 is preferably a thin substrate to reduce the thickness of the MEMS package structure finally formed.
  • an interconnection structure 300 is provided in the device wafer 100, the interconnection structure 300 and the contact pad of the MEMS chip and the device wafer
  • the control units in 100 are electrically connected.
  • the interconnect structure 300 may include a first conductive plug 310 and a second conductive plug 320.
  • the first conductive plug 310 at least penetrates a part of the device wafer 100 and corresponds to The control unit is electrically connected
  • the second conductive plug 320 penetrates the device wafer 100 and is electrically connected to the contact pad of the corresponding MEMS chip.
  • both the first conductive plug 310 and the second conductive plug 320 penetrate the isolation structure 102 to avoid or reduce the influence on the circuit of the control unit in the device wafer 100.
  • MEMS chips can be selected from MEMS chips with the same or different functions, uses, and structures, and can be manufactured on different substrates (such as silicon wafers) using different MEMS chip manufacturing processes known in the art.
  • microactuators such as micromotors, microresonators, microrelays, microlight/RF switches, light projection displays, smart skins, micropumps/valves
  • a certain number or multiple types of MEMS chips may be selected and arranged on the first surface 100 a of the device wafer 100 according to the needs of design and application.
  • one or more sensing performance MEMS chips may be bonded on the first surface 100 a of the device wafer 100.
  • this embodiment focuses on the MEMS package structure including the device wafer 100 and the MEMS chip provided on the first surface 100a thereof, but this does not mean that the MEMS package structure of this embodiment includes only the above-mentioned components and the device wafer 100 can also be provided with/bonded with other chips (such as memory chips, communication chips, processor chips, etc.), or provided with other devices (such as power devices, bipolar devices, resistors, capacitors, etc.), which are well known in the art The device and connection relationship can also be included.
  • the MEMS chips bonded on the device wafer 100 are not limited to one, but may be two or more than three, and the structure and/or types of these MEMS chips may also be changed accordingly as needed.
  • the above-mentioned multiple MEMS chips belong to the same or different categories according to the manufacturing process.
  • the manufacturing processes of the two types of MEMS chips are not completely the same.
  • Each of the multiple MEMS chips may have an opening communicating with the outside, or at least one of the MEMS chips may have a closed microcavity, and the closed microcavity may be filled with damping gas or in a vacuum state.
  • the first MEMS chip 210 is, for example, a gyroscope, in which the first microcavity 211 is closed, and the second microcavity 221 of the second MEMS chip 220 communicates with the atmosphere and belongs to an air inlet MEMS chip (air inlet MEMS) ).
  • the multiple MEMS chips may include gyroscopes, accelerometers, inertial sensors, pressure sensors, displacement sensors, humidity sensors, optical sensors, gas sensors, catalytic sensors, microwave filters, DNA amplification microsystems, At least two of MEMS microphones and microactuators.
  • the second MEMS chip 220 is, for example, a pressure sensor (FIG. 9) or an optical sensor (FIG. 10), wherein the pressure sensor may include a closed microcavity and a communication with the outside For the optical cavity of the micro-cavity, the external light signal can be received through the transparent component on the micro-cavity.
  • the MEMS package structure of this embodiment may further include a bonding layer 500, which is used to bond and fix the MEMS chip and the device wafer 100 described above.
  • the bonding layer 500 covers the first surface 100 a of the device wafer 100, and the MEMS chip is bonded to the first surface 100 a of the device wafer 100 through the bonding layer 500.
  • the material of the bonding layer 500 may include oxide or other suitable materials.
  • the bonding layer 500 may be a bonding material to bond the plurality of MEMS chips and the first surface 100 a of the device wafer 100 by fusing bonding or vacuum bonding.
  • the bonding layer 500 may further include an adhesive material, for example, including an adhesive film (Die Attach Film, DAF) or a dry film (dry film) to bond the MEMS chip and the device wafer 100 together by means of bonding.
  • DAF Die Attach Film
  • dry film dry film
  • it is a tacky photoresist film that can undergo a polymerization reaction after ultraviolet irradiation to form a stable substance to adhere to the adhesive surface, which has the advantages of blocking electroplating and etching.
  • the MEMS chip is preferably bonded with the contact pad facing the bonding surface of the device wafer 100 (for example, the first surface 100a in this embodiment).
  • the surface of the contact pad is opposite to the first surface 100a of the device wafer 100, and the opening 221a of the second microcavity 221 communicating with the outside faces the first away from the device wafer 100 The direction of the surface 100a.
  • the MEMS packaging structure of this embodiment may further include a packaging layer 501 that covers the MEMS chip bonded on the device wafer 100 and the bonding layer 500 described above, and exposes an opening through which the micro cavity of the MEMS chip communicates with the outside.
  • the encapsulation layer 501 is disposed on the first surface 100 a side of the device wafer 100 to make the MEMS chip more stable on the device wafer 100 and to prevent the MEMS chip from being damaged externally.
  • the encapsulation layer 501 is, for example, a layer of plastic encapsulating material. For example, an injection molding process can be used to fill gaps between multiple MEMS chips and fix the multiple MEMS chips on the bonding layer 500.
  • the encapsulation layer 501 can be made of a material that can be softened or flowed during the molding process, that is, has plasticity to form a certain shape.
  • the material of the encapsulation layer 501 can also undergo chemical reaction to crosslink and solidify.
  • the The material of the encapsulation layer 501 may include at least one of thermosetting resins such as phenol resin, urea resin, formaldehyde resin, epoxy resin, unsaturated resin, polyurethane, polyimide, etc.
  • epoxy resin is preferably used for encapsulation
  • the material of the layer 501, wherein the epoxy resin may include filler materials, and may also include various additives (for example, curing agent, modifier, mold release agent, thermochromic agent, flame retardant, etc.), for example, phenol resin
  • the curing agent uses solid particles (such as silicon fine powder) or the like as a filler.
  • the MEMS package structure of this embodiment further includes a re-wiring layer 400 provided on the second surface 100b of the device wafer 100.
  • the re-wiring layer 400 may use a conductive material and be electrically connected to the above-mentioned interconnect structure 300. Specifically, as shown in FIG. 8, the rewiring layer 400 may be electrically connected to the interconnection structure 300 by covering the first conductive plug 310 and the second conductive plug 320.
  • the rewiring layer 400 may include rewiring and an I/O pad (not shown) electrically connected to the rewiring.
  • the pad is connected to other external signals or devices. To process or control the electrical signals transmitted by the rewiring.
  • the above-mentioned MEMS packaging structure integrates the MEMS chip with the device wafer 100, and the rewiring layer 400 is disposed on the other side opposite to the bonding direction, which is beneficial for reducing the size of the overall MEMS packaging structure and improving the integration.
  • the rewiring layer 400 may include rewiring and pads electrically connected to the rewiring. Arranging the pads on the second surface 100b is also beneficial for reducing the size of the MEMS package structure.
  • multiple MEMS chips can be integrated on the same device wafer 100, and the multiple MEMS chips can correspond to the same or different functions (uses) and structures, wherein at least one of the microcavities of the MEMS chip has an opening communicating with the outside , Help to improve the functional integration capability of MEMS packaging structure.
  • the embodiment of the invention also includes a method for manufacturing a MEMS packaging structure, which can be used for manufacturing the MEMS packaging structure.
  • the manufacturing method of the MEMS packaging structure includes the following steps:
  • the first step providing a plurality of EMS chips, a device wafer for controlling the MEMS chip, the MEMS chip having a micro cavity and a contact pad for connecting an external electrical signal, the micro cavity of the MEMS chip has A communicating opening, the device wafer has a first surface, and a control unit is formed in the device wafer;
  • the second step bonding the MEMS chip to the first surface
  • the third step forming an interconnect structure in the device wafer, the interconnect structure is electrically connected to both the contact pad and the control unit;
  • Fourth step forming a rewiring layer on a surface of the device wafer opposite to the first surface, the rewiring layer is electrically connected to the interconnect structure.
  • FIG. 1 is a schematic cross-sectional view of a device wafer and a plurality of MEMS chips provided by a method for manufacturing a MEMS packaging structure according to an embodiment of the invention.
  • a first step is first performed to provide a MEMS chip and a device wafer 100 for controlling the MEMS chip, the MEMS chip having a microcavity and a contact pad for connecting an external electrical signal, the MEMS chip
  • the microcavity has an opening communicating with the outside
  • the device wafer 100 has a first surface 100a
  • a control unit is formed in the device wafer 100.
  • the device wafer 100 is generally in a flat plate shape, and a plurality of control units may be arranged in the device wafer 100 in parallel.
  • the device wafer 100 of this embodiment may include a substrate 101, such as a silicon substrate or a silicon-on-insulator (SOI) substrate.
  • a mature semiconductor process can be used to form a plurality of control units based on the substrate 101 to facilitate subsequent control of a plurality of MEMS chips.
  • Each control unit may be a group of CMOS control circuits.
  • each control unit may include one or more MOS transistors, and adjacent MOS transistors may be provided in the substrate 101 (or device wafer 100).
  • the isolation structure 102 and the insulating material covering the substrate 101 are isolated.
  • the isolation structure 102 is, for example, a shallow trench isolation structure (STI) and/or a deep trench isolation structure (DTI).
  • STI shallow trench isolation structure
  • DTI deep trench isolation structure
  • the device wafer 100 may further include a first dielectric layer 103 formed on one side surface of the substrate 101, and the connection terminal of each control unit for outputting control electrical signals may be provided in the first dielectric layer 103 for convenience.
  • the surface of the first dielectric layer 103 away from the substrate 101 can be used as the first surface 100 a of the device wafer 100.
  • the device wafer 100 can be manufactured using methods disclosed in the art.
  • the multiple MEMS chips may be selected from MEMS chips having the same or different functions, uses, and structures.
  • the multiple MEMS chips to be integrated are preferably selected from two types Or more than two categories, for example, multiple MEMS chips can be selected from gyroscopes, accelerometers, inertial sensors, pressure sensors, flow sensors, displacement sensors, humidity sensors, optical sensors, gas sensors, catalytic sensors, microwave filters, DNA Expand at least two of microsystems, MEMS microphones, and microactuators.
  • each MEMS chip may be an independent chip (or die), and has a micro cavity as a sensing component and a contact pad for accessing an external electrical signal (for controlling the operation of the MEMS chip) .
  • the microcavities of the MEMS chip can be fully connected to the outside (such as the atmosphere), or part of the microcavities of the MEMS chip can communicate with the outside of the chip and some of the microcavities of the MEMS chip can be closed.
  • the enclosed microcavity can be high or low vacuum
  • the environment can also be filled with damping gas (damping gas).
  • a plurality of MEMS chips include a first MEMS chip 210 and a second MEMS chip 220, the first MEMS chip 210 is, for example, a gyroscope, and the second MEMS chip 220 is, for example, a pressure sensor, wherein the first The micro cavity of the second MEMS chip 220 is not closed. It can be understood that although only two MEMS chips are shown in FIG. 1, the MEMS packaging structure of this embodiment may also be applied to a situation including one or more than two MEMS chips.
  • the first MEMS chip 210 includes a first microcavity 211 as a sensing component and a first contact pad 212 for accessing an external electrical signal
  • the second MEMS chip 220 includes a second microcavity 221 as a sensing component And a second contact pad 222 for accessing an external electrical signal
  • the second microcavity 221 also has an opening 221a communicating with the outside of the chip.
  • the first contact pad 212 and the second contact pad 222 are exposed on the surface of the corresponding MEMS chip.
  • the manufacturing method of the MEMS chip can be manufactured by a method disclosed in the art.
  • FIG. 2 is a schematic cross-sectional view of a method for manufacturing a MEMS package structure according to an embodiment of the present invention after bonding the multiple MEMS chips and the device wafer using a bonding layer.
  • a second step is performed to bond the plurality of MEMS chips to the first surface 100 a of the device wafer 100. If there are multiple MEMS chips, the multiple MEMS chips are arranged side by side on the first surface 100a.
  • a bonding layer 500 may be formed on the first surface 100a of the device wafer 100, and the bonding layer 500 is used to bond the MEMS chip and the first surface 100a.
  • the bonding layer 500 covers the first surface 100 a of the device wafer 100.
  • a bonding method such as fusion bonding or vacuum bonding may be used to bond the device wafer 100 to the multiple MEMS chips, where the material of the bonding layer 500 is a bond Composite material (such as silicon oxide); in another embodiment, the device wafer 100 and the plurality of MEMS chips may be bonded together by bonding and light (or thermal) curing.
  • the layer 500 may include an adhesive material, specifically, an adhesive film or a dry film may be used. Multiple MEMS chips can be bonded one by one, or they can be bonded to a carrier board by part or all of them, and then bonded to the device wafer 100 in batches or at the same time.
  • the plurality of MEMS chips are preferably directed to the bonding surface of the device wafer 100 with contact pads (in this embodiment, for example, the first surface 100a)
  • the bonding is performed in an azimuth direction.
  • the opening communicating with the outside is preferably directed away from the device wafer 100 (or the first surface 100a).
  • the manufacturing method of the MEMS package structure in this embodiment is as follows: Before the third step, a step of forming a sacrificial layer and an encapsulation layer on the first surface 100a side of the device wafer 100 is also included.
  • FIG. 3 is a schematic cross-sectional view of a method for manufacturing a MEMS package structure after forming a sacrificial layer according to an embodiment of the invention.
  • a sacrificial layer 223 is formed on the first surface 100a.
  • the material may include one or more of photoresist, silicon carbide, and amorphous carbon.
  • the sacrificial layer 223 can be formed into a film using a chemical vapor deposition process and manufactured through a photomask process and an etching process.
  • FIG. 4 is a schematic cross-sectional view of a method for manufacturing a MEMS package structure after forming a packaging layer according to an embodiment of the invention.
  • a step of forming an encapsulation layer 501 on the device wafer 100 is also included.
  • the encapsulation layer 501 covers the multiple MEMS chips and the bonding layer 500 on the first surface 100a.
  • the encapsulation layer 501 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, etc., and may also include materials such as polycarbonate, polyethylene terephthalate, polyethersulfone, polyphenylene oxide,
  • Thermoplastic resins such as polyamide, polyetherimide, methacrylic resin, or cyclic polyolefin resin, may also include resins such as epoxy resin, phenolic resin, urea-formaldehyde resin, formaldehyde resin, polyurethane, acrylic resin, vinyl ester resin, acyl
  • Thermosetting resins such as imine resins, urea resins or melamine resins may also include organic insulating materials such as polystyrene and polyacrylonitrile.
  • the encapsulation layer 501 may be formed by, for example, a chemical vapor deposition process or an injection molding process.
  • a step of planarizing the side of the device wafer 100 where the bonding layer 500 is formed may be further included to make the top surface of the encapsulation layer 501 flat ( For example, parallel to the first surface 100a), in order to use the encapsulation layer 501 as a supporting surface in the subsequent formation of the interconnection structure and the rewiring layer, after the planarization process, the sacrificial layer 223 covering the opening 221a is preferably removed from the encapsulation layer 501 Exposed to facilitate subsequent direct removal of the sacrificial layer 223 to open the covered microcavity opening.
  • the manufacturing method of the MEMS package structure of this embodiment may further include: thinning from the side of the device wafer 100 opposite to the first surface 100a in the thickness direction Device wafer 100.
  • the device wafer 100 may be thinned using a back grinding process, a wet etching process, or hydrogen ion implantation.
  • the substrate 101 may be thinned from the side opposite to the first surface 100a.
  • the thinned position of the substrate 101 may be flush with the bottom of the isolation structure 102 in the substrate 101.
  • a dielectric material may be deposited on the thinned surface of the device wafer 100 to form As in the second dielectric layer 104 in FIG. 5, the second dielectric layer 104 covers the thinned surface of the device wafer 100.
  • the side of the second dielectric layer 104 away from the first surface 100 a of the device wafer 100 is used as the second surface 100 b of the device wafer 100.
  • FIG. 6 is a schematic cross-sectional view of a method for manufacturing a MEMS package structure after forming an interconnect structure according to an embodiment of the invention.
  • a third step is then performed to form an interconnect structure 300 in the device wafer 100, and the interconnect structure 300 is electrically connected to both the contact pad and the control unit.
  • the device wafer 100 is not shown as the orientation after flipping, but the process of performing the third step and the fourth step in this embodiment may also use the packaging layer 501 away from the first surface 100a One side of the surface is used as a supporting surface, after the device wafer 100 is turned over.
  • the interconnection structure 300 may include more than one electrical contacts, electrical connectors, and electrical connection lines connecting any two of them formed in the device wafer 100.
  • the interconnection structure 300 is included in the device crystal
  • the first conductive plug 310 and the second conductive plug 320 formed in the circle 300.
  • the first conductive plug 310 and the second conductive plug 320 may also be multiple.
  • Each of the first conductive plugs 310 penetrates at least part of the device wafer 100 and is electrically connected to the corresponding control unit
  • the second conductive plugs 320 penetrates the device wafer 100 and is connected to the corresponding MEMS
  • the contact pads of the chip are electrically connected, wherein one ends of the plurality of first conductive plugs 310 and the plurality of second conductive plugs 320 are opposite to the first surface 100a of the device wafer 100 One side surface (such as the second surface 100b in FIG. 6) is exposed.
  • the interconnect structure 300 forms an electrical connection with the contact pads of the multiple MEMS chips and the multiple control units in the device wafer 100 and has electrical contacts on the second surface 100 b of the device wafer 100.
  • the first conductive plug 310 and the second conductive plug 320 may be formed using methods disclosed in the art. As an example, the following process may be included: first, a first through hole and a second through hole are formed in the device wafer 100 using a photomask and an etching process, and specifically, the first through hole penetrates a part of the device wafer 100 to The second surface 100b side exposes the electrical connection end of each control unit, the second through hole penetrates the device wafer 100 and the bonding layer 500 to expose the corresponding MEMS chip contacts to be drawn from the second surface 100b side Pad, when forming the first through hole and the second through hole, it is preferable to pass through the isolation structure 102 region of the device wafer 100 to reduce or avoid the impact on the control unit; then, in the above first through hole and The second through hole is filled with a conductive material to form a first conductive plug 310 and a second conductive plug 320, respectively.
  • the filled conductive material may be disclosed in the art by using physical vapor deposition (PVD), chemical vapor deposition (CVD), or electroplating processes
  • the conductive material can be selected from metals or alloys containing elements such as cobalt, molybdenum, aluminum, copper, tungsten, etc.
  • the conductive material can also be selected from metal silicides (such as titanium silicide, tungsten silicide, cobalt silicide, etc.), metals Nitride (such as titanium nitride) or doped polysilicon, etc.
  • forming the first conductive plug 310 and the second conductive plug 320 is not limited to the above method.
  • the first through hole may be formed and then filled with a conductive material to obtain the first conductive plug 310
  • a second through hole is formed and then filled with conductive material to obtain a second conductive plug 320.
  • the conductive material covering the second surface 100b may be removed using a CMP process.
  • FIG. 7 is a schematic cross-sectional view of a method for manufacturing a MEMS package structure after forming a rewiring layer according to an embodiment of the invention.
  • a fourth step is then performed to form a redistribution layer 400 on the surface of the device wafer 100 opposite to the first surface 100a (in this embodiment, the second surface 100b of the device wafer 100) ), the rewiring layer 400 is electrically connected to the interconnect structure 300.
  • the rewiring layer 400 may cover the second dielectric layer 104 and contact the first conductive plug 310 and the second conductive plug 320 to be electrically connected to the interconnect structure 300.
  • the formation process of the redistribution layer 400 is, for example, first depositing a metal layer on the second surface 100b of the device wafer 100.
  • the metal layer may use a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) or a chemical vapor deposition (CVD) process After forming, a patterning process is performed to form the rewiring layer 400.
  • the rewiring layer 400 may use the same material as the first conductive plug 310 or the second conductive plug 320.
  • the rewiring layer 400 may further include rewiring and pads electrically connected to the rewiring.
  • the rewiring is electrically connected to the interconnect structure 300 to lead the electrical interconnection of the MEMS chip and the device wafer 100 to the device crystal. The round side away from the MEMS chip.
  • the pads electrically connected to the rewiring can be used to connect the rewiring layer 400 with other external signals or devices to process or control the electrical signals transmitted by the rewiring.
  • the manufacturing method of the integrated circuit device of this embodiment may further include the following step: removing the sacrificial layer 223 to expose the opening of the corresponding micro cavity of the MEMS chip to the outside.
  • the opening 221a corresponding to the second microcavity 221 in the second MEMS chip 220 is exposed (or opened), so that the second microcavity 221 communicates with the outside of the chip to facilitate the first Second, the normal operation of the MEMS chip 220.
  • the MEMS chip is bonded to the first surface 100 a of the device wafer 100, and the contact pad with the MEMS chip and the control unit in the device wafer 100 are formed in the device wafer 100
  • An interconnection structure 300 that is electrically connected, and a rewiring layer 400 is formed on a surface of the device wafer 100 opposite to the first surface 100a, the MEMS chip has a microcavity and contacts for connecting external electrical signals
  • the micro cavity of the MEMS chip has an opening communicating with the outside.

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Abstract

一种MEMS封装结构及其制作方法。其中MEMS封装结构包括MEMS芯片(200)及器件晶圆(100)，MEMS芯片(200)具有微腔(211、221)和用于连接外部电信号的接触垫(212、222)， MEMS芯片(200)的微腔(221)具有与外部连通的开口(221a)，器件晶圆(100)中设置有与MEMS芯片(200)对应的控制单元，互连结构(300)设置于器件晶圆(100)中并与接触垫(212、222)和控制单元均电连接，在器件晶圆(100)的第二表面设置有与互连结构(300)电连接的再布线层(400)。通过将MEMS芯片(200)和再布线层(400)分别设置在器件晶圆的两侧，有利于缩小MEMS封装结构的尺寸，同一器件晶圆上可集成多种MEMS芯片，有利于满足实际应用中对MEMS封装结构的功能集成能力的要求。

Description

MEMS封装结构及其制作方法 技术领域
本发明涉及半导体领域，特别涉及一种MEMS封装结构及其制作方法。
背景技术
随着超大规模集成电路的发展趋势，集成电路特征尺寸持续减小，人们对集成电路的封装技术的要求相应也不断提高。在传感器类MEMS封装结构的市场上，微机电系统(MEMS)芯片在诸如智能手机、健身手环、打印机、汽车、无人机以及VR/AR头戴式设备等产品领域得到了广泛的应用。常用的MEMS芯片有压力传感器、加速度计、陀螺仪、MEMS麦克风、光传感器、催化传感器等等。MEMS芯片与其他芯片通常是利用系统级封装(system in package，SIP)进行集成以形成微机电装置。具体而言，通常是在一个晶圆上制作MEMS芯片，而在另一个晶圆上制作控制电路，然后进行集成。目前常用的集成方法主要有两种：一种是将MEMS芯片晶圆和控制电路晶圆分别接合在同一个封装基底上，并利用引线将MEMS芯片晶圆和控制电路晶圆与封装基底上的焊盘键合，从而将控制电路与MEMS芯片电连接；另一种是直接将制作有MEMS芯片晶圆和控制电路晶圆接合，并使它们对应的焊盘形成电连接，进而实现控制电路与MEMS芯片的电连接。
但是，利用上述前一种集成方法制备得到的微机电装置，封装基底上需要预留出焊盘区，通常尺寸较大，不利于整体装置缩小。此外，由于不同功能(或结构)的MEMS芯片制造工艺差别较大，在同一个晶圆上通常仅能制作一种功能(或结构)的MEMS芯片，利用上述后一种集成方法难以在同一晶圆上利用半导体工艺形成多种功能的MEMS芯片，而如果将不同功能的MEMS芯片晶圆分多次集成在不同的控制晶圆上再进行互连，工序复杂，成本高，并且得到的微机电装置尺寸仍然较大。因此，现有集成MEMS芯片的方法和所得到的MEMS封装结构仍不能满足实际应用中对尺寸和功能集成能力的要求。
发明内容
为了缩小MEMS封装结构的尺寸，本发明提供了一种MEMS封装结构及其制作方法。本发明的另一目的是提高MEMS封装结构的功能集成能力。
根据本发明的一个方面，提供了一种MEMS封装结构，包括：
MEMS芯片，所述MEMS芯片具有微腔和用于连接外部电信号的接触垫，所述MEMS芯片的微腔具有与外部连通的开口；器件晶圆，所述器件晶圆具有彼此相对的第一表面和第二表面，所述MEMS芯片接合于所述第一表面，所述器件晶圆中设置有与所述MEMS芯片对应的控制单元；互连结构，位于所述器件晶圆中，所述互连结构与所述接触垫和所述控制单元均电连接；以及再布线层，设置于所述第二表面，所述再布线层与所述互连结构电连接。
可选的，多个所述MEMS芯片接合于所述第一表面，且多个所述MEMS芯片根据制作工艺区分属于相同或不同的类别。
可选的，多个所述MEMS芯片接合于所述第一表面，且多个所述MEMS芯片的微腔均具有与外部连通的开口或者至少一个所述MEMS芯片具有封闭的微腔。
可选的，所述封闭的微腔内填充有阻尼气体或者为真空。
可选的，多个所述MEMS芯片接合于所述第一表面，且多个所述MEMS芯片包括陀螺仪、加速度计、惯性传感器、压力传感器、位移传感器、湿度传感器、光学传感器、气体传感器、催化传感器、微波滤波器、DNA扩增微系统、MEMS麦克风、微致动器中的至少两种。
可选的，所述控制单元包括一个或多个MOS晶体管。
可选的，所述互连结构包括：
第一导电插塞和第二导电插塞，所述第一导电插塞至少贯穿部分所述器件晶圆并与所述控制单元电连接，所述第二导电插塞贯穿所述器件晶圆并与所述接触垫电连接，其中，所述再布线层与所述第一导电插塞和所述第二导电插塞均电连接。
可选的，所述器件晶圆中还设置有隔离结构，所述隔离结构位于相邻的MOS晶体管之间，所述第一导电插塞和所述第二导电插塞均贯穿所述隔离结构。
可选的，所述MEMS封装结构还包括：
接合层，所述接合层覆盖所述第一表面，所述MEMS芯片通过所述接合层接合于所述第一表面；以及封装层，所述封装层覆盖所述MEMS芯片和所述接合层，并暴露出所述开口以使对应的微腔与外部连通。
可选的，所述接合层包括胶黏材料。
可选的，所述胶黏材料包括干膜。
可选的，所述接触垫所在表面与所述第一表面相对，所述微腔与外部连通的开口朝向远离所述第一表面的方向。
可选的，所述再布线层包括再布线以及与所述再布线电连接的焊垫。
根据本发明的另一方面，还提供了一种MEMS封装结构的制作方法，包括以下步骤：
提供MEMS芯片、用于控制所述MEMS芯片的器件晶圆，所述MEMS芯片具有微腔和用于连接外部电信号的接触垫，所述MEMS芯片的微腔具有与外部连通的开口，所述器件晶圆具有第一表面，所述器件晶圆中形成有控制单元；将所述MEMS芯片接合于所述第一表面；在所述器件晶圆中形成互连结构，所述互连结构与所述接触垫和所述控制单元均电连接；以及形成再布线层于所述器件晶圆的与所述第一表面相对的一侧表面，所述再布线层与所述互连结构电连接。
可选的，将所述MEMS芯片接合于所述第一表面的步骤包括：
形成接合层，利用所述接合层接合所述MEMS芯片与所述第一表面；形成牺牲层，所述牺牲层覆盖所述开口；以及形成封装层，所述封装层覆盖所述MEMS芯片和所述接合层，并暴露出所述牺牲层。
可选的，在形成所述再布线层后，还包括：
去除所述牺牲层，以暴露出所述开口。
可选的，在所述器件晶圆中形成所述互连结构的步骤包括：
在所述器件晶圆中形成第一导电插塞和第二导电插塞，所述第一导电插塞至少贯穿部分所述器件晶圆并与所述控制单元电连接，所述第二导电插塞贯穿所述器件晶圆并与所述接触垫电连接，其中，所述第一导电插塞和所述第二导电插塞的一端在所述器件晶圆的与所述第一表面相对的一侧表面被暴露出来。
可选的，在所述器件晶圆中形成所述互连结构之前，还包括：
从所述器件晶圆的与所述第一表面相对的一侧沿厚度方向减薄所述器件晶圆。
本发明提供的MEMS封装结构，包括MEMS芯片及器件晶圆，所述MEMS芯片具有微腔和用于连接外部电信号的接触垫，所述MEMS芯片的微腔具有与外部连通的开口，所述器件晶圆具有彼此相对的第一表面和第二表面，所述 MEMS芯片接合于所述第一表面，所述器件晶圆中设置有与所述接触垫和控制单元均电连接的互连结构，在器件晶圆的第二表面设置有再布线层，所述再布线层与所述互连结构电连接。上述MEMS封装结构实现了MEMS芯片与器件晶圆的电性互连，并且，将MEMS芯片和再布线层分别设置在器件晶圆的两侧表面，有利于缩小MEMS封装结构的尺寸。进一步的，所述MEMS封装结构可以包括多个具有相同或不同的功能及结构的所述MEMS芯片，在缩小尺寸的同时有利于提高所述MEMS封装结构的功能集成能力。
本发明提供的MEMS封装结构的形成方法，将多个MEMS芯片接合于器件晶圆的第一表面，在所述器件晶圆中形成与MEMS芯片的接触垫和器件晶圆中的控制单元均电连接的互连结构，并在器件晶圆的与所述第一表面相对的一侧表面形成再布线层，其中每个所述MEMS芯片具有微腔和用于连接外部电信号的接触垫，并且至少一个所述MEMS芯片的微腔具有与外部连通的开口。通过将MEMS芯片和再布线层分别设置在器件晶圆的两侧，有利于缩小MEMS封装结构的尺寸。此外，可将多个具有相同或不同的功能及结构的所述MEMS芯片与同一器件晶圆进行封装集成，在缩小尺寸的同时有利于提高所述MEMS封装结构的功能集成能力。
附图说明
图1是依照本发明一实施例的MEMS封装结构的制作方法提供的器件晶圆和多个MEMS芯片的剖面示意图。
图2是依照本发明一实施例的MEMS封装结构的制作方法利用接合层接合多个MEMS芯片与器件晶圆后的剖面示意图。
图3是依照本发明一实施例的MEMS封装结构的制作方法在形成牺牲层后的剖面示意图。
图4是依照本发明一实施例的MEMS封装结构的制作方法在形成封装层后的剖面示意图。
图5是依照本发明一实施例的MEMS封装结构的制作方法在减薄衬底后的剖面示意图。
图6是依照本发明一实施例的MEMS封装结构的制作方法在形成互连结构后的剖面示意图。
图7是依照本发明一实施例的MEMS封装结构的制作方法在形成再布线层后的剖面示意图。
图8是依照本发明一实施例的集成电路器件的制作方法在暴露出微腔的开口后的剖面示意图。
图9是依照本发明一实施例的MEMS封装结构的剖面示意图。
图10是依照本发明另一实施例的MEMS封装结构的剖面示意图。
附图标记说明：
100-器件晶圆；100a-第一表面；100b-第二表面；101-衬底；102-隔离结构；103-第一介质层；104-第二介质层；210-第一MEMS芯片；211-第一微腔；212-第一接触垫；220-第二MEMS芯片；221-第二微腔；221a-开口；222-第二接触垫；300-互连结构；310-第一导电插塞；320-第二导电插塞；400-再布线层；500-接合层；223-牺牲层；501-封装层。
具体实施方式
以下结合附图和具体实施例对本发明的MEMS封装结构及其制作方法作进一步详细说明。根据下面的说明，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
下文中的术语“第一”、“第二”等用于在类似要素之间进行区分，且未必是用于描述特定次序或时间顺序。要理解，在适当情况下，如此使用的这些术语可替换，例如可使得本文所述的本发明实施例能够不同于本文所述的或所示的其他顺序来操作。类似的，如果本文所述的方法包括一系列步骤，且本文所呈现的这些步骤的顺序并非必须是可执行这些步骤的唯一顺序，且一些所述的步骤可被省略和/或一些本文未描述的其他步骤可被添加到该方法。若某附图中的构件与其他附图中的构件相同，虽然在所有附图中都可轻易辨认出这些构件，但为了使附图的说明更为清楚，本说明书不会将所有相同构件的标号标于每一图中。
参照图8，本实施例的MEMS封装结构包括MEMS芯片(如图6中的第二MEMS芯片220)以及器件晶圆100，所述MEMS芯片具有微腔和用于连接外部电信号的接触垫，所述MEMS芯片的微腔具有与外部连通的开口(如图8中， 第二MEMS芯片220具有第二微腔221和第二接触垫222，第二微腔221具有与外部连通的开口221a)，所述器件晶圆100包括第一表面100a和与所述第一表面100b相对的第二表面100b，器件晶圆100中设置有与所述MEMS芯片对应的控制单元以及互连结构300，互连结构400与MEMS芯片的接触垫和器件晶圆中的控制单元均电连接，在器件晶圆100的第二表面100b设置有再布线层400，所述再布线层400与互连结构300电连接。
上述MEMS封装结构可包括多个所述MEMS芯片，器件晶圆100用于控制上述多个MEMS芯片，其中设置了多个控制单元，以分别驱动接合在其第一表面100a的多个MEMS芯片工作。器件晶圆100可以利用通用的半导体工艺形成，例如，可以在一衬底(例如硅衬底)上制作上述多个控制单元以形成器件晶圆100。
具体的，如图8所示，本实施例中，器件晶圆100可包括衬底101，所述衬底101例如是硅衬底或绝缘体上硅(SOI)衬底等，所述衬底101的材料还可以包括锗、锗化硅、碳化硅、砷化镓、镓化铟或其他Ⅲ、Ⅴ族化合物。所述衬底101优选是易于进行半导体工艺处理或集成的衬底。上述多个控制单元可基于衬底101形成。
每个所述控制单元可包括一个或多个MOS晶体管，相邻的MOS晶体管可通过在器件晶圆100(或衬底101)中设置的隔离结构102以及在衬底101上覆盖的绝缘材料隔离，所述隔离结构102例如是浅沟槽隔离结构(STI)和/或深沟槽隔离结构(DTI)。作为示例，控制单元通过其中一个MOS晶体管的一个源/漏极将控制电信号输出，以控制MEMS芯片。本实施例中，器件晶圆100还包括在衬底101的一侧表面上形成的第一介质层103，控制单元的用于输出控制电信号的一个源/漏极(作为电连接端)设置于第一介质层103中，在衬底101的另一侧表面上形成有第二介质层104，第一介质层103和第二介质层104的材料可包括氧化硅、氮化硅、碳化硅和氮氧化硅等绝缘材料中的至少一种。
方便起见，可将第一介质层103远离衬底101的表面作为器件晶圆100的第一表面100a，而将第二介质层104远离衬底101的表面作为器件晶圆100的第二表面100b。所述衬底101优选是薄型衬底，以减小最终形成的MEMS封装结构的厚度。
为了将MEMS芯片与器件晶圆100中的控制单元形成电气互连，本实施例 中，在器件晶圆100中设置了互连结构300，互连结构300与MEMS芯片的接触垫和器件晶圆100中的控制单元均电连接。具体的，参照图8，所述互连结构300可包括第一导电插塞310和第二导电插塞320，所述第一导电插塞310至少贯穿部分所述器件晶圆100并与对应的所述控制单元电连接，所述第二导电插塞320贯穿所述器件晶圆100并与对应的MEMS芯片的所述接触垫电连接。优选的，上述第一导电插塞310和第二导电插塞320均贯穿隔离结构102，以避免或减小对器件晶圆100中控制单元的电路的影响。
多个MEMS芯片可以选自相同或不同的功能、用途和结构的MEMS芯片，可以分别利用本领域公知的MEMS芯片的制造工艺在不同的衬底(例如硅晶圆)上制作诸如陀螺仪、加速度计、惯性传感器、压力传感器、湿度传感器、位移传感器、气体传感器、催化传感器、微波滤波器、光学传感器(例如MEMS扫描镜、ToF图像传感器、光电探测器、垂直腔面发射激光器(VCSEL)、衍射光学元件(DOE))、DNA扩增微系统、MEMS麦克风、微致动器(例如微型马达、微型谐振器、微继电器、微型光/RF开关、光投影显示器、灵巧蒙皮、微型泵/阀)等MEMS器件，然后分割出独立的芯片晶粒并选择至少两类作为本实施例中的MEMS芯片。具体实施时，可以根据设计及用途的需要，选择一定数量或多个种类的MEMS芯片设置在器件晶圆100的第一表面100a。例如，可在器件晶圆100的第一表面100a上接合一种或者多种传感性能的MEMS芯片。可以理解，本实施例重点说明的是包括器件晶圆100及在其第一表面100a设置了MEMS芯片的MEMS封装结构，但并不表示本实施例的MEMS封装结构仅包括上述部件，器件晶圆100上也可以设置/接合有其他芯片(例如存储芯片、通讯芯片、处理器芯片等等)，或者设置有其他器件(例如功率器件、双极型器件、电阻、电容等等)，本领域公知的器件和连接关系也可包含在其中。并且，器件晶圆100上所接合的MEMS芯片并不局限于一个，也可以是两个或三个以上，且这些MEMS芯片的结构和/或种类也可以根据需要作相应变化。
为了提高MEMS封装结构的功能集成能力，优选的，上述多个MEMS芯片根据制作工艺区分属于相同或不同的类别，此处两类MEMS芯片的制作工艺不完全相同。多个MEMS芯片可均具有与外部连通的开口，或者至少一个所述MEMS芯片具有封闭的微腔，所述封闭的微腔内可填充有阻尼气体(damping gas)或者为真空状态。本实施例中，第一MEMS芯片210例如是陀螺仪，其中 第一微腔211是封闭的，第二MEMS芯片220的第二微腔221与大气连通，属于进气型MEMS芯片(air inlet MEMS)。在又一实施例中，多个MEMS芯片可包括陀螺仪、加速度计、惯性传感器、压力传感器、位移传感器、湿度传感器、光学传感器、气体传感器、催化传感器、微波滤波器、DNA扩增微系统、MEMS麦克风、微致动器中的至少两种。参照图9和图10，在另外的实施例中，第二MEMS芯片220例如是压力传感器(图9)或者光学传感器(图10)，其中压力传感器可包括一个封闭的微腔和一个与外部连通的微腔，对于光学传感器，可通过微腔上的透明部件接收外部的光信号。
本实施例的MEMS封装结构还可包括接合层500，接合层500用于将上述MEMS芯片与器件晶圆100接合固定。所述接合层500覆盖器件晶圆100的第一表面100a，上述MEMS芯片通过所述接合层500接合于器件晶圆100的第一表面100a。
接合层500的材料可包括氧化物或其他合适的材料。例如，接合层500可以是键合材料，以通过熔融键合(fusing bonding)或真空键合等方式将上述多个MEMS芯片与器件晶圆100的第一表面100a键合在一起。接合层500还可以包括胶黏材料，例如包括粘片膜(Die Attach Film，DAF)或干膜(dry film)，以通过粘接方式将上述MEMS芯片与器件晶圆100接合在一起。以干膜为例，其是一种具有粘性的光致抗蚀膜，通过紫外线的照射后能够发生聚合反应形成一种稳定的物质附着于粘着面上，具有阻挡电镀和蚀刻的优点。为了方便在第二表面100b一侧进行互连，上述MEMS芯片优选以接触垫朝向器件晶圆100的接合面(本实施例中例如是第一表面100a)的方位进行接合。优选的，对应于每个MEMS芯片，所述接触垫所在表面与器件晶圆100的第一表面100a相对，而第二微腔221的与外部连通的开口221a朝向远离器件晶圆100的第一表面100a的方向。
本实施例的MEMS封装结构还可包括封装层501，所述封装层501覆盖器件晶圆100上接合的MEMS芯片和上述接合层500，并暴露出MEMS芯片的微腔与外部连通的开口。封装层501设置于器件晶圆100的第一表面100a一侧以使所述MEMS芯片在器件晶圆100上更加稳固，并避免所述MEMS芯片受到外部损伤。所述封装层501例如是塑封材料层，例如可通过注塑工艺将多个MEMS芯片之间的间隙填满并将上述多个MEMS芯片固定在接合层500上。所述封装 层501可采用在成型过程中能软化或流动、即具有可塑性的材料，以制成一定形状，所述封装层501的材料还可发生化学反应而交联固化，作为示例，所述封装层501的材料可以包括酚醛树脂、脲醛树脂、甲醛树脂、环氧树脂、不饱和树脂、聚氨酯、聚酰亚胺等热固性树脂中的至少一种，其中，较佳地使用环氧树脂作为封装层501的材料，其中环氧树脂中可包括填料物质，还可包括各种添加剂(例如，固化剂、改性剂、脱模剂、热色剂、阻燃剂等)，例如以酚醛树脂作为固化剂，以固体颗粒(例如硅微粉)等作为填料。
本实施例的MEMS封装结构还包括在器件晶圆100的第二表面100b设置的再布线层400，再布线层400可采用导电材料，并与上述互连结构300电连接。具体的，如图8所示，再布线层400可通过覆盖第一导电插塞310和第二导电插塞320的部分与互连结构300电连接。
优选的，所述再布线层400可包括再布线以及与所述再布线电连接的焊垫(I/O pad)(未示出)，所述焊垫与用于与其他外部信号或装置连接，以对所述再布线传输的电信号进行处理或控制。
上述MEMS封装结构将MEMS芯片与器件晶圆100集成，并将再布线层400设置在与接合方向相对的另一侧，有利于缩小整体MEMS封装结构的尺寸，提高集成度。进一步的，再布线层400可包括再布线以及与所述再布线电连接的焊垫，将焊垫设置于第二表面100b也有利于减小MEMS封装结构的尺寸。进一步的，同一器件晶圆100上可集成多个MEMS芯片，多个MEMS芯片可以对应于相同或不同的功能(用途)及结构，其中至少一个所述MEMS芯片的微腔具有与外部连通的开口，有助于提高MEMS封装结构的功能集成能力。
本发明实施例还包括一种MEMS封装结构的制作方法，可以用于制作上述MEMS封装结构。所述MEMS封装结构的制作方法包括以下步骤：
第一步骤：提供多个EMS芯片、用于控制所述MEMS芯片的器件晶圆，所述MEMS芯片具有微腔和用于连接外部电信号的接触垫，所述MEMS芯片的微腔具有与外部连通的开口，所述器件晶圆具有第一表面，所述器件晶圆中形成有控制单元；
第二步骤：将所述MEMS芯片接合于所述第一表面；
第三步骤：在所述器件晶圆中形成互连结构，所述互连结构与所述接触垫和所述控制单元均电连接；
第四步骤：形成再布线层于所述器件晶圆的与所述第一表面相对的一侧表面，所述再布线层与所述互连结构电连接。
以下结合图1至图8对本发明实施例的MEMS封装结构的制作方法进行详细说明。
图1是依照本发明一实施例的MEMS封装结构的制作方法提供的器件晶圆和多个MEMS芯片的剖面示意图。参照图1，首先执行第一步骤，提供MEMS芯片和用于控制所述MEMS芯片的器件晶圆100，所述MEMS芯片具有微腔和用于连接外部电信号的接触垫，所述MEMS芯片的微腔具有与外部连通的开口，所述器件晶圆100具有第一表面100a，所述器件晶圆100中形成有控制单元。本实施例中，同一器件晶圆100上要集成的MEMS芯片可以不止一个，对应的器件晶圆100中的控制单元也可不止一个。所述器件晶圆100通常为平板状，多个控制单元可并列排布在器件晶圆100中。
本实施例的器件晶圆100可包括衬底101，所述衬底101例如是硅衬底或绝缘体上硅(SOI)衬底等。可以利用成熟的半导体制程，基于衬底101形成多个控制单元，以便于后续控制多个MEMS芯片。每个所述控制单元可以是一组CMOS控制电路，例如，每个控制单元可包括一个或多个MOS晶体管，相邻的MOS晶体管可通过在衬底101(或器件晶圆100)中设置的隔离结构102以及在衬底101上覆盖的绝缘材料隔离，所述隔离结构102例如是浅沟槽隔离结构(STI)和/或深沟槽隔离结构(DTI)。器件晶圆100还可包括在衬底101的一侧表面上形成的第一介质层103，每个控制单元的用于输出控制电信号的连接端可设置于第一介质层103中，方便起见，可将第一介质层103的远离所述衬底101的表面作为器件晶圆100的第一表面100a。器件晶圆100可利用本领域公开的方法制作。
多个MEMS芯片可选自具有相同或不同的功能、用途及结构的MEMS芯片，本实施例中，为了使MEMS封装结构具备多种用途或功能，待集成的多个MEMS芯片优选选自两种或两种以上的类别，例如多个MEMS芯片可选自陀螺仪、加速度计、惯性传感器、压力传感器、流量传感器、位移传感器、湿度传感器、光学传感器、气体传感器、催化传感器、微波滤波器、DNA扩增微系统、MEMS麦克风、微致动器中的至少两种。本实施例中，每个MEMS芯片可以是一独立的芯片(或晶粒)，并具有作为传感部件的微腔以及用于接入外部电信号(用于 控制使MEMS芯片工作)的接触垫。MEMS芯片的微腔可以全部与外部(如大气)连通，也可以是部分MEMS芯片的微腔与芯片外部连通而部分MEMS芯片的微腔封闭，其中封闭的微腔内可以是高真空或低真空的环境，或者也可填充有阻尼气体(damping gas)。
参照图1，作为示例，多个MEMS芯片包括第一MEMS芯片210和第二MEMS芯片220，所述第一MEMS芯片210例如是陀螺仪，所述第二MEMS芯片220例如是压力传感器，其中第二MEMS芯片220的微腔不是封闭的。可以理解，虽然图1中仅示出了两个MEMS芯片，但本实施例的MEMS封装结构也可以应用于包括一个或两个以上的MEMS芯片的情形。
具体的，第一MEMS芯片210包括作为传感部件的第一微腔211以及用于接入外部电信号的第一接触垫212，第二MEMS芯片220包括作为传感部件的第二微腔221以及用于接入外部电信号的第二接触垫222，并且，第二微腔221还具有与芯片外部连通的开口221a。第一接触垫212和第二接触垫222在对应的MEMS芯片表面被暴露出来。MEMS芯片的制作方法可利用本领域公开的方法制作。
图2是依照本发明一实施例的MEMS封装结构的制作方法利用接合层接合所述多个MEMS芯片与所述器件晶圆后的剖面示意图。参照图2，执行第二步骤，将所述多个MEMS芯片接合于器件晶圆100的第一表面100a。如果是多个MEMS芯片，则多个MEMS芯片在所述第一表面100a上并列排布。
具体的，可形成接合层500于器件晶圆100的第一表面100a，利用所述接合层500接合所述MEMS芯片与所述第一表面100a。本实施例中，接合层500覆盖于器件晶圆100的第一表面100a。
在一种实施方式中，可以采用键合方式诸如熔融键合、真空键合的方法使器件晶圆100与所述多个MEMS芯片键合在一起，此处所述接合层500的材料为键合材料(例如氧化硅)；在另一种实施方式中，可以采用接合且光(或热)固化的方式使器件晶圆100与所述多个MEMS芯片粘接在一起，此处所述接合层500可包括胶黏材料，具体可选用粘片膜或干膜。多个MEMS芯片可以逐个进行接合，也可以通过部分或全部先贴合在一载板上，再分批或同时与器件晶圆100接合。为了方便在器件晶圆100的远离接合面的一侧进行互连及再布线，上述多个MEMS芯片优选以接触垫朝向器件晶圆100的接合面(本实施例例如 是第一表面100a)的方位进行接合，对于非封闭的微腔，其与外部连通的开口优选朝向远离器件晶圆100(或第一表面100a)的方向。
为了避免接合在器件晶圆100上的MEMS芯片受到外部因素(例如水汽、氧气、碰撞、刻蚀以及电镀等)的影响，以及使MEMS芯片更稳固，本实施例的MEMS封装结构的制作方法在进行第三步骤之前，还包括在器件晶圆100的第一表面100a一侧形成牺牲层和封装层的步骤。
图3是依照本发明一实施例的MEMS封装结构的制作方法在形成牺牲层后的剖面示意图。参照图3，为了避免后续工艺对第二微腔221的影响，在将MEMS芯片接合于器件晶圆100的第一表面100a之后，还在第一表面100a上形成了牺牲层223，牺牲层223的材料可包括光刻胶、碳化硅和无定型碳中的一种或多种。牺牲层223可利用化学气相沉积工艺成膜并经过光罩工艺及蚀刻工艺制作。
图4是依照本发明一实施例的MEMS封装结构的制作方法在形成封装层后的剖面示意图。参照图4，在将多个MEMS芯片通过接合层500接合于器件晶圆100的第一表面100a后，还包括在器件晶圆100上形成封装层501的步骤。所述封装层501覆盖第一表面100a上的多个MEMS芯片和接合层500。封装层501可包括诸如氧化硅、氮化硅、碳化硅、氮氧化硅等无机绝缘材料，也可包括诸如聚碳酸脂、聚对苯二甲酸乙二醇酯、聚醚砜、聚苯醚、聚酰胺、聚醚酰亚胺、甲基丙烯酸树脂或环聚烯烃系树脂等热塑性树脂，也可包括诸如环氧树脂、酚醛树脂、脲醛树脂、甲醛树脂、聚氨酯、亚克力树脂、乙烯酯树脂、酰亚胺类树脂、尿素树脂或三聚氰胺树脂等热固性树脂，也可包括诸如聚苯乙烯、聚丙烯腈等有机绝缘材料。封装层501可通过例如化学气相沉积工艺或者注塑工艺形成。优选地，在制作所述封装层501的过程中，还可包括在器件晶圆100的形成有所述接合层500的一侧进行平坦化处理的步骤，以使封装层501的顶表面平坦(例如平行于第一表面100a)，以在后续形成互连结构及再布线层的过程中利用封装层501作为支撑面，经过平坦化处理，覆盖在开口221a上的牺牲层223优选从封装层501中暴露出来，以便后续直接去除牺牲层223以打开所覆盖的微腔开口。
图5是依照本发明一实施例的MEMS封装结构的制作方法在减薄器件晶圆后的剖面示意图。为了减小MEMS封装结构的尺寸，在执行第三步骤之前，本实施例的MEMS封装结构的制作方法还可包括：从器件晶圆100的与第一表面 100a相对的一侧沿厚度方向减薄器件晶圆100。
可采用背部研磨工艺、湿法刻蚀工艺或氢离子注入等工艺减薄器件晶圆100。本实施例中，可以通过从与第一表面100a相对的一侧减薄衬底101，衬底101减薄的位置可与隔离结构102在衬底101中的底部齐平。
为了优化减薄后的表面，提高后续形成的再布线层的附着力以及减少表面缺陷，在减薄衬底101之后，可在器件晶圆100的减薄后的表面上沉积介质材料，以形成如图5中的第二介质层104，第二介质层104覆盖器件晶圆100的经减薄后的表面。方便起见，以下以第二介质层104远离器件晶圆100的第一表面100a的一侧表面作为器件晶圆100的第二表面100b。
图6是依照本发明一实施例的MEMS封装结构的制作方法在形成互连结构后的剖面示意图。参照图6，接着执行第三步骤，在所述器件晶圆100中形成互连结构300，所述互连结构300与所述接触垫和所述控制单元均电连接。可以理解，为了体现与上述步骤的关联，器件晶圆100并没有示意为翻转之后的方位，但本实施例执行第三步骤、第四步骤的工艺也可利用封装层501的远离第一表面100a的一侧表面作为支撑面，将器件晶圆100翻转之后进行。
互连结构300可包括在器件晶圆100中形成的一个以上的电接触、电连接件以及连接它们中任意两个的电连接线，本实施例中，互连结构300包括在所述器件晶圆300中形成的第一导电插塞310和第二导电插塞320。在集成多个MEMS芯片时，第一导电插塞310和第二导电插塞320也可以是多个。每个所述第一导电插塞310至少贯穿部分所述器件晶圆100并与对应的所述控制单元电连接，所述第二导电插塞320贯穿所述器件晶圆100并与对应的MEMS芯片的所述接触垫电连接，其中，所述多个第一导电插塞310和所述多个第二导电插塞320的一端在所述器件晶圆100的与所述第一表面100a相对的一侧表面(如图6中的第二表面100b)被暴露出来。从而，互连结构300与多个MEMS芯片的接触垫和器件晶圆100中的多个控制单元形成了电连接，并具有在器件晶圆100的第二表面100b上的电接触。
第一导电插塞310和第二导电插塞320可以利用本领域公开的方法形成。作为示例，可包括以下过程：首先，在器件晶圆100中利用光罩及刻蚀工艺形成第一通孔和第二通孔，具体使所述第一通孔贯穿部分器件晶圆100以从第二表面100b一侧暴露出每个控制单元的电连接端，所述第二通孔贯穿器件晶圆100 和接合层500以从第二表面100b一侧暴露出对应的MEMS芯片要引出的接触垫，在形成上述第一通孔和第二通孔时，优选从器件晶圆100的隔离结构102区域穿过，以减小或避免对控制单元的影响；然后，在上述第一通孔和第二通孔中填充导电材料以分别形成第一导电插塞310和第二导电插塞320，填充导电材料可利用物理气相沉积(PVD)、化学气相沉积(CVD)或者电镀工艺等本领域公开的方法，所述导电材料可选择含有钴、钼、铝、铜、钨等元素的金属或合金，所述导电材料还可以选择金属硅化物(如硅化钛、硅化钨、硅化钴等)、金属氮化物(如氮化钛)或者掺杂多晶硅等等。但形成第一导电插塞310和第二导电插塞320并不限于上述方法，例如，在另一实施例中，也可以在形成第一通孔继而填充导电材料以得到第一导电插塞310后，再形成第二通孔继而填充导电材料以得到第二导电插塞320。此外，在形成上述第一导电插塞310和第二导电插塞320后，可以利用CMP工艺去除覆盖在第二表面100b上的导电材料。
图7是依照本发明一实施例的MEMS封装结构的制作方法在形成再布线层后的剖面示意图。参照图7，接着执行第四步骤，形成再布线层400于所述器件晶圆100的与所述第一表面100a相对的一侧表面(本实施例中为器件晶圆100的第二表面100b)，所述再布线层400与所述互连结构300电连接。
具体的，上述再布线层400可覆盖于所述第二介质层104上，并与上述第一导电插塞310和第二导电插塞320接触，从而与互连结构300电连接。再布线层400的形成过程例如是先在器件晶圆100的第二表面100b沉积金属层，金属层可以利用物理气相沉积(PVD)工艺、原子层沉积(ALD)或者化学气相沉积(CVD)工艺形成，然后进行图形化处理以形成再布线层400。再布线层400可采用与第一导电插塞310或第二导电插塞320相同的材料。
上述再布线层400进一步可包括再布线以及与所述再布线电连接的焊垫，再布线通过与互连结构300电连接以使MEMS芯片和器件晶圆100的电气互连引出至与器件晶圆的远离MEMS芯片的一侧。与所述再布线电连接的焊垫可用于再布线层400与其他外部信号或装置连接，以对再布线传输的电信号进行处理或控制。
图8是依照本发明一实施例的集成电路器件的制作方法在暴露出MEMS芯片的开口后的剖面示意图。参照图8，本实施例的集成电路器件的制作方法在形 成再布线层400之后，还可包括以下步骤：去除上述牺牲层223，以暴露出对应的MEMS芯片的微腔与外部连通的开口。本实施例中，在去除牺牲层223之后，对应于第二MEMS芯片220中第二微腔221的开口221a被暴露(或打开)，从而使第二微腔221与芯片外部连通，以便于第二MEMS芯片220的正常工作。
本实施例的MEMS封装结构的形成方法，将MEMS芯片接合于器件晶圆100的第一表面100a，在所述器件晶圆100中形成与MEMS芯片的接触垫和器件晶圆100中的控制单元均电连接的互连结构300，并在器件晶圆100的与所述第一表面100a相对的一侧表面形成再布线层400，所述MEMS芯片具有微腔和用于连接外部电信号的接触垫，所述MEMS芯片的微腔具有与外部连通的开口。通过将MEMS芯片和再布线层400分别设置在器件晶圆100的两侧，有利于缩小MEMS封装结构的尺寸，提高集成度。此外，可将多个具有相同或不同的功能(或用途)及结构的MEMS芯片与同一器件晶圆100进行封装集成，有利于满足实际应用中对包括MEMS芯片的MEMS封装结构的集成度、便携性和高性能的要求。
上述描述仅是对本发明较佳实施例的描述，并非对本发明权利范围的任何限定，任何本领域技术人员在不脱离本发明的精神和范围内，都可以利用上述揭示的方法和技术内容对本发明技术方案做出可能的变动和修改，因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化及修饰，均属于本发明技术方案的保护范围。

Claims (18)

  1. 一种MEMS封装结构，其特征在于，包括：
    MEMS芯片，所述MEMS芯片具有微腔和用于连接外部电信号的接触垫，所述MEMS芯片的微腔具有与外部连通的开口；
    器件晶圆，所述器件晶圆具有彼此相对的第一表面和第二表面，所述MEMS芯片接合于所述第一表面，所述器件晶圆中设置有与所述MEMS芯片对应的控制单元；
    互连结构，位于所述器件晶圆中，所述互连结构与所述接触垫和所述控制单元均电连接；以及
    再布线层，设置于所述第二表面，所述再布线层与所述互连结构电连接。
  2. 如权利要求1所述的MEMS封装结构，其特征在于，多个所述MEMS芯片接合于所述第一表面，且多个所述MEMS芯片根据制作工艺区分属于相同或不同的类别。
  3. 如权利要求1所述的MEMS封装结构，其特征在于，多个所述MEMS芯片接合于所述第一表面，且多个所述MEMS芯片的微腔均具有与外部连通的开口或者至少一个所述MEMS芯片具有封闭的微腔。
  4. 如权利要求3所述的MEMS封装结构，其特征在于，所述封闭的微腔内填充有阻尼气体或者为真空。
  5. 如权利要求1所述的MEMS封装结构，其特征在于，多个所述MEMS芯片接合于所述第一表面，且多个所述MEMS芯片包括陀螺仪、加速度计、惯性传感器、压力传感器、位移传感器、湿度传感器、光学传感器、气体传感器、催化传感器、微波滤波器、DNA扩增微系统、MEMS麦克风、微致动器中的至少两种。
  6. 如权利要求1所述的MEMS封装结构，其特征在于，所述控制单元包括一个或多个MOS晶体管。
  7. 如权利要求6所述的MEMS封装结构，其特征在于，所述互连结构包括：
    第一导电插塞和第二导电插塞，所述第一导电插塞至少贯穿部分所述器件晶圆并与所述控制单元电连接，所述第二导电插塞贯穿所述器件晶圆并与所述接触垫电连接，其中，所述再布线层与所述第一导电插塞和所述第二导电插塞 均电连接。
  8. 如权利要求7所述的MEMS封装结构，其特征在于，所述器件晶圆中还设置有隔离结构，所述隔离结构位于相邻的MOS晶体管之间，所述第一导电插塞和所述第二导电插塞均贯穿所述隔离结构。
  9. 如权利要求1所述的MEMS封装结构，其特征在于，还包括：
    接合层，所述接合层覆盖所述第一表面，所述MEMS芯片通过所述接合层接合于所述第一表面；以及
    封装层，所述封装层覆盖所述MEMS芯片和所述接合层，并暴露出所述开口以使对应的微腔与外部连通。
  10. 如权利要求9所述的MEMS封装结构，其特征在于，所述接合层包括胶黏材料。
  11. 如权利要求10所述的MEMS封装结构，其特征在于，所述胶黏材料包括干膜。
  12. 如权利要求1所述的MEMS封装结构，其特征在于，所述接触垫所在表面与所述第一表面相对，所述微腔与外部连通的开口朝向远离所述第一表面的方向。
  13. 如权利要求1所述的MEMS封装结构，其特征在于，所述再布线层包括再布线以及与所述再布线电连接的焊垫。
  14. 一种MEMS封装结构的制作方法，其特征在于，包括：
    提供MEMS芯片、用于控制所述MEMS芯片的器件晶圆，所述MEMS芯片具有微腔和用于连接外部电信号的接触垫，所述MEMS芯片的微腔具有与外部连通的开口，所述器件晶圆具有第一表面，所述器件晶圆中形成有控制单元；
    将所述MEMS芯片接合于所述第一表面；
    在所述器件晶圆中形成互连结构，所述互连结构与所述接触垫和所述控制单元均电连接；以及
    形成再布线层于所述器件晶圆的与所述第一表面相对的一侧表面，所述再布线层与所述互连结构电连接。
  15. 如权利要求14所述的MEMS封装结构的制作方法，其特征在于，将所述MEMS芯片接合于所述第一表面的步骤包括：
    形成接合层，利用所述接合层接合所述MEMS芯片与所述第一表面；
    形成牺牲层，所述牺牲层覆盖所述开口；以及
    形成封装层，所述封装层覆盖所述MEMS芯片和所述接合层，并暴露出所述牺牲层。
  16. 如权利要求15所述的MEMS封装结构的制作方法，其特征在于，在形成所述再布线层后，还包括：
    去除所述牺牲层，以暴露出所述开口。
  17. 如权利要求14所述的MEMS封装结构的制作方法，其特征在于，在所述器件晶圆中形成所述互连结构的步骤包括：
    在所述器件晶圆中形成第一导电插塞和第二导电插塞，所述第一导电插塞至少贯穿部分所述器件晶圆并与所述控制单元电连接，所述第二导电插塞贯穿所述器件晶圆并与所述接触垫电连接，其中，所述第一导电插塞和所述第二导电插塞的一端在所述器件晶圆的与所述第一表面相对的一侧表面被暴露出来。
  18. 如权利要求14所述的MEMS封装结构的制作方法，其特征在于，在所述器件晶圆中形成所述互连结构之前，还包括：
    从所述器件晶圆的与所述第一表面相对的一侧沿厚度方向减薄所述器件晶圆。
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CN114284306A (zh) * 2021-12-15 2022-04-05 武汉新芯集成电路制造有限公司 深度兼图像传感器器件及制作方法、深度兼图像传感器芯片

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