WO2022153628A1 - 撮像装置及びカメラシステム - Google Patents

撮像装置及びカメラシステム Download PDF

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Publication number
WO2022153628A1
WO2022153628A1 PCT/JP2021/037712 JP2021037712W WO2022153628A1 WO 2022153628 A1 WO2022153628 A1 WO 2022153628A1 JP 2021037712 W JP2021037712 W JP 2021037712W WO 2022153628 A1 WO2022153628 A1 WO 2022153628A1
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Prior art keywords
potential
transistor
charge storage
storage unit
drain
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Ceased
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PCT/JP2021/037712
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English (en)
French (fr)
Japanese (ja)
Inventor
雅史 村上
信 荘保
好弘 佐藤
佳壽子 西村
順司 平瀬
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Panasonic Intellectual Property Management Co Ltd
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Panasonic Intellectual Property Management Co Ltd
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Priority to EP21919519.5A priority Critical patent/EP4280591A4/en
Priority to JP2022575079A priority patent/JP7720574B2/ja
Priority to CN202180087529.XA priority patent/CN116711321A/zh
Publication of WO2022153628A1 publication Critical patent/WO2022153628A1/ja
Priority to US18/340,886 priority patent/US12407951B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H04N25/59—Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H04N25/571—Control of the dynamic range involving a non-linear response
    • H04N25/575—Control of the dynamic range involving a non-linear response with a response composed of multiple slopes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/771—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/803—Pixels having integrated switching, control, storage or amplification elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/803—Pixels having integrated switching, control, storage or amplification elements
    • H10F39/8037—Pixels having integrated switching, control, storage or amplification elements the integrated elements comprising a transistor

Definitions

  • JP-A-2009-164604 Japanese Patent No. 4317115 International Publication No. 2020/144910
  • the camera system is Equipped with an image pickup device and a control circuit
  • the image pickup apparatus has a charge storage unit that stores charges generated by photoelectric conversion, and a first gate that is electrically connected to one of a first source, a first drain, and the first source or the first drain.
  • the first transistor with electrodes and A first capacitive element that retains the charge and has a first terminal, and has.
  • the first source or the other of the first drain is supplied with a fixed potential and is always electrically connected to the first terminal of the capacitive element.
  • the specific circuit may change the capacitance value of the charge storage capacity according to the capacitance value of the first capacitance element in response to a change in the potential of the charge storage unit.
  • the specific circuit may change the capacitance value of the charge storage capacity when the potential of the charge storage unit changes across the first threshold potential.
  • the image pickup apparatus may further include a control circuit.
  • the control circuit may control the first threshold potential by applying a control potential to the specific circuit.
  • the specific circuit may further include a first transistor.
  • the shooting mode may have a first mode and a second mode.
  • the first transistor In the first mode, the first transistor may be kept off.
  • the capacitance value of the charge storage capacity may increase when or after the first transistor turns on in response to a change in the potential of the charge storage unit.
  • the specific circuit may further include a first transistor.
  • the first transistor may have a first source, a first drain and a first gate electrode.
  • the first capacitance element may have a first terminal and a second terminal.
  • the first gate electrode may be electrically connected to the first terminal.
  • the first source or the first drain may be electrically connected to the charge storage unit.
  • the features of the 16th aspect can be realized by applying a control potential to the second terminal of the first capacitance element.
  • the specific circuit may further include a first transistor.
  • the first transistor may have a first source, a first drain and a first gate electrode.
  • the first capacitance element may have a first terminal and a second terminal.
  • the first gate electrode may be electrically connected to the first terminal and the charge storage portion.
  • One of the first source and the first drain may be electrically connected to the second terminal.
  • the image pickup apparatus may further include a control circuit.
  • a control potential may be applied to the other of the first source and the first drain from the control circuit.
  • the control circuit may apply a reset potential to the charge storage section.
  • the control circuit may temporarily turn on the first transistor by changing the level of the reset potential in a pulsed manner.
  • the potential of the second terminal can be reset as well as the potential of the charge storage unit.
  • the specific circuit may further include a second capacitive element.
  • the specific circuit has a capacity of the charge storage capacity when the potential of the charge storage unit changes across the first threshold potential and when the potential of the charge storage unit changes across the second threshold potential. The value may be changed.
  • the first capacitive element may include at least one selected from the group consisting of MIM capacitance, MOM capacitance and MOS capacitance.
  • the MIM capacity, MOM capacity, and MOS capacity are specific examples of the first capacitance element.
  • the camera system is Equipped with an image pickup device and a control circuit
  • the imaging device includes a charge storage unit that stores charges generated by photoelectric conversion, a node electrically connected to the charge storage unit, and a specific circuit having a first capacitance element.
  • the specific circuit determines the capacity value of the charge storage capacity when the potential of the charge storage unit changes across the first threshold potential. Change, The control circuit controls the first threshold potential by applying a control potential to the specific circuit.
  • the technique according to the twentieth aspect is suitable for realizing a wide dynamic range.
  • adjustment of each element due to the difference in the positive and negative of the signal charge such as changing the conductive type of the impurity region, can be appropriately performed.
  • the replacement of terms due to the difference in the positive and negative of the signal charge can be performed as appropriate.
  • node means an electrical connection between a plurality of elements in an electric circuit, and is a concept including wiring and the like that are responsible for the electrical connection between the elements.
  • the first capacitance element is connected to the first transistor
  • the first capacitance element is configured by using the first transistor. It should be interpreted as an expression that includes the case where. That is, this expression should be interpreted as including the case where the first capacitive element and the first transistor partially or wholly overlap.
  • the ordinal numbers 1st, 2nd, 3rd ... may be used. If an element has an ordinal number, it is not essential that a younger element of the same type exists. In addition, the ordinal numbers can be changed, the ordinal numbers can be deleted, and the ordinal numbers can be added as needed.
  • FIG. 1 schematically shows an exemplary circuit configuration of the image pickup apparatus 101 according to the first embodiment.
  • the image pickup apparatus 101 shown in FIG. 1 includes a plurality of pixels 11a and peripheral circuits.
  • the plurality of pixels 11a form a photosensitive region by being arranged two-dimensionally on the semiconductor substrate.
  • the photosensitive area may be referred to as a pixel area.
  • the semiconductor substrate is, for example, a silicon substrate.
  • the semiconductor substrate is not limited to a substrate whose entire structure is a semiconductor.
  • the semiconductor substrate may include an insulating substrate and a semiconductor layer provided on the insulating substrate. A photosensitive region can be formed on the side of the semiconductor layer.
  • the plurality of pixels 11a are arranged in the row direction and the column direction.
  • the row direction and the column direction mean the directions in which the rows and columns extend, respectively.
  • the vertical direction on the paper is the column direction
  • the horizontal direction is the row direction.
  • the plurality of pixels 11a may be arranged one-dimensionally.
  • the imaging device 101 can be a line sensor.
  • each of the pixels 11a is connected to the power supply wiring 22.
  • a predetermined power supply voltage is supplied to each pixel 11a via the power supply wiring 22.
  • each of the pixels 11a of the present embodiment includes a photoelectric conversion unit laminated on the semiconductor substrate.
  • the "photoelectric conversion unit laminated on the semiconductor substrate” is an expression intended to include a form in which another element is interposed between the semiconductor substrate and the photoelectric conversion unit.
  • the image pickup apparatus 101 has a storage control line 17 for applying the same constant voltage to all the photoelectric conversion units.
  • Each of the pixels 11a is also connected to the reset voltage line 77.
  • the reset potential Vrst is supplied to each pixel 11a via the reset voltage line 77.
  • the peripheral circuit of the image pickup apparatus 101 includes a vertical scanning circuit 16, a load circuit 19, a column signal processing circuit 20, and a horizontal signal reading circuit 21.
  • the vertical scanning circuit 16 may also be referred to as a row scanning circuit 16.
  • the column signal processing circuit 20 may also be referred to as a row signal storage circuit 20.
  • the horizontal signal readout circuit 21 may also be referred to as a column scanning circuit 21.
  • the column signal processing circuit 20 and the load circuit 19 are arranged for each row of pixels 11a arranged in two dimensions. That is, in this example, the peripheral circuit includes a plurality of column signal processing circuits 20 and a plurality of load circuits 19.
  • An address signal line 30 is provided for each line of the pixel 11a.
  • the pixels 11a in each row are electrically connected to the vertical scanning circuit 16 via the corresponding address signal lines 30.
  • the vertical scanning circuit 16 selects a plurality of pixels 11a arranged in each row in units of rows by applying a predetermined voltage to the address signal line 30. As a result, the electric signal of the selected pixel 11a is read out.
  • a reset signal line 26 is provided for each line of the pixel 11a.
  • the pixels 11a in each row are electrically connected to the vertical scanning circuit 16 via the corresponding reset signal line 26.
  • a specific reset signal line 75 is provided for each line of the pixel 11a.
  • the pixels 11a in each row are electrically connected to the vertical scanning circuit 16 via the corresponding specific reset signal line 75.
  • a vertical signal line 18 is provided for each row of pixels 11a.
  • the pixels 11a in each row are electrically connected to the corresponding vertical signal line 18.
  • a load circuit 19 is provided for each vertical signal line 18. Each load circuit 19 is electrically connected to a corresponding vertical signal line 18.
  • FIG. 2 shows an exemplary circuit configuration of pixel 11a shown in FIG.
  • Pixel 11a includes a photoelectric conversion unit 15, a signal detection circuit SC, and a specific circuit GSC.
  • an electric charge is generated by photoelectric conversion.
  • this charge may be referred to as a signal charge.
  • the photoelectric conversion unit 15 converts light into electric charges.
  • the photoelectric conversion unit 15 has a counter electrode 15a, a photoelectric conversion layer 15b, and a pixel electrode 15c.
  • the photoelectric conversion layer 15b is arranged between the counter electrode 15a and the pixel electrode 15c.
  • the photoelectric conversion layer 15b is laminated on the semiconductor substrate in the pixel region.
  • the material of the photoelectric conversion layer 15b may be an organic material or an inorganic material. Amorphous silicon is exemplified as an inorganic material.
  • the photoelectric conversion layer 15b may include a layer made of an organic material and a layer made of an inorganic material. Typically, the photoelectric conversion layer 15b has a film shape.
  • the pixel electrode 15c is provided on the side facing the counter electrode 15a via the photoelectric conversion layer 15b.
  • the pixel electrode 15c collects the signal charge generated by the photoelectric conversion in the photoelectric conversion layer 15b.
  • the material of the pixel electrode 15c is, for example, a metal, a metal compound, polysilicon, or the like. Examples of the metal include aluminum and copper. Examples of the metal compound include metal nitrides.
  • the polysilicon may be made conductive by being doped with impurities.
  • the counter electrode 15a is electrically connected to the storage control line 17.
  • the pixel electrode 15c is electrically connected to the node 44.
  • node 44 may also be referred to as a charge storage node or a floating diffusion node.
  • the potential of the counter electrode 15a is controlled via the storage control line 17.
  • the holes or the electrons can be collected by the pixel electrode 15c.
  • holes are collected by the pixel electrode 15c as signal charges.
  • the potential of the counter electrode 15a is set so that the potential of the counter electrode 15a exceeds the potential of the pixel electrode 15c.
  • a voltage of about 10 V is applied to the counter electrode 15a via the storage control line 17.
  • electrons may be used as the signal charge.
  • a photodiode can also be used as the photoelectric conversion unit 15.
  • the photodiode can be located within the semiconductor substrate.
  • the charge storage unit 37 is electrically connected to the node 44.
  • the electric charge generated by the photoelectric conversion is accumulated in the electric charge storage unit 37.
  • the electric charge generated by the photoelectric conversion in the photoelectric conversion unit 15 is accumulated in the charge storage unit 37.
  • the charge storage unit 37 is a diffusion region provided on the semiconductor substrate.
  • the photoelectric conversion unit 15, the charge storage unit 37, and the specific circuit GSC are electrically connected.
  • "exposure" can be realized by applying a voltage to the counter electrode 15a.
  • the transfer transistor is not provided between the photoelectric conversion unit 15 and the charge storage unit 37, whereby the above-mentioned electrical connection configuration is realized.
  • the signal detection circuit SC includes an amplification transistor 34, an address transistor 40, and a first reset transistor 36.
  • One of the source and drain of the first reset transistor 36 is electrically connected to the node 44.
  • one of the source and drain of the first reset transistor 36 constitutes a charge storage unit 37.
  • the other of the source and drain of the first reset transistor 36 is electrically connected to the reset voltage line 77.
  • the gate electrode of the amplification transistor 34 is electrically connected to the node 44, the charge storage unit 37, and the photoelectric conversion unit 15. Specifically, the gate electrode of the amplification transistor 34 is electrically connected to the pixel electrode 15c. One of the source and drain of the amplification transistor 34 is electrically connected to the power supply wiring 22. The other of the source and drain of the amplification transistor 34 is electrically connected to one of the source and drain of the address transistor 40. The other of the source and drain of the address transistor 40 is electrically connected to the vertical signal line 18. The gate electrode of the address transistor 40 is connected to the address signal line 30.
  • the power supply wiring 22 is a source follower power supply.
  • a source follower circuit is formed by the amplification transistor 34 and the load circuit 19 shown in FIG.
  • the charge storage unit 37 has a potential corresponding to the amount of signal charge stored in the charge storage unit 37. Therefore, a potential corresponding to the amount of signal charge accumulated in the charge storage unit 37 is applied to the gate electrode of the amplification transistor 34.
  • the amplification transistor 34 outputs an electric signal corresponding to this potential.
  • the electrical signal is selectively read by the address transistor 40.
  • the electrical signal is specifically a signal voltage.
  • the first reset transistor 36 resets the potential of the charge storage unit 37. Specifically, when the first reset transistor 36 is turned on, the reset potential Vrst is supplied from the reset voltage line 77 to the charge storage unit 37 via the first reset transistor 36, and the potential of the charge storage unit 37 is reset. To.
  • the specific circuit GSC includes a first capacitance element 71, a first transistor 81, and a specific reset transistor 76.
  • the first capacitive element 71 includes a first terminal 71a, a second terminal 71b, and a dielectric layer.
  • the first capacitive element 71 may include at least one selected from the group consisting of MIM (Metal Insulator Metal) capacitance, MOM (Metal Oxide Metal) capacitance, and MOS (Metal Oxide Semiconductor) capacitance. This point is the same for the second capacitance element 72 and the third capacitance element 73, which will be described later.
  • MIM Metal Insulator Metal
  • MOM Metal Oxide Metal
  • MOS Metal Oxide Semiconductor
  • the first capacitance element 71 has a MIM capacitance or a MOM capacitance.
  • the first capacitance element 71 has a MIM capacitance or a MOM capacitance, it is easy to realize the first capacitance element 71 having a large capacitance value. This is advantageous from the viewpoint of realizing a wide dynamic range.
  • the first capacitance element 71 having a MIM capacitance or a MOM capacitance can be provided outside the semiconductor substrate.
  • such a first capacitance element 71 may be provided between the semiconductor substrate and the photoelectric conversion unit 15. This means that the capacitance value of the first capacitive element 71 can be obtained without being restricted by the layout of the elements on the semiconductor substrate.
  • the first capacitance element 71 has a MIM capacitance or a MOM capacitance
  • the first capacitance element 71 has a MIM capacitance or a MOM capacitance
  • the source of the first transistor 81 may be referred to as a first source.
  • the drain of the first transistor 81 may be referred to as a first drain.
  • the gate electrode of the first transistor 81 may be referred to as a first gate electrode.
  • the first gate electrode is electrically connected to the charge storage unit 37.
  • One of the first source and the first drain is electrically connected to the charge storage unit 37.
  • the other of the first source and the first drain is electrically connected to the first terminal 71a.
  • the control potential VF is applied to the second terminal 71b from the control circuit of the image pickup apparatus 101.
  • This control potential VF may be a fixed potential.
  • Fixed potential refers to a constant potential or ground potential.
  • one of the first source and the first drain constitutes the charge storage unit 37. More specifically, the charge storage unit 37 has a function of accumulating signal charges, a function as one of a source and a drain of the first reset transistor 36, and a function of the first source and the first drain of the first transistor 81. It also functions as one side.
  • the first transistor 81 is electrically connected to the first capacitance element 71. Specifically, at least one selected from the group consisting of the first source, the first drain, and the first gate electrode of the first transistor 81 is from the first terminal 71a and the second terminal 71b pole of the first capacitance element 71. It is electrically elected to at least one selected from the group. As will be described later, the first capacitive element 71 may be configured by using the first transistor 81.
  • control circuit is a vertical scanning circuit 16.
  • control circuit may be provided separately from the vertical scanning circuit 16.
  • the node to which the control potential VF is supplied may be referred to as a node 48.
  • the node 48 is electrically connected to the second terminal 71b of the first capacitance element 71.
  • a node electrically connected to the first source or the first drain of the first transistor 81 and the first capacitance element 71 may be referred to as a node 47.
  • the node 47 is electrically connected to the other of the first source and the first drain of the first transistor 81 and to the first terminal 71a of the first capacitive element 71.
  • these need only be electrically connected for at least the exposure period of the pixels.
  • control potential VF is a DC potential.
  • the level of the control potential VF, which is a DC potential, may differ between one period and another.
  • the charge storage capacity X is a capacity electrically connected to the node 44.
  • the charge storage capacity X stores the charge generated by the photoelectric conversion.
  • the charge storage capacity X may include the charge storage unit 37.
  • the charge storage capacity X may include a first capacitance element 71.
  • the charge storage capacity X may have an action other than the action of accumulating charges.
  • the charge storage capacity X may constitute a combined impedance capacity.
  • the specific circuit GSC changes the capacity value of the charge storage capacity X in response to the change in the potential of the charge storage unit 37.
  • This configuration is suitable for achieving a wide dynamic range. Specifically, this configuration is suitable for realizing a wide dynamic range while ensuring an S / N ratio in low illuminance.
  • the potential of the specific circuit GSC changes according to the change of the potential of the charge storage unit 37.
  • the specific circuit GSC changes the capacitance value of the charge storage capacitance X in response to a change in the potential of the specific circuit GSC.
  • the capacity of the charge storage capacity X is automatically and in real time by changing the potential of the charge storage unit 37 in the analog circuit provided in the image pickup apparatus 101. The value can change.
  • the specific circuit GSC changes the capacitance value of the charge storage capacity X according to the capacitance value of the first capacitance element 71 in response to the change in the potential of the charge storage unit 37.
  • the specific circuit GSC changes the capacitance value of the charge storage capacitance X by the capacitance value of the first capacitance element 71 in response to the change in the potential of the charge storage unit 37.
  • "Changing the capacitance value of the charge storage capacity X by the capacitance value of the first capacitance element 71” means that the amount of change in the capacitance value of the charge storage capacity X matches the capacitance value of the first capacitance element 71. Means.
  • the specific circuit GSC changes the capacity value of the charge storage capacity X when the potential of the charge storage unit 37 changes across the first threshold potential.
  • Such a change in capacitance value can be realized by using the first transistor 81.
  • the image pickup apparatus 101 includes a control circuit.
  • the control circuit switches the first threshold potential according to the photographing mode.
  • the photographing mode has a first mode and a second mode.
  • the control circuit can switch the photographing mode between the first mode and the second mode by changing the first threshold potential.
  • the control circuit is the vertical scanning circuit 16.
  • FIG. 4 is a timing chart for explaining an example of the operation of the transistor in the first mode of the image pickup apparatus 101 according to the first embodiment.
  • ADD schematically shows an example of a change in the potential of the gate electrode of the address transistor 40.
  • RST1 schematically shows an example of a change in the potential of the gate electrode of the first reset transistor 36.
  • VF schematically shows an example of a change in the control potential VF.
  • RST3 schematically shows an example of a change in the potential of the gate electrode of the specific reset transistor 76.
  • the address transistor 40, the first reset transistor 36, and the specific reset transistor 76 are all off.
  • the potential of the control potential VF is maintained at a high level.
  • the high level is described as High.
  • the description of the operation of the electronic shutter will be omitted below.
  • the address transistor 40 is turned on by controlling the potential of the address signal line 30. At this time, the signal charge stored in the charge storage capacity X is read out.
  • the first reset transistor 36 is turned on by controlling the potential of the reset signal line 26.
  • the reset potential Vrst is supplied from the reset voltage line 77 to the charge storage unit 37, and the potential of the charge storage unit 37 is reset.
  • the reset potential Vrst is, for example, 1V.
  • the reset potential Vrst may be 0V depending on the threshold voltage Vt of the amplification transistor 34.
  • the threshold voltage Vt refers to the gate-source voltage when the drain current starts to flow in the amplification transistor 34.
  • the specific reset transistor 76 is turned on by controlling the potential of the specific reset signal line 75.
  • the control potential VF is supplied to the first terminal 71a of the first capacitance element 71 via the source and drain of the specific reset transistor 76, and the potential of the first terminal 71a is reset.
  • the control potential VF supplied to the first terminal 71a is at a high level.
  • the first reset transistor 36 and the specific reset transistor 76 are turned off.
  • the period from turning on the first reset transistor 36 and the specific reset transistor 76 at time t2 to turning off the first reset transistor 36 and the specific reset transistor 76 may be referred to as a “reset period”. ..
  • the reset period is a period from time t2 to time t3.
  • the reset period is schematically shown by the arrow Rst.
  • the period during which the first reset transistor 36 is on and the period during which the specific reset transistor 76 is on are both from time t2 to t3, which are the same. This configuration enables simultaneous control of the transistors 36 and 76, and makes it possible to reduce the time required for one frame.
  • the exposure is started at time t4.
  • time t4 there is a time lag between the time when the first reset transistor 36 and the specific reset transistor 76 are turned off and the time when the exposure is started.
  • the exposure may be started at the same time when the first reset transistor 36 and the specific reset transistor 76 are turned off.
  • the exposure period is schematically shown by the arrow Exp.
  • the reset voltage is read out at a predetermined timing during the exposure period. This timing corresponds to time t5. Since the time required to read the reset voltage is short, the reset voltage may be read while the address transistor 40 remains on.
  • FIG. 5 is a timing chart for explaining an example of the operation of the transistor in the second mode of the image pickup apparatus 101 according to the first embodiment.
  • the second mode is a highly saturated mode as compared with the first mode.
  • the second mode differs from the first mode in that the potential of the control potential VF is maintained at a low level.
  • the low level is referred to as Low.
  • FIG. 6 is a schematic diagram showing a typical example of the potential state of the transistor in the first mode of the image pickup apparatus 101 according to the first embodiment. As described above, in the present embodiment, the signal charge is a hole. Therefore, FIG. 6 also relates to the case where the signal charge is a hole.
  • the state (a) in FIG. 6 is the state at the start of exposure.
  • the potential of the charge storage unit 37 is the reset potential Vrst.
  • the potential of the first terminal 71a of the first capacitance element 71 is the control potential VF.
  • the potential of the charge storage unit 37 is higher than the potential under the gate of the first transistor 81.
  • the potential of the first terminal 71a of the first capacitance element 71 is higher than the potential of the charge storage unit 37.
  • the first transistor 81 is off.
  • the state (b) in FIG. 6 is a state during exposure. Since the signal charge is a hole, the potential of the charge storage unit 37 rises during exposure. The gate electrode of the first transistor 81 is electrically connected to the charge storage unit 37. Therefore, as the potential of the charge storage unit 37 rises, the potential under the gate of the first transistor 81 also rises.
  • the state (c) in FIG. 6 is the state at the end of exposure.
  • the control potential VF is at a high level. Therefore, the potential under the gate of the first transistor 81 has not become higher than the control potential VF. Further, the first transistor 81 is off.
  • FIG. 7 is a graph schematically showing a typical example of a change in the level of an electric signal output from the amplification transistor 34 with respect to a change in the amount of light incident on the photoelectric conversion unit 15 in the first mode.
  • the horizontal axis is the amount of light.
  • the vertical axis is the level of the electric signal output from the amplification transistor 34.
  • the values on the horizontal axis and the vertical axis in FIG. 7 are standardized values. These points are the same for FIG. 9A, which will be described later.
  • the level of the electric signal output from the amplification transistor 34 continuously increases as the amount of light increases. However, when the amount of light is 1, the increase in the signal level has reached a plateau.
  • the state (a) in FIG. 8 is the state at the start of exposure.
  • the potential of the charge storage unit 37 is the reset potential Vrst.
  • the potential of the first terminal 71a of the first capacitance element 71 is the control potential VF.
  • the potential of the charge storage unit 37 is higher than the potential under the gate of the first transistor 81.
  • the potential of the first terminal 71a of the first capacitance element 71 is higher than the potential of the charge storage unit 37.
  • the first transistor 81 is off.
  • the state (b) in FIG. 8 is a state during exposure. Since the signal charge is a hole, the potential of the charge storage unit 37 rises during exposure. The gate electrode of the first transistor 81 is electrically connected to the charge storage unit 37. Therefore, as the potential of the charge storage unit 37 rises, the potential under the gate of the first transistor 81 also rises.
  • the gate-source voltage of the first transistor 81 eventually exceeds the threshold voltage, and the first transistor 81 turns on. As a result, the charge storage unit 37 and the first terminal 71a are electrically connected via the first transistor 81.
  • the timing at which the first transistor 81 turns on is the same as the timing at which the potential under the gate of the first transistor 81 reaches the potential of the first terminal 71a.
  • the former timing may be earlier or later than the latter timing.
  • the potential under the gate of the first transistor 81 is higher than the potential of the first terminal 71a and the potential of the charge storage unit 37 is the potential of the first transistor 81.
  • a situation can occur where the potential is higher than the under-gate potential. In this situation, electrons are injected from the first terminal 71a into the charge storage unit 37 via the first transistor 81. Due to the injection of electrons, the potential of the charge storage unit 37 is lowered. Along with this, the potential under the gate of the first transistor 81 also decreases. On the other hand, the potential of the first terminal 71a rises.
  • the potential of the charge storage unit 37 and the potential of the first terminal 71a are balanced.
  • the potential of the charge storage unit 37 and the potential of the first terminal 71a can increase while this balance is maintained.
  • the voltage between the first terminal 71a and the second terminal 71b changes as the signal charge is generated. That is, the first capacitance element 71 functions as a part of the charge storage capacitance X for accumulating charges, so that the capacitance value of the charge storage capacitance X is increased. By that amount, the change in the potential of the charge storage unit 37 becomes gradual.
  • the state (c) in FIG. 8 is the state at the end of exposure. Compared to the first mode shown in FIG. 6, in the second mode, the potential of the charge storage unit 37 at the end of exposure is lower because the change in the potential of the charge storage unit 37 is gradual as described above. Therefore, the difference voltage ⁇ V is lower in the second mode than in the first mode.
  • FIG. 9A is a graph schematically showing a typical example of a change in the level of an electric signal output from the amplification transistor 34 with respect to a change in the amount of light incident on the photoelectric conversion unit 15 in the second mode.
  • the level of the electric signal output from the amplification transistor 34 gradually increases when the amount of light increases across the first threshold light amount. This is because, in the region where the amount of light is equal to or greater than the first threshold amount of light, the phenomenon that the potential of the charge storage unit 37 described with reference to FIG. 8 changes slowly appears. In other words, when the amount of light increases across the first threshold amount of light, the capacity value of the charge storage capacity X increases. As can be seen from FIGS.
  • the signal charge in the second mode, can be accumulated in the charge storage capacity X up to a region where the amount of light is larger than that in the first mode.
  • the first capacitive element 71 if the first capacitive element 71 does not function as a charge accumulating charge generated by photoelectric conversion, the first capacitive element 71 accumulates charge. Does not form part of the capacity X.
  • the first capacitance element 71 when the first capacitance element 71 functions as a capacitance for accumulating charges generated by photoelectric conversion, the first capacitance element 71 constitutes a part of the charge storage capacitance X.
  • the charge storage capacity X increases as the first capacitance element 71 functions as a capacity for storing charges generated by photoelectric conversion. In other words, the charge storage capacity X increases by making it "visible" as a capacity from the first capacitance element 71.
  • the charge storage capacity X can be explained as follows. That is, the capacity value of the capacity that does not function as the capacity for storing the charge generated by the photoelectric conversion in the image pickup apparatus 101 is not counted as the capacity value of the charge storage capacity X. On the other hand, the capacity value of the capacity that functions as the capacity for storing the charge generated by the photoelectric conversion in the image pickup apparatus 101 is counted as the capacity value of the charge storage capacity X. In other words, the capacitance value of the "invisible” capacitance in the image pickup apparatus 101 is not counted as the capacitance value of the charge storage capacity X. On the other hand, the capacity value of the capacity "visible” as the capacity in the image pickup apparatus 101 is counted as the capacity value of the charge storage capacity X.
  • gamma correction may be performed in the image processing in the subsequent stage of the image pickup apparatus.
  • FIG. 9B is a graph for explaining gamma correction.
  • the horizontal axis of FIG. 9B is the amount of light.
  • the vertical axis is the signal level held by the camera system.
  • the values on the horizontal axis and the vertical axis in FIG. 9B are standardized values.
  • the alternate long and short dash line curve shows the light intensity-signal level characteristic obtained by gamma correction in the image processing in the subsequent stage of the imaging device.
  • the straight line of the alternate long and short dash line shows the light intensity-signal level characteristic obtained when this gamma correction is not performed.
  • the straight line of the alternate long and short dash line indicates that the amount of light and the signal level held by the camera system take the same value when gamma correction is not performed. From the dashed line curve, it can be seen that gamma correction increases the ratio of the signal level value to the light intensity value in the low light intensity region. For example, in the two-dot chain line curve, the signal level is 0.5 when the amount of light is 0.2.
  • the solid line shows the light intensity-signal level characteristic that can be obtained by the second mode of this embodiment.
  • a pseudo gamma characteristic is obtained in the pixel 11a.
  • the pseudo gamma characteristic obtained in the present embodiment is a characteristic having the following advantages. These advantages are useful in camera systems. ⁇ It is easy to secure the S / N ratio in the region where the amount of light is low. ⁇ It is easy to assign abundant gradations or bit numbers to the region where the amount of light is low. ⁇ It is easy to secure the capacity value of the charge storage capacity X in the region where the amount of light is high.
  • the electrical signal is an electrical signal that the amplification transistor 34 outputs according to the potential of the charge storage unit 37.
  • the amount of light incident on the image pickup apparatus 101 is the amount of light incident on the photoelectric conversion unit 15.
  • the above ratio is a value obtained by differentiating the level of an electric signal by the amount of light.
  • FIG. 10 is a graph for explaining the adjustment of the gamma characteristic.
  • the potential VFA is greater than the potential VFB and the potential VFB is greater than the potential VFC.
  • the first threshold light amount is the light amount QA.
  • the first threshold light amount is the light amount QB.
  • the first threshold light amount is the light amount QC.
  • the light quantity QA is larger than the light quantity QB, and the light quantity QB is larger than the light quantity QC.
  • VFA potential VFA> potential VFB> potential VFC
  • light quantity QA> light quantity QB> light quantity QC light quantity QC.
  • FIG. 11 is a timing chart for explaining an example of the operation of the transistor in the second mode of the image pickup apparatus according to the second embodiment.
  • the dotted line in which the character RST3 is also written schematically shows an example of the change in the potential of the gate electrode of the specific reset transistor 76 in the first embodiment.
  • the dotted line with the letter ta schematically shows an example of the change in the potential of the gate electrode of the specific reset transistor 76 in the second embodiment.
  • FIG. 12 is a schematic diagram showing a typical example of the potential state of the transistor in the second mode of the image pickup apparatus according to the second embodiment.
  • the state (a) of FIG. 12 is a state before the turn-on of the specific reset transistor 76 and the turn-on of the first reset transistor 36 are performed.
  • the state (b) in FIG. 12 is a state during the period when the specific reset transistor 76 is on.
  • node 47 is set to the control potential VF.
  • the potential of the charge storage unit 37 is also set to the control potential VF.
  • the state (c) in FIG. 12 is a state during the period when the first reset transistor 36 is on.
  • the potential of the charge storage unit 37 is reset to the reset potential Vrst.
  • the potential of the node 47 is also reset to the reset potential Vrst.
  • the first transistor 81 may have a substrate bias effect. In this case, a potential difference may occur between the first source and the first drain of the first transistor 81. However, even in this case, according to the operation of the transistor based on the timing chart of FIG. 11, the potential states of the charge storage unit 37 and the node 47 can be stabilized.
  • FIG. 13 is a schematic view showing another example of the potential state of the transistor in the second mode of the image pickup apparatus according to the second embodiment. Specifically, FIG. 13 relates to a case where the first transistor 81 has a substrate bias effect.
  • the state (a) in FIG. 13 is a state before the specific reset transistor 76 is turned on and the first reset transistor 36 is turned on.
  • the state (b) in FIG. 13 is a state during the period when the specific reset transistor 76 is on.
  • the potential of the node 47 is set to the control potential VF.
  • the potential of the charge storage unit 37 is set to a potential slightly larger than the control potential VF due to the substrate bias effect.
  • FIG. 14 is a schematic diagram showing an exemplary circuit configuration of the image pickup apparatus 201 according to the third embodiment.
  • the negative input terminal of the inverting amplifier 24 is connected to the corresponding vertical signal line 18.
  • a predetermined voltage Vref is supplied to the input terminal on the positive side of the inverting amplifier 24.
  • the voltage Vref is, for example, 1V or a positive voltage in the vicinity of 1V.
  • the output terminal of the inverting amplifier 24 is connected to a plurality of pixels 11b connected to the input terminal on the negative side of the inverting amplifier 24 via the feedback line 25.
  • the inverting amplifier 24 constitutes a part of a feedback circuit that negatively feeds back an electric signal from the pixel 11b.
  • the inverting amplifier 24 may be called a feedback amplifier.
  • the inverting amplifier 24 includes a gain adjusting terminal 24a for changing the inverting amplification gain.
  • Pixel 11b includes a capacitance circuit 45 in which a capacitance element 41 and a capacitance element 42 are connected in series.
  • the capacitance value of the capacitance element 42 is larger than the capacitance value of the capacitance element 41.
  • One of the source and drain of the first reset transistor 36, one electrode of the capacitive element 41, the pixel electrode 15c, and the node 44 are electrically connected.
  • the formation of the feedback circuit FC is performed on one of the plurality of pixels 11b that share the feedback line 25.
  • the pixel 11b to be formed of the feedback circuit FC is selected, and at least one of the group consisting of reset and noise cancellation is executed for the desired pixel 11b. Can be done.
  • the feedback circuit FC is a negative feedback amplifier circuit including an amplifier transistor 34, an inverting amplifier 24, and a second reset transistor 38.
  • the address transistor 40 turned on at time t1 supplies the output of the amplification transistor 34 as an input to the feedback circuit FC.
  • the specific reset transistor 76 is turned on by controlling the potential of the specific reset signal line 75.
  • the control potential VF is supplied to the first terminal 71a of the first capacitance element 71 via the source and drain of the specific reset transistor 76, and the potential of the first terminal 71a is reset.
  • the control potential VF supplied to the first terminal 71a is at a high level.
  • the first reset transistor 36 and the specific reset transistor 76 are turned off. Turn off.
  • the period from turning on the first reset transistor 36, the second reset transistor 38 and the specific reset transistor 76 to turning off the first reset transistor 36 and the specific reset transistor 76 at time t2 is "reset”.
  • the reset period is a period from time t2 to time t3.
  • the reset period is schematically shown by the arrow Rst.
  • the voltage of the vertical signal line 18 immediately before turning off the first reset transistor 36 is substantially equal to the voltage Vref applied to the negative input terminal of the inverting amplifier 24.
  • the period from turning off the first reset transistor 36 to turning off the second reset transistor 38 may be referred to as a “noise canceling period”.
  • the noise cancellation period is a period from time t3 to time t4.
  • the noise cancellation period is schematically shown by an arrow Ncl.
  • the third embodiment it is possible to reduce the kTC noise generated by turning off the first reset transistor 36 and cancel the generated kTC noise in a relatively short time. ..
  • the exposure period is schematically shown by the arrow Exp.
  • the reset voltage with the kTC noise canceled is read out at a predetermined timing during the exposure period. This timing corresponds to time t5. Since the time required to read the reset voltage is short, the reset voltage may be read while the address transistor 40 remains on.
  • FIG. 18 is a schematic diagram showing an exemplary circuit configuration of pixels 11c in the image pickup apparatus according to the fourth embodiment.
  • the image pickup apparatus 201 of the third embodiment is provided with a switching circuit 50 instead of the inverting amplifier 24 in each row of the pixels 11c.
  • the feedback line 25 does not connect the pixels 11c.
  • one of the source and drain of the second reset transistor 38 is electrically connected to the node 46.
  • the other of the source and drain of the second reset transistor 38 is electrically connected to the feedback line 25.
  • One of the source and drain of the address transistor 40 is electrically connected to the feedback line 25 and the vertical signal line 18.
  • the other of the source and drain of the address transistor 40 is electrically connected to one of the source and drain of the amplification transistor 34.
  • the other of the source and drain of the amplification transistor 34 is electrically connected to the power supply wiring 22.
  • the switching circuit 50 includes switch elements 51 and 51', switch elements 52 and 52', and constant current sources 27 and 27'.
  • the switch elements 51 and 51' are electrically connected to the power supply wiring 22.
  • the power supply potential A VDD can be connected to the power supply wiring 22 via the switch element 51.
  • the reference potential AVSS may be connected to the power supply wiring 22 via the switch element 51'.
  • a voltage is applied to the gate electrode of the address transistor 40 via the address signal line 30.
  • one of the pixels 11c in each column is selected.
  • a current flows from the constant current source 27 in the direction from the amplification transistor 34 to the address transistor 40, and the electric charge amplified by the amplification transistor 34.
  • the potential of the storage unit 37 is detected.
  • the switch element 51'and the switch element 52'of the switching circuit 50 are turned on.
  • a current flows through the address transistor 40 and the amplification transistor 34 in the direction opposite to that at the time of signal reading.
  • a feedback circuit FC including an amplification transistor 34, an address transistor 40, a feedback line 25, a second reset transistor 38, and a first reset transistor 36 is configured. Since the address transistor 40 and the amplification transistor 34 are cascode-connected, a large gain can be obtained. Therefore, the feedback circuit FC can cancel noise with a large gain.
  • the image pickup apparatus of this embodiment does not include the inverting amplifier 24, and the address transistor 40 and the amplification transistor 34 are included in the signal detection circuit SC and function as an amplifier of the feedback circuit FC. Therefore, the area of the circuit of the image pickup apparatus can be reduced. In addition, the power consumption of the imaging device can be reduced. Further, since a large gain can be obtained by cascode connection, kTC noise can be reduced even when the capacitances of the capacitance element 41 and the capacitance element 42 are small.
  • FIG. 19A is a schematic diagram showing an exemplary circuit configuration of the image pickup apparatus according to the fifth embodiment.
  • the circuit configuration of the pixel 11d of the fifth embodiment shown in FIG. 19A is different from the circuit configuration of the pixel 11a of the first embodiment shown in FIG. 2 in the specific circuit GSC.
  • the first gate electrode of the first transistor 81 is electrically connected to the first terminal 71a of the first capacitance element 71 and the charge storage unit 37.
  • One of the first source and the first drain of the first transistor 81 is electrically connected to the second terminal 71b of the first capacitive element 71.
  • the control potential VF is applied from the control circuit to the other of the first source and the first drain of the first transistor 81.
  • the node 47 is electrically connected to one of the first source and the first drain of the first transistor 81 and the second terminal 71b of the first capacitance element 71.
  • the node 48 is electrically connected to the other of the first source and the first drain of the first transistor 81.
  • one of the source and drain of the first reset transistor 36 constitutes a charge storage unit 37.
  • the potential of the charge storage unit 37 When the potential of the charge storage unit 37 is low, the potential of the gate electrode of the first transistor 81 is also low. The first transistor 81 is off. The control potential VF is not supplied to the second terminal 71b of the node 47 and the first capacitance element 71. The node 47 and the second terminal 71b are in a floating state. In this case, the first capacitance element 71 does not function as a capacitance for accumulating the electric charge generated by the photoelectric conversion. Therefore, the capacitance value of the charge storage capacitance X by the first capacitance element 71 is not increased.
  • FIG. 20 is a timing chart for explaining a typical example of the operation of the transistor in the second mode of the image pickup apparatus according to the fifth embodiment.
  • the period in which the first reset transistor 36 is turned on differs between the example shown in FIG. 20 according to the fifth embodiment and the example shown in FIG. 5 according to the first embodiment. Specifically, in the example shown in FIG. 20, the first reset transistor 36 is on during the period from time t2 to t4.
  • Vrst schematically shows an example of a change in the reset potential Vrst applied to the reset voltage line 77.
  • the reset potential Vrst applied to the reset voltage line 77 has a low level in the period from time t0 to time t2, a high level in the period from time t2 to t3, and after time t3. Low level during the period.
  • the end of the reset period corresponds to the disclosure of the exposure period. However, there may be a time lag between the end of the reset period and the disclosure of the exposure period.
  • FIG. 21 is a schematic diagram showing a typical example of the potential state of the transistor in the second mode of the image pickup apparatus according to the fifth embodiment. The state of FIG. 21 can be obtained by the control of FIG.
  • the state (a) in FIG. 21 is a state during the period from time t2 to t3.
  • the first reset transistor 36 is in the ON state, and the reset potential Vrst is at a high level. Therefore, a high level reset potential Vrst is applied to the first gate electrode of the first transistor 81.
  • the first transistor 81 is on.
  • the control potential VF is supplied not only to the node 48 but also to the node 47 and the second electrode 71b via the first source and the first drain of the first transistor 81. In this way, the potentials of the node 47 and the second electrode 71b are reset to the control potential VF.
  • the state (b) in FIG. 21 is a state during the period from time t3 to t4. During this period, the first reset transistor 36 is on, but the reset potential Vrst is at a low level. Therefore, the first transistor 81 is off. During this period, the potential of the charge storage unit 37 is reset to the low level reset potential Vrst.
  • the control circuit applies the reset potential Vrst to the charge storage unit 37 during the reset period.
  • the control circuit temporarily turns on the first transistor 81 by changing the level of the reset potential Vrst in a pulsed manner.
  • the first transistor 81 is temporarily turned on, so that the control potential VF is applied from the control circuit to the second terminal 71b via the first source and the first drain of the first transistor 81.
  • the potential of the second terminal 71b is reset.
  • the potential of the second terminal 71b can be reset at the same time as the potential of the charge storage unit 37 can be reset during the reset period.
  • the first period corresponds to the period from time t2 to t3 in FIG.
  • the second period corresponds to the period from time t3 to t4 in FIG.
  • the first level corresponds to the high level of FIG.
  • the second level corresponds to the low level of FIG.
  • FIG. 22 is a timing chart for explaining another example of the operation of the transistor in the second mode of the image pickup apparatus according to the fifth embodiment.
  • the reset potential Vrst applied to the reset voltage line 77 is different between the example shown in FIG. 22 and the example shown in FIG. 20. Specifically, in the example shown in FIG. 22, the reset potential Vrst applied to the reset voltage line 77 is constant at a low level.
  • FIG. 23 is a schematic diagram showing an example of the potential state of the transistor in the second mode of the image pickup apparatus according to the fifth embodiment. The state of FIG. 23 can be obtained by the control of FIG.
  • the state (b) in FIG. 23 is a state in the period from time t3 to t4. During this period, the control potential VF is at a relatively high first low level. The first low level is higher than the under-gate potential of the first transistor 81 in the off state.
  • the potentials of the node 47 and the second electrode 71b are reset to the potentials of the potential under the gate of the first transistor 81 in the off state.
  • the reset period has a first period and a second period following the first period.
  • the first period is the period following the 0th period.
  • the reset potential Vrst is at a level that keeps the first transistor 81 in the off state.
  • the control potential VF is at the 3rd level.
  • the control potential VF is at the fourth level.
  • the third level does not short the first source and the first drain of the first transistor 81.
  • the fourth level shorts the first source and the first drain of the first transistor 81.
  • the control circuit changes the control potential VF between the third and fourth levels, in other words, across the level of the subgate potential of the first transistor 81 that is in the off state.
  • the potential of the second electrode 71b is reset to the potential of the potential under the gate of the first transistor 81 in the off state.
  • the potential of the charge storage unit 37 is reset to the reset potential Vrst.
  • the control potential VF after the reset period is a potential that realizes auto gamma ON.
  • the first period corresponds to the period from time t2 to t3 in FIG.
  • the second period corresponds to the period from time t3 to t4 in FIG.
  • the third level corresponds to the first low level in FIG.
  • the fourth level corresponds to the second low level in FIG.
  • FIG. 19B is a schematic diagram showing another exemplary circuit configuration of the image pickup apparatus according to the fifth embodiment.
  • one of the source and the drain of the specific reset transistor 76 is connected to the node 47.
  • a control potential VF is applied from the control circuit to the other of the source and drain of the specific reset transistor 76.
  • the first terminal 71a of the first capacitance element 71 is electrically connected to the gate electrode of the amplification transistor 34, the charge storage unit 37, the node 44, and the photoelectric conversion unit 15. Specifically, the first terminal 71a is electrically connected to the pixel electrode 15c.
  • the first capacitance element 71 having a MOS capacitance By adopting the first capacitance element 71 having a MOS capacitance, it is possible to realize a specific circuit GSC with a small number of elements. This is advantageous from the viewpoint of reducing the size of the pixel 11f, improving the resolution, and the like.
  • the first capacitance element 71 which has a MOS capacitance, is configured by using the first transistor 81.
  • One of the first terminal 71a and the second terminal 71b is electrically connected to the first source and the first drain of the first transistor 81.
  • the other of the first terminal 71a and the second terminal 71b is electrically connected to the first gate electrode of the first transistor 81.
  • the second terminal 71b is electrically connected to the first source and the first drain of the first transistor 81.
  • the first terminal 71a is electrically connected to the first gate electrode of the first transistor 81.
  • the first source and the first drain of the first transistor 81 are electrically connected to each other. According to this configuration, the first transistor 81 can be turned on when the difference between the potential of the first capacitance element 71 and the potential of the second terminal 71b reaches a certain value.
  • the first source and the first drain of the first transistor 81 can be electrically connected by wiring or the like.
  • the term voltage between terminals of the first capacitive element 71 may be used.
  • the voltage between terminals is the difference between the potential of the first capacitance element 71 and the potential of the second terminal 71b.
  • the control potential VF is applied to the second terminal 71b of the first capacitance element 71.
  • the first terminal 71a is electrically connected to the charge storage unit 37. Therefore, when the photoelectric conversion unit 15 performs the photoelectric conversion, the potential of the first terminal 71a changes together with the potential of the charge storage unit 37, and the voltage between the terminals also changes. Specifically, since the signal charge is a hole, when the photoelectric conversion unit 15 performs the photoelectric conversion, the potential of the first terminal 71a rises together with the potential of the charge storage unit 37. When the voltage between the terminals reaches a certain value, the first transistor 81 turns on. As a result, the first capacitance element 71 functions as a capacitance for accumulating the electric charge generated by the photoelectric conversion. In this way, the capacity value of the charge storage capacity X increases.
  • the control potential VF applied to the second terminal 71b may be switched.
  • the imaging mode of the imaging apparatus has a first mode and a second mode.
  • the control potential VF applied to the second terminal 71b is the potential VFA.
  • the control potential VF applied to the second terminal 71b is the potential VFB.
  • the potential VFA and the potential VFB are different from each other. According to this example, it is possible to make a difference between the first threshold potential of the first mode and the first threshold potential of the second mode.
  • the first capacitance element 71 which has a MOS capacitance, can function as a capacitance for accumulating the electric charge generated by the photoelectric conversion.
  • this function changes stepwise when the potential of the charge storage unit 37 changes across the first threshold potential.
  • this function may change continuously when the potential of the charge storage unit 37 changes across the first threshold potential.
  • the expression "the specific circuit GSC changes the capacity value of the charge storage capacity X when the potential of the charge storage unit 37 changes across the first threshold potential” includes any of these forms. Is.
  • the expression “the specific circuit GSC changes the capacitance value of the charge storage capacitance X by the capacitance value of the first capacitance element 71 in response to the change in the potential of the charge storage unit 37" is any of these forms. It is an expression that also includes. Further, the expression “the specific circuit GSC changes the capacity value of the charge storage capacity X in response to the change in the potential of the charge storage unit 37" is an expression that includes any of these forms.
  • FIG. 25 is a schematic diagram showing an exemplary circuit configuration of the image pickup apparatus according to the seventh embodiment.
  • the circuit configuration of the pixel 11g of the seventh embodiment shown in FIG. 25 is different from the circuit configuration of the pixel 11d of the fifth embodiment shown in FIG. 19A in the specific circuit GSC.
  • the specific circuit GSC of the seventh embodiment shown in FIG. 25 has a plurality of stages of circuits corresponding to the specific circuit GSC of the fifth embodiment shown in FIG. 19A.
  • the specific circuit GSC includes the first transistor 81, the second transistor 82, the third transistor 83, the first capacitance element 71, the second capacitance element 72, and the third capacitance element 73. Have.
  • the second capacitance element 72 includes a first terminal 72a and a second terminal 72b.
  • the third capacitive element 73 includes a first terminal 73a and a second terminal 73b.
  • the first gate electrode of the first transistor 81 is electrically connected to the first terminal 71a of the first capacitance element 71 and the charge storage unit 37.
  • One of the first source and the first drain of the first transistor 81 is electrically connected to the second terminal 71b of the first capacitive element 71.
  • the first control potential VF1 is applied from the control circuit to the other of the first source and the first drain of the first transistor 81.
  • the second gate electrode of the second transistor 82 is electrically connected to the first terminal 72a of the second capacitance element 72 and the charge storage unit 37.
  • One of the second source and the second drain of the second transistor 82 is electrically connected to the second terminal 72b of the second capacitance element 72.
  • a second control potential VF2 is applied from the control circuit to the other of the second source and the second drain of the second transistor 82.
  • the third gate electrode of the third transistor 83 is electrically connected to the first terminal 73a of the third capacitance element 73 and the charge storage unit 37.
  • One of the third source and the third drain of the third transistor 83 is electrically connected to the second terminal 73b of the third capacitance element 73.
  • a third control potential VF3 is applied from the control circuit to the other of the third source and the third drain of the third transistor 83.
  • FIG. 26 is a diagram schematically showing a typical example of a change in the level of an electric signal output from the amplification transistor 34 with respect to a change in the amount of light incident on the photoelectric conversion unit 15 in the second mode according to the seventh embodiment. be.
  • the first capacitance element 71 when the amount of light incident on the image pickup apparatus increases across the first threshold light amount Qth1, the first capacitance element 71 functions as a capacitance for accumulating the electric charge generated by the photoelectric conversion. As a result, the capacity value of the charge storage capacity X increases.
  • the second capacitance element 72 functions as a capacitance for accumulating the electric charge generated by the photoelectric conversion.
  • the capacity value of the charge storage capacity X increases.
  • the third capacitance element 73 functions as a capacitance for accumulating the electric charge generated by the photoelectric conversion.
  • the capacity value of the charge storage capacity X increases.
  • the amount of light incident on the image pickup apparatus is specifically the amount of light incident on the photoelectric conversion unit 15.
  • the band in which the light amount is equal to or more than the first threshold light amount Qth1 and less than the second threshold light amount Qth2 is referred to as a band (1).
  • the band in which the amount of light is equal to or greater than the second threshold amount of light Qth2 and less than or equal to the third threshold amount of light Qth3 is referred to as band (2).
  • the band in which the amount of light is equal to or greater than the third threshold amount of light Qth3 is referred to as a band (3).
  • the potential of the charge storage unit 37 when the amount of light is the first threshold light amount Qth1 is referred to as the first threshold potential.
  • the potential of the charge storage unit 37 when the light amount is the second threshold light amount Qth2 is referred to as a second threshold potential.
  • the potential of the charge storage unit 37 when the light amount is the second threshold light amount Qth3 is referred to as a third threshold potential.
  • the third control potential VF3, the second control potential VF2, and the first control potential VF1 are different from each other.
  • the first threshold light amount Qth1, the second threshold light amount Qth2, and the third threshold light amount Qth3 can be set to different light amounts.
  • the threshold voltage is the gate-source voltage of the transistor as it turns on.
  • the third control potential VF3 is larger than the second control potential VF2.
  • the second control potential VF2 is larger than the first control potential VF1.
  • the third threshold light amount Qth3 can be made larger than the second threshold light amount Qth2, and the second threshold light amount Qth2 can be made larger than the first threshold light amount Qth1.
  • the threshold voltage Vth3 of the third transistor 83, the threshold voltage Vth2 of the second transistor 82, and the threshold voltage Vth1 of the first transistor 81 are different from each other.
  • the first threshold light amount Qth1, the second threshold light amount Qth2, and the third threshold light amount Qth3 can be different light amounts from each other.
  • the threshold voltage Vth3 of the third transistor 83 is larger than the threshold voltage Vth2 of the second transistor 82.
  • the threshold voltage Vth2 of the second transistor 82 is larger than the threshold voltage Vth1 of the first transistor 81.
  • the third threshold light amount Qth3 can be made larger than the second threshold light amount Qth2, and the second threshold light amount Qth2 can be made larger than the first threshold light amount Qth1.
  • the capacitance value C3 of the third capacitance element 73 is larger than the capacitance value C2 of the second capacitance element 72.
  • the capacitance value C2 of the second capacitance element 72 is larger than the capacitance value C1 of the first capacitance element 71.
  • the specific circuit GSC changes the capacitance value of the charge storage capacity X according to the capacitance value of the first capacitance element 71 when the potential of the charge storage unit 37 changes across the first threshold potential.
  • the specific circuit GSC changes the capacitance value of the charge storage capacity X according to the capacitance value of the second capacitance element 72 when the potential of the charge storage unit 37 changes across the second threshold potential.
  • the specific circuit GSC changes the capacitance value of the charge storage capacity X according to the capacitance value of the third capacitance element 73 when the potential of the charge storage unit 37 changes across the third threshold potential.
  • the specific circuit GSC changes the capacitance value of the charge storage capacity X by the capacitance value of the first capacitance element 71 when the potential of the charge storage unit 37 changes across the first threshold potential.
  • the specific circuit GSC changes the capacitance value of the charge storage capacity X by the capacitance value of the second capacitance element 72 when the potential of the charge storage unit 37 changes across the second threshold potential.
  • the specific circuit GSC changes the capacitance value of the charge storage capacity X by the capacitance value of the third capacitance element 73 when the potential of the charge storage unit 37 changes across the third threshold potential.
  • the specific circuit GSC of the seventh embodiment shown in FIG. 25 has a plurality of stages corresponding to the specific circuit GSC of the fifth embodiment shown in FIG. 19A.
  • the specific circuit GSC may have a plurality of stages of circuits corresponding to the specific circuit GSC of other embodiments.
  • the number of stages is 3, but the number of stages may be 2 or 4 or more.
  • the photoelectric conversion unit 15 is a photodiode. Specifically, the photoelectric conversion unit 15 is a silicon photodiode. The photoelectric conversion unit 15 is also a charge storage unit 55 in which the charges generated by the photoelectric conversion are accumulated. The signal charge is an electron.
  • the first gate electrode of the first transistor 81 is electrically connected to the first terminal 71a of the first capacitance element 71.
  • One of the first source and the first drain of the first transistor 81 is electrically connected to the first terminal 71a.
  • the other of the first source and the first drain is electrically connected to the charge storage unit 55.
  • a control potential is applied from the control circuit to the second terminal 71b of the first capacitance element 71.
  • the node 48 is electrically connected to the second terminal 71b of the first capacitance element 71.
  • the node 47 is electrically connected to one of the first source and the first drain of the first transistor 81 and to the first terminal 71a of the first capacitance element 71.
  • FIG. 28 is a schematic diagram showing a typical example of the potential state of the transistor in the second mode of the image pickup apparatus according to the eighth embodiment.
  • the state (b) in FIG. 28 is a state during exposure. Since the signal charge is an electron, the potential of the charge storage unit 55 drops during exposure.
  • the gate-source voltage of the first transistor 81 eventually exceeds the threshold voltage, and the first transistor 81 turns on. As a result, the charge storage unit 55 and the first terminal 71a are electrically connected via the first transistor 81.
  • the node 44 is electrically connected to the other of the source and drain of the transfer transistor 39, one of the first source and first drain of the first transistor 81, and the photoelectric conversion unit 15, that is, the charge storage unit 55. It is connected to the.
  • a node electrically connected to one of the source and drain of the transfer transistor 39 and the gate electrode of the amplification transistor 34 is referred to as a node 49.
  • the state (a) in FIG. 30 is the state at the start of exposure. In the state (a), the signal charge is not accumulated in the charge storage unit 55.
  • the potential of the first terminal 71a of the first capacitance element 71 is the control potential VF.
  • the potential of the first terminal 71a of the first capacitance element 71 is higher than the potential under the gate of the first transistor 81.
  • the potential of the charge storage unit 55 is higher than the potential of the first terminal 71a of the first capacitance element 71.
  • the state (b) in FIG. 30 is a state during exposure. Since the signal charge is an electron, the potential of the photoelectric conversion unit 15 drops during exposure. That is, the potential of the charge storage unit 55 decreases.
  • the gate-source voltage of the first transistor 81 eventually exceeds the threshold voltage, and the first transistor 81 turns on. As a result, the charge storage unit 55 and the first terminal 71a are electrically connected via the first transistor 81.
  • the potential under the gate of the first transistor 81 is lower than the potential of the first terminal 71a and the potential of the charge storage unit 55 is the potential of the first transistor 81.
  • a situation can occur where the potential is lower than the under-gate potential. In this situation, electrons are injected from the charge storage unit 55 into the first terminal 71a via the first transistor 81. The potential of the charge storage unit 55 rises due to the injection of electrons. Along with this, the potential under the gate of the first transistor 81 also increases. On the other hand, the potential of the first terminal 71a decreases.
  • the state (c) in FIG. 30 is the state at the end of exposure.
  • the transfer transistor 39 is turned on from this state, the charge is transferred from the charge storage unit 55 to the charge storage unit 37. In this way, the signal is read out. In this way, the state (d) of FIG. 30 is obtained.
  • the transfer transistor 39 transfers the charge from the charge storage unit 55 to the charge storage unit 37.
  • This transfer can be a so-called complete transfer. Therefore, ktc noise can be suitably reduced without a noise canceling circuit such as the feedback circuit FC of FIGS. 15 and 18.
  • FIG. 31 is a schematic diagram showing an exemplary circuit configuration of the image pickup apparatus according to the tenth embodiment.
  • the circuit configuration of the pixel 11j of the tenth embodiment shown in FIG. 31 is different from the circuit configuration of the pixel 11h of the eighth embodiment shown in FIG. 27 in the specific circuit GSC.
  • the first capacitance element 71 has a MOS capacitance.
  • the first terminal 71a of the first capacitance element 71 is electrically connected to the gate electrode of the amplification transistor 34, the charge storage unit 37, the node 44, and the photoelectric conversion unit 15.
  • the photoelectric conversion unit 15 is a photodiode.
  • the photoelectric conversion unit 15 is also a charge storage unit 55.
  • the first capacitance element 71 which has a MOS capacitance, is configured by using the first transistor 81.
  • One of the first terminal 71a and the second terminal 71b is electrically connected to the first source and the first drain of the first transistor 81.
  • the other of the first terminal 71a and the second terminal 71b is electrically connected to the first gate electrode of the first transistor 81.
  • the first terminal 71a is electrically connected to the first source and the first drain of the first transistor 81.
  • the second terminal 71b is electrically connected to the gate electrode of the first transistor 81.
  • the first source and the first drain of the first transistor 81 are electrically connected to each other. According to this configuration, the first transistor 81 can be turned on when the difference between the potential of the first capacitance element 71 and the potential of the second terminal 71b reaches a certain value.
  • the first source and the first drain of the first transistor 81 can be electrically connected by wiring or the like.
  • the first transistor 81 turns on.
  • the first capacitance element 71 functions as a capacitance for accumulating the electric charge generated by the photoelectric conversion. In this way, the capacity value of the charge storage capacity X increases.
  • FIG. 32 is a diagram schematically showing an example of a change in the output of the horizontal signal readout circuit 21 with respect to an increase in the exposure amount.
  • the solid line L1 is a straight line.
  • the broken line L2 and the broken line L3 are polygonal lines. The broken lines L2 and L3 deviate from the straight line of the solid line L1 as the exposure amount increases.
  • FIG. 33 schematically shows an outline of the linearity compensation process.
  • a table for converting the output from the horizontal signal reading circuit 21 into an appropriate digital value may be prepared for each control potential VF.
  • the characteristic shown by the broken line L2 can be corrected as shown by the linear solid line L1 in FIG. 32. Further, the characteristic indicated by the broken line L3 can be corrected as shown by the linear solid line L1.
  • the linearity compensation process may be executed by the image processing circuit 164. Instead of converting the digital value by the table, the linearity may be compensated by multiplying the sensor output from the image processing circuit 164 by an appropriate coefficient.
  • FIG. 35 is a diagram for explaining the difference in linearity deviation for each imaging device or each camera system.
  • the broken line M1 shows an exemplary change in the output of the horizontal signal readout circuit 21 with respect to an increase in exposure for one imaging device or camera system
  • the broken line M2 relates to another imaging device or camera system.
  • the correction value calculated based on the data related to the light intensity-signal level characteristic can be prepared for each control potential VF.
  • the exposure is executed beyond the predetermined exposure time, or the control potential VF is set to a value that was not expected in advance.
  • the value of P13 when the value of P13 is not obtained in advance in the correction table of FIG. 39, the value of P13 can be calculated by linear interpolation from, for example, the correction value P11 and the correction value P12. Further, for example, a correction value for setting the control potential VF to a value that was not expected in advance can be calculated. For example, from P22, P23, P32 and P33, the correction value when the exposure amount is between t2 and t3 and the control potential VF is set to the value between Vb and Vc can be calculated ex post facto.
  • FIG. 41 schematically shows an outline of linearity compensation processing including interpolation processing.
  • the control circuit 160 may include an interpolation processing circuit 166 that performs such linear interpolation as a part thereof.
  • FIG. 42 is a schematic view showing a configuration example of the camera system 600.
  • the camera system 600 includes a lens optical system 601, an image pickup device 602, a system controller 603, and a camera signal processing unit 604.
  • the lens optical system 601 includes, for example, an autofocus lens, a zoom lens, and an aperture.
  • the lens optical system 601 collects light on the imaging surface of the imaging device 602.
  • the image pickup device 602 the image pickup device according to the first to tenth embodiments described above can be used.
  • the system controller 603 controls the entire camera system 600.
  • the system controller 603 can be realized, for example, by a microcomputer.
  • the camera signal processing unit 604 functions as a signal processing circuit that processes the output signal from the image pickup device 602.
  • the camera signal processing unit 604 performs processing such as color interpolation processing, spatial interpolation processing, and auto white balance.
  • the camera signal processing unit 604 can be realized by, for example, a DSP (Digital Signal Processor) or the like.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
PCT/JP2021/037712 2021-01-15 2021-10-12 撮像装置及びカメラシステム Ceased WO2022153628A1 (ja)

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CN202180087529.XA CN116711321A (zh) 2021-01-15 2021-10-12 摄像装置及相机系统
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