WO2022151728A1 - 一种氮化镓衬底及半导体复合衬底 - Google Patents

一种氮化镓衬底及半导体复合衬底 Download PDF

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WO2022151728A1
WO2022151728A1 PCT/CN2021/112383 CN2021112383W WO2022151728A1 WO 2022151728 A1 WO2022151728 A1 WO 2022151728A1 CN 2021112383 W CN2021112383 W CN 2021112383W WO 2022151728 A1 WO2022151728 A1 WO 2022151728A1
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substrate
threading dislocation
gan
gallium nitride
nitride substrate
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French (fr)
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徐俞
王建峰
徐科
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苏州纳维科技有限公司
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Priority to EP21918921.4A priority patent/EP4220728A1/en
Priority to US18/030,641 priority patent/US11881679B2/en
Publication of WO2022151728A1 publication Critical patent/WO2022151728A1/zh

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Definitions

  • the present invention relates to the technical field of semiconductors, and in particular, to a gallium nitride substrate with lower stress.
  • GaN As the core key material of the third-generation semiconductor industry, GaN has excellent properties such as extremely high electrical-optical conversion efficiency and low power consumption. It is the core foundation of the future generation of optoelectronics, power electronics and high-frequency microelectronics.
  • the metal Ga was placed in the 850°C temperature zone of the quartz tube, and the substrate was placed in the 1050°C temperature zone, and then ammonia gas NH3 and hydrogen chloride gas HCl as reactants were passed from the left end of the quartz tube into the 850°C temperature zone. , the following chemical reactions take place in this region:
  • the reactant GaCl gas obtained above is guided into a high temperature zone of 1050 °C by mixing N with an appropriate amount of H as a carrier gas, and reacts with NH:
  • GaCl(g)+NH 3 (g) GaN(s)+HCl(g)+H 2 (g) (1-2)
  • the characterization of the wave number difference at the peak of its micro-Raman scattering mapping is defined for the gallium nitride substrate, and it is considered that when the gallium nitride substrate satisfies the limited parameters in the patent, it can Reduce the stress of the gallium nitride substrate and effectively reduce the cracking and debris in the subsequent epitaxy process.
  • the periodic fluctuation of stress occurs only when the GaN substrate is prepared by patterned periodic epitaxial growth, and it is required to control the wavenumber difference at the peak of the micro-Raman scattering mapping to fluctuate within a certain range.
  • the GaN substrate prepared by epitaxial growth of aperiodic structure its stress must be controlled within a certain relatively small range.
  • the latest research shows that a large number of defects in the epitaxial GaN substrate mainly exist in the form of edge dislocations, screw dislocations, and mixed dislocations, where the component of edge dislocation or mixed dislocation in the horizontal direction (or called Lateral dislocation) is related to GaN internal stress (see Non-Patent Document 1 for details).
  • the purpose of the present invention is to propose a gallium nitride substrate, which needs to control lateral dislocations (that is, control two aspects: 1. edge dislocation or mixed dislocation density, 2. edge dislocation or Mixed dislocation tilt angle), reducing stress, thereby reducing cracking and debris during processing of GaN substrates or during epitaxy fabrication of related devices thereon.
  • the gallium nitride substrate has a surface with a diameter of not less than 100 mm, and the maximum value and the minimum value of the product of the threading dislocation density and the tangent of the threading dislocation inclination angle in the nine circular regions are equal to each other.
  • the quotient of the difference divided by the mean is not more than 40%.
  • the 8 surrounding positions are located on the same circumference and are divided into 8 equal parts along the circumference.
  • a semiconductor composite substrate with the above-mentioned gallium nitride substrate as a supporting substrate is also proposed.
  • Figure 1 shows the structure of a two-photon fluorescence microscope.
  • FIG. 3 shows a schematic diagram of the surface of the free-standing GaN substrate of the first embodiment.
  • 5a-5d are schematic diagrams of a method for preparing the free-standing GaN substrate of the first embodiment.
  • FIG. 6 is a schematic diagram of the structure of an epitaxial growth laser.
  • threading dislocations refer to edge dislocations, screw dislocations or mixed dislocations in the C-axis direction existing in the GaN substrate, and the dislocations are dislocations that pass through the interior of the GaN crystal and reach the surface of the GaN.
  • the threading dislocation density is the number of dislocations penetrating to the GaN surface within a certain surface area, and the unit is cm -2 (abbreviated as cm -2 ), which can be estimated by the following methods:
  • the GaN substrate is immersed in an acidic (H 3 PO 4 ) or alkaline (molten KOH) solution to corrode, and the dislocations are easily etched out pits, and the density of the etched pits on the GaN surface is the threading dislocation density;
  • the existing technology generally uses cathodoluminescence (CL) to test the GaN surface image. Since the dislocation position does not emit light, the image appears as a dark spot, and the calculated dark spot density is the threading dislocation density;
  • two-photon or multi-photon excitation photoluminescence images are used to test the GaN surface image (see Non-Patent Document 2).
  • a very short time about 10 -18 s
  • two long-wavelength photons are simultaneously absorbed, thereby transitioning from the ground state to the excited state. short photons.
  • Figure 1 shows the structure of the two-photon fluorescence microscope. Due to the requirement of high photon density, the lasers used in the two-photon fluorescence microscope are generally femtosecond pulsed lasers with high instantaneous power and low average power.
  • the imaging process of the two-photon fluorescence microscope is as follows: after the femtosecond pulsed laser 101 emits laser light, the beam is expanded by the beam expander 102 , and after passing through the dichroic mirror 103 , is focused on the surface of the sample 105 by the objective lens 104 . After the sample 105 is excited to fluoresce, it is reflected by the dichroic mirror 103 through the objective lens 104 and filtered by the filter 106. The fluorescence signal carrying the sample information is finally detected by the detector 107 to realize the imaging of the object. Two-photon imaging technology was used to study the evolution of dislocations within GaN.
  • dislocation lines appear as black lines on the two-photon image.
  • the dislocation density of the GaN material can be quantitatively obtained by calculating the number of black lines per unit area.
  • a three-dimensional three-dimensional map can be constructed, which opens up a way for us to intuitively observe the generation and evolution of dislocations in GaN.
  • Figure 2 is a two-photon excitation photoluminescence image of a typical free-standing GaN substrate.
  • (a) is the excitation photoluminescence image of its outermost surface
  • the black line in the figure is the threading dislocation. By calculating the density of the black line, the threading dislocation density can be obtained.
  • Figure (b) is an excitation photoluminescence image at a depth of 30 ⁇ m.
  • Figure (c) is a three-dimensional composite image. The images tested at different depths are synthesized to construct a three-dimensional image. The distribution of threading dislocations in the GaN substrate can be clearly seen. The main threading dislocations have a certain slope. The angle of the mixed dislocation, from which the threading dislocation tilt angle can be calculated.
  • FIG. 3 shows a schematic diagram of the surface of the free-standing GaN substrate of the first embodiment.
  • the diameter D of the self-supporting GaN substrate 2 is 50 mm (the diameter is the diameter of the dotted circle 24 when the reference edge 23 is not used in FIG. 3 ), and the concentric circle 25 with the dotted circle 24 is the dotted circle 24 on the outer periphery of the self-supporting GaN substrate 2 5mm inward circle.
  • 8 points 1-8 are equally divided, and the 8 points are combined with the 9th point (the center of the dotted circle 24).
  • the straight line where the points 5, 9, and 1 are located and the points 3, 9, and 7 The straight lines where they are located respectively form mutually orthogonal straight lines, and the straight line formed by the points 5 , 9 , and 1 is perpendicular to the reference edge 23 .
  • a circle with a diameter of 1 mm was constructed, and the multiphoton excitation photoluminescence image was carried out in the circle to measure the three-dimensional dislocation imaging image within a certain length, width and depth.
  • ⁇ /Ave[ ⁇ TD ⁇ D *tan( ⁇ ⁇ D )] ⁇ Max[ ⁇ TD ⁇ 1-9 *tan( ⁇ ⁇ 1-9 )]-Min[ ⁇ TD ⁇ 1-9 *tan( ⁇ ⁇ 1-9 )] ⁇ /Ave[ ⁇ TD ⁇ D *tan( ⁇ ⁇ D )].
  • the average value Ave[ ⁇ TD ⁇ 1 *tan( ⁇ ⁇ 1 )] of the product of the threading dislocation density and the threading dislocation tilt angle tangent value and the threading dislocation density and the threading dislocation tilt angle are used.
  • the quotient ⁇ /Ave[ ⁇ TD ⁇ 1 *tan( ⁇ ⁇ 1 )] of the difference between the maximum value and the minimum value of the product of the tangent value divided by the average value can characterize the defects of the gallium nitride substrate, which can be more It is close to the real situation of the internal stress of the gallium nitride substrate, especially, after the inventor's research, when the produced gallium nitride substrate is within a certain range of the values of the above two parameters, it has good epitaxial performance , the GaN substrate obtained by this or the epitaxial wafer prepared on the GaN substrate is not easy to crack and break.
  • the gallium nitride substrate has a surface with a diameter of not less than 50 mm, and nine circular regions with a diameter of 1 mm are taken on the surface. The regions are located at the center of the surface of the GaN substrate and eight surrounding locations.
  • the average value of the product of the threading dislocation density and the tangent of the threading dislocation tilt angle calculated in the multiphoton excitation photoluminescence spectra of the 9 circular regions is not greater than 1E6cm -2 , and the threading dislocation density is equal to The quotient of the difference between the maximum value and the minimum value of the product of the tangent value of the threading dislocation inclination angle divided by the average value is not more than 50%.
  • the gallium nitride substrate of the present invention further has a surface with a diameter of not less than 100 mm, and nine circular areas with a diameter of 1 mm are taken on the surface.
  • the average value of the product of the threading dislocation density calculated in the excitation photoluminescence spectrum and the tangent of the threading dislocation tilt angle is not greater than 5E5cm -2 . Further, the quotient of the difference between the maximum value and the minimum value divided by the average value of the product of the threading dislocation density and the tangent of the threading dislocation tilt angle of the nine circular regions is not more than 40%.
  • the present invention also proposes a semiconductor composite substrate prepared by an epitaxy process using the above-mentioned gallium nitride substrate as a supporting substrate.
  • a GaN thick film 22 with a certain thickness is first grown on the substrate 1 by HVPE method.
  • This process is epitaxial growth of aperiodic structures directly on the substrate, that is, a formula is used for a period of time in the growth process.
  • the substrate 1 selects a GaN template, sapphire, silicon carbide, silicon, and the like.
  • the preferred solution is to use a GaN template as a homogenous substrate for epitaxy, so that a better quality gallium nitride substrate can be obtained.
  • the GaN template can be obtained by using a metal organic chemical vapor deposition system to grow a GaN thin film 21 substrate with a thickness of >2 ⁇ m on sapphire, and the substrate is only screened for dislocation density or formed by electrochemical etching to form micro or nano columns surface without periodic mask structure.
  • the separated self-supporting GaN crystal 20 is processed into a specific circular shape with a reference edge 23, and the surface is flattened by plane grinding, and then the surface is polished to obtain the first embodiment.
  • the epitaxial growth of GaN on sapphire belongs to heteroepitaxy, and the low temperature buffer layer must be grown first, and then the high temperature layer must be grown.
  • Epitaxial growth of GaN on a substrate with a GaN layer belongs to homoepitaxy and can be directly grown at high temperature.
  • the excellent point of the preparation method in the above-mentioned embodiment is:
  • HVPE method because the biggest advantage of HVPE method over MOCVD is the fast growth rate. Generally, the growth rate of HVPE is 50-200um/h, and the growth rate of MOCVD is 0.5-5um/h. Therefore, in the process of heteroepitaxial growth, the growth mode of HVPE growth interface is relatively MOCVD is not easy to control, resulting in more severe bending of threading dislocations than MOCVD. Therefore, using the MOCVD-grown GaN template as the substrate is more conducive to the control of the inclination angle of threading dislocations in HVPE-grown GaN.
  • MOCVD-grown GaN templates with different dislocation densities can effectively control the threading dislocation density of HVPE-grown GaN.
  • the high growth rate is beneficial to the production efficiency of GaN thick films, but it also causes threading dislocations in GaN to tilt more easily.
  • Electrochemical etching of the GaN template grown by MOCVD can effectively reduce the threading dislocation density of the GaN thick film grown by HVPE.
  • the principle is that during electrochemical corrosion, the corrosion is first started from the place with dislocation defects. Therefore, after etching, micro- or nano-pillars are formed on the GaN template, and there are basically no dislocations in the micro- or nano-pillars.
  • the HVPE-grown GaN thick film on the bottom has low threading dislocation density.
  • Free-standing GaN substrate 2 has a diameter of not less than 100 mm.
  • the three-dimensional image of the successfully constructed self-supporting GaN substrate in which the dark lines actually measured will be displayed as bright lines, and the bright lines are threading dislocations. From this, the distribution of threading dislocations in the GaN substrate can be clearly seen, and the main threading dislocations are mixed dislocations with a certain tilt angle, from which the threading dislocation density and tilt angle can be calculated.
  • Substrate separation, shape processing or grinding and polishing and other processing and epitaxy preparation related device process evaluation :
  • MOCVD was used to epitaxially grow the laser structure, and the specific structure is shown in FIG. 6 .
  • trimethylgallium, trimethylaluminum, trimethylindium and magnesium dimethylocene are used as gallium, aluminum, indium, and magnesium source materials;
  • NH3 is used as nitrogen source material;
  • silane gas is used as doping source, and
  • H 2 is the carrier gas, which is passed into the cold-wall heating system to epitaxially grow the device structure on the self-supporting GaN substrate.
  • Tables 1.1 to 1.4 the surface conditions of the examples after epitaxial growth were observed, and the results are shown in Tables 1.1 to 1.4. Among them, cracks appeared on the surface of Example 8.
  • Substrate separation, shape processing or grinding and polishing and other processing and epitaxy preparation related device process evaluation :
  • the value of ⁇ ⁇ 1 within a 1 mm circle is relatively small.
  • the ⁇ in the local micro area is small, the micro stress in the local area is small, otherwise the stress in the local area increases with the tangent function of the ⁇ angle, and the local micro stress is large, which is easy to cause local cracking of GaN.
  • the inventors have found in long-term research that the difference between the maximum value and the minimum value of the product of the threading dislocation density and the tangent of the threading dislocation inclination angle is divided by the quotient of the average value (the quotient of the nine product values. Uniformity) must be controlled within 50%, so that the cracking of the GaN substrate can be effectively suppressed. Otherwise, even if there is no problem in the process of substrate separation, shape processing or grinding and polishing, the GaN substrate will still be cracked during the epitaxial preparation of related devices on the substrate, such as the preparation of laser epitaxial wafers.

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Abstract

本发明提出了一种氮化镓衬底，所述氮化镓衬底具有直径不小于50mm的表面，在该氮化镓衬底表面取9个直径1mm范围内的圆形区域，以多光子激发光致发光图谱对所述9个圆形区计算穿透位错密度与穿透位错倾斜角，该9个圆形区域中的穿透位错密度与穿透位错倾斜角的正切值的积的平均值不大于1E6cm -2，该9个圆形区域内穿透位错密度与穿透位错倾斜角的正切值的积的最大值与最小值的差值除以平均值的商不大于50％。本发明能降低氮化镓衬底的应力，使其在支撑其它外延层时，具有抑制开裂和碎片的效果。

Description

一种氮化镓衬底及半导体复合衬底 技术领域
本发明涉及半导体技术领域，尤其涉及一种具有较低应力的氮化镓衬底。
背景技术
GaN作为第三代半导体产业的核心关键材料，具备极高的电-光转换效率、低功耗等优异性能，是未来新一代光电子、功率电子和高频微电子的核心基础。
目前主流的制备自支撑GaN衬底的方法是氢化物气相外延法(HVPE)，该方法的所有反应是在HVPE设备的石英管中进行的，该反应设备中分为两个不同温度区域。
首先，将金属Ga放置在石英管的850℃温度区，衬底放置在1050℃温度区，之后将作为反应物的氨气NH 3和氯化氢气体HCl从石英管的左端先通入850℃温度区，该区域发生以下化学反应：
2Ga(l)+2HCl(g)＝2GaCl(g)+H 2(g)       (1-1)
上述得到的反应物GaCl气体通过混合适量H 2的N 2作为载气引导进入1050℃高温区，与NH 3发生反应：
GaCl(g)+NH 3(g)＝GaN(s)+HCl(g)+H 2(g)       (1-2)
这两个反应生成了GaN材料，构成了HVPE外延GaN的生长机制，产生的废气从石英管的一端排放到尾气管中。在高温区内放置适当的异质衬底(例如蓝宝石等)，GaN就可以实现在衬底上外延生长，生长到一定厚度后取出，再经过对衬底分离、外形加工、研磨抛光后获得自支撑衬底。
然而，异质外延生长过程中由于异质衬底与GaN之间存在晶格常数和热膨胀系数的差别(晶格失配和热失配)，因此在GaN衬底中产生多种晶体缺陷，这些缺陷将导致后续GaN加工或者在使用GaN衬底作为基底外延时， 容易产生碎片和开裂，带来不利。
为了解决上述问题，在CN106536794中，对氮化镓衬底限定了其微拉曼散射映射的波峰处的波数差值表征，并且认为当氮化镓衬底满足该专利中的限定参数时，能够降低氮化镓衬底的应力，有效减少后续外延工艺的开裂和碎片。
然而，采用图案化周期性外延生长制备GaN衬底时才会出现应力的周期起伏，才会要求控制微拉曼散射映射的波峰处的波数差值在一定范围内波动。对于非周期性结构外延生长制备的GaN衬底而言，一定是要控制其应力在某个特定的比较小的范围内。最新的研究显示，外延后的GaN衬底中的大量缺陷主要以刃位错、螺位错、混合位错的形式存在，其中刃位错或混合位错在水平方向上的分量(或者称为横向位错)与GaN内部应力有关(详细参见非专利文献1)。因此，通过控制位错密度和位错在水平方向上的分量，可以有效控制GaN内部应力，而单纯的使用微拉曼散射映射参数来表征氮化镓衬底，并不能完全代表氮化镓衬底中的缺陷形式，而且由于其分辨率有限(一般为0.1cm -1)，也不能很好的表征其内部比较小的应力。尤其是在一些器件外延过程中会产生很大应力的使用场合，比如GaN蓝光或绿光激光器的外延中，对于GaN衬底的要求更高，必须寻求更好的检测方法来控制GaN衬底内部应力，以适应更高的外延要求。
引用非专利文献：
[1]Foronda,H.M.；Romanov,A.E.；Young,E.C.；Roberston,C.A.；Beltz,G.E.；Speck,J.S.Curvature and bow of bulk GaN substrates.Journal of Applied Physics 2016,120(3)035104.
[2]Tanikawa,T.；Ohnishi,K.；Kanoh,M.；Mukai,T.；Matsuoka,T.Three-dimensional imaging of threading dislocations in GaN crystals using two-photon excitation photoluminescence.Applied Physics Express 2018,11(3)031004.。
发明内容
有鉴于此，本发明的目的在于提出一种氮化镓衬底，通过限定制备需要控 制横向位错(即控制2个方面：1、刃位错或混合位错密度，2、刃位错或混合位错的倾斜角度)，降低应力，从而降低GaN衬底加工过程或在其上外延制备相关器件过程中开裂和碎片。
为实现上述发明目的，本发明提供一种氮化镓衬底，所述氮化镓衬底具有直径不小于50mm的表面，在该氮化镓衬底表面取9个直径1mm范围内的圆形区域，所述9个圆形区域的位置分布再所述氮化镓衬底表面的中心位置和8个四周位置，以光子激发光致发光图谱对所述9个圆形区计算穿透位错密度与穿透位错倾斜角，该9个圆形区域中的穿透位错密度与穿透位错倾斜角的正切值的积的平均值不大于1E6cm -2，该9个圆形区域内穿透位错密度与穿透位错倾斜角的正切值的积的最大值与最小值的差值除以平均值的商不大于50％。
优选的，所述氮化镓衬底具有直径不小于100mm的表面，所述9个圆形区域中的穿透位错密度与穿透位错倾斜角的正切值的积的平均值不大于5E5cm -2。
优选的，所述氮化镓衬底具有直径不小于100mm的表面，所述9个圆形区域内穿透位错密度与穿透位错倾斜角的正切值的积的最大值与最小值的差值除以平均值的商不大于40％。
优选的，所述8个四周位置位于同一个圆周上，且沿该圆周8等分。
根据本发明的目的还提出了一种以上所述的氮化镓衬底作为支撑衬底的半导体复合衬底。
与现有技术相比，本发明的有益效果是：降低氮化镓衬底的应力，使其在支撑其它外延层时，具有抑制开裂和碎片的效果，从而提升半导体复合衬底的良率，降低成本。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明中记载的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1所示为双光子荧光显微镜的结构图。
图2是典型的自支撑GaN衬底的双光子激发光致发光图。
图3给出了第一实施例的自支撑GaN衬底表面示意图。
图4是2层晶体之间形成倾斜位错的示意图。
图5a-5d是制备第一实施例的自支撑GaN衬底的方法示意图。
图6是外延生长激光器结构示意图。
具体实施方式
下面结合各实施方式对本发明进行详细说明，但应当说明的是，这些实施方式并非对本发明的限制，本领域普通技术人员根据这些实施方式所作的功能、方法、或者结构上的等效变换或替代，均属于本发明的保护范围之内。
为了便于本发明的创新方案，先对本发明中的穿透位错密度表征方法做原理介绍。
通常，穿透位错是指GaN衬底中存在的C轴方向的刃位错、螺位错或者混合位错，该位错是穿过GaN晶体内部，到达GaN表面的位错。
穿透位错密度是在一定表面面积范围内穿透到GaN表面的位错数量，单位是个cm -2(简写为cm -2)，可以通过如下方法来评估：
将GaN衬底浸泡在酸性(H 3PO 4)或碱性(熔融KOH)溶液中腐蚀，位错的地方容易被腐蚀出坑，获得GaN表面腐蚀坑密度即为穿透位错密度；
现有的技术普遍采用阴极荧光(CL)来测试GaN表面图像，由于位错位置不发光，图像上表现为暗点，计算暗点密度即为穿透位错密度；
在本发明中，采用双光子或多光子激发光致发光图来测试GaN表面图像(参见非专利文献2)，它的基本原理是：在满足一定的高光子密度情况下，GaN中的电子能在极短时间内(约10 -18s)同时吸收两个长波长的光子，从而由基态跃迁到激发态，经过能量弛豫后，又从激发态再回到基态，并辐射出一个波长较短的光子。如图1所示为双光子荧光显微镜的结构图，由于需要满足高光子密度的条件，双光子荧光显微镜所用的激光器一般都是高瞬时 功率、低平均功率的飞秒脉冲激光器。双光子荧光显微镜成像过程如下：飞秒脉冲激光器101发出激光后，经扩束镜102扩束，通过二向色反射镜103后，被物镜104聚焦到样品105表面。样品105被激发出荧光后，再经物镜104，由二向色反射镜103反射，通过滤光片106过滤后，携带样品信息的荧光信号最终被探测器107检测到，实现对物体的成像。利用双光子成像技术，来研究GaN内部位错演变的情况。由于GaN内部的位错是非辐射复合中心，样品中存在穿透位错时，非平衡载流子由于非辐射复合而大量减少，位错中心无光子发出。因此，位错线在双光子所成图像上表现为黑线。通过计算单位面积上黑线的个数可以定量得出GaN材料的位错密度。此外，通过探测GaN材料内部不同深度下的双光子成像图还可构建三维立体图，这对我们直观观察GaN内位错的产生和演变开辟了道路。
图2是典型的自支撑GaN衬底的双光子激发光致发光图。如图所示，图2中，(a)图是其最表面的激发光致发光图，图中的黑线是穿透位错，通过计算黑线密度，可以获得穿透位错密度。(b)图是30μm深度下的激发光致发光图。(c)图是三维合成图，对不同深度测试的图像进行合成，构建其三维立体图像，可以清晰地看出GaN衬底中的穿透位错分布情况，主要穿透位错为具有一定倾斜角度的混合位错，由此可以计算穿透位错倾斜角度。
穿透位错倾斜角α Ф1、穿透位错密ρ TDФ1、穿透位错密度与穿透位错倾斜角正切值的积的平均值Ave[ρ TDФ1*tan(α Ф1)]、穿透位错密度与穿透位错倾斜角正切值的积的均匀性Δ/Ave[ρ TDФ1*tan(α Ф1)]计算方法：
图3给出了第一实施例的自支撑GaN衬底表面示意图。该自支撑GaN衬底2直径D为50mm(直径是图3中没用参考边23时的虚线圆24的直径)，与虚线圆24的同心圆25是自支撑GaN衬底2外周虚线圆24向内5mm的圆。在虚线圆24上等分取8个点1-8，该8个点与第9点(虚线圆24的中心)组合，其中，点5、9、1所在的直线和点3、9、7所在的直线分别形成相互正交的直线，并且点5、9、1组成的直线垂直于参考边23。以这9个点为圆心，构建直径1mm的圆，在该圆内进行多光子激发光致发光图，测定一定 长宽深范围内三维位错成像图。
在Ф1内部(直径1mm的圆内)，首先获得穿透位错密度ρ TDФ1；然后对获得的每一根穿透位错计算其倾斜角α，获得所有穿透位错倾斜角平均值α Ф1；
在ФD内部(直径50mm的圆内)，对9个位置做测试，分别获得9个点位置穿透位错密度与穿透位错倾斜角正切值的积ρ TDФ1*tan(α Ф1)，从而得到其平均值Ave[ρ TDФD*tan(α ФD)]，并进一步得到穿透位错密度与穿透位错倾斜角的正切值的积的最大值与最小值的差值除以平均值的商(9个积值的均匀性):
Δ/Ave[ρ TDΦD*tan(α ΦD)]＝{Max[ρ TDΦ1-9*tan(α Φ1-9)]-Min[ρ TDΦ1-9*tan(α Φ1-9)]}/Ave[ρ TDΦD*tan(α ΦD)]。
非专利文献1详细阐述了穿透位错对GaN晶体应力的影响：如图4所示，一个直的穿透位错在界面处发生弯折，弯折的角度为α，则在X方向上投影的位错长度为L＝htan(α)，其中h是上层GaN的厚度，α是穿透位错倾斜角度。GaN晶体整体平均应力
Figure PCTCN2021112383-appb-000001
其中b是位错伯克斯矢量，ρTD是穿透位错密度。由此可见GaN中的应力与穿透位错密度存在线性正比例关系，与穿透位错倾斜角存在正切函数关系(即角度增加，应力大幅度增加)。当GaN中局部存在穿透位错密度比较大或者穿透位错倾斜角比较大时，该局部区域就存在比较大的应力，当对HVPE生长的GaN晶体进行衬底分离、外形加工或研磨抛光过程中或者在该衬底上外延制备相关器件过程中，局部应力比较大的区域很可能出现GaN衬底开裂。当GaN中整体存在穿透位错密度比较大或者穿透位错倾斜角比较大时，整个样品存在比较大的应力，当对HVPE生长的GaN晶体进行衬底分离、外形加工或研磨抛光时或者在该衬底上外延生长器件结构时，整体应力比较大的情况下，很可能出现GaN衬底碎片。
因此在本发明中，使用穿透位错密度与穿透位错倾斜角正切值的积的平 均值Ave[ρ TDФ1*tan(α Ф1)]和穿透位错密度与穿透位错倾斜角正切值的积的最大值与最小值的差值除以平均值的商Δ/Ave[ρ TDФ1*tan(α Ф1)]这两个参数，对氮化镓衬底的缺陷进行表征，能够更加接近氮化镓衬底内部应力的真实情况，尤其是，经过发明人的研究，当生产得到的氮化镓衬底在上述两个参数的取值限定在一定范围内时，具有良好的外延性能，以此获得的GaN衬底或在GaN衬底上制备的外延片，不易开裂和破碎。
具体的，在本发明的一个实施例的一种GaN衬底，该氮化镓衬底具有直径不小于50mm表面，在表面上取9个直径1mm范围内的圆形区域，这9个圆形区域位于GaN衬底表面中心位置和8个四周位置。该9个圆形区域的多光子激发光致发光图谱中计算得到的穿透位错密度与穿透位错倾斜角的正切值的积的平均值不大于1E6cm -2，穿透位错密度与穿透位错倾斜角的正切值的积的最大值与最小值的差值除以平均值的商不大于50％。
作为一种优选的实施方式，本发明的氮化镓衬底进一步具有直径不小于100mm的表面，在表面上取9个直径1mm范围内的圆形区域，该9个圆形区域内的多光子激发光致发光图谱中计算得到的穿透位错密度与穿透位错倾斜角的正切值的积的平均值不大于5E5cm -2。进一步的，该9个圆形区域的穿透位错密度与穿透位错倾斜角的正切值的积的最大值与最小值的差值除以平均值的商不大于40％。
其中，该9个圆形区域中，位于边缘的8个圆形区域以8等分的方式分布于同一圆周上。
本发明还提出以上述氮化镓衬底作为支撑衬底，通过外延工艺制备得到的半导体复合衬底。
下面就本发明的GaN衬底的获取例举一种实施方式。需要注意的是，下述的制作方法，仅仅是得到该GaN衬底的一种较优方式，但并非本发明限定的制作该GaN的唯一方法，对于本领域技术人员而言，应当理解，通过其它技术手段得到的具有上述本发明限定的氮化镓衬底的特性的方案，也应当属于本发明的发明精神范围内。
参照图5a-5d的示意图，用于描述制备第一实施例的自支撑GaN衬底的示意方法：
如图5a所示，先在衬底1采用HVPE法生长一定厚度的GaN厚膜22，此过程是直接在衬底上非周期性结构外延生长，即该生长过程中采用一种配方持续一段时间外延生长。衬底1选择GaN模板、蓝宝石、碳化硅、硅等。其中优选的方案为采用GaN模板作为同质衬底进行外延，这样可以获得较优品质的氮化镓衬底。该GaN模板可以是采用金属有机化学气相沉积系统在蓝宝石上生长厚度>2μm的GaN薄膜21衬底来获取，并且对该衬底仅做位错密度筛选或通过电化学腐蚀形成了微米或纳米柱的表面，而不做周期性掩膜结构。
接下来，如图5b所示，将衬底1与GaN晶体20(包括GaN薄膜21和GaN厚膜22)分离，具体方案可以是激光剥离、机械研磨、化学腐蚀等；
接下来，如图5c所示，将分离后的自支撑GaN晶体20通过外形加工成具有参考边23的特定圆形，再平面研磨实现表面平坦化，然后进行表面抛光，从而获得第一实施例的自支撑GaN衬底2。
此外，如图5d所示，可以将自支撑GaN衬底2结合到异质衬底3表面，从而产生复合衬底32，异质衬底可以是蓝宝石、碳化硅、硅、氮化铝等。其结合的方法不受限制，可以采用金属键合、熔融键合等，优选金属键合。
在蓝宝石上外延生长GaN，属于异质外延，必须采用先生长低温缓冲层，然后再生长高温层。在有GaN层的衬底上外延生长GaN，属于同质外延，可以直接高温生长。而上述实施方式中的制备方法的优异点在于：
1、由于HVPE法相对于MOCVD最大的优势是生长速度快，一般情况下HVPE生长速度50-200um/h，MOCVD生长速度0.5-5um/h，因此异质外延生长过程中，HVPE生长界面生长模式相对MOCVD不容易控制，导致穿透位错弯曲程度比MOCVD严重。因此，采用MOCVD生长的GaN模板作为衬底，更有利于HVPE生长GaN中穿透位错的倾斜角度的控制。
2、采用不同位错密度的MOCVD生长的GaN模板，可以有效控制HVPE 生长GaN的穿透位错密度。
3、高的生长速度有利于GaN厚膜的产出效率，但是其也导致了GaN中穿透位错更容易出现倾斜。
4、将MOCVD生长的GaN模板通过电化学腐蚀方法，可以有效降低生长HVPE生长的GaN厚膜的穿透位错密度。其原理是电化学腐蚀时，首先从有位错缺陷的地方开始腐蚀，因此，腐蚀后GaN模板上形成了微米或纳米柱，该微米或纳米柱中基本没有位错，在没有位错的衬底上HVPE生长GaN厚膜穿透位错密度低。
综上所述，将1-4这4个技术手段结合到一起，有利用HVPE生长低穿透位错密度、小倾斜角度穿透位错的GaN厚膜，这样制备的自支撑GaN衬底应力比较小。从而抑制其加工过程或在其上外延制备相关器件过程中开裂和碎片。
第二实施例：
第二实施例与第一实施例不同点在于：
自支撑GaN衬底2具有不小于100mm的直径。
在Ф1内部(直径1mm的圆内)，首先获得穿透位错密度ρ TDФ1；然后对获得的每一根穿透位错计算其倾斜角α，获得所有穿透位错倾斜角平均值α Ф1；
在ФD内部(直径100mm的圆内)，对9个位置做测试，分别获得9个点位置穿透位错密度与穿透位错倾斜角正切值的积ρ TDФ1*tan(α Ф1)，其平均值Ave[ρ TDФD*tan(α ФD)]设置不大于5E5cm -2；穿透位错密度与穿透位错倾斜角的正切值的积的最大值与最小值的差值除以平均值的商(9个积值的均匀性)Δ/Ave[ρ TDФD*tan(α ФD)]设置不大于40％。
在第二实施例中，相比第一实施例，自支撑GaN衬底2的直径D较大，因此更容易出现开裂或碎片。在这种情况下，通过将Ave[ρ TDФD*tan(α ФD)]控制在不大于5E5cm -2、Δ/Ave[ρ TDФD*tan(α ФD)]控制在不大于40％，这样可以有效抑制GaN衬底开裂或碎片。除了以上不同之外，第二实施例与第一实施例 相同，不再赘述。
对比实施例1:
采用直径55mm的蓝宝石作为衬底，直接采用HVPE法生长GaN，具体方法如下：首先将蓝宝石衬底放置在管式电阻炉高温恒温区内，HCl气体通过一定比例的N 2/H 2混合气体作为载气，进入管式电阻炉低温恒温区(850度)，与金属镓反应生成GaCl气体，然后进入高温恒温区与NH 3气体反应后在衬底上生成GaN。首先设置高温恒温区为650度，生长约50-100nm的低温GaN缓冲层，然后再升高温度到1040度进一步生长约10小时，控制生长速率为低速率条件生长(<100um/h)，获得厚度约800μm的GaN厚膜。
然后通过激光剥离技术将衬底与GaN厚膜分离，将分离后的自支撑GaN晶体通过外形加工成具有参考边的特定圆形，再平面研磨实现表面平坦化，然后进行表面抛光，从而获得对比实施例1的自支撑GaN衬底，该衬底直径控制在50mm，厚度控制在400μm。
接来下，对该自支撑GaN衬底执行双光子激发光致发光测试。选用波长为700nm的脉冲飞秒激光器，脉冲持续时间100fs，频率10ns，具有较高的瞬时功率，物镜使用放大倍率为40倍水镜。测试一定范围内成像图。通过探测表面到内部几十μm深度范围的同一位置，并以每1μm采集一张图的测试步长，即可构建其三维立体图像。为方便观察，我们对三维图像的对比度进行反转。成功构建的自支撑GaN衬底三维立体图，其中实际测得的暗线会显示为亮线，亮线即为穿透位错。由此可以清晰地看出GaN衬底中的穿透位错分布情况，主要穿透位错为具有一定倾斜角度的混合位错，由此可以计算穿透位错密度和倾斜角度。
然后对该自支撑GaN衬底上9个点位置分别都测试双光子激发光致发光图，获得9个三维位错成像图。对每一个三维位错成像图进行计算，如表1.1至表1.4所示，首先获得穿透位错密度ρ TDФ1；然后，获得每一根穿透位错倾斜角α，计算所有穿透位错倾斜角平均值α Ф1；再对9个三维位错成像图数据进行统计分析，分别获得9个点位置穿透位错密度与穿透位错倾斜角正切 值的积ρ TDФ1*tan(α Ф1)，获得平均值Ave[ρ TDФD*tan(α ФD)]和穿透位错密度与穿透位错倾斜角的正切值的积的最大值与最小值的差值除以平均值的商(9个积值的均匀性)Δ/Ave[ρ TDФD*tan(α ФD)]。在表一中出示了其结果。
对比实施例2:
对比实施例2与对比实施例1不同点在于：HVPE生长GaN厚膜的生长速率控制为高速率条件生长(>150um/h)，1040度高温生长5小时获得厚度约800μm的GaN厚膜。除了以上不同之外，对比实施例2与对比实施例1相同，不再赘述。
对比实施例3:
对比实施例3与对比实施例1不同点在于：
(1)采用位错密度5E8cm -2的GaN模板作为衬底1；
(2)生长过程中直接采用高温1040度生长GaN厚膜，没有650度低温GaN缓冲层生长过程。除了以上不同之外，对比实施例3与对比实施例1相同，不再赘述。
对比实施例4与对比实施例2不同点在于：
(1)采用位错密度5E8cm -2的GaN模板作为衬底1；
(2)生长过程中直接采用高温1040度生长GaN厚膜，没有650度低温GaN缓冲层生长过程。除了以上不同之外，对比实施例4与对比实施例2相同，不再赘述。
对比实施例5与对比实施例3不同点在于：采用位错密度7E7cm -2的GaN模板作为衬底1，除了以上不同之外，对比实施例5与对比实施例3相同，不再赘述。
对比实施例6与对比实施例4不同点在于：采用位错密度7E7cm -2的GaN模板作为衬底1，除了以上不同之外，对比实施例6与对比实施例4相同，不再赘述。
对比实施例7与对比实施例3不同点在于：对衬底1先进行电化学腐蚀，详细见本公司原有专利CN102163545A，由于腐蚀是先从GaN模板的位错开 始的，因此，腐蚀后形成的GaN微米柱(纳米柱)中的位错密度极低，可以获得相对较低的穿透位错密度的GaN厚膜。除了以上不同之外，对比实施例7与对比实施例3相同，不再赘述。
对比实施例8与对比实施例4不同点在于：对衬底先进行电化学腐蚀，详细见本公司原有专利CN102163545A，由于腐蚀是先从GaN模板的位错开始的，因此，腐蚀后形成的GaN微米柱(纳米柱)中的位错密度极低，可以获得相对较低的穿透位错密度的GaN厚膜。除了以上不同之外，对比实施例8与对比实施例4相同，不再赘述。
对比实施例9与对比实施例5不同点在于：对衬底先进行电化学腐蚀，详细见本公司原有专利CN102163545A，由于腐蚀是先从GaN模板的位错开始的，因此，腐蚀后形成的GaN微米柱(纳米柱)中的位错密度极低，可以获得相对较低的穿透位错密度的GaN厚膜。除了以上不同之外，对比实施例9与对比实施例5相同，不再赘述。
对比实施例10与对比实施例6不同点在于：对衬底先进行电化学腐蚀，详细见本公司原有专利CN102163545A，由于腐蚀是先从GaN模板的位错开始的，因此，腐蚀后形成的GaN微米柱(纳米柱)中的位错密度极低，可以获得相对较低的穿透位错密度的GaN厚膜。除了以上不同之外，对比实施例10与对比实施例6相同，不再赘述。
衬底分离、外形加工或研磨抛光等加工过程及外延制备相关器件过程评估：
对上述实施例1-10进行评估，其中实施例1、2、4在加工过程中已经出现碎裂；实施例3、6在加工过程中已经出现开裂(出现碎裂或开裂不影响测试，但不再投入到外延制备相关器件)。这里，开裂是指裂纹数量小于3条，碎裂是指裂纹数量大于等于3条。
对实施例5、7、8、9、10采用MOCVD进行外延生长激光器结构，具体结构如图6所示。该生长条件采用三甲基镓、三甲基铝、三甲基铟和二茂镁作为镓、铝、铟、镁源材料；采用NH 3作为氮源材料；采用硅烷气体作为 掺杂源，以H 2为载气，通入冷壁加热系统中，在自支撑GaN衬底上外延生长器件结构。然后观察外延生长后实施例的表面情况，其结果如表1.1至表1.4所示。其中实施例8表面出现开裂现象。从以上结果来看，Ave[ρ TDФD*tan(α ФD)]>1E6cm -2的自支撑GaN衬底2整体应力比较大，容易在加工过程中就出现碎裂；Δ/Ave[ρ TDФD*tan(α ФD)]>50％的自支撑GaN衬底2局部应力比较大，容易在加工过程中出现开裂，即使加工过程不开裂，进一步外延相关器件后也容易出现开裂。
对比实施例11:
基于对直径50mm的GaN衬底的控制情况(对比实施例1-10)，制备不小于直径100mm的GaN衬底时，不再采取1-4，6，8方案。本实施例采用直径105mm、位错密度7E7cm -2的GaN模板作为衬底1，直接采用HVPE法生长GaN厚膜，其生长方法与对比实施例5类似，不同点是生长厚度控制约1000μm的GaN厚膜。然后通过激光剥离技术将衬底与GaN厚膜分离，将分离后的自支撑GaN晶体通过外形加工成具有参考边的特定圆形，再平面研磨实现表面平坦化，然后进行表面抛光，从而获得对比实施例11的自支撑GaN衬底，该衬底直径控制在100mm，厚度控制在600μm。
接来下，对该自支撑GaN衬底执行双光子激发光致发光测试。测试方法与对比实施例1相同，然后对该自支撑GaN衬底上9个点位置分别都测试双光子激发光致发光图，获得9个三维位错成像图。对每一个三维位错成像图进行计算，如表2.1至表2.2所示，首先获得穿透位错密度ρ TDФ1；然后，获得每一根穿透位错倾斜角α，计算所有穿透位错倾斜角平均值α Ф1；再对9个三维位错成像图数据进行统计分析，分别获得9个点位置穿透位错密度与穿透位错倾斜角正切值的积ρ TDФ1*tan(α Ф1)，获得平均值Ave[ρ TDФD*tan(α ФD)]和穿透位错密度与穿透位错倾斜角的正切值的积的最大值与最小值的差值除以平均值的商(9个积值的均匀性)Δ/Ave[ρ TDФD*tan(α ФD)]。表2.1至表2.2出示实施例11-14的结果。
对比实施例12:
对比实施例12与对比实施例11不同点在于：采用位错密度5E8cm -2的GaN模板作为衬底1，对衬底1先进行电化学腐蚀，详细见本公司原有专利CN102163545A，由于腐蚀是先从GaN模板的位错开始的，因此，腐蚀后形成的GaN微米柱(纳米柱)中的位错密度极低，可以获得相对较低的穿透位错密度的GaN厚膜。除了以上不同之外，对比实施例12与对比实施例11相同，不再赘述。
对比实施例13:
对比实施例13与对比实施例12不同点在于：采用位错密度7E7cm -2的GaN模板作为衬底1，除了以上不同之外，对比实施例13与对比实施例12相同，不再赘述。
对比实施例14:
对比实施例14与对比实施例13不同点在于：HVPE生长GaN厚膜的生长速率控制为高速率条件生长(>150um/h)，1040度高温生长6小时多，获得厚度约1000μm的GaN厚膜。除了以上不同之外，对比实施例14与对比实施例13相同，不再赘述。
衬底分离、外形加工或研磨抛光等加工过程及外延制备相关器件过程评估：
对上述实施例11-14进行评估，其中实施例11在加工过程中已经出现碎裂；实施例14在加工过程中已经出现开裂(出现碎裂或开裂不影响测试，但不再投入到外延制备相关器件)。
对实施例12、13采用MOCVD进行外延生长激光器结构，具体结构如图6所示。该生长条件采用三甲基镓、三甲基铝、三甲基铟和二茂镁作为镓、铝、铟、镁源材料；采用NH 3作为氮源材料；采用硅烷气体作为掺杂源，以H 2为载气，通入冷壁加热系统中，在自支撑GaN衬底上外延生长器件结构。然后观察外延生长后实施例的表面情况，其结果如表2.1至表2.2所示。其中实施例12表面出现开裂现象。从以上结果来看，Ave[ρ TDФD*tan(α ФD)]>5E5cm -2的自支撑GaN衬底2整体应力比较大，容易在加工过程中就出现碎裂； Δ/Ave[ρ TDФD*tan(α ФD)]>40％的自支撑GaN衬底2局部应力比较大，容易在加工过程中出现开裂，即使加工过程不开裂，进一步外延相关器件后也容易出现开裂。
Figure PCTCN2021112383-appb-000002
表1.1
Figure PCTCN2021112383-appb-000003
表1.2
Figure PCTCN2021112383-appb-000004
表1.3
Figure PCTCN2021112383-appb-000005
表1.4
Figure PCTCN2021112383-appb-000006
表2.1
Figure PCTCN2021112383-appb-000007
表2.2
上述实施例中，开裂是指自支撑GaN衬底内部出现裂纹，但没有达到将衬底分成2块或多块的情况，该裂纹可以是自支撑GaN衬底内部没有上下表面穿透的裂纹，也可以是上下表面穿透的裂纹，定义为裸眼可见裂纹；
碎片是指自支撑GaN衬底出现裂纹，且将自支撑GaN衬底分成至少2块以上的情况。
可见，在第一实施例中，自支撑GaN衬底的9个点位置穿透位错密度与穿透位错倾斜角正切值的积ρ TDФ1*tan(α Ф1)，其平均值Ave[ρ TDФD*tan(α ФD)]设置不大于1E6cm -2，因此，自支撑GaN衬底2穿透位错所导致的宏观应力比较小，可以有效抑制衬底分离、外形加工或研磨抛光过程中或者在该衬底上外延制备相关器件过程中出现的GaN衬底碎片。穿透位错密度与穿透位错倾斜角的正切值的积的最大值与最小值的差值除以平均值的商(9个积值的均匀性)Δ/Ave[ρ TDФD*tan(α ФD)]设置不大于50％。因此，自支撑GaN衬底2穿透位错所导致的微观应力比较小，从而可以实现更加均匀的微观应力分布。可以有效抑制衬底分离、外形加工或研磨抛光过程中或者在该衬底上外延制备相关器件过程中出现的GaN衬底开裂。应该注意，更优选的是，在1mm圆内的α Ф1的值比较小。局部微区范围内的α在较小的情况下，局部区域微观应力就小，否则局部范围内应力随α角呈正切函数上升，局部的微观应力大容易造成GaN局部开裂。另外，本发明人在长期的研究中发现，穿透位错密度与穿透位错倾斜角的正切值的积的最大值与最小值的差值除以平均值的商(9个积值的均匀性)必须控制在50％以内，这样才能有效抑制GaN衬底开裂。否则，即使衬底分离、外形加工或研磨抛光过程中没有问题，在该衬底上外延制备相关器件过程中，例如制备激光器外延片过程中，仍然会出现GaN衬底开裂。
对于本领域技术人员而言，显然本发明不限于上述示范性实施例的细节，而且在不背离本发明的精神或基本特征的情况下，能够以其他的具体形式实现本发明。因此，无论从哪一点来看，均应将实施例看作是示范性的，而且是非限制性的，本发明的范围由所附权利要求而不是上述说明限定，因此旨在将落 在权利要求的等同要件的含义和范围内的所有变化囊括在本发明内。
此外，应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施例中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。

Claims (5)

  1. 一种氮化镓衬底，其特征在于：所述氮化镓衬底通过非周期性结构外延生长所得，所述氮化镓衬底具有直径不小于50mm的表面，在该氮化镓衬底表面取9个直径1mm范围内的圆形区域，9个所述圆形区域的位置分别分布在所述氮化镓衬底表面的中心位置和8个四周位置，以多光子激发光致发光图谱对所述9个圆形区域计算穿透位错密度与穿透位错倾斜角，该9个圆形区域中的穿透位错密度与穿透位错倾斜角的正切值的积的平均值不大于1E6cm -2，该9个圆形区域内穿透位错密度与穿透位错倾斜角的正切值的积的最大值与最小值的差值除以平均值的商不大于50％。
  2. 如权利要求1所述的氮化镓衬底，其特征在于：所述氮化镓衬底具有直径不小于100mm的表面，所述9个圆形区域中的穿透位错密度与穿透位错倾斜角的正切值的积的平均值不大于5E5cm -2。
  3. 如权利要求1所述的氮化镓衬底，其特征在于：所述氮化镓衬底具有直径不小于100mm的表面，所述9个圆形区域内穿透位错密度与穿透位错倾斜角的正切值的积的最大值与最小值的差值除以平均值的商不大于40％。
  4. 如权利要求1所述的氮化镓衬底，其特征在于：所述8个四周位置位于同一个圆周上，且沿该圆周8等分。
  5. 一种以权利要求1-4任意一项所述的氮化镓衬底作为支撑衬底的半导体复合衬底。
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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112397571B (zh) * 2021-01-18 2021-04-23 苏州纳维科技有限公司 一种氮化镓衬底及半导体复合衬底
CN114220740B (zh) * 2022-02-22 2022-05-13 苏州浪潮智能科技有限公司 一种氮化镓衬底剥离方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1894446A (zh) * 2003-11-13 2007-01-10 克利公司 大面积、均匀低位错密度GaN衬底及其制造工艺
CN101447542A (zh) * 2007-11-30 2009-06-03 住友电气工业株式会社 第ⅲ族氮化物晶体衬底、发光器件及其制造方法
CN102163545A (zh) 2011-03-18 2011-08-24 苏州纳维科技有限公司 微柱阵列的制备方法、阵列结构及生长晶体材料的方法
CN106536794A (zh) 2014-07-24 2017-03-22 住友电气工业株式会社 氮化镓衬底
CN112397571A (zh) * 2021-01-18 2021-02-23 苏州纳维科技有限公司 一种氮化镓衬底及半导体复合衬底

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4145437B2 (ja) * 1999-09-28 2008-09-03 住友電気工業株式会社 単結晶ＧａＮの結晶成長方法及び単結晶ＧａＮ基板の製造方法と単結晶ＧａＮ基板
JP4432180B2 (ja) * 1999-12-24 2010-03-17 豊田合成株式会社 Ｉｉｉ族窒化物系化合物半導体の製造方法、ｉｉｉ族窒化物系化合物半導体素子及びｉｉｉ族窒化物系化合物半導体
JP2001313259A (ja) * 2000-04-28 2001-11-09 Toyoda Gosei Co Ltd Ｉｉｉ族窒化物系化合物半導体基板の製造方法及び半導体素子
JP4229005B2 (ja) * 2003-06-26 2009-02-25 住友電気工業株式会社 ＧａＮ基板及びその製造方法、並びに窒化物半導体素子
JP5082278B2 (ja) * 2005-05-16 2012-11-28 ソニー株式会社 発光ダイオードの製造方法、集積型発光ダイオードの製造方法および窒化物系ｉｉｉ−ｖ族化合物半導体の成長方法
JP2010184833A (ja) * 2009-02-12 2010-08-26 Denso Corp 炭化珪素単結晶基板および炭化珪素単結晶エピタキシャルウェハ
JP4786730B2 (ja) * 2009-05-28 2011-10-05 シャープ株式会社 電界効果型トランジスタおよびその製造方法
JP6106932B2 (ja) * 2012-03-19 2017-04-05 株式会社リコー １３族窒化物結晶、及び１３族窒化物結晶基板
KR102140789B1 (ko) * 2014-02-17 2020-08-03 삼성전자주식회사 결정 품질 평가장치, 및 그것을 포함한 반도체 발광소자의 제조 장치 및 제조 방법
EP2947045B1 (en) * 2014-05-19 2019-08-28 IMEC vzw Low defect-density vertical nanowire semiconductor structures and method for making such structures
JP6269368B2 (ja) * 2014-07-24 2018-01-31 住友電気工業株式会社 窒化ガリウム基板
JP7063736B2 (ja) * 2018-06-13 2022-05-09 株式会社サイオクス 窒化物結晶基板の製造方法
JP6984571B2 (ja) * 2018-09-25 2021-12-22 豊田合成株式会社 半導体装置の製造方法
CN113454272B (zh) * 2019-02-22 2024-03-08 三菱化学株式会社 GaN结晶和基板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1894446A (zh) * 2003-11-13 2007-01-10 克利公司 大面积、均匀低位错密度GaN衬底及其制造工艺
CN101447542A (zh) * 2007-11-30 2009-06-03 住友电气工业株式会社 第ⅲ族氮化物晶体衬底、发光器件及其制造方法
CN102163545A (zh) 2011-03-18 2011-08-24 苏州纳维科技有限公司 微柱阵列的制备方法、阵列结构及生长晶体材料的方法
CN106536794A (zh) 2014-07-24 2017-03-22 住友电气工业株式会社 氮化镓衬底
CN112397571A (zh) * 2021-01-18 2021-02-23 苏州纳维科技有限公司 一种氮化镓衬底及半导体复合衬底

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
FORONDA, H. M.ROMANOV, A. E.YOUNG, E. C.ROBERSTON, C. A.BELTZ, G. E.SPECK, J. S.: "Curvature and bow of bulk GaN substrates", JOURNAL OF APPLIED PHYSICS, vol. 120, no. 3, 2016, pages 035104, XP012210446, DOI: 10.1063/1.4959073
TANIKAWA, T.OHNISHI, K.KANOH, M.MUKAI, T.MATSUOKA, T.: "Three-dimensional imaging of threading dislocations in GaN crystals using two-photon excitation photoluminescence", APPLIED PHYSICS EXPRESS, vol. 11, no. 3, 2018, pages 031004

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