WO2022118633A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2022118633A1 WO2022118633A1 PCT/JP2021/041692 JP2021041692W WO2022118633A1 WO 2022118633 A1 WO2022118633 A1 WO 2022118633A1 JP 2021041692 W JP2021041692 W JP 2021041692W WO 2022118633 A1 WO2022118633 A1 WO 2022118633A1
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- Prior art keywords
- wiring layer
- electrode
- main surface
- gate
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 318
- 239000000758 substrate Substances 0.000 claims abstract description 86
- 238000001514 detection method Methods 0.000 claims description 126
- 238000000605 extraction Methods 0.000 claims description 50
- 229920005989 resin Polymers 0.000 claims description 45
- 239000011347 resin Substances 0.000 claims description 45
- 238000007789 sealing Methods 0.000 claims description 45
- 239000003990 capacitor Substances 0.000 claims description 14
- 239000010410 layer Substances 0.000 description 295
- 239000010949 copper Substances 0.000 description 22
- 239000000463 material Substances 0.000 description 22
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 21
- 229910052802 copper Inorganic materials 0.000 description 21
- 229910000881 Cu alloy Inorganic materials 0.000 description 17
- 229910052751 metal Inorganic materials 0.000 description 16
- 239000002184 metal Substances 0.000 description 16
- 238000007747 plating Methods 0.000 description 12
- 239000011241 protective layer Substances 0.000 description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 9
- 239000000203 mixture Substances 0.000 description 9
- 239000010931 gold Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003985 ceramic capacitor Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
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- H—ELECTRICITY
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
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Definitions
- the present disclosure relates to a semiconductor device, and more particularly to a semiconductor device including a plurality of semiconductor elements.
- Patent Document 1 discloses an example of such a semiconductor device.
- two wiring layers metal patterns 4a and 4b
- three wiring relay regions are arranged on the surface of the insulating substrate.
- Each wiring layer and each wiring relay region constitutes a conductive path of the semiconductor device.
- a heat sink is attached to the back surface of the insulating substrate via a third metal pattern.
- the above-mentioned conventional semiconductor device has a parasitic capacitance between a specific wiring relay area and a heat sink. In this case, if the voltage change is remarkable in the wiring relay region, a leakage current from the heat sink is generated thereby. Depending on the magnitude of the leakage current, there is concern about the adverse effect of noise around the semiconductor device. Therefore, a measure for suppressing the leakage current from the semiconductor device is desired.
- one object of the present disclosure is to provide a semiconductor device capable of reducing noise caused by leakage current.
- the semiconductor device provided by the present disclosure includes a substrate having a main surface facing the thickness direction, a first wiring layer arranged on the main surface, and the semiconductor device arranged on the main surface and with respect to the thickness direction. It has a second wiring layer separated from the first wiring layer in the first orthogonal direction, and a first main surface electrode and a first back surface electrode located on opposite sides in the thickness direction, and the first back surface electrode. Has a first semiconductor element bonded to the first wiring layer, a second main surface electrode and a second back surface electrode located on opposite sides in the thickness direction, and the second back surface electrode is the second back surface electrode.
- the substrate includes an exposed portion located between the first wiring layer and the second wiring layer, and the conductive member overlaps the exposed portion when viewed in the thickness direction.
- FIG. 1 It is a top view of the semiconductor device which concerns on 1st Embodiment. It is a plan view corresponding to FIG. 1, and is transparent to the sealing resin. It is a plan view corresponding to FIG. 2, and is further transmitted through the conductive member and the output terminal. It is a bottom view of the semiconductor device shown in FIG. 1. It is sectional drawing which follows the VV line of FIG. It is sectional drawing which follows the VI-VI line of FIG. FIG. 2 is a cross-sectional view taken along the line VII-VII of FIG. FIG. 2 is a cross-sectional view taken along the line VIII-VIII of FIG. It is a partially enlarged view of FIG. 9 is a cross-sectional view taken along the line XX of FIG.
- FIG. 9 is a cross-sectional view taken along the line XI-XI of FIG. 9 is a cross-sectional view taken along the line XII-XII of FIG.
- FIG. 7 is a partially enlarged view of FIG. 7. It is a partially enlarged view of FIG. It is a partially enlarged plan view of the semiconductor device which concerns on 2nd Embodiment, and is transmitted through a sealing resin. It is sectional drawing which follows the XVI-XVI line of FIG. It is sectional drawing which follows the XVII-XVII line of FIG. It is sectional drawing which follows the XVIII-XVIII line of FIG.
- FIG. 2 is a cross-sectional view taken along the line XXII-XXII of FIG.
- FIG. 2 is a cross-sectional view taken along the line XXIII-XXIII of FIG.
- the semiconductor device A10 includes a substrate 11, a first wiring layer 12, a second wiring layer 13, a first semiconductor element 21, a second semiconductor element 22, a pair of diodes 23, a capacitor 24, a conductive member 30, a first input terminal 41, and the like. It includes a second input terminal 42, an output terminal 43, a sealing resin 60, and a heat sink 70. Further, the semiconductor device A10 includes a first gate wiring layer 141, a second gate wiring layer 142, a first detection wiring layer 151, a second detection wiring layer 152, a second gate electrode extraction layer 162, a back surface electrode extraction layer 17, and a first.
- the sealing resin 60 is transmitted.
- the conductive member 30 and the output terminal 43 are further transmitted to FIG. 2.
- the permeated sealing resin 60 is shown by an imaginary line (dashed-dotted line).
- the transmitted conductive member 30 and the output terminal 43 are shown by imaginary lines.
- the direction orthogonal to the main surface 111 (described later) of the substrate 11 is referred to as "thickness direction z".
- the thickness direction z corresponds to, for example, the thickness direction of each of the first wiring layer 12 and the second wiring layer 13.
- One direction orthogonal to the thickness direction z is called “first direction x”.
- the direction orthogonal to both the thickness direction z and the first direction x is referred to as a "second direction y".
- the semiconductor device A10 converts the DC power supply voltage applied to the first input terminal 41 and the second input terminal 42 into AC power by the first semiconductor element 21 and the second semiconductor element 22.
- the converted AC power is input from the output terminal 43 to a power supply target such as a motor.
- the semiconductor device A10 forms a part of a power conversion circuit such as an inverter.
- the substrate 11 has a first wiring layer 12, a second wiring layer 13, a first gate wiring layer 141, a second gate wiring layer 142, a first detection wiring layer 151, and a second detection. It supports the wiring layer 152, the second gate electrode extraction layer 162, the back surface electrode extraction layer 17, and the sealing resin 60. Further, as shown in FIGS. 7 and 8, the substrate 11 supports the first gate terminal 441, the second gate terminal 442, the first detection terminal 451 and the second detection terminal 452.
- the substrate 11 has electrical insulation. Further, the constituent material of the substrate 11 preferably has a relatively large thermal conductivity.
- the substrate 11 is made of ceramics, and the ceramics are, for example, aluminum nitride (AlN).
- the substrate 11 has a main surface 111 and a back surface 112 separated from each other in the thickness direction z, and the back surface 112 faces the side opposite to the main surface 111. As shown in FIGS. 5 to 8, the main surface 111 is in contact with the sealing resin 60. The back surface 112 is exposed from the sealing resin 60.
- the first wiring layer 12 is arranged on the main surface 111 of the substrate 11 as shown in FIGS. 2, 3 and 7.
- the first wiring layer 12 includes a first semiconductor element 21 and one of the pair of diodes 23, the diode 23.
- the first wiring layer 12 is made of a material containing copper (Cu) or a copper alloy. Seen in the thickness direction z, the first wiring layer 12 has a rectangular shape with the second direction y as a long side. The first wiring layer 12 is located inward of the peripheral edge of the substrate 11 when viewed in the thickness direction z.
- the second wiring layer 13 is arranged on the main surface 111 of the substrate 11 as shown in FIGS. 2, 3 and 8.
- the second wiring layer 13 mounts the second semiconductor element 22 and the other diode 23 of the pair of diodes 23.
- the second wiring layer 13 is made of a material containing copper or a copper alloy.
- the second wiring layer 13 is separated from the first wiring layer 12 in the first direction x. When viewed in the thickness direction z, the second wiring layer 13 has a long side in the second direction y, and the side where the second gate wiring layer 142 and the second detection wiring layer 152 are located is cut out in the first direction x. It has a rectangular shape.
- the second wiring layer 13 is located inward of the peripheral edge of the substrate 11 when viewed in the thickness direction z.
- the thickness of each of the first wiring layer 12 and the second wiring layer 13 is larger than the thickness of the substrate 11.
- the substrate 11 includes an exposed portion 11A located between the first wiring layer 12 and the second wiring layer 13 in the thickness direction z.
- the exposed portion 11A extends along the second direction y.
- the first semiconductor element 21 is bonded to the first wiring layer 12 as shown in FIGS. 2, 3 and 5.
- the first semiconductor element 21 is, for example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).
- each of the first semiconductor elements 21 may be a field effect transistor including a MISFET (Metal-Insulator-Semiconductor Field-Effect Transistor) or a bipolar transistor such as an IGBT (Insulated Gate Bipolar Transistor).
- the first semiconductor element 21 includes a compound semiconductor substrate.
- the composition of the compound semiconductor substrate contains silicon carbide (SiC). That is, the compound semiconductor substrate contains silicon carbide (SiC).
- SiC silicon carbide
- the first semiconductor element 21 has a first back surface electrode 211, a first main surface electrode 212, and a first gate electrode 213.
- the first back surface electrode 211 is provided so as to face the first wiring layer 12. A current corresponding to the electric power converted by the first semiconductor element 21 flows through the first back surface electrode 211. That is, the first back surface electrode 211 corresponds to the drain electrode of the first semiconductor element 21.
- the first back surface electrode 211 is bonded to the first wiring layer 12 by the first bonding layer 25.
- the first bonding layer 25 has conductivity.
- the first bonding layer 25 is, for example, lead-free solder.
- the first bonding layer 25 may be a sintered metal containing silver (Ag) or the like. As a result, the first back surface electrode 211 is conductive to the first wiring layer 12.
- the first main surface electrode 212 is provided on the side facing the main surface 111 of the substrate 11 in the thickness direction z. Therefore, the first back surface electrode 211 and the first main surface electrode 212 are located on opposite sides in the thickness direction z. A current corresponding to the electric power converted by the first semiconductor element 21 flows through the first main surface electrode 212. That is, the first main surface electrode 212 corresponds to the source electrode of the first semiconductor element 21.
- the first main surface electrode 212 includes a plurality of metal plating layers.
- the first main surface electrode 212 includes a nickel (Ni) plating layer and a gold (Au) plating layer laminated on the nickel plating layer.
- the first main surface electrode 212 includes a nickel plating layer, a palladium (Pd) plating layer laminated on the nickel plating layer, and a gold plating layer laminated on the palladium plating layer. But it may be.
- the first gate electrode 213 is located on the same side as the first main surface electrode 212 in the thickness direction z.
- a gate voltage for driving the first semiconductor element 21 is applied to the first gate electrode 213.
- the first semiconductor element 21 converts a current corresponding to the voltage applied to the first back surface electrode 211 based on the gate voltage.
- the area of the first gate electrode 213 is smaller than the area of the first main surface electrode 212 when viewed in the thickness direction z.
- the second semiconductor element 22 is bonded to the second wiring layer 13 as shown in FIGS. 2, 3 and 5.
- the second semiconductor element 22 is a transistor of the same type as the first semiconductor element 21. Therefore, in the semiconductor device A10, the second semiconductor element 22 is a MOSFET.
- the second semiconductor element 22 has a second back surface electrode 221, a second main surface electrode 222, and a second gate electrode 223.
- the second back surface electrode 221 is provided so as to face the second wiring layer 13. A current corresponding to the electric power converted by the second semiconductor element 22 flows through the second back surface electrode 221. That is, the second back surface electrode 221 corresponds to the source electrode of the second semiconductor element 22.
- the second back surface electrode 221 is bonded to the second wiring layer 13 by the first bonding layer 25. As a result, the second back surface electrode 221 is conductive to the second wiring layer 13.
- the second main surface electrode 222 is provided on the side facing the main surface 111 of the substrate 11 in the thickness direction z. Therefore, the second back surface electrode 221 and the second main surface electrode 222 are located on opposite sides in the thickness direction z. A current corresponding to the electric power converted by the second semiconductor element 22 flows through the second main surface electrode 222. That is, the second main surface electrode 222 corresponds to the drain electrode of the second semiconductor element 22.
- the second main surface electrode 222 includes a plurality of metal plating layers like the first main surface electrode 212 of the first semiconductor element 21. The configuration of the plurality of metal plating layers is the same as the configuration of the plurality of metal plating layers included in the first main surface electrode 212.
- the second gate electrode 223 is located on the same side as the second back surface electrode 221 in the thickness direction z.
- a gate voltage for driving the second semiconductor element 22 is applied to the second gate electrode 223.
- the current corresponding to the voltage applied to the second main surface electrode 222 is converted based on the gate voltage.
- the area of the second gate electrode 223 is smaller than the area of the second back surface electrode 221 when viewed in the thickness direction z.
- the structure of the second semiconductor element 22 is the same as the structure when the first semiconductor element 21 is inverted in a direction orthogonal to the thickness direction z. That is, the second semiconductor element 22 is obtained by flip-chip bonding the first semiconductor element 21 to the second wiring layer 13.
- the polarities of the first main surface electrode 212 of the first semiconductor element 21 and the second main surface electrode 222 of the second semiconductor element 22 are different from each other.
- the pair of diodes 23 are individually bonded to the first wiring layer 12 and the second wiring layer 13.
- the pair of diodes 23 includes a first diode 23A and a second diode 23B.
- the first diode 23A is bonded to the first wiring layer 12.
- the second diode 23B is bonded to the second wiring layer 13.
- the pair of diodes 23 are, for example, Schottky barrier diodes.
- the first diode 23A is connected in parallel to the first semiconductor element 21.
- the second diode 23B is connected in parallel to the second semiconductor element 22.
- each of the pair of diodes 23 When a reverse bias is applied to at least one of the first semiconductor element 21 and the second semiconductor element 22, the pair of diodes 23 are not for each of the first semiconductor element 21 and the second semiconductor element 22, but for them. It is a so-called freewheeling diode in which a current is passed through the diode 23 connected in parallel. As shown in FIGS. 13 and 14, each of the pair of diodes 23 has an anode electrode 231 and a cathode electrode 232. The anode electrode 231 and the cathode electrode 232 are located opposite to each other in the thickness direction z.
- each of the first semiconductor element 21 and the second semiconductor element 22 is a MOSFET
- a diode instead of the pair of diodes 23 is built in each of the first semiconductor element 21 and the second semiconductor element 22. You may. In this case, the pair of diodes 23 becomes unnecessary.
- the cathode electrode 232 of the first diode 23A is provided so as to face the first wiring layer 12.
- the cathode electrode 232 of the first diode 23A is bonded to the first wiring layer 12 by the first bonding layer 25.
- the cathode electrode 232 of the first diode 23A is conducting to the first wiring layer 12.
- the cathode electrode 232 is provided on the side facing the main surface 111 of the substrate 11 in the thickness direction z. Therefore, the anode electrode 231 of the second diode 23B is provided so as to face the second wiring layer 13.
- the anode electrode 231 of the second diode 23B is bonded to the second wiring layer 13 by the first bonding layer 25. As a result, the anode electrode 231 of the second diode 23B is conducting to the second wiring layer 13.
- the capacitor 24 is joined to the first wiring layer 12 and the second wiring layer 13. When viewed in the thickness direction z, the capacitor 24 overlaps the exposed portion 11A of the substrate 11.
- the capacitor 24 is, for example, a ceramic capacitor.
- the capacitor 24 has a pair of electrodes 241.
- the pair of electrodes 241 are separated from each other in the first direction x.
- One of the electrodes 241 of the pair of electrodes 241 is bonded to the first wiring layer 12 by the first bonding layer 25.
- the other electrode 241 of the pair of electrodes 241 is bonded to the second wiring layer 13 by the first bonding layer 25.
- the capacitor 24 is conducting to the first wiring layer 12 and the second wiring layer 13.
- the first gate wiring layer 141 is arranged on the main surface 111 of the substrate 11 as shown in FIGS. 2, 3 and 5.
- the first gate wiring layer 141 is located on the side opposite to the second wiring layer 13 with respect to the first wiring layer 12 in the first direction x.
- the first gate wiring layer 141 is conductive to the first gate electrode 213 of the first semiconductor element 21.
- the first gate wiring layer 141 extends along the second direction y.
- the first gate wiring layer 141 is made of a material containing copper or a copper alloy.
- the first gate terminal 441 is located on one side of the first direction x with respect to the substrate 11, as shown in FIGS. 2 and 3.
- the first gate terminal 441 is conductive to the first gate wiring layer 141.
- the first gate terminal 441 is a metal lead made of a material containing copper or a copper alloy. As shown in FIGS. 1 and 6, a part of the first gate terminal 441 is covered with the sealing resin 60.
- the first gate terminal 441 is L-shaped when viewed in the second direction y. As shown in FIG. 6, the first gate terminal 441 includes a portion that stands upright in the thickness direction z. The portion is exposed from the sealing resin 60.
- a gate voltage for driving the first semiconductor element 21 is applied to the first gate terminal 441.
- the second gate wiring layer 142 is arranged on the main surface 111 of the substrate 11 as shown in FIGS. 2, 3 and 5.
- the second gate wiring layer 142 is located on the side opposite to the first wiring layer 12 with respect to the second wiring layer 13 in the first direction x.
- the second gate wiring layer 142 is conductive to the second gate electrode 223 of the second semiconductor element 22.
- the second gate wiring layer 142 extends along the second direction y.
- the second gate wiring layer 142 is made of a material containing copper or a copper alloy.
- the second gate electrode extraction layer 162 is arranged on the main surface 111 of the substrate 11 as shown in FIGS. 2, 3, and 9.
- the second gate electrode extraction layer 162 is located at a notched portion of the second wiring layer 13. Seen in the thickness direction z, the second semiconductor element 22 overlaps the second gate electrode extraction layer 162.
- the second gate electrode extraction layer 162 is conductive to the second gate wiring layer 142.
- the second gate electrode extraction layer 162 extends along the first direction x.
- the second gate electrode lead-out layer 162 is made of a material containing copper or a copper alloy.
- the second gate electrode 223 of the second semiconductor element 22 is bonded to the second gate electrode extraction layer 162 by the third bonding layer 27.
- the third bonding layer 27 has conductivity.
- the third bonding layer 27 is, for example, lead-free solder.
- the first bonding layer 25 may be a sintered metal containing silver or the like.
- the second gate electrode 223 is conductive to the second gate electrode extraction layer 162.
- the second gate terminal 442 is located on the side opposite to the first gate terminal 441 with respect to the substrate 11 in the first direction x.
- the second gate terminal 442 is conductive to the second gate wiring layer 142.
- the second gate terminal 442 is a metal lead made of a material containing copper or a copper alloy.
- a part of the second gate terminal 442 is covered with the sealing resin 60.
- the second gate terminal 442 is L-shaped when viewed in the second direction y.
- the second gate terminal 442 includes a portion that stands upright in the thickness direction z. The portion is exposed from the sealing resin 60.
- a gate voltage for driving the second semiconductor element 22 is applied to the second gate terminal 442.
- the pair of first wires 53 are individually separated from the first gate terminal 441 and the second gate terminal 442 and the first gate wiring layer 141 and the second gate wiring layer 142. It is joined to. As a result, the first gate terminal 441 is conducting to the first gate wiring layer 141, and the second gate terminal 442 is conducting to the second gate wiring layer 142.
- Each composition of the pair of first wires 53 contains gold. In addition, each composition of the pair of first wires 53 may contain copper or aluminum (Al).
- the first detection wiring layer 151 is arranged on the main surface 111 of the substrate 11 as shown in FIGS. 2, 3 and 5.
- the first detection wiring layer 151 is located next to the first gate wiring layer 141 in the first direction x.
- the first detection wiring layer 151 is conductive to the first main surface electrode 212 of the first semiconductor element 21.
- the first detection wiring layer 151 extends along the second direction y.
- the first detection wiring layer 151 is made of a material containing copper or a copper alloy.
- the first detection terminal 451 is located on the same side as the first gate terminal 441 with respect to the substrate 11 in the first direction x, and the first gate terminal 441 is located in the second direction y. Located next to. Therefore, the first detection terminal 451 is located closer to the first gate terminal 441 than the second gate terminal 442.
- the first detection terminal 451 is conductive to the first detection wiring layer 151.
- the first detection terminal 451 is a metal lead made of a material containing copper or a copper alloy. As shown in FIGS. 1 and 5, a part of the first detection terminal 451 is covered with the sealing resin 60.
- the first detection terminal 451 is L-shaped when viewed in the second direction y. As shown in FIG. 5, the first detection terminal 451 includes a portion that stands upright in the thickness direction z. The portion is exposed from the sealing resin 60. A voltage corresponding to the current flowing through the first main surface electrode 212 of the first semiconductor element 21 is applied to the first detection terminal 451.
- the second detection wiring layer 152 is arranged on the main surface 111 of the substrate 11 as shown in FIGS. 2, 3 and 5.
- the second detection wiring layer 152 is located next to the second gate wiring layer 142 in the first direction x.
- the second detection wiring layer 152 is conductive to the second back surface electrode 221 of the second semiconductor element 22.
- the second detection wiring layer 152 extends along the second direction y.
- the second detection wiring layer 152 is made of a material containing copper or a copper alloy.
- the back surface electrode extraction layer 17 is arranged on the main surface 111 of the substrate 11 as shown in FIGS. 2, 3, and 9.
- the back surface electrode extraction layer 17 is located in the notched portion of the second wiring layer 13 and next to the second gate electrode extraction layer 162 in the second direction y. Seen in the thickness direction z, the second semiconductor element 22 overlaps the back surface electrode extraction layer 17.
- the back surface electrode extraction layer 17 is conductive to the second detection wiring layer 152.
- the back surface electrode extraction layer 17 extends along the first direction x.
- the back electrode lead-out layer 17 is made of a material containing copper or a copper alloy.
- the second back surface electrode 221 of the second semiconductor element 22 is bonded to the back surface electrode extraction layer 17 by the third bonding layer 27. As a result, the second back surface electrode 221 is conductive to the back surface electrode extraction layer 17.
- the second detection terminal 452 is located on the same side as the second gate terminal 442 with respect to the substrate 11 in the first direction x, and is the second gate terminal 442 in the second direction y. Located next to. Therefore, the second detection terminal 452 is located closer to the second gate terminal 442 than the first gate terminal 441.
- the second detection terminal 452 is conductive to the second detection wiring layer 152.
- the second detection terminal 452 is a metal lead made of a material containing copper or a copper alloy. As shown in FIGS. 1 and 5, a part of the second detection terminal 452 is covered with the sealing resin 60.
- the second detection terminal 452 is L-shaped when viewed in the second direction y. As shown in FIG. 5, the second detection terminal 452 includes a portion that stands upright in the thickness direction z. The portion is exposed from the sealing resin 60. A voltage corresponding to the current flowing through the second back surface electrode 221 of the second semiconductor element 22 is applied to the second detection terminal 452.
- the pair of second wires 54 are individually separated from the first detection terminal 451 and the second detection terminal 452 and the first detection wiring layer 151 and the second detection wiring layer 152. It is joined to. As a result, the first detection terminal 451 is conducting to the first detection wiring layer 151, and the second detection terminal 452 is conducting to the second detection wiring layer 152.
- Each composition of the pair of second wires 54 contains gold. In addition, each composition of the pair of second wires 54 may contain copper or aluminum.
- the conductive member 30 is separated from the substrate 11 on the side facing the main surface 111 in the thickness direction z.
- the conductive member 30 is joined to the first main surface electrode 212 of the first semiconductor element 21 and the second main surface electrode 222 of the second semiconductor element 22. Further, the conductive member 30 is joined to the anode electrode 231 of the first diode 23A and the cathode electrode 232 of the second diode 23B.
- the conductive member 30 is composed of a single lead frame.
- the lead frame is made of a material containing, for example, copper or a copper alloy. As shown in FIG. 2, the conductive member 30 overlaps the exposed portion 11A of the substrate 11 when viewed in the thickness direction z.
- the conductive member 30 has a base 31, a pair of first joints 32, and a pair of second joints 33.
- the base 31 extends along the second direction y. When viewed in the thickness direction z, the base portion 31 overlaps the exposed portion 11A of the substrate 11, the first wiring layer 12, the second wiring layer 13, and the capacitor 24.
- the pair of first joints 32 are connected to both ends of the base 31 in the first direction x.
- the pair of first junction portions 32 is second with respect to the first main surface electrode 212 of the first semiconductor element 21 and the second main surface electrode 222 of the second semiconductor element 22. They are individually bonded by the bonding layer 26.
- the second bonding layer 26 has conductivity.
- the second bonding layer 26 is, for example, lead-free solder.
- the second bonding layer 26 may be a sintered metal containing silver or the like.
- the first main surface electrode 212 and the second main surface electrode 222 are conductive to the conductive member 30.
- the pair of second joints 33 are connected to both ends of the base 31 in the first direction x and are separated from the pair of first joints 32 in the second direction y.
- the pair of second junctions 33 are individually bonded by the second junction layer 26 to the anode electrode 231 of the first diode 23A and the cathode electrode 232 of the second diode 23B. ing.
- the anode electrode 231 of the first diode 23A and the cathode electrode 232 of the second diode 23B are conductive to the conductive member 30.
- the first input terminal 41 is located on one side of the second direction y with respect to the substrate 11.
- the first input terminal 41 is conductive to the first wiring layer 12.
- the first input terminal 41 is joined to the first wiring layer 12.
- the first input terminal 41 is a metal plate made of a material containing copper or a copper alloy. A part of the first input terminal 41 is covered with the sealing resin 60.
- the first input terminal 41 has a first mounting hole 411 penetrating in the thickness direction z. The first mounting hole 411 is exposed from the sealing resin 60.
- the first input terminal 41 is a P terminal (positive electrode) to which a DC power supply voltage to be converted into power is applied.
- the second input terminal 42 is located on the same side as the first input terminal 41 (one side of the second direction y) with respect to the substrate 11 in the second direction y.
- the second input terminal 42 is separated from the first input terminal 41 in the first direction x.
- the second input terminal 42 is conductive to the second wiring layer 13.
- the second input terminal 42 is a metal plate made of a material containing copper or a copper alloy. A part of the second input terminal 42 is covered with the sealing resin 60.
- the second input terminal 42 has a second mounting hole 421 that penetrates in the thickness direction z. The second mounting hole 421 is exposed from the sealing resin 60.
- the second input terminal 42 is an N terminal (negative electrode) to which a DC power supply voltage to be converted into power is applied.
- the output terminal 43 is located on the side opposite to the first input terminal 41 and the second input terminal 42 (the other side in the second direction y) with respect to the substrate 11 in the second direction y. To position. As shown in FIG. 7, the output terminal 43 is separated from the substrate 11 on the side facing the main surface 111 in the thickness direction z.
- the output terminal 43 is conductive to the conductive member 30.
- the output terminal 43 is joined to the base 31 of the conductive member 30.
- the output terminal 43 is a metal plate made of a material containing copper or a copper alloy. A part of the output terminal 43 is covered with the sealing resin 60.
- the output terminal 43 has a third mounting hole 431 penetrating in the thickness direction z. The third mounting hole 431 is exposed from the sealing resin 60.
- the AC power converted by the first semiconductor element 21 and the second semiconductor element 22 is output from the output terminal 43.
- one of the gate wires 51 of the pair of gate wires 51 is joined to the first gate electrode 213 of the first semiconductor element 21 and the first gate wiring layer 141. ing. As a result, the first gate electrode 213 conducts to the first gate wiring layer 141 and also conducts to the first gate terminal 441 via one of the pair of first wires 53.
- the other gate wire 51 of the pair of gate wires 51 is joined to the second gate electrode extraction layer 162 and the second gate wiring layer 142 as shown in FIGS. 2, 3 and 9. As a result, the second gate electrode 223 of the second semiconductor element 22 conducts to the second gate wiring layer 142 and also conducts to the second gate terminal 442 via the other of the pair of first wires 53.
- Each composition of the pair of gate wires 51 contains gold. In addition, each composition of the pair of gate wires 51 may contain aluminum or copper.
- one of the pair of detection wires 52 is joined to the first main surface electrode 212 of the first semiconductor element 21 and the first detection wiring layer 151.
- the first main surface electrode 212 is conductive to the first detection wiring layer 151 and to the first detection terminal 451 via one of the pair of second wires 54.
- the other detection wire 52 of the pair of detection wires 52 is joined to the back surface electrode extraction layer 17 and the second detection wiring layer 152 as shown in FIGS. 2, 3 and 9.
- the second back surface electrode 221 of the second semiconductor element 22 conducts to the second detection wiring layer 152 and also to the second detection terminal 452 via the other of the pair of second wires 54.
- Each composition of the plurality of detection wires 52 contains gold.
- the composition of each of the plurality of detection wires 52 may include aluminum or copper.
- the sealing resin 60 includes a first wiring layer 12, a second wiring layer 13, a first gate wiring layer 141, a second gate wiring layer 142, and a first detection wiring. It covers the layer 151, the second detection wiring layer 152, the second gate electrode extraction layer 162, the back surface electrode extraction layer 17, the first semiconductor element 21, the second semiconductor element 22, the pair of diodes 23, the capacitor 24, and the conductive member 30. There is. Further, the sealing resin 60 includes the substrate 11, the first input terminal 41, the second input terminal 42, the output terminal 43, the first gate terminal 441, the second gate terminal 442, the first detection terminal 451 and the second detection terminal 452. It covers a part of each. The sealing resin 60 has electrical insulation. The sealing resin 60 is made of a material containing, for example, a black epoxy resin. The sealing resin 60 includes a portion sandwiched between the exposed portion 11A of the substrate 11 and the base portion 31 of the conductive member 30 in the thickness direction z.
- the sealing resin 60 has a top surface 61, a bottom surface 62, a pair of first side surfaces 63, and a pair of second side surfaces 64.
- the top surface 61 faces the same side as the main surface 111 of the substrate 11 in the thickness direction z.
- the area of the top surface 61 is larger than the area of the main surface 111.
- the bottom surface 62 faces the side opposite to the top surface 61 in the thickness direction z.
- the back surface 112 of the substrate 11 is exposed from the bottom surface 62.
- the pair of first side surfaces 63 are separated from each other in the first direction x and are connected to the top surface 61 and the bottom surface 62.
- the first gate terminal 441 and the first detection terminal 451 are exposed from the first side surface 63 of one of the pair of first side surfaces 63.
- the second gate terminal 442 and the second detection terminal 452 are exposed from the other first side surface 63 of the pair of first side surfaces 63.
- the pair of second side surfaces 64 are separated from each other in the second direction y and are connected to the top surface 61 and the bottom surface 62.
- the first input terminal 41 and the second input terminal 42 are exposed from the second side surface 64 of one of the pair of second side surface 64s.
- the output terminal 43 is exposed from the other second side surface 64 of the pair of second side surface 64s.
- the heat sink 70 is joined to the back surface 112 of the substrate 11.
- the substrate 11 is located between the heat sink 70 and the first wiring layer 12, the second wiring layer 13, and the conductive member 30 in the thickness direction z.
- the heat sink 70 is made of a material containing, for example, aluminum.
- the semiconductor device A10 includes a conductive member 30 separated from the substrate 11 on the side facing the main surface 111 in the thickness direction z.
- the conductive member 30 is joined to the first main surface electrode 212 of the first semiconductor element 21 and the second main surface electrode 222 of the second semiconductor element 22.
- the polarities of the first main surface electrode 212 and the second main surface electrode 222 are different from each other.
- the substrate 11 includes an exposed portion 11A located between the first wiring layer 12 and the second wiring layer 13 when viewed in the thickness direction z.
- the conductive member 30 overlaps the exposed portion 11A when viewed in the thickness direction z. As a result, the distance in the thickness direction z from the exposed portion 11A to the conductive member 30 becomes larger.
- the parasitic capacitance of the semiconductor device A10 on the conductive member 30 and the substrate 11 is inversely proportional to the distance. Therefore, the larger the distance, the smaller the parasitic capacitance. It becomes. Therefore, the electric charge stored in the conductive member 30 becomes smaller as the first semiconductor element 21 and the second semiconductor element 22 are switched, so that the leakage current from the semiconductor device A10 is suppressed. Therefore, according to the semiconductor device A10, it is possible to reduce the noise caused by the leakage current from the device.
- the semiconductor device A10 further includes a second gate electrode extraction layer 162 that is arranged on the main surface 111 of the substrate 11 and conducts to the second gate wiring layer 142.
- the second gate electrode 223 of the second semiconductor element 22 is located on the same side as the second back surface electrode 221 in the thickness direction z.
- the second gate electrode 223 is bonded to the second gate electrode extraction layer 162.
- the conductive member 30 has a base portion 31 extending in the second direction y and a pair of joint portions (first joint portion 32) connected to both ends of the base portion 31 in the first direction x.
- the conductive member 30 can shorten the length of the conductive path between the first main surface electrode 212 of the first semiconductor element 21 and the second main surface electrode 222 of the second semiconductor element 22 as compared with the conventional case. This makes it possible to reduce the inductance and parasitic resistance applied to the conductive member 30.
- the semiconductor device A10 further includes a sealing resin 60 that covers the conductive member 30.
- the sealing resin 60 includes a portion sandwiched between the exposed portion 11A of the substrate 11 and the base portion 31 of the conductive member 30 in the thickness direction z. As a result, the holding of the conductive member 30 by the sealing resin 60 becomes more stable, and the parasitic capacitance of the semiconductor device A10 on the conductive member 30 and the substrate 11 can be further reduced.
- the semiconductor device A10 further includes a capacitor 24 bonded to the first wiring layer 12 and the second wiring layer 13.
- the semiconductor device A10 is configured with a snubber circuit for reducing the surge voltage applied to the first input terminal 41 and the second input terminal 42, so that the first semiconductor element 21 and the first semiconductor device 21 with respect to the surge voltage are configured. 2 It is possible to protect the semiconductor element 22. In this case, by adopting a configuration in which the capacitor 24 overlaps the exposed portion 11A of the substrate 11 in the thickness direction z, it is possible to avoid an increase in the size of the semiconductor device A10.
- each of the first wiring layer 12 and the second wiring layer 13 is larger than the thickness of the substrate 11. Thereby, in each of the first wiring layer 12 and the second wiring layer 13, the heat conduction efficiency in the direction orthogonal to the thickness direction z can be improved. This contributes to the improvement of the heat dissipation property of the semiconductor device A10.
- FIG. 15 is transparent to the sealing resin 60 for convenience of understanding.
- the semiconductor device A20 the configuration of the first semiconductor element 21, the second semiconductor element 22, the pair of gate wires 51, and the pair of detection wires 52, and the first gate electrode extraction layer instead of the second gate electrode extraction layer 162.
- the point that 161 is provided is different from the above-mentioned semiconductor device A10.
- the first semiconductor element 21 further includes a first detection electrode 214, a first element main body 215, a plurality of first rewiring layers 216, and a first protective layer 217.
- the first element main body 215 is a transistor of the same type as the first semiconductor element 21 of the semiconductor device A10, and has the same structure as the first semiconductor element 21.
- the first element main body 215 has a first electrode 215A, a second electrode 215B, and a gate electrode 215C.
- the first electrode 215A corresponds to the first back surface electrode 211 and the drain electrode of the first semiconductor element 21 of the semiconductor device A10.
- the second electrode 215B corresponds to the first main surface electrode 212 and the source electrode of the first semiconductor element 21 of the semiconductor device A10.
- the gate electrode 215C corresponds to the first gate electrode 213 of the first semiconductor element 21 of the semiconductor device A10.
- the plurality of first rewiring layers 216 include a first electrode 215A, a second electrode 215B, and a gate electrode 215C, and a first back surface electrode 211, a first main surface electrode 212, and a first gate electrode 213. And a conductive path with the first detection electrode 214.
- the first electrode 215A is conducted to the first back surface electrode 211 by the plurality of first rewiring layers 216.
- the second electrode 215B is conductive to the first main surface electrode 212 and the first detection electrode 214.
- the gate electrode 215C is conductive to the first gate electrode 213.
- the first gate electrode 213 is located on the same side as the first back surface electrode 211 in the thickness direction z.
- the first gate electrode 213 is located outside the first element main body 215 when viewed in the thickness direction z.
- the area of the first main surface electrode 212 is larger than the area of the second electrode 215B when viewed in the thickness direction z.
- the first detection electrode 214 is located on the same side as the first main surface electrode 212 in the thickness direction z. A voltage having the same potential as that of the first main surface electrode 212 is applied to the first detection electrode 214.
- the first protective layer 217 covers the first element main body 215 and the plurality of first rewiring layers 216.
- the first back surface electrode 211, the first main surface electrode 212, the first gate electrode 213, and the first detection electrode 214 are exposed from the first protective layer 217.
- the first protective layer 217 is made of a material containing, for example, polyimide.
- the first gate electrode extraction layer 161 is arranged on the main surface 111 of the substrate 11. Seen in the thickness direction z, the first semiconductor element 21 overlaps with the first gate electrode extraction layer 161.
- the first gate electrode extraction layer 161 is conductive to the first gate wiring layer 141.
- the first gate electrode extraction layer 161 extends along the first direction x.
- the first gate electrode lead-out layer 161 is made of a material containing copper or a copper alloy.
- the first gate electrode 213 of the first semiconductor element 21 is bonded to the first gate electrode extraction layer 161 by the third bonding layer 27. As a result, the first gate electrode 213 is conductive to the first gate electrode extraction layer 161.
- the second semiconductor element 22 further includes a second detection electrode 224, a second element main body 225, a plurality of second rewiring layers 226, and a second protective layer 227. ..
- the second element main body 225 is a transistor of the same type as the second semiconductor element 22 of the semiconductor device A10, and has the same structure as the second semiconductor element 22.
- the second element main body 225 has a first electrode 225A, a second electrode 225B, and a gate electrode 225C.
- the first electrode 225A corresponds to the second main surface electrode 222 and the drain electrode of the second semiconductor element 22 of the semiconductor device A10.
- the second electrode 225B corresponds to the second back surface electrode 221 and the source electrode of the second semiconductor element 22 of the semiconductor device A10.
- the gate electrode 225C corresponds to the second gate electrode 223 of the second semiconductor element 22 of the semiconductor device A10.
- the plurality of second rewiring layers 226 include a first electrode 225A, a second electrode 225B and a gate electrode 225C, a second back surface electrode 221 and a second main surface electrode 222, and a second. It forms a conductive path with the gate electrode 223 and the second detection electrode 224.
- the first electrode 225A is conducted to the second main surface electrode 222 by the plurality of second rewiring layers 226.
- the second electrode 225B is conductive to the second back surface electrode 221 and the second detection electrode 224.
- the gate electrode 225C is conductive to the second gate electrode 223.
- the second gate electrode 223 is located on the same side as the second main surface electrode 222 in the thickness direction z.
- the second gate electrode 223 is located outside the second element main body 225 when viewed in the thickness direction z.
- the area of the second back surface electrode 221 is larger than the area of the second electrode 225B when viewed in the thickness direction z.
- the second detection electrode 224 is located on the same side as the second back surface electrode 221 in the thickness direction z. A voltage having the same potential as that of the second back surface electrode 221 is applied to the second detection electrode 224. As shown in FIG. 18, the second detection electrode 224 is bonded to the back surface electrode extraction layer 17 by the third bonding layer 27. As a result, the second detection electrode 224 is conductive to the back surface electrode extraction layer 17.
- the second protective layer 227 covers the second element main body 225 and the plurality of second rewiring layers 226.
- the second back surface electrode 221 and the second main surface electrode 222, the second gate electrode 223, and the second detection electrode 224 are exposed from the second protective layer 227.
- the second protective layer 227 is made of, for example, a material containing polyimide.
- one of the gate wires 51 of the pair of gate wires 51 is joined to the first gate electrode extraction layer 161 and the first gate wiring layer 141.
- the first gate electrode 213 of the first semiconductor element 21 is conducting to the first gate terminal 441.
- the other gate wire 51 of the pair of gate wires 51 is joined to the second gate electrode 223 of the second semiconductor element 22 and the second gate wiring layer 142.
- the second gate electrode 223 is conducting to the second gate terminal 442.
- one of the pair of detection wires 52, the detection wire 52 is joined to the first detection electrode 214 of the first semiconductor element 21 and the first detection wiring layer 151.
- the first main surface electrode 212 of the first semiconductor element 21 is conducting to the first detection terminal 451.
- the other detection wire 52 of the pair of detection wires 52 is joined to the back surface electrode extraction layer 17 and the second detection wiring layer 152.
- the second back surface electrode 221 of the second semiconductor element 22 is conducting to the second detection terminal 452.
- the semiconductor device A20 includes a conductive member 30 separated from the substrate 11 on the side facing the main surface 111 in the thickness direction z.
- the conductive member 30 is joined to the first main surface electrode 212 of the first semiconductor element 21 and the second main surface electrode 222 of the second semiconductor element 22.
- the polarities of the first main surface electrode 212 and the second main surface electrode 222 are different from each other.
- the substrate 11 includes an exposed portion 11A located between the first wiring layer 12 and the second wiring layer 13 when viewed in the thickness direction z.
- the conductive member 30 overlaps the exposed portion 11A when viewed in the thickness direction z. Therefore, the semiconductor device A20 can also reduce the noise caused by the leakage current from the device.
- the second gate electrode 223 of the second semiconductor element 22 is located on the same side as the second main surface electrode 222 in the thickness direction z. This eliminates the need to arrange the second gate electrode extraction layer 162.
- the first semiconductor element 21 has a first element main body 215 and a plurality of first rewiring layers 216.
- the area of the first main surface electrode 212 of the first semiconductor element 21 can be made larger in the thickness direction z. This contributes to an increase in the bonding strength of the conductive member 30 with respect to the first main surface electrode 212 and an improvement in the heat conduction efficiency from the first main surface electrode 212 to the conductive member 30.
- the second semiconductor element 22 has a second element main body 225 and a second rewiring layer 226.
- the area of the second back surface electrode 221 of the second semiconductor element 22 can be made larger when viewed in the thickness direction z. This contributes to an increase in the bonding strength of the second back surface electrode 221 with respect to the second wiring layer 13 and an improvement in the heat conduction efficiency from the second back surface electrode 221 to the second wiring layer 13.
- FIG. 19 is transparent to the sealing resin 60 for convenience of understanding.
- the configuration of the second semiconductor element 22 is different from the configuration of the semiconductor device A10 described above.
- the configuration of the first semiconductor element 21 is the same as the configuration of the first semiconductor element 21 of the semiconductor device A10. Therefore, in the semiconductor device A30, the first gate electrode 213 of the first semiconductor element 21 is located on the same side as the first main surface electrode 212 in the thickness direction z.
- the configuration of the second semiconductor element 22 is the same as the configuration of the second semiconductor element 22 of the semiconductor device A20. Therefore, in the semiconductor device A30, the second gate electrode 223 of the second semiconductor element 22 is located on the same side as the second main surface electrode 222 in the thickness direction z.
- the semiconductor device A30 includes a conductive member 30 that is separated from the substrate 11 on the side facing the main surface 111 in the thickness direction z.
- the conductive member 30 is joined to the first main surface electrode 212 of the first semiconductor element 21 and the second main surface electrode 222 of the second semiconductor element 22.
- the polarities of the first main surface electrode 212 and the second main surface electrode 222 are different from each other.
- the substrate 11 includes an exposed portion 11A located between the first wiring layer 12 and the second wiring layer 13 when viewed in the thickness direction z.
- the conductive member 30 overlaps the exposed portion 11A when viewed in the thickness direction z. Therefore, the semiconductor device A30 can also reduce the noise caused by the leakage current from the device.
- the first gate electrode 213 of the first semiconductor element 21 is located on the same side as the first main surface electrode 212 in the thickness direction z. This eliminates the need to arrange the first gate electrode extraction layer 161. Further, in the semiconductor device A30, the second gate electrode 223 of the second semiconductor element 22 is located on the same side as the second main surface electrode 222 in the thickness direction z. This eliminates the need to arrange the second gate electrode extraction layer 162.
- FIG. 20 is transparent to the sealing resin 60 for convenience of understanding.
- the configuration of the first semiconductor element 21 is different from the configuration of the semiconductor device A10 described above.
- the configuration of the first semiconductor element 21 is the same as the configuration of the first semiconductor element 21 of the semiconductor device A20. Therefore, in the semiconductor device A40, the first gate electrode 213 of the first semiconductor element 21 is located on the same side as the first back surface electrode 211 in the thickness direction z. Therefore, in the semiconductor device A40, the arrangement of the first gate electrode extraction layer 161 is indispensable.
- the configuration of the second semiconductor element 22 is the same as the configuration of the second semiconductor element 22 of the semiconductor device A10. Therefore, in the semiconductor device A40, the second gate electrode 223 of the second semiconductor element 22 is located on the same side as the second back surface electrode 221 in the thickness direction z. Therefore, in the semiconductor device A40, the arrangement of the second gate electrode extraction layer 162 is indispensable.
- the semiconductor device A40 includes a conductive member 30 separated from the substrate 11 on the side facing the main surface 111 in the thickness direction z.
- the conductive member 30 is joined to the first main surface electrode 212 of the first semiconductor element 21 and the second main surface electrode 222 of the second semiconductor element 22.
- the polarities of the first main surface electrode 212 and the second main surface electrode 222 are different from each other.
- the substrate 11 includes an exposed portion 11A located between the first wiring layer 12 and the second wiring layer 13 when viewed in the thickness direction z.
- the conductive member 30 overlaps the exposed portion 11A when viewed in the thickness direction z. Therefore, the semiconductor device A40 can also reduce the noise caused by the leakage current from the device.
- FIG. 21 is transparent to the sealing resin 60 for convenience of understanding.
- the configuration of the second semiconductor element 22 and the configuration of the gate wire 51 and the detection wire 52 joined to the second semiconductor element 22 among the pair of gate wires 51 and the pair of detection wires 52 is different from the configuration of the semiconductor device A10 described above.
- the configuration of the first semiconductor element 21 is the same as the configuration of the first semiconductor element 21 of the semiconductor device A10. Therefore, in the semiconductor device A30, the first gate electrode 213 of the first semiconductor element 21 is located on the same side as the first main surface electrode 212 in the thickness direction z.
- the second semiconductor element 22 further includes a second detection electrode 224, a second element main body 225, a plurality of second rewiring layers 226, and a second protective layer 227.
- the second gate electrode 223 and the second detection electrode 224 are located on the same side as the second main surface electrode 222 in the thickness direction z.
- the second gate electrode 223 and the second detection electrode 224 are located outside the second element main body 225 when viewed in the thickness direction z.
- the area of the second back surface electrode 221 is larger than the area of the second electrode 225B when viewed in the thickness direction z.
- one of the gate wires 51 of the pair of gate wires 51 is joined to the first gate electrode 213 of the first semiconductor element 21 and the first gate wiring layer 141.
- the first gate electrode 213 is conducting to the first gate terminal 441.
- the other gate wire 51 of the pair of gate wires 51 is joined to the second gate electrode 223 of the second semiconductor element 22 and the second gate wiring layer 142.
- the second gate electrode 223 is conducting to the second gate terminal 442.
- one of the pair of detection wires 52, the detection wire 52 is joined to the first main surface electrode 212 of the first semiconductor element 21 and the first detection wiring layer 151.
- the first main surface electrode 212 is conducting to the first detection terminal 451.
- the other detection wire 52 of the pair of detection wires 52 is joined to the second detection electrode 224 of the second semiconductor element 22 and the second detection wiring layer 152.
- the second back surface electrode 221 of the second semiconductor element 22 is conducting to the second detection terminal 452.
- the semiconductor device A50 includes a conductive member 30 separated from the substrate 11 on the side facing the main surface 111 in the thickness direction z.
- the conductive member 30 is joined to the first main surface electrode 212 of the first semiconductor element 21 and the second main surface electrode 222 of the second semiconductor element 22.
- the polarities of the first main surface electrode 212 and the second main surface electrode 222 are different from each other.
- the substrate 11 includes an exposed portion 11A located between the first wiring layer 12 and the second wiring layer 13 when viewed in the thickness direction z.
- the conductive member 30 overlaps the exposed portion 11A when viewed in the thickness direction z. Therefore, the semiconductor device A50 can also reduce the noise caused by the leakage current from the device.
- the second gate electrode 223 of the second semiconductor element 22 is located on the same side as the second main surface electrode 222 in the thickness direction z. This eliminates the need to arrange the second gate electrode extraction layer 162. Further, in the semiconductor device A50, the second semiconductor element 22 has a second detection electrode 224 located on the same side as the second main surface electrode 222 in the thickness direction z. The second detection electrode 224 is conductive to the second back surface electrode 221 of the second semiconductor element 22. This eliminates the need to arrange the back surface electrode extraction layer 17.
- the present disclosure is not limited to the above-described embodiment.
- the specific configuration of each part of the present disclosure can be freely redesigned.
- Appendix 1 A substrate with a main surface facing the thickness direction, The first wiring layer arranged on the main surface and A second wiring layer arranged on the main surface and separated from the first wiring layer in the first direction orthogonal to the thickness direction.
- a first semiconductor device having a first main surface electrode and a first back surface electrode located on opposite sides in the thickness direction, and the first back surface electrode bonded to the first wiring layer.
- a second semiconductor element having a second main surface electrode and a second back surface electrode located on opposite sides in the thickness direction and having the second back surface electrode bonded to the second wiring layer.
- a conductive member separated from the substrate in the thickness direction and bonded to the first main surface electrode and the second main surface electrode is provided.
- the polarities of the first main surface electrode and the second main surface electrode are different from each other.
- the substrate includes an exposed portion located between the first wiring layer and the second wiring layer.
- Appendix 2. The first gate terminal separated from the first wiring layer and Further, a second gate terminal separated from the second wiring layer is provided.
- the first semiconductor element has a first gate electrode conducting to the first gate terminal.
- the semiconductor device according to Appendix 1, wherein the second semiconductor element has a second gate electrode conducting to the second gate terminal.
- Appendix 3. A first detection terminal that is separated from the first wiring layer and conducts to the first main surface electrode.
- the semiconductor device according to Appendix 2 further comprising a second detection terminal that is separated from the second wiring layer and conducts to the second back surface electrode.
- Appendix 4. Further provided with a gate electrode lead-out layer that is separated from the second wiring layer and conducts to the second gate terminal.
- the first gate electrode is located on the same side as the first main surface electrode in the thickness direction.
- the semiconductor device according to Appendix 3, wherein the second gate electrode is located on the same side as the second back surface electrode in the thickness direction and is bonded to the gate electrode extraction layer.
- Appendix 5 The first gate electrode is located on the same side as the first main surface electrode in the thickness direction.
- the semiconductor device according to Appendix 3, wherein the second gate electrode is located on the same side as the second main surface electrode in the thickness direction.
- the second semiconductor element has a detection electrode located on the same side as the second main surface electrode in the thickness direction.
- Appendix 7. A first gate electrode lead-out layer that is separated from the first wiring layer and conducts to the first gate terminal.
- the first gate electrode is located on the same side as the first back surface electrode in the thickness direction, and is bonded to the first gate electrode extraction layer.
- the first input terminal and the second input terminal are located on one side of the second direction orthogonal to both the thickness direction and the first direction with respect to the substrate.
- the semiconductor device according to any one of Supplementary note 3 to 10 wherein the output terminal is located on the other side of the second direction with respect to the substrate.
- Appendix 12. The semiconductor device according to Appendix 11, wherein the output terminal is joined to the conductive member.
- Appendix 13 The first gate terminal is located on the side opposite to the second wiring layer with respect to the first wiring layer in the first direction.
- the semiconductor device according to any one of Supplementary note 3 to 12, wherein the second gate terminal is located on the side opposite to the first wiring layer with respect to the second wiring layer in the first direction. Appendix 14.
- the first detection terminal is located closer to the first gate terminal than the second gate terminal.
- Appendix 15. Further comprising a sealing resin covering the first wiring layer, the second wiring layer, the first semiconductor element, the second semiconductor element, and the conductive member.
- the substrate has a back surface facing away from the main surface in the thickness direction.
- the semiconductor device according to Appendix 15, wherein the back surface is exposed from the sealing resin.
- Appendix 17. The semiconductor device according to Appendix 16, further comprising a heat sink bonded to the back surface.
- A10, A20, A30, A40, A50 Semiconductor device 11: Substrate 11A: Exposed part 111: Main surface 112: Back surface 12: First wiring layer 13: Second wiring layer 141: First gate Wiring layer 142: Second gate Wiring layer 151: 1st detection wiring layer 152: 2nd detection wiring layer 161: 1st gate electrode drawer layer 162: 2nd gate electrode drawer layer 17: Backside electrode drawer layer 21: 1st semiconductor element 211: 1st backside electrode 212: 1st main surface electrode 213: 1st gate electrode 214: 1st detection electrode 215: 1st element main body 215A: 1st electrode 215B: 2nd electrode 215C: Gate electrode 216: 1st rewiring layer 217: 1st Protective layer 22: 2nd semiconductor element 221: 2nd back surface electrode 222: 2nd main surface electrode 223: 2nd gate electrode 224: 2nd detection electrode 225: 2nd element main body 226: 2nd rewiring
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Abstract
Description
付記1.
厚さ方向を向く主面を有する基板と、
前記主面に配置された第1配線層と、
前記主面に配置され、かつ前記厚さ方向に対して直交する第1方向において前記第1配線層から離間する第2配線層と、
前記厚さ方向において互いに反対側に位置する第1主面電極および第1裏面電極を有するとともに、前記第1裏面電極が前記第1配線層に接合された第1半導体素子と、
前記厚さ方向において互いに反対側に位置する第2主面電極および第2裏面電極を有するとともに、前記第2裏面電極が前記第2配線層に接合された第2半導体素子と、
前記厚さ方向において前記基板から離間し、かつ前記第1主面電極と前記第2主面電極とに接合された導電部材と、を備え、
前記第1主面電極および前記第2主面電極の極性が互いに異なり、
前記基板は、前記第1配線層と前記第2配線層との間に位置する露出部を含み、
前記厚さ方向に視て、前記導電部材が前記露出部に重なる、半導体装置。
付記2.
前記第1配線層から離間する第1ゲート端子と、
前記第2配線層から離間する第2ゲート端子と、をさらに備え、
前記第1半導体素子は、前記第1ゲート端子に導通する第1ゲート電極を有し、
前記第2半導体素子は、前記第2ゲート端子に導通する第2ゲート電極を有する、付記1に記載の半導体装置。
付記3.
前記第1配線層から離間し、かつ前記第1主面電極に導通する第1検出端子と、
前記第2配線層から離間し、かつ前記第2裏面電極に導通する第2検出端子と、をさらに備える、付記2に記載の半導体装置。
付記4.
前記第2配線層から離間し、かつ前記第2ゲート端子に導通するゲート電極引出層をさらに備え、
前記第1ゲート電極は、前記厚さ方向において前記第1主面電極と同じ側に位置し、
前記第2ゲート電極は、前記厚さ方向において前記第2裏面電極と同じ側に位置し、かつ、前記ゲート電極引出層に接合されている、付記3に記載の半導体装置。
付記5.
前記第1ゲート電極は、前記厚さ方向において前記第1主面電極と同じ側に位置し、
前記第2ゲート電極は、前記厚さ方向において前記第2主面電極と同じ側に位置する、付記3に記載の半導体装置。
付記6.
前記第2半導体素子は、前記厚さ方向において前記第2主面電極と同じ側に位置する検出電極を有し、
前記検出電極は、前記第2裏面電極および前記第2検出端子に導通している、付記5に記載の半導体装置。
付記7.
前記第1配線層から離間し、かつ前記第1ゲート端子に導通する第1ゲート電極引出層と、
前記第2配線層から離間し、かつ前記第2ゲート端子に導通する第2ゲート電極引出層と、をさらに備え、
前記第1ゲート電極は、前記厚さ方向において前記第1裏面電極と同じ側に位置し、かつ、前記第1ゲート電極引出層に接合されており、
前記第2ゲート電極は、前記厚さ方向において前記第2裏面電極と同じ側に位置し、かつ、前記第2ゲート電極引出層に接合されている、付記3に記載の半導体装置。
付記8.
前記第1配線層および前記第2配線層に対して個別に接合された一対のダイオードをさらに備え、
前記一対のダイオードは、前記導電部材に接合されている、付記3から7のいずれかに記載の半導体装置。
付記9.
前記第1配線層と前記第2配線層とに接合されたコンデンサをさらに備える、付記3から8のいずれかに記載の半導体装置。
付記10.
前記厚さ方向に視て、前記コンデンサが前記露出部に重なる、付記9に記載の半導体装置。
付記11.
前記第1配線層に導通する第1入力端子と、
前記第2配線層に導通する第2入力端子と、
前記厚さ方向において前記主面が向く側に前記基板から離間し、かつ前記導電部材に導通する出力端子と、をさらに備え、
前記第1入力端子および前記第2入力端子は、前記基板に対して前記厚さ方向および前記第1方向の双方に対して直交する第2方向の一方側に位置し、
前記出力端子は、前記基板に対して前記第2方向の他方側に位置する、付記3から10のいずれかに記載の半導体装置。
付記12.
前記出力端子は、前記導電部材に接合されている、付記11に記載の半導体装置。
付記13.
前記第1ゲート端子は、前記第1方向において前記第1配線層に対して前記第2配線層とは反対側に位置し、
前記第2ゲート端子は、前記第1方向において前記第2配線層に対して前記第1配線層とは反対側に位置する、付記3から12のいずれかに記載の半導体装置。
付記14.
前記第1検出端子は、前記第2ゲート端子よりも前記第1ゲート端子の近くに位置し、
前記第2検出端子は、前記第1ゲート端子よりも前記第2ゲート端子の近くに位置する、付記13に記載の半導体装置。
付記15.
前記第1配線層、前記第2配線層、前記第1半導体素子、前記第2半導体素子および前記導電部材を覆う封止樹脂をさらに備え、
前記封止樹脂は、前記厚さ方向において前記露出部と前記導電部材とに挟まれた部分を含む、付記1から14のいずれかに記載の半導体装置。
付記16.
前記基板は、前記厚さ方向において前記主面とは反対側を向く裏面を有し、
前記裏面は、前記封止樹脂から露出している、付記15に記載の半導体装置。
付記17.
前記裏面に接合されたヒートシンクをさらに備える、付記16に記載の半導体装置。
11:基板 11A:露出部 111:主面
112:裏面 12:第1配線層
13:第2配線層 141:第1ゲート配線層
142:第2ゲート配線層 151:第1検出配線層
152:第2検出配線層 161:第1ゲート電極引出層
162:第2ゲート電極引出層 17:裏面電極引出層
21:第1半導体素子 211:第1裏面電極
212:第1主面電極 213:第1ゲート電極
214:第1検出電極 215:第1素子本体
215A:第1電極 215B:第2電極
215C:ゲート電極 216:第1再配線層
217:第1保護層 22:第2半導体素子
221:第2裏面電極 222:第2主面電極
223:第2ゲート電極 224:第2検出電極
225:第2素子本体 226:第2再配線層
227:第2保護層 23:ダイオード
23A:第1ダイオード 23B:第2ダイオード
231:アノード電極 232:カソード電極
24:コンデンサ 241:電極
25:第1接合層 26:第2接合層
27:第3接合層 30:導電部材
31:基部 32:第1接合部
33:第2接合部 41:第1入力端子
411:第1取付け孔 42:第2入力端子
421:第2取付け孔 43:出力端子
431:第3取付け孔 441:第1ゲート端子
442:第2ゲート端子 451:第1検出端子
452:第2検出端子 51:ゲートワイヤ
52:検出ワイヤ 53:第1ワイヤ
54:第2ワイヤ 60:封止樹脂
61:頂面 62:底面
63:第1側面 64:第2側面
z:厚さ方向 x:第1方向 y:第2方向
Claims (17)
- 厚さ方向を向く主面を有する基板と、
前記主面に配置された第1配線層と、
前記主面に配置され、かつ前記厚さ方向に対して直交する第1方向において前記第1配線層から離間する第2配線層と、
前記厚さ方向において互いに反対側に位置する第1主面電極および第1裏面電極を有するとともに、前記第1裏面電極が前記第1配線層に接合された第1半導体素子と、
前記厚さ方向において互いに反対側に位置する第2主面電極および第2裏面電極を有するとともに、前記第2裏面電極が前記第2配線層に接合された第2半導体素子と、
前記厚さ方向において前記基板から離間し、かつ前記第1主面電極と前記第2主面電極とに接合された導電部材と、を備え、
前記第1主面電極および前記第2主面電極の極性が互いに異なり、
前記基板は、前記第1配線層と前記第2配線層との間に位置する露出部を含み、
前記厚さ方向に視て、前記導電部材が前記露出部に重なる、半導体装置。 - 前記第1配線層から離間する第1ゲート端子と、
前記第2配線層から離間する第2ゲート端子と、をさらに備え、
前記第1半導体素子は、前記第1ゲート端子に導通する第1ゲート電極を有し、
前記第2半導体素子は、前記第2ゲート端子に導通する第2ゲート電極を有する、請求項1に記載の半導体装置。 - 前記第1配線層から離間し、かつ前記第1主面電極に導通する第1検出端子と、
前記第2配線層から離間し、かつ前記第2裏面電極に導通する第2検出端子と、をさらに備える、請求項2に記載の半導体装置。 - 前記第2配線層から離間し、かつ前記第2ゲート端子に導通するゲート電極引出層をさらに備え、
前記第1ゲート電極は、前記厚さ方向において前記第1主面電極と同じ側に位置し、
前記第2ゲート電極は、前記厚さ方向において前記第2裏面電極と同じ側に位置し、かつ、前記ゲート電極引出層に接合されている、請求項3に記載の半導体装置。 - 前記第1ゲート電極は、前記厚さ方向において前記第1主面電極と同じ側に位置し、
前記第2ゲート電極は、前記厚さ方向において前記第2主面電極と同じ側に位置する、請求項3に記載の半導体装置。 - 前記第2半導体素子は、前記厚さ方向において前記第2主面電極と同じ側に位置する検出電極を有し、
前記検出電極は、前記第2裏面電極および前記第2検出端子に導通している、請求項5に記載の半導体装置。 - 前記第1配線層から離間し、かつ前記第1ゲート端子に導通する第1ゲート電極引出層と、
前記第2配線層から離間し、かつ前記第2ゲート端子に導通する第2ゲート電極引出層と、をさらに備え、
前記第1ゲート電極は、前記厚さ方向において前記第1裏面電極と同じ側に位置し、かつ、前記第1ゲート電極引出層に接合され、
前記第2ゲート電極は、前記厚さ方向において前記第2裏面電極と同じ側に位置し、かつ、前記第2ゲート電極引出層に接合されている、請求項3に記載の半導体装置。 - 前記第1配線層および前記第2配線層に対して個別に接合された一対のダイオードをさらに備え、
前記一対のダイオードは、前記導電部材に接合されている、請求項3から7のいずれかに記載の半導体装置。 - 前記第1配線層と前記第2配線層とに接合されたコンデンサをさらに備える、請求項3から8のいずれかに記載の半導体装置。
- 前記厚さ方向に視て、前記コンデンサが前記露出部に重なる、請求項9に記載の半導体装置。
- 前記第1配線層に導通する第1入力端子と、
前記第2配線層に導通する第2入力端子と、
前記厚さ方向において前記主面が向く側に前記基板から離間し、かつ前記導電部材に導通する出力端子と、をさらに備え、
前記第1入力端子および前記第2入力端子は、前記基板に対して前記厚さ方向および前記第1方向の双方に対して直交する第2方向の一方側に位置し、
前記出力端子は、前記基板に対して前記第2方向の他方側に位置する、請求項3から10のいずれかに記載の半導体装置。 - 前記出力端子は、前記導電部材に接合されている、請求項11に記載の半導体装置。
- 前記第1ゲート端子は、前記第1方向において前記第1配線層に対して前記第2配線層とは反対側に位置し、
前記第2ゲート端子は、前記第1方向において前記第2配線層に対して前記第1配線層とは反対側に位置する、請求項3から12のいずれかに記載の半導体装置。 - 前記第1検出端子は、前記第2ゲート端子よりも前記第1ゲート端子の近くに位置し、
前記第2検出端子は、前記第1ゲート端子よりも前記第2ゲート端子の近くに位置する、請求項13に記載の半導体装置。 - 前記第1配線層、前記第2配線層、前記第1半導体素子、前記第2半導体素子および前記導電部材を覆う封止樹脂をさらに備え、
前記封止樹脂は、前記厚さ方向において前記露出部と前記導電部材とに挟まれた部分を含む、請求項1から14のいずれかに記載の半導体装置。 - 前記基板は、前記厚さ方向において前記主面とは反対側を向く裏面を有し、
前記裏面は、前記封止樹脂から露出している、請求項15に記載の半導体装置。 - 前記裏面に接合されたヒートシンクをさらに備える、請求項16に記載の半導体装置。
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