WO2022116289A1 - 像素结构及其制备方法、显示装置 - Google Patents

像素结构及其制备方法、显示装置 Download PDF

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Publication number
WO2022116289A1
WO2022116289A1 PCT/CN2020/137541 CN2020137541W WO2022116289A1 WO 2022116289 A1 WO2022116289 A1 WO 2022116289A1 CN 2020137541 W CN2020137541 W CN 2020137541W WO 2022116289 A1 WO2022116289 A1 WO 2022116289A1
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Prior art keywords
functional
layer
metal layer
wiring
pixel structure
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PCT/CN2020/137541
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English (en)
French (fr)
Inventor
宋利旺
高冬子
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深圳市华星光电半导体显示技术有限公司
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Priority to US17/264,815 priority Critical patent/US20220399424A1/en
Publication of WO2022116289A1 publication Critical patent/WO2022116289A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the invention relates to the field of display, in particular to a pixel structure, a preparation method thereof, and a display device.
  • Particulate matter still cannot be completely eliminated in the AM-LCD preparation process. Due to the existence of the particulate matter, the proportion of poor circuit connections between different signal lines is relatively high. The defectiveness needs to be repaired by laser, but due to the accuracy of the machine and the pixel structure. The design leads to the risk of failure in the repair process, and leads to the side effect of bad lines. Usually, such defects will not appear in the early stage of use. After a period of use, the bad circuit will lead to bad lines on the client side, resulting in the risk of customer complaints. high, affecting product quality and customer satisfaction.
  • the purpose of the present invention is to solve the technical problem that the repairing of the second functional wiring in the existing pixel structure causes serious disconnection or short circuit of the circuit.
  • the present invention provides a pixel structure, comprising: a base layer; a first metal layer with a plurality of first functional traces spaced from each other, arranged on the surface of one side of the base layer; a second metal layer with a plurality of The second functional traces spaced apart from each other are arranged above the first metal layer in an insulating manner, wherein at least one second functional trace spans at least two first functional traces, and at least one of the first functional traces An edge is provided with a space gap for repairing the second functional wiring, and the forward projection of the second functional wiring on the first metal layer covers the corresponding spatial gap; the insulating layer, Each first functional trace is covered and the space gap is filled.
  • one of the second functional wirings spans two adjacent first functional wirings, and the space gap is arranged at the edges of the two first functional wirings and is oppositely arranged.
  • the second functional wiring is a voltage dividing electrode wiring
  • the first functional wiring is a common electrode wiring.
  • one of the second functional wirings spans two adjacent first functional wirings, and the space gap is provided at an edge of one of the two first functional wirings.
  • the second functional wiring is a source wiring and a drain wiring
  • the first functional wiring is a gate wiring
  • the pixel structure further includes: an active layer disposed on a surface of the insulating layer away from the first metal layer; a passivation layer disposed on a surface of the second metal layer away from the insulating layer and a pixel definition layer disposed on the surface of the passivation layer away from the second metal layer
  • the present invention also provides a method for preparing a pixel structure, which includes the following steps: providing a base layer; preparing a first metal layer on the upper surface of the base layer, and the first metal layer has a plurality of mutually spaced layers. a first functional wiring; a space gap is provided on at least one edge of the first functional wiring; an insulating layer is prepared on the upper surface of the first metal layer and in the space gap; A second metal layer is prepared on the upper surface, and the second metal layer has a plurality of second functional traces spaced from each other, wherein at least one second functional trace spans at least two first functional traces, and the second functional traces The forward projection of the trace on the first metal layer covers the corresponding space gap.
  • a layer of metal material is coated on the upper surface of the insulating layer, and the metal material is patterned to form a plurality of second metal layers.
  • functional wiring; the second functional wiring includes a source wiring and a drain wiring; the first functional wiring comprises a gate wiring; the drain wiring is on the first metal layer.
  • a layer of metal material is coated on the upper surface of the insulating layer, and the metal material is patterned to form a plurality of second metal layers.
  • functional wiring; the second functional wiring includes a voltage dividing electrode wiring; the second functional wiring includes a common electrode wiring; the voltage dividing electrode wiring is at the orthographic projection of the common electrode wiring The space gap is provided.
  • the present invention also provides a display device including the pixel structure as described above.
  • the technical effect of the present invention is that a space gap is provided at the two first functional lines of the first metal layer spanned by the second functional line in the second metal layer, and the space gap is the width of the second functional line. Repairing provides space to prevent short circuit between the first metal layer and the second metal layer during the repairing process, so as to ensure the smooth circuit of the pixel structure.
  • FIG. 1 is a cross-sectional view of the pixel structure according to Embodiment 1 or 2 of the present invention
  • FIG. 2 is a top view of the first metal layer according to Embodiment 1 of the present invention.
  • FIG. 3 is a top view of the second metal layer according to Embodiment 1 or 2 of the present invention.
  • FIG. 4 is a top view of the first metal layer according to Embodiment 2 of the present invention.
  • FIG. 5 is a flowchart of the method for preparing the pixel structure according to Embodiment 1 or 2 of the present invention.
  • Base layer 2. First metal layer; 3. Insulating layer; 4. Active layer; 5. Second metal layer; 6. Pixel definition layer; 7. Pixel electrode;
  • an embodiment of the present invention provides a pixel structure including a base layer 1 , a first metal layer 2 , an insulating layer 3 , an active layer 4 , a second metal layer 5 , and a pixel definition layer 6 and pixel electrode 7 and other film layers.
  • the base layer 1 is a base substrate, which plays a good supporting role, and is generally a glass substrate.
  • the first metal layer 2 is disposed on the upper surface of the base layer 1.
  • the first metal layer 2 has a plurality of first functional traces 21 spaced apart from each other.
  • the first functional traces 21 are gate traces.
  • the gate traces can be used as scan lines.
  • the insulating layer 3 is disposed on the upper surface of the first metal layer 2 , and the insulating layer 3 is made of insulating material and has a good insulating effect.
  • the active layer 4 is disposed on the upper surface of the insulating layer 3 and is made of semiconductor material, and the active layer 4 provides circuit support for the pixel structure.
  • the second metal layer 5 is disposed on the upper surface of the active layer 4 , and the second metal layer 5 has a plurality of second functional traces 51 spaced apart from each other, and is insulatingly disposed above the first metal layer 2 , wherein at least one second function line 51 is provided.
  • the wiring 51 spans at least two first functional wirings 21 , and a space gap 20 for repairing the second functional wiring 51 is provided at the edge of one of the at least two first functional wirings 21 , and this
  • the forward projection of the second functional trace 51 on the first metal layer 2 covers the corresponding space gap 20 (see FIG. 3 ).
  • the second functional trace 51 includes a source trace and a drain trace, and the forward projection of the drain trace on the first metal layer 2 covers the corresponding space gap 20 , and The space gap 20 is set at the edge of the first functional trace 21 in the first metal layer 2 (see FIG. 2 ), and the space gap 20 is reserved for the subsequent repair of the second functional trace 51 .
  • a space gap 20 is provided, and the insulating layer 3 can cover the first metal layer 2 to completely insulate the first metal layer 2 from other conductive layers, for example, the first functional trace 21 of the first metal layer 2 and the second metal layer 2
  • the second functional traces 51 of the layer 5 are completely insulated, which avoids a short circuit between the first functional traces 21 of the first metal layer 2 and the second functional traces 51 of the second metal layer 5 .
  • the pixel structure in this embodiment may further include film layers such as a passivation layer and a flat layer, which may cover the top of the second metal layer 5 and play a role of smoothing the surface of the film layer.
  • film layers such as a passivation layer and a flat layer, which may cover the top of the second metal layer 5 and play a role of smoothing the surface of the film layer.
  • the pixel definition layer 6 is arranged above the passivation layer and/or the flat layer, and plays a role in defining the size of the light-emitting layer.
  • the circuit structure can emit light after being driven.
  • the pixel electrode 7 is disposed in the through hole of the pixel definition layer 6 and above the light emitting layer, and the pixel electrode 7 also provides circuit support for the light emission of the light emitting layer.
  • the technical effect of the pixel structure in this embodiment is that a space is provided at the edge of one of the two first functional traces 21 of the first metal layer 2 spanned by the second functional trace 51 in the second metal layer 5 .
  • the gap 20 provides space for repairing the second functional wiring 51 to prevent a short circuit between the first metal layer 2 and the second metal layer 5 during the repair process, and ensure the circuit of the pixel structure is smooth.
  • this embodiment further provides a method for preparing a pixel structure, including steps S1 to S5.
  • the base layer 1 is a base substrate, which plays a good supporting role, and is generally a glass substrate.
  • a first metal layer 2 is prepared on the upper surface of the base layer 1. Specifically, a layer of metal material is coated on the upper surface of the base layer 1, and the metal material is patterned to form a plurality of first functional layers spaced from each other. Line 21, the first metal layer 2 is obtained.
  • the space gap 20 is located at the edge of one of the at least two first functional traces 21 (see FIG. 2), the two space gaps 20 at the edge of the first functional wiring 21 may be arranged at mutual dislocation (see FIG. 2 ).
  • the insulating layer 3 is prepared on the upper surface of the first metal layer 2 and in the space gap 20. Specifically, a layer of insulating material is coated on the upper surface of the first metal layer 2 and in the space gap 20.
  • the material is an inorganic material, and the inorganic material includes silicon oxide or silicon nitride or a multi-layer thin film structure, and has good insulating properties.
  • the first functional trace 21 is a gate trace
  • the second functional trace 51 includes a source trace and a drain trace
  • the drain trace is on the positive side of the first metal layer 2 .
  • the projection covers its corresponding space gap 20, and the space gap 20 is set at the edge of the first functional trace 21 in the first metal layer 2 (see FIG. 2).
  • the space gap 20 is used for the subsequent second function routing.
  • Line 51 fixes the reserved space.
  • the technical effect of the method for fabricating the pixel structure in this embodiment is that a space gap 20 is prepared at the two first functional wires 21 of the first metal layer 2 , and the space gap 20 is the second space in the second functional layer 5 .
  • the repairing of the functional traces 51 provides space to prevent a short circuit between the first metal layer 2 and the second metal layer 5 during the repairing process, so as to ensure the smooth circuit of the pixel structure.
  • This embodiment can also provide a display device including the pixel structure described above, to avoid a short circuit between the first metal layer 2 and the second metal layer 5 , and the space gap 20 provides a repair space for the disconnection of the second metal layer 5 , which can prevent the circuit breakage, improve the circuit safety performance of the display device, and ensure the yield of the display device.
  • an embodiment of the present invention provides a pixel structure including a base layer 1 , a first metal layer 2 , an insulating layer 3 , a second metal layer 5 , a pixel definition layer 6 and a pixel Electrode 7 and other film layers.
  • the base layer 1 is a base substrate, which plays a good supporting role, and is generally a glass substrate.
  • the first metal layer 2 is disposed on the upper surface of the base layer 1 , and the first metal layer 2 has a plurality of first functional traces 21 spaced apart from each other.
  • the first functional traces 21 are common electrode traces.
  • the insulating layer 3 is disposed on the upper surface of the first metal layer 2 , and the insulating layer 3 is made of insulating material and has a good insulating effect.
  • the second metal layer 5 is disposed on the upper surface of the active layer 4 , and the second metal layer 5 has a plurality of second functional traces 51 spaced apart from each other, and is insulatingly disposed above the first metal layer 2 , wherein at least one second function line 51 is provided.
  • the wiring 51 spans at least two first functional wirings 21 , and a space gap 20 for repairing the second functional wiring 51 is provided at the edges of the at least two first functional wirings 21 , and the second functional wiring 51 is The forward projection of the functional trace 51 on the first metal layer 2 covers the corresponding space gap 20 (see FIG. 3 ).
  • the first functional wiring 21 is a common electrode wiring
  • the second functional wiring 51 is a voltage dividing electrode wiring
  • the voltage dividing electrode wiring and the common electrode wiring have an overlapping portion
  • the forward projection of the overlapping portion on the first metal layer 2 covers the corresponding space gap 20
  • the space gap 20 is set at the edges of the two first functional traces 21 in the first metal layer 2
  • the two space gaps 20 are disposed opposite to each other (see FIG. 4 ), and the space gap 20 is a reserved space for the subsequent repair of the second functional wiring 51 .
  • a space gap 20 is provided, and the insulating layer 3 can cover the first metal layer 2 to completely insulate the first metal layer 2 from other conductive layers, for example, the first functional trace 21 of the first metal layer 2 and the second metal layer 2
  • the second functional traces 51 of the layer 5 are completely insulated, which avoids a short circuit between the first functional traces 21 of the first metal layer 2 and the second functional traces 51 of the second metal layer 5 .
  • the pixel structure in this embodiment may further include film layers such as a passivation layer and a flat layer, which may cover the top of the second metal layer 5 and play a role of smoothing the surface of the film layer.
  • film layers such as a passivation layer and a flat layer, which may cover the top of the second metal layer 5 and play a role of smoothing the surface of the film layer.
  • the pixel definition layer 6 is arranged above the passivation layer and/or the flat layer, and plays a role in defining the size of the light-emitting layer.
  • the circuit structure can emit light after being driven.
  • the pixel electrode 7 is disposed in the through hole of the pixel definition layer 6 and above the light emitting layer, and the pixel electrode 7 also provides circuit support for the light emission of the light emitting layer.
  • the technical effect of the pixel structure in this embodiment is that the space gap 20 is provided at the edges of the two first functional traces 21 of the first metal layer 2 spanned by the second functional traces 51 in the second metal layer 5 .
  • the space gap 20 provides space for the repair of the second functional wiring 51 to prevent a short circuit between the first metal layer 2 and the second metal layer 5 during the repair process, and to ensure the smooth circuit of the pixel structure.
  • this embodiment further provides a method for preparing a pixel structure, including steps S1 to S5.
  • the base layer 1 is a base substrate, which plays a good supporting role, and is generally a glass substrate.
  • a first metal layer 2 is prepared on the upper surface of the base layer 1. Specifically, a layer of metal material is coated on the upper surface of the base layer 1, and the metal material is patterned to form a plurality of first functional layers spaced from each other. Line 21, the first metal layer 2 is obtained.
  • the space gaps 20 are located at the edges of at least two first functional traces 21 (see FIG. 2 ) , the two space gaps 20 at the edge of the first functional wiring 21 may be disposed opposite to each other (see FIG. 4 ).
  • the insulating layer 3 is prepared on the upper surface of the first metal layer 2 and in the space gap 20. Specifically, a layer of insulating material is coated on the upper surface of the first metal layer 2 and in the space gap 20.
  • the material is an inorganic material, and the inorganic material includes silicon oxide or silicon nitride or a multi-layer thin film structure, and has good insulating properties.
  • S5 Prepare film layers such as the second metal layer 5 on the upper surface of the insulating layer 3. Specifically, a layer of metal material is coated on the upper surface of the insulating layer 3, and after patterning, a number of second functional layers spaced apart from each other are formed. Line 51, wherein at least one second functional line 51 spans at least two of the first functional lines 21, and the forward projection of the second functional line 51 on the first metal layer 2 covers its corresponding space gap 20,
  • the first functional wiring 21 is a common electrode wiring
  • the second functional wiring 51 is a voltage electrode wiring
  • the overlapping portion of the voltage dividing electrode wiring at the common electrode wiring is It is a space gap 20
  • the space gap 20 is set at the edges of the two first functional traces 21 in the first metal layer 2, and the two space gaps 20 are arranged opposite to each other (see FIG. 4).
  • the space gap 20 is for The subsequent second function wiring 51 repairs the reserved space.
  • the technical effect of the method for fabricating the pixel structure in this embodiment is that a space gap 20 is prepared at the two first functional wires 21 of the first metal layer 2 , and the space gap 20 is the second space in the second functional layer 5 .
  • the repairing of the functional traces 51 provides space to prevent a short circuit between the first metal layer 2 and the second metal layer 5 during the repairing process, so as to ensure the smooth circuit of the pixel structure.

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Abstract

本发明公开了一种像素结构及其制备方法、显示装置，所述像素结构包括基层、第一金属层、绝缘层和第二金属层；所述第一金属层具有若干相互间隔的第一功能走线；所述第二金属层具有若干相互间隔的第二功能走线，其中至少一第二功能走线横跨至少两根第一功能走线，在这至少两根第一功能走线的至少一个边缘设置空间缺口。

Description

像素结构及其制备方法、显示装置 技术领域
本发明涉及显示领域，特别涉及一种像素结构及其制备方法、显示装置。
 背景技术
AM-LCD制备过程中颗粒物仍无法完全消除，由于所述颗粒物的存在，导致不同信号线路间电路连接不良的比例较高，所述不良均需要进行镭射修补，但由于机台精度和像素结构的设计导致修补过程中存在失败风险，并导致线不良的副作用，通常该类不良在使用初期并不会表现出来，在使用一段时间后所述电路不良会导致客端发生线不良，导致客诉风险高，影响产品品质及客户满意度。
 技术问题
本发明的目的在于，解决现有的像素结构中第二功能走线的修补导致线路断线或短路问题严重的技术问题。
 技术解决方案
为实现上述目的，本发明提供一种像素结构，包括：基层；第一金属层，具有若干相互间隔的第一功能走线，设于所述基层一侧的表面；第二金属层，具有若干相互间隔的第二功能走线，绝缘地设于所述第一金属层的上方，其中至少一第二功能走线横跨至少两根第一功能走线，在这些第一功能走线的至少一个边缘设置有用以修补这一第二功能走线的空间缺口，且这一第二功能走线在所述第一金属层上的正向投影覆盖其所对应的所述空间缺口；绝缘层，包覆每一第一功能走线且填充所述空间缺口。
进一步地，其中一第二功能走线横跨两根相邻的第一功能走线，所述空间缺口设置在这两根第一功能走线的边缘，且相对设置。
进一步地，所述第二功能走线为分压电极走线，所述第一功能走线为公共电极走线。
进一步地，其中一第二功能走线横跨两根相邻的第一功能走线，所述空间缺口设置在这两根第一功能走线之一的边缘。
进一步地，所述第二功能走线为源极走线和漏极走线，所述第一功能走线为栅极走线。
进一步地，所述像素结构还包括：有源层，设于所述绝缘层远离所述第一金属层一侧的表面；钝化层，设于所述第二金属层远离所述绝缘层一侧的表面；以及像素定义层，设于所述钝化层远离所述第二金属层一侧的表面
为实现上述目的，本发明还提供一种像素结构的制备方法，包括以下步骤：提供一基层；在所述基层的上表面制备出第一金属层，所述第一金属层具有若干相互间隔的第一功能走线；在所述第一功能走线的至少一个边缘设置空间缺口；在所述第一金属层的上表面以及所述空间缺口内制备出绝缘层；以及在所述绝缘层的上表面制备出第二金属层，所述第二金属层具有若干相互间隔的第二功能走线，其中至少一第二功能走线横跨至少两根第一功能走线，所述第二功能走线在所述第一金属层上的正向投影覆盖其所对应的所述空间缺口。
进一步地，在所述绝缘层的上表面制备出第二金属层的步骤中，在所述绝缘层的上表面涂布一层金属材料，对所述金属材料进行图案化处理，形成若干第二功能走线；所述第二功能走线包括源极走线和漏极走线；所述第一功能走线包括栅极走线；所述漏极走线在所述第一金属层上的正向投影覆盖其所对应的所述空间缺口。
进一步地，在所述绝缘层的上表面制备出第二金属层的步骤中，在所述绝缘层的上表面涂布一层金属材料，对所述金属材料进行图案化处理，形成若干第二功能走线；所述第二功能走线包括分压电极走线；所述第二功能走线包括公共电极走线；所述分压电极走线在所述公共电极走线上的正投影处设有所述空间缺口。
为实现上述目的，本发明还提供一种显示装置，包括如前文所述的像素结构。
 有益效果
本发明的技术效果在于，在第二金属层内的第二功能走线横跨的第一金属层的两条第一功能走线处设置空间缺口，空间缺口为所述第二功能走线的修补提供空间，防止在修补过程中第一金属层与第二金属层之间发生短路现象，保证像素结构的电路畅通。
 附图说明
图1为本发明实施例1或2所述像素结构的截面图；
图2为本发明实施例1所述第一金属层的俯视图；
图3为本发明实施例1或2所述第二金属层的俯视图；
图4为本发明实施例2所述第一金属层的俯视图；
图5为本发明实施例1或2所述像素结构的制备方法的流程图。
部分组件标识如下：
1、基层；2、第一金属层；3、绝缘层；4、有源层；5、第二金属层；6、像素定义层；7、像素电极；
20、空间缺口；21、第一功能走线；
51、第二功能走线。
 本发明的实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
下文的公开提供了许多不同的实施方式或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
实施例1
具体的，请参阅图1至图3，本发明实施例提供一种像素结构，包括基层1、第一金属层2、绝缘层3、有源层4、第二金属层5、像素定义层6和像素电极7等膜层。
基层1为衬底基板，起到良好的支撑作用，一般为玻璃基板。
第一金属层2设于基层1的上表面，第一金属层2具有若干相互间隔的第一功能走线21，在本实施例中，第一功能走线21为栅极走线，所述栅极走线可用作扫描线。
绝缘层3设于第一金属层2的上表面，绝缘层3的材质为绝缘材料，具有良好的绝缘效果。
有源层4设于绝缘层3的上表面，其材质为半导体材料，有源层4给像素结构提供电路支持。
第二金属层5设于有源层4的上表面，第二金属层5具有若干相互间隔的第二功能走线51，绝缘地设于第一金属层2的上方，其中至少一第二功能走线51横跨至少两根第一功能走线21，在这至少两根第一功能走线21之一的边缘设置有用以修补这一第二功能走线51的空间缺口20，且这一第二功能走线51在第一金属层2上的正向投影覆盖其所对应的空间缺口20（参见图3）。
在本实施例中，第二功能走线51包括源极走线和漏极走线，所述漏极走线在第一金属层2上的正向投影覆盖其所对应的空间缺口20，且空间缺口20设于第一金属层2内的第一功能走线21的边缘处（参见图2），空间缺口20是给后续的第二功能走线51修补预留空间。
同时，设置空间缺口20，绝缘层3可包覆第一金属层2，使第一金属层2与其他导电层完全绝缘，例如，第一金属层2的第一功能走线21与第二金属层5的第二功能走线51之间完全处于绝缘状态，避免了第一金属层2的第一功能走线21与第二金属层5的第二功能走线51之间产生短路的现象。
本实施例所述像素结构还可包括钝化层和平坦层等膜层，可覆盖于第二金属层5的上方，起到平滑膜层表面的作用。
像素定义层6设于所述钝化层和/或所述平坦层的上方，起到定义发光层大小的作用，发光层可设于像素定义层6上开设的通孔内，获得像素结构的电路结构驱动后可发光。
像素电极7设于像素定义层6的通孔内，且设于所述发光层的上方，像素电极7同时为所述发光层的发光提供电路支持。
本实施例所述像素结构的技术效果在于，在第二金属层5内的第二功能走线51横跨的第一金属层2的两条第一功能走线21之一的边缘处设置空间缺口20，空间缺口20为第二功能走线51的修补提供空间，防止在修补过程中第一金属层2与第二金属层5之间发生短路现象，保证像素结构的电路畅通。
如图5所示，本实施例还提供一种像素结构的制备方法，包括步骤S1~S5。
S1 提供一基层，基层1为衬底基板，起到良好的支撑作用，一般为玻璃基板。
S2 在基层1的上表面制备出第一金属层2，具体地，在基层1的上表面涂布一层金属材料，对所述金属材料进行图案化处理，形成若干相互间隔的第一功能走线21，获得第一金属层2。
S3 在第一金属层2上进行挖孔处理，形成若干空间缺口20，可采用蚀刻方式形成空间缺口20，空间缺口20设于至少两根第一功能走线21之一的边缘处（参见图2），在第一功能走线21的边缘处的两个空间缺口20可为相互错位设置（参见图2）。
S4 在第一金属层2的上表面以及空间缺口20内制备出绝缘层3，具体地，才第一金属层2的上表面以及空间缺口20内涂布一层绝缘材料，所述绝缘材料的材质为无机材料，所述无机材料包括硅的氧化物或硅的氮化物或是多层薄膜结构，具有良好的绝缘性能。
S5 在绝缘层3的上表面制备出有源层4和第二金属层5等膜层，具体地，在绝缘层3的上表面涂布一层半导体材料，沟道处理后形成有源层4，在有源层4的上表面涂布一层金属材料，图案化处理后，形成若干相互间隔的第二功能走线51，其中至少一第二功能走线51横跨至少两根所述第一功能走线21，第二功能走线51在第一金属层2上的正向投影覆盖其所对应的空间缺口20，
在本实施例中，第一功能走线21为栅极走线，第二功能走线51包括源极走线和漏极走线，所述漏极走线在第一金属层2上的正向投影覆盖其所对应的空间缺口20，且空间缺口20设于第一金属层2内的第一功能走线21的边缘处（参见图2），空间缺口20是给后续的第二功能走线51修补预留空间。
本实施例所述像素结构的制备方法的技术效果在于，在第一金属层2的两条第一功能走线21处制备出空间缺口20，空间缺口20为第二功能层5内的第二功能走线51的修补提供空间，防止在修补过程中第一金属层2与第二金属层5之间发生短路现象，保证像素结构的电路畅通。
本实施例还可提供一显示装置，包括前文所述的像素结构，避免第一金属层2与第二金属层5之间的短路，空间缺口20给第二金属层5断线处提供修补空间，可防止其断路，提高显示装置的电路安全性能，保证显示装置的良率。
实施例2
具体的，请参阅图1、图3、图4，本发明实施例提供一种像素结构，包括基层1、第一金属层2、绝缘层3、第二金属层5、像素定义层6和像素电极7等膜层。
基层1为衬底基板，起到良好的支撑作用，一般为玻璃基板。
第一金属层2设于基层1的上表面，第一金属层2具有若干相互间隔的第一功能走线21，在本实施例中，第一功能走线21为公共电极走线。
绝缘层3设于第一金属层2的上表面，绝缘层3的材质为绝缘材料，具有良好的绝缘效果。
第二金属层5设于有源层4的上表面，第二金属层5具有若干相互间隔的第二功能走线51，绝缘地设于第一金属层2的上方，其中至少一第二功能走线51横跨至少两根第一功能走线21，在这至少两根第一功能走线21的边缘设置有用以修补这一第二功能走线51的空间缺口20，且这一第二功能走线51在第一金属层2上的正向投影覆盖其所对应的空间缺口20（参见图3）。
在本实施例中，第一功能走线21为公共电极走线，第二功能走线51为分压电极走线，所述分压电极走线和所述公共电极走线具有一重叠部，所述重叠部在第一金属层2上的正向投影覆盖其所对应的空间缺口20，且空间缺口20设于第一金属层2内的两条第一功能走线21的边缘处，且这两个空间缺口20相对设置（参见图4），空间缺口20是给后续的第二功能走线51修补预留空间。
同时，设置空间缺口20，绝缘层3可包覆第一金属层2，使第一金属层2与其他导电层完全绝缘，例如，第一金属层2的第一功能走线21与第二金属层5的第二功能走线51之间完全处于绝缘状态，避免了第一金属层2的第一功能走线21与第二金属层5的第二功能走线51之间产生短路的现象。
本实施例所述像素结构还可包括钝化层和平坦层等膜层，可覆盖于第二金属层5的上方，起到平滑膜层表面的作用。
像素定义层6设于所述钝化层和/或所述平坦层的上方，起到定义发光层大小的作用，发光层可设于像素定义层6上开设的通孔内，获得像素结构的电路结构驱动后可发光。
像素电极7设于像素定义层6的通孔内，且设于所述发光层的上方，像素电极7同时为所述发光层的发光提供电路支持。
本实施例所述像素结构的技术效果在于，在第二金属层5内的第二功能走线51横跨的第一金属层2的两条第一功能走线21的边缘处设置空间缺口20，空间缺口20为第二功能走线51的修补提供空间，防止在修补过程中第一金属层2与第二金属层5之间发生短路现象，保证像素结构的电路畅通。
如图5所示，本实施例还提供一种像素结构的制备方法，包括步骤S1~S5。
S1 提供一基层，基层1为衬底基板，起到良好的支撑作用，一般为玻璃基板。
S2 在基层1的上表面制备出第一金属层2，具体地，在基层1的上表面涂布一层金属材料，对所述金属材料进行图案化处理，形成若干相互间隔的第一功能走线21，获得第一金属层2。
S3 在第一金属层2上进行挖孔处理，形成若干空间缺口20，可采用蚀刻方式形成空间缺口20，空间缺口20设于至少两根第一功能走线21的边缘处（参见图2），在第一功能走线21的边缘处的两个空间缺口20可为相互相对设置（参见图4）。
S4 在第一金属层2的上表面以及空间缺口20内制备出绝缘层3，具体地，才第一金属层2的上表面以及空间缺口20内涂布一层绝缘材料，所述绝缘材料的材质为无机材料，所述无机材料包括硅的氧化物或硅的氮化物或是多层薄膜结构，具有良好的绝缘性能。
S5 在绝缘层3的上表面制备出第二金属层5等膜层，具体地，在绝缘层3的上表面涂布一层金属材料，图案化处理后，形成若干相互间隔的第二功能走线51，其中至少一第二功能走线51横跨至少两根所述第一功能走线21，第二功能走线51在第一金属层2上的正向投影覆盖其所对应的空间缺口20，
在本实施例中，第一功能走线21为公共电极走线，第二功能走线51为压电极走线，所述分压电极走线在所述公共电极走线处的重叠部分即为空间缺口20，且空间缺口20设于第一金属层2内的两条第一功能走线21的边缘处，且这两个空间缺口20相对设置（参见图4），空间缺口20是给后续的第二功能走线51修补预留空间。
本实施例所述像素结构的制备方法的技术效果在于，在第一金属层2的两条第一功能走线21处制备出空间缺口20，空间缺口20为第二功能层5内的第二功能走线51的修补提供空间，防止在修补过程中第一金属层2与第二金属层5之间发生短路现象，保证像素结构的电路畅通。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本发明实施例所提供的一种像素结构及其制备方法、显示装置进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例的技术方案的范围。

Claims (10)

  1. 一种像素结构，其包括：
    基层；
    第一金属层，具有若干相互间隔的第一功能走线，设于所述基层一侧的表面；
    第二金属层，具有若干相互间隔的第二功能走线，绝缘地设于所述第一金属层的上方，其中至少一第二功能走线横跨至少两根第一功能走线，在这些第一功能走线的至少一个边缘设置有用以修补这一第二功能走线的空间缺口，且这一第二功能走线在所述第一金属层上的正向投影覆盖其所对应的所述空间缺口；
    绝缘层，包覆每一第一功能走线且填充所述空间缺口。
  2. 如权利要求1所述的像素结构，其中，其中一第二功能走线横跨两根相邻的第一功能走线，所述空间缺口设置在这两根第一功能走线的边缘，且相对设置。
  3. 如权利要求2所述的像素结构，其中，所述第二功能走线为分压电极走线，所述第一功能走线为公共电极走线。
  4. 如权利要求1所述的像素结构，其中，其中一第二功能走线横跨两根相邻的第一功能走线，所述空间缺口设置在这两根第一功能走线之一的边缘。
  5. 如权利要求4所述的像素结构，其中，所述第二功能走线为源极走线和漏极走线，所述第一功能走线为栅极走线。
  6. 如权利要求5所述的像素结构，其还包括：
    有源层，设于所述绝缘层远离所述第一金属层一侧的表面；
    钝化层，设于所述第二金属层远离所述绝缘层一侧的表面；以及
    像素定义层，设于所述钝化层远离所述第二金属层一侧的表面。
  7. 一种像素结构的制备方法，其包括以下步骤：
    提供一基层；
    在所述基层的上表面制备出第一金属层，所述第一金属层具有若干相互间隔的第一功能走线；
    在所述第一功能走线的至少一个边缘设置空间缺口；
    在所述第一金属层的上表面以及所述空间缺口内制备出绝缘层；以及
    在所述绝缘层的上表面制备出第二金属层，所述第二金属层具有若干相互间隔的第二功能走线，其中至少一第二功能走线横跨至少两根第一功能走线，所述第二功能走线在所述第一金属层上的正向投影覆盖其所对应的所述空间缺口。
  8. 如权利要求7所述的像素结构的制备方法，其中，在所述绝缘层的上表面制备出第二金属层的步骤中，
    在所述绝缘层的上表面涂布一层金属材料，对所述金属材料进行图案化处理，形成若干第二功能走线；
    所述第二功能走线包括源极走线和漏极走线；
    所述第一功能走线包括栅极走线；
    所述漏极走线在所述第一金属层上的正向投影覆盖其所对应的所述空间缺口。
  9. 如权利要求7所述的像素结构的制备方法，其中，在所述绝缘层的上表面制备出第二金属层的步骤中，
    在所述绝缘层的上表面涂布一层金属材料，对所述金属材料进行图案化处理，形成若干第二功能走线；
    所述第二功能走线包括分压电极走线；
    所述第二功能走线包括公共电极走线；
    所述分压电极走线在所述公共电极走线上的正投影处设有所述空间缺口。
  10. 一种显示装置，其包括如权利要求1所述的像素结构。
PCT/CN2020/137541 2020-12-02 2020-12-18 像素结构及其制备方法、显示装置 WO2022116289A1 (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104485337A (zh) * 2014-09-10 2015-04-01 深圳市华星光电技术有限公司 薄膜晶体管阵列基板及薄膜晶体管阵列基板的制备方法
CN107579078A (zh) * 2017-08-31 2018-01-12 上海天马有机发光显示技术有限公司 显示面板及其制造方法和显示装置
CN108183125A (zh) * 2017-12-28 2018-06-19 武汉华星光电半导体显示技术有限公司 有机发光二极管显示面板
CN108649039A (zh) * 2018-06-01 2018-10-12 深圳市华星光电技术有限公司 阵列基板、显示面板和显示装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100495182C (zh) * 2004-02-04 2009-06-03 友达光电股份有限公司 主动式阵列液晶显示器及其制作方法
CN104898333B (zh) * 2015-06-17 2017-07-28 合肥鑫晟光电科技有限公司 一种阵列基板及其线不良维修方法、显示装置
US10446632B2 (en) * 2017-12-28 2019-10-15 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Organic light-emitting diode display panel
KR20200087912A (ko) * 2019-01-11 2020-07-22 삼성디스플레이 주식회사 유기 발광 표시 장치 및 유기 발광 표시 장치의 제조 방법
CN210403730U (zh) * 2019-10-22 2020-04-24 北京京东方技术开发有限公司 显示面板及阵列基板
CN115244599B (zh) * 2020-03-11 2023-08-01 夏普株式会社 显示装置
CN111613624B (zh) * 2020-05-18 2022-08-05 武汉华星光电半导体显示技术有限公司 阵列基板及其制备方法
CN112002715B (zh) * 2020-09-15 2023-03-31 武汉华星光电技术有限公司 阵列基板及显示面板

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104485337A (zh) * 2014-09-10 2015-04-01 深圳市华星光电技术有限公司 薄膜晶体管阵列基板及薄膜晶体管阵列基板的制备方法
CN107579078A (zh) * 2017-08-31 2018-01-12 上海天马有机发光显示技术有限公司 显示面板及其制造方法和显示装置
CN108183125A (zh) * 2017-12-28 2018-06-19 武汉华星光电半导体显示技术有限公司 有机发光二极管显示面板
CN108649039A (zh) * 2018-06-01 2018-10-12 深圳市华星光电技术有限公司 阵列基板、显示面板和显示装置

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