WO2011131072A1 - 液晶面板及其制造方法和维修方法 - Google Patents

液晶面板及其制造方法和维修方法 Download PDF

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Publication number
WO2011131072A1
WO2011131072A1 PCT/CN2011/072107 CN2011072107W WO2011131072A1 WO 2011131072 A1 WO2011131072 A1 WO 2011131072A1 CN 2011072107 W CN2011072107 W CN 2011072107W WO 2011131072 A1 WO2011131072 A1 WO 2011131072A1
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WO
WIPO (PCT)
Prior art keywords
lead
chip
array substrate
repair line
gate
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Application number
PCT/CN2011/072107
Other languages
English (en)
French (fr)
Inventor
秦纬
彭志龙
Original Assignee
北京京东方光电科技有限公司
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Application filed by 北京京东方光电科技有限公司 filed Critical 北京京东方光电科技有限公司
Priority to US13/381,022 priority Critical patent/US8848127B2/en
Publication of WO2011131072A1 publication Critical patent/WO2011131072A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1306—Details
    • G02F1/1309—Repairing; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals

Definitions

  • Liquid crystal panel manufacturing method thereof and maintenance method
  • Embodiments of the present invention relate to a liquid crystal panel for a thin film transistor liquid crystal display (TFT-LCD). Background technique
  • the leads on the array substrate ie, the array substrate leads, including the gate leads, the data leads, etc.
  • the driving chip assembly ie, the chip leads
  • the driver chip component can be a thin film chip (also known as a chip on film, COF, Chip On Film) or a chip on glass (COG, Chip On Glass).
  • the poor disconnection (ie, poor Open) of the connection between the driver chip component and the array substrate is a common defect.
  • the disconnection position it can be divided into three categories: 1.
  • the disconnection of the array substrate leads mainly Caused by dust in the array process, crushing of foreign matter in the process of forming a box, water vapor corrosion of the post-engineering, etc. 2.
  • Broken wire of the chip lead is mainly caused by scratching of the edge of the thin film driving chip component and the glass substrate;
  • the disconnection of the electrical connection position between the lead and the array substrate lead is mainly caused by metal corrosion at the position of the via hole, dust, loss of conductive particles, and the like. If the above various disconnection failures are not repairable, the liquid crystal panel will become a waste product.
  • 1 is a conventional repair structure of a pixel region with poor disconnection, in which the pixel area repair line 1 surrounds the pixel area, and the pixel area repair line 1 overlaps the gate lead 3 and the data lead 2.
  • the gate leads 3 and the data leads 2 intersect within the pixel regions to define a matrix of pixels distributed in a matrix.
  • the soldering 5 can be performed at the overlapping position of the pixel area repair line 1 and the data lead 2, so that the data line signal of the disconnected portion is transmitted through the pixel area repair line 1.
  • An embodiment of the present invention provides a liquid crystal panel comprising: a driving chip assembly having a chip lead and a chip repair line, the chip repair line overlapping the chip lead but insulated; the array substrate having the array substrate lead and An array substrate repair line, the array substrate repair line is overlapped with the array substrate lead but insulated; wherein the driving chip component is mounted on the array substrate, and the array substrate lead is electrically connected to the corresponding chip lead The two ends of the chip repair line are electrically connected to the two ends of the corresponding array substrate repair line.
  • Another embodiment of the present invention provides a method of manufacturing a liquid crystal panel, comprising the steps of: forming an array substrate lead and an array substrate repair line on an array substrate, wherein the array substrate repair line overlaps the array substrate lead But insulating; forming a chip lead and a chip repair line on the driving chip component, wherein the chip repairing line overlaps but is insulated from the chip lead; mounting the driving chip component on the array substrate to make the array Both ends of the substrate repair line are electrically connected to the opposite ends of the corresponding chip repair line, so that the array substrate leads are electrically connected to the chip leads.
  • Another embodiment of the present invention provides a method of repairing a disconnection failure of a connection position of a driving chip component of a liquid crystal panel as described above.
  • FIG. 1 is a front view showing a maintenance structure of a conventional pixel panel of a liquid crystal panel.
  • FIG. 2 is a schematic view showing a maintenance method when a pixel region of the liquid crystal panel of FIG. 1 is broken.
  • 3 is a schematic plan view showing a connection position of a driving chip component of a liquid crystal panel according to Embodiment 1 of the present invention.
  • Figure 4 is a schematic cross-sectional view of the A-A position in Figure 3.
  • Fig. 5 is a front elevational view showing the connection position of a driving chip component of a liquid crystal panel according to a second embodiment of the present invention.
  • Fig. 6 is a front elevational view showing the connection position of a driving chip component of a liquid crystal panel according to a third embodiment of the present invention.
  • FIG. 7 is a front view showing the structure of a liquid crystal panel according to Embodiment 4 of the present invention.
  • FIG. 8 is a schematic front view showing the connection position of the driving chip assembly of the array substrate after the step 1 is completed in the method for fabricating the liquid crystal panel according to the fifth embodiment of the present invention.
  • FIG. 9 is a schematic front view showing the connection position of the driving chip assembly of the array substrate after the step 3 is completed in the method for fabricating the liquid crystal panel according to the fifth embodiment of the present invention.
  • FIG. 10 is a schematic front view showing the connection position of the driving chip assembly of the array substrate after the step 4 of the method for manufacturing the liquid crystal panel according to the fifth embodiment of the present invention.
  • FIG. 11 is a front view showing the connection position of the driving chip assembly of the array substrate after the step 5 of the method for fabricating the liquid crystal panel of the fifth embodiment of the present invention.
  • FIG. 12 is a front view showing the connection position of a driving chip component of the driving chip component after the step 8 of the liquid crystal panel manufacturing method of the fifth embodiment of the present invention is completed.
  • Fig. 13 is a view showing a maintenance method of a disconnection of a disconnection position of a driving chip component of a liquid crystal panel according to an eighth embodiment of the present invention.
  • Fig. 14 is a view showing a maintenance method of a defective gate lead disconnection at a connection position of a driving chip component of a liquid crystal panel according to Embodiment 9 of the present invention.
  • Fig. 15 is a view showing a maintenance method of a chip lead disconnection failure in a connection position of a driving chip component of a liquid crystal panel according to a ninth embodiment of the present invention.
  • Fig. 16 is a view showing a maintenance method of a disconnection failure at a position where a gate lead of a driving chip component of a liquid crystal panel of the ninth embodiment of the present invention is electrically connected to a chip lead.
  • the liquid crystal panel of the embodiment of the present invention includes a driving chip component having chip leads and an array substrate having array substrate leads, and the chip leads are electrically connected to the corresponding array substrate leads.
  • the liquid crystal panel further has a repair line including a chip repair line on the driving chip assembly that overlaps but is insulated from the chip lead, and an array substrate repair line on the array substrate that overlaps but is insulated from the array substrate lead, wherein Both ends of the chip repair line are electrically connected to both ends of the corresponding array substrate repair line.
  • the liquid crystal panel of the embodiment of the invention has a chip repair line and an array substrate repair line, and the overlapping position of the repair line and the corresponding lead wire is performed; t is connected early, and the disconnection fault of the connection position of the driving chip component of the liquid crystal panel can be performed. service.
  • Embodiment 1 3 and 4 illustrate a liquid crystal panel including a driving chip assembly and an array substrate in accordance with an embodiment of the present invention.
  • FIG. 3 is a schematic plan view showing a connection position of a driving chip component of a liquid crystal panel according to Embodiment 1 of the present invention.
  • Figure 4 is a schematic cross-sectional view of the A-A position in Figure 3.
  • the driver chip assembly 7 includes a chip substrate 71 having a chip (not shown) and a chip repair line 9 thereon.
  • the chip repair line 9 is also covered with a chip insulating layer 16 (Fig. 4).
  • the chip insulating layer 16 has a chip lead 12 connected to the chip, and the chip repair line 9 overlaps the chip lead 12 (Fig. 3), and both pass The intermediate spaced chip insulation layer 16 is insulated.
  • a via hole 191 is formed in the chip insulating layer 16 above the end of the chip repair line 9, thereby exposing the end of the chip repair line 9.
  • the driver chip assembly 7 can also adopt such a structure: the chip lead 12 is below the chip insulating layer 16 and part of it can be exposed through the via hole, and the chip repair line 9 is above the chip insulating layer 16, the chip repair line 9 and the chip The leads 12 overlap and the two are still insulated by the intervening chip insulation layer 16.
  • the array substrate leads include a gate lead 3 and a data lead (not shown), and the gate lead 3 is electrically connected to the chip lead 12 on the driving chip assembly 7.
  • the driving chip component 7 is a gate driving chip component;
  • the gate wiring 3 has a gate insulating layer 14, and the data wiring and the gate wiring repairing wire 8 are located on the gate insulating layer 14 and are in the same layer, which can be the same time.
  • the gate lead repair line 8 overlaps the gate lead 3 and is insulated from the gate lead 3 by the gate insulating layer 14;
  • a protective layer 13 may be formed on the gate insulating layer 14 and the gate lead repair line 8.
  • the protective layer 13 forms a via 101 at the end of the gate lead repair line 8, and the via 101 is connected to the gate lead repair line 8.
  • the conductive electrode 11 has an anisotropic conductive adhesive 15 on the conductive electrode 11, and the anisotropic conductive adhesive 15 is connected to the chip repair line 9 on the driving chip assembly 7, thereby realizing the chip repair line 9 and the gate lead repair line 8. Electrical connection.
  • a via hole 111 is formed in the protective layer 13, and the via hole 111 has a conductive electrode 11 connected to the gate lead 3, and the conductive electrode 11 has an anisotropic conductive paste 15 thereon.
  • the isotropic conductive paste 15 is connected to the chip leads 12 on the driving chip package 7, thereby achieving electrical connection between the gate leads 3 and the chip leads 12.
  • the liquid crystal panel of this embodiment has a liquid crystal panel similar to that of the first embodiment.
  • the structure is different in that the gate lead repair line 8 over the array substrate 20 includes two overlapping portions 8-1 which are overlapped with the gate lead 3 but insulated, and the two ends of the two overlapping portions 8-1 are respectively connected.
  • the common end is electrically connected to the chip repair line 9; at this time, if the open circuit occurs between the two overlapping portions 8-1 (that is, on the array substrate lead), the repair; t early is only in the array
  • the substrate 20 is carried out, so that maintenance operations such as soldering on the driving chip component 7 can be avoided, and the possibility of damaging the driving chip component 7 due to soldering can be reduced.
  • the liquid crystal panel of the present embodiment has a structure similar to that of the liquid crystal panels of the first embodiment and the second embodiment, except that the present embodiment is directed to the data driving chip component in the liquid crystal panel and the data line on the array substrate.
  • the service line is a data lead repair line 18, which is in the same layer as the gate lead (not shown), and can be formed by the same patterning process;
  • the data lead repair line 18 is located at the data lead 2 is insulated from the data lead 2 by a gate insulating layer; wherein the electrical connection between the data lead repair line 18 and the chip repair line 9 on the driving chip component 7 can also pass through the via 101, the conductive electrode 11, and the conductive paste 15. Way to achieve.
  • the driver chip component 7 is a data driving chip component.
  • the data lead repair line 18 on the array substrate in this embodiment may further include two overlapping portions which are overlapped with the data lead 2 but insulated, and the two ends of the two overlapping portions are respectively connected. The common end is electrically connected to the chip repair line 9.
  • the repair; t is performed only on the array substrate, thereby avoiding soldering on the data driving chip assembly. Maintenance operations reduce the possibility of driving the chip assembly due to solder damage.
  • the liquid crystal panel of the present embodiment has a structure similar to that of the liquid crystal panels of Embodiments 1 to 3, which has both a gate lead repair line for a gate lead and a data lead repair for a data lead.
  • the line is a combination of the first embodiment and the third embodiment.
  • the array substrate 20 includes a plurality of laterally extending gate leads 3 and a plurality of longitudinally extending plurality of data arches 2 intersecting within the pixel regions to define a matrix array of pixels.
  • a plurality of driving chip assemblies 7 are disposed on the left side of the array substrate 20 for driving the gate lines 3; and a plurality of driving chip assemblies 7 are disposed on the upper side of the array substrate 20 for the data lines 3.
  • Each of the driver chip assemblies 7 has a corresponding driver chip 72, chip leads 12 and chip repair lines 9.
  • the gate lead repair line 8 and the data lead 2 are in the same layer, and can be formed by the same patterning process; and the data lead repair line 18 and the gate lead 3 are in the same layer, and can be processed by the same patterning process.
  • the data lead repair line 18 is electrically connected to the chip repair line 9 on the drive chip assembly 7 driving the data line and the gate lead repair line 8 and the chip repair line 9 on the drive chip assembly 7 of the drive gate line
  • the electrical connection can be realized by the above-mentioned via 101, conductive electrode 11, and conductive paste 15 as shown in FIG.
  • the driving chip component 7 may be a thin film chip, and of course, a flip-chip glass chip or the like.
  • the chip repair lines 9 on the driving chip component 7 may be one or more groups, and each set of repair lines 9 may overlap with one or more chip leads 12; on the array substrate 20
  • the array substrate repair lines 8 or 18 may be one or more sets, each set of service lines 8 or 18 correspondingly overlapping one or more gate lines 3 or data lines 2.
  • the repair line 9, 8 or 18 may be a single-layer structure or a composite layer structure, and each layer of the repair line may be made of any material selected from the group consisting of aluminum, chromium, tungsten, tantalum, titanium, molybdenum, aluminum-nickel alloy, and tungsten-molybdenum alloy. .
  • Each lead (chip lead 12 and/or data lead 2 and/or gate lead 3) may also have a layer structure similar to the above-described repair line and be fabricated from the material of the above-described repair line.
  • the electrical connection between the gate lead 3 and/or the data lead 2 and the chip lead 12 can pass through the via 101, the conductive electrode 11, and the anisotropic conductive paste 15 as shown in FIG.
  • the structural realization realizes that the electrical connection of the leads and the electrical connection of the repair lines can be realized in the same process step, thereby simplifying the manufacturing process.
  • Each of the conductive electrodes 11 is preferably a transparent electrode made of indium tin oxide or indium oxide or aluminum oxide, so that the transparent electrode can be formed simultaneously with the pixel electrode to simplify the process.
  • the conductive electrode 11 can also be a general metal electrode or the like.
  • the array substrate repair line is electrically connected to the chip repair line to electrically connect the array substrate leads to the chip leads.
  • the method for manufacturing a liquid crystal panel according to an embodiment of the present invention can produce a liquid crystal panel that is poorly repairable and can be repaired by driving a chip assembly.
  • Embodiment 5 is a diagrammatic representation of a liquid crystal panel of an embodiment of the present invention.
  • a method of manufacturing a liquid crystal panel according to an embodiment of the present invention includes the following process.
  • the gate lead 3 is taken as an example of the array substrate lead
  • the gate lead repair line 8 is taken as an example of the array substrate repair line.
  • the array substrate 20 is fabricated, which includes the following steps.
  • Step 1 depositing a gate metal layer on a base substrate (for example, a glass substrate) of the array substrate, forming a gate electrode (not shown) in the gate metal layer by a patterning process and a gate lead 3 as shown in FIG.
  • the deposition method may use a magnetron sputtering method, and the thickness of the gate metal layer is 1000 to 7000, and the material thereof is usually aluminum, chromium, tungsten, tantalum, titanium, molybdenum, aluminum-nickel alloy or tungsten-molybdenum alloy.
  • a multilayer structure composed of a plurality of films of the above materials, and the patterning process may include a photolithography process and a chemical etching process.
  • Step 2 depositing a gate insulating layer and an amorphous silicon film on the glass substrate on which the step 1 is completed, and forming a semiconductor layer (ie, active layer) pattern on the gate electrode of the same layer as the gate lead 3 by a patterning process Etching the semiconductor layer at the position of the gate lead 3; wherein a gate insulating layer of 1000 to 6000 people and an amorphous silicon film of 1000 to 6000 persons may be deposited by chemical vapor deposition, and the material of the gate insulating layer is usually It is silicon nitride, and may be silicon oxide or silicon oxynitride.
  • An amorphous silicon film is an example of an active layer of a formed thin film transistor.
  • Step 3 depositing a data metal layer on the glass substrate completing step 2, forming a data lead and a gate lead repair line 8 in the data metal layer by a patterning process, and obtaining a structure as shown in FIG. 9 (due to the position distance of the data lead)
  • the driver chip assembly is connected far away, so it is not marked in the figure; wherein the data metal layer has a thickness of 1000 to 7000 people.
  • This approach allows the data leads and gate lead repair lines 8 to be formed simultaneously, simplifying the process.
  • the step 3 and the step 2 may be combined into one step by using a half exposure process, and the half exposure process may use a mask such as a semi-transmissive reticle or a slit mask.
  • Step 4 depositing a protective layer on the glass substrate completing step 3, forming a via hole 10 therein by a patterning process, to obtain a structure as shown in FIG. 10; wherein the protective layer has a thickness of 1000
  • the material is usually silicon nitride or silicon dioxide, and the via 101 is located at the end of the gate lead repair line 8.
  • vias 111 at the ends of the gate leads 3 can be formed simultaneously in this step, thereby simplifying the process.
  • Step 5 depositing a conductive electrode layer 11 on the substrate on which the step 4 is completed, and forming a conductive electrode at the end of the gate lead repair line 8 by a patterning process, thereby obtaining a structure as shown in FIG. 11; wherein the conductive electrode 11 is preferably
  • the transparent electrode can be formed in one step with the pixel electrode.
  • the transparent electrode is usually indium tin oxide, indium oxide or alumina, and the thickness thereof is
  • the conductive electrodes 11 at the ends of the gate leads 3 can also be formed simultaneously in this step, thereby simplifying the process.
  • driver chip assembly manufacturing a driver chip assembly (obviously, the process can also be performed simultaneously with or before the process of fabricating the array substrate), including the following steps.
  • the driver chip assembly is used to drive the gate leads.
  • the chip lead 12 is manufactured by a patterning process.
  • the chip substrate 71 may be made of a polyimide resin or the like, and the deposited metal film may be an alloy film in which nickel and copper are first formed by sputtering, and then plated to obtain a thickened copper layer, and examples of the patterning process include photolithography and chemical etching.
  • Photolithography involves exposing and developing a photoresist on a copper layer to obtain a pattern protected by a corrosion resistant resist.
  • Chemical etching involves spraying a etchant to obtain a fine line pattern, removing the resist and performing an oxidation treatment to obtain a chip lead.
  • Step 7 A chip insulating layer 16 (insulating resist film) is coated on the chip substrate on which the step 6 is completed.
  • Step 8 as shown in Fig. 12, a metal thin film is deposited again, and a chip repair line 9 is formed by a patterning process, and the chip repair line 9 is separated from the chip lead 12 by a chip insulating layer 16.
  • Step 9 A via hole is formed in the chip insulating layer above the end of the chip lead 12 by a patterning process to expose the end of the chip lead.
  • the chip repairing line 9 can be manufactured first, then the chip insulating layer 16 is fabricated, then the chip lead 12 is fabricated, and finally the hole 191 is opened in the chip insulating layer above the chip repairing line 9 ( As shown in Figure 4).
  • Process 3 connecting the driver chip component 7 and the array substrate 20 to each other, includes the following steps.
  • step 10 an anisotropic conductive paste is applied on the conductive electrode 11 of the via 101 at the end of the gate lead repair line 8 and the conductive electrode 11 of the via 111 at the end of the gate lead 3.
  • step 11 Align the driving chip component 7 through the alignment mark, and align the gate lead repair line 8 and the chip repair line through the indenter, for example, at a pressure of 0.1 to 0.4 MPa and a temperature of 100 to 200 degrees Celsius.
  • 9 and the gate lead 3 and the chip lead 12 are respectively electrically connected to obtain a structure as shown in FIG.
  • the conductive ball 151 (for example, gold particles or graphite particles, etc.) is contained in the anisotropic conductive paste 15, and after the chip repair line 9 and the gate lead repair line 8 are pressed together, the conductive balls 151 conduct the two metal wires; The electrical connection between the gate lead 3 and the chip lead 12 is also achieved by the conductive ball 151 in the anisotropic conductive paste 15.
  • a method of manufacturing a liquid crystal panel according to an embodiment of the present invention includes the following process.
  • the data lead is taken as an example of the array substrate lead
  • the data lead repair line is taken as an example of the array substrate repair line.
  • Process 1 manufacturing an array substrate, comprising the following steps.
  • Step 1 Deposit a gate metal layer on a base substrate (for example, a glass substrate) of the array substrate, and form a gate electrode, a gate lead, and a data lead repair line in the gate metal layer by a patterning process.
  • a base substrate for example, a glass substrate
  • Step 2 depositing a gate insulating layer and an amorphous silicon film on the glass substrate on which the step 1 is completed, forming a semiconductor layer pattern on the gate electrode by a patterning process, and forming a semiconductor layer on the gate electrode line and the data lead repair line. Etched off.
  • An amorphous silicon film is an example of an active layer of a formed thin film transistor.
  • Step 3 depositing a data metal layer on the glass substrate completing step 2, and forming a data lead in the data metal layer by a patterning process.
  • Step 4 depositing a protective layer on the glass substrate on which step 3 is completed, and forming a data located therein by a patterning process? a via hole above the end of the line repair line;
  • Step 5 depositing a conductive electrode layer on the substrate on which the step 4 is completed, and forming a conductive electrode in the via hole at the end of the data lead repair line by a patterning process.
  • Process 2 manufacturing a driver chip component, includes the following steps.
  • the drive chip assembly is used to drive data leads.
  • Step 6 After depositing a metal film on the chip substrate, the chip leads are fabricated by a patterning process.
  • step 8 a metal film is deposited again, and a chip repair line is formed by a patterning process.
  • Step 9 A via hole is formed in the chip insulating layer above the end of the chip lead by a patterning process.
  • Process 3 connecting the driver chip component and the array substrate to each other, includes the following steps.
  • step 10 an anisotropic conductive paste is applied to the conductive electrodes of the vias at the ends of the data lead repair lines and the conductive electrodes of the vias at the ends of the data leads.
  • Step 11 Align the driving chip component through the alignment mark, and electrically connect the data lead maintenance line and the chip maintenance line through the indenter.
  • a method of manufacturing a liquid crystal panel according to an embodiment of the present invention includes the following process.
  • the gate lead and the data lead are examples of the array substrate lead
  • the gate lead repair line and the data lead repair line are exemplified as the array substrate repair line.
  • Process 1 manufacturing an array substrate, comprising the following steps.
  • Step 1 depositing a gate metal layer on the glass substrate of the array substrate, and forming a gate electrode, a gate lead and a data lead repair line in the gate metal layer by a patterning process;
  • Step 2 depositing a gate insulating layer and an amorphous silicon film on the glass substrate on which the step 1 is completed, forming a semiconductor layer pattern on the gate electrode by a patterning process, etching the semiconductor layer at the position of the gate lead and the data lead repair line Off
  • Step 3 depositing a data metal layer on the glass substrate completing step 2, and forming a data lead and a gate lead repair line in the data metal layer by a patterning process;
  • Step 4 depositing a protective layer on the glass substrate on which the step 3 is completed, and forming a via hole at the end of the gate lead repair line and the end of the data lead repair line through a patterning process.
  • Step 5 depositing a conductive electrode layer on the substrate on which the step 4 is completed, and forming a conductive electrode at the end of the data lead repair line and the end of the gate lead repair line by a patterning process.
  • Process 2 manufacturing a driver chip component, includes the following steps.
  • drive chip assemblies for driving the gate leads and driving the data leads are formed, respectively.
  • Step 6 After depositing a metal film on the chip substrate, the chip leads are fabricated by a patterning process.
  • Step 8 depositing a metal film again, and forming a chip repair line by a patterning process.
  • Step 9 A via hole is formed in the chip insulating layer above the end of the chip lead by a patterning process.
  • Process 3 connecting the driver chip component and the array substrate to each other, includes the following steps.
  • Step 10 conducting the vias at the end of the data lead repair line and at the end of the gate lead repair line An anisotropic conductive paste is applied to the electrodes.
  • Step 11 Align the driver chip component through the alignment mark, and use the indenter to make the data lead wire repair line and gate?
  • the I-line repair lines are electrically connected to the chip repair lines of the corresponding driver chip components.
  • the method of repairing the disconnection of the connection position of the driving chip component of the liquid crystal panel includes the following steps.
  • the disconnection position 17 of the drive chip assembly connection position is determined.
  • the overlapping position of the array substrate repair line and the array substrate lead of the disconnection position 17 is performed; 1: early connection is made to achieve electrical connection between the two, wherein the array substrate repair line overlaps the array substrate lead but is insulated before soldering.
  • the overlapping position of the chip dimension 9 and the chip lead 12 on the other side of the disconnection position 17 is soldered to achieve electrical connection therebetween, wherein the power between the corresponding chip lead 12 and the array substrate lead on the driver chip assembly is driven.
  • the connection is broken due to the disconnected position 17, and the chip repair line 9 overlaps but is insulated from the chip leads 12 before soldering, and the chip repair line 9 is electrically connected to the array substrate repair line.
  • a gate lead is taken as an example of an array substrate lead
  • a gate lead repair line is taken as an example of an array substrate repair line.
  • this embodiment is also applicable to data leads and data lead repair lines.
  • the method for repairing the disconnection failure of the driving chip component connection position of the liquid crystal panel as shown in the first embodiment includes:
  • the horizontal line or the longitudinal bright line is found by checking the process, and the coordinates of the bright line are determined; the connection position of the driving chip component corresponding to the bright line, that is, the chip lead 12 and the array substrate lead, is found by the known coordinates under the dynamometer (
  • the connection position of the gate lead 3 is taken as an example; the disconnection position 17 of the connection position of the driving chip component is determined.
  • the overlapping position 5 of the chip repair line 9 and the chip lead 12 on the side of the disconnection position is melted and welded by a laser device, and the chip repair line 9 is electrically connected to the chip lead 12, and the laser wavelength for maintenance is 800 to lOOOnm, energy is 100 to 200 nJ;
  • the overlap position 5 of the gate lead repair line 8 and the gate lead 3 on the other side of the disconnection position 17 is also melted by a laser device to make the gate lead repair line 8 and the gate Polar lead 3 for electrical connection, for maintenance
  • the laser has a wavelength of 800 to 100 nm and an energy of 100 to 500 nJ. After soldering, the signal of the gate lead 3 can be transmitted through the repair lines 8, 9, thereby eliminating the malfunction caused by the open circuit 17.
  • Another method for repairing a disconnection fault in a connection position of a driving chip component of a liquid crystal panel includes the following steps:
  • the two overlapping portions 8-1 of the array substrate repair line on both sides of the disconnection position 17 and the two overlapping positions 5 of the array substrate lead are respectively soldered to realize the array substrate lead and Electrical connection of the array substrate repair line.
  • the electrical connection between the array substrate leads and the corresponding chip leads 12 on the driver chip assembly is broken due to the break position 17, and the two overlapping portions 8-1 of the array substrate repair lines overlap the array substrate leads before soldering.
  • the two ends of the two overlapping portions are respectively connected, and the connected common terminals are electrically connected to the chip repairing line 9 on the driving chip assembly.
  • the chip repairing line 9 and the chip lead 12 are in the front; Overlap but insulated;
  • the overlapping position of any overlapping portion of the array substrate repair line on the side of the disconnection position and the array substrate lead is soldered to realize the array
  • the substrate lead is electrically connected to the array substrate repair line, and the overlapping position of the chip repair line and the chip lead on the other side of the disconnection position is soldered to realize electrical connection between the chip repair line and the chip lead.
  • the method of the embodiment of the invention can repair the disconnection of the connection position of the driving chip component of the liquid crystal panel, thereby reducing waste and reducing the cost.
  • a gate lead is taken as an example of an array substrate lead
  • a gate lead repair line is taken as an example of an array substrate repair line.
  • this embodiment is also applicable to data leads and data lead repair lines.
  • the method for repairing the disconnection of the driving chip assembly connection position of the liquid crystal panel as shown in the second embodiment is similar to the maintenance method of the eighth embodiment, and the difference is that it needs to be selected according to the disconnection position 17; Connection method.
  • the gate leads 3 on both sides of the open position are And grid
  • the two overlapping positions 5 of the two overlapping portions 8-1 of the pole lead repair line 8 are respectively performed; t is connected early to realize maintenance; in this case, since both soldering are performed on the array substrate, the soldering process
  • the parameters of the laser melting device are not adjusted, and the operation is simple; further, laser melting on the driving chip component 7 (especially on the thin film chip) is easy to burn out the driving chip component 7, and the method of the embodiment can be reduced in the driving chip component. 7 early; t early, thereby reducing the possibility of damaging the driver chip assembly 7 during maintenance;
  • the repair is performed using a method similar to that of the eighth embodiment, wherein the gate lead is used. There are two overlapping positions of the overlapping portion 8-1 of the repair line 8 and the gate lead 3, which can be performed for any one of them;

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Description

液晶面板及其制造方法和维修方法
技术领域
本发明的实施例涉及用于薄膜晶体管液晶显示器（TFT-LCD ) 的液晶面 板。 背景技术
在薄膜晶体管液晶显示器的生产过程中， 需将阵列基板上的引线（即 阵列基板引线， 包括栅极引线、数据引线等）与驱动芯片组件上的引线（即 芯片引线）连接， 以实现对液晶显示器的控制。 该驱动芯片组件可为薄膜 芯片（又称覆晶薄膜， COF, Chip On Film ), 也可为覆晶玻璃（COG, Chip On Glass )等。
驱动芯片组件与阵列基板的连接处（即驱动芯片组件连接位置） 的断 路不良（即 Open不良）是一种常见不良， 按断路位置可分为三类： 1.阵列 基板引线的断线，主要由阵列工艺过程中的灰尘、成盒过程中异物的压断、 后工程的水汽腐蚀等造成； 2.芯片引线的断线， 主要由薄膜驱动芯片组件 与玻璃基板边缘划伤导致； 3.芯片引线与阵列基板引线电连接位置的断线， 主要由过孔位置的金属腐蚀、 灰尘、 导电粒子缺失等导致。 上述各种断路 不良如不能维修将导致液晶面板成为废品。
目前有多种对液晶面板中的断路不良进行的维修方法。 图 1为一种常 规的像素区断路不良的维修结构， 其中像素区维修线 1围绕像素区一周， 并且该像素区维修线 1与栅极引线 3、 数据引线 2均有交叠。 栅极引线 3 与数据引线 2在像素区域内交叉以限定按矩阵分布的像素阵列。 如图 2所 示， 当数据引线 2上有断路位置 17时， 可在像素区维修线 1与数据引线 2 的交叠位置进行焊接 5, 使断路部分的数据线信号通过像素区维修线 1传 输以实现正常显示。
但本发明人发现， 现有的维修液晶面板中断路不良的技术均不能用于维 修驱动芯片组件连接位置的断路不良， 故传统的驱动芯片组件连接位置的断 路不良是无法维修的， 一旦出现产品只能按照废品处理。 发明内容
本发明的一个实施例提供了一种液晶面板， 包括： 驱动芯片组件， 具 有芯片引线和芯片维修线， 所述芯片维修线与所述芯片引线交叠但绝缘； 阵列基板， 具有阵列基板引线和阵列基板维修线， 所述阵列基板维修线与 所述阵列基板引线交叠但绝缘； 其中所述驱动芯片组件安装到所述阵列基 板上， 所述阵列基板引线与对应的所述芯片引线电连接， 所述芯片维修线 的两端分别与对应的所述阵列基板维修线的两端电连接。
本发明的另一个实施例提供了一种制造液晶面板的方法， 包括以 下步骤： 在阵列基板上形成阵列基板引线和阵列基板维修线， 其中 所述阵列基板维修线与所述阵列基板引线交叠但绝缘； 在驱动芯片 组件上形成芯片引线和芯片维修线， 其中所述芯片维修线与所述芯 片引线交叠但绝缘； 使所述驱动芯片组件安装到所述阵列基板上， 使所述阵列基板维修线的两端与相应的所述芯片维修线的两端形成 电连接， 使所述阵列基板引线与所述芯片引线形成电连接。
本发明的另一个实施例提供了一种维修如上所述的液晶面板的驱动芯片 组件连接位置的断路不良的方法。 附图说明
图 1为一种传统的液晶面板像素区的维修结构的主视结构示意图。 图 2为图 1的液晶面板像素区发生断路不良时的维修方法示意图。 图 3为本发明实施例一的液晶面板的驱动芯片组件连接位置的俯视结 构示意图。
图 4为图 3中 A-A位置的截面结构示意图。
图 5为本发明实施例二的液晶面板的驱动芯片组件连接位置的主视结 构示意图。
图 6为本发明实施例三的液晶面板的驱动芯片组件连接位置的主视结 构示意图。
图 7为本发明实施例四的液晶面板的主视结构示意图。
图 8为本发明实施例五的液晶面板制造方法完成步骤 1后的阵列基板 的驱动芯片组件连接位置的主视结构示意图。 图 9为本发明实施例五的液晶面板制造方法完成步骤 3后的阵列基板 的驱动芯片组件连接位置的主视结构示意图。
图 10为本发明实施例五的液晶面板制造方法完成步骤 4后的阵列基板 的驱动芯片组件连接位置的主视结构示意图。
图 11为本发明实施例五的液晶面板制造方法完成步骤 5后的阵列基板 的驱动芯片组件连接位置的主视结构示意图。
图 12为本发明实施例五的液晶面板制造方法完成步骤 8后的驱动芯片 组件的驱动芯片组件连接位置的主视结构示意图。
图 13 为本发明实施例八的液晶面板的驱动芯片组件连接位置的断路 不良的维修方法的示意图。
图 14 为本发明实施例九的液晶面板的驱动芯片组件连接位置的栅极 引线断路不良的维修方法的示意图。
图 15 为本发明实施例九的液晶面板的驱动芯片组件连接位置的芯片 引线断路不良的维修方法的示意图。
图 16 为本发明实施例九的液晶面板的驱动芯片组件连接位置的栅极引 线与芯片引线电连接位置的断路不良的维修方法的示意图。 具体实施方式
下面结合附图对本发明实施例的液晶面板及其制造与维修方法进行详 细描述。
本发明实施例的液晶面板包括具有芯片引线的驱动芯片组件以及具有 阵列基板引线的阵列基板， 芯片引线与对应的阵列基板引线电连接。 该液 晶面板还具有维修线， 维修线包括位于驱动芯片组件上的与芯片引线交叠 但绝缘的芯片维修线， 以及位于阵列基板上的与阵列基板引线交叠但绝缘 的阵列基板维修线， 其中芯片维修线两端分别与对应的阵列基板维修线的 两端电连接。
本发明实施例的液晶面板具有芯片维修线和阵列基板维修线， 通过将 维修线与对应的引线的交叠位置进行； t早接， 即可对液晶面板的驱动芯片组 件连接位置的断路不良进行维修。
实施例一 如图 3和图 4示出了本发明实施例的一种液晶面板， 其包括驱动芯片 组件和阵列基板。
图 3为本发明实施例一的液晶面板的驱动芯片组件连接位置的俯视结 构示意图。 图 4为图 3中 A-A位置的截面结构示意图。
其中驱动芯片组件 7包括芯片基板 71 , 芯片基板 71上有芯片 （未示 出）和芯片维修线 9。 芯片维修线 9上还覆盖有芯片绝缘层 16 (图 4 ), 芯 片绝缘层 16上有与芯片相连的芯片引线 12, 芯片维修线 9与芯片引线 12 交叠（图 3 ), 且二者通过中间间隔的芯片绝缘层 16实现绝缘。 在芯片维 修线 9末端上方的芯片绝缘层 16中形成有过孔 191 , 从而使芯片维修线 9 的末端暴露。 显然， 驱动芯片组件 7 也可釆用这样的结构： 芯片引线 12 在芯片绝缘层 16以下并且其部分可以通过过孔露出，而芯片维修线 9在芯 片绝缘层 16以上， 芯片维修线 9与芯片引线 12交叠， 且二者仍然通过中 间间隔的芯片绝缘层 16实现绝缘。
本实施例中， 在阵列基板 20的基地基板 21上， 阵列基板引线包括栅 极引线 3和数据引线（未示出 ),该栅极引线 3与驱动芯片组件 7上的芯片 引线 12电连接。 这里， 驱动芯片组件 7为栅极驱动芯片组件； 栅极引线 3 上有栅极绝缘层 14, 数据引线和栅极引线维修线 8位于栅极绝缘层 14上 并处于同一层中，可由同一次构图工艺 (构图工艺的示例可包括光刻工艺和 化学腐蚀工艺)形成； 该栅极引线维修线 8与栅极引线 3交叠， 并通过栅极 绝缘层 14与栅极引线 3绝缘； 在栅极绝缘层 14、 栅极引线维修线 8上还 可有保护层 13 ,保护层 13在栅极引线维修线 8末端处形成过孔 101 ,该过 孔 101中有与栅极引线维修线 8连接的导电电极 11 , 导电电极 11上有各 向异性导电胶 15,各向异性导电胶 15与驱动芯片组件 7上的芯片维修线 9 连接， 从而实现芯片维修线 9和栅极引线维修线 8的电连接。
类似地，在栅极引线 3上方，保护层 13中形成了过孔 111 ,该过孔 111 中有与栅极引线 3连接的导电电极 11 , 导电电极 11上有各向异性导电胶 15 , 各向异性导电胶 15与驱动芯片组件 7上的芯片引线 12连接， 从而实 现栅极引线 3和芯片引线 12的电连接。
实施例二
如图 5所示， 本实施例的液晶面板具有与实施例一的液晶面板相似的 结构，区别在于在阵列基板 20之上的栅极引线维修线 8包括两段与栅极引 线 3交叠但绝缘的交叠部分 8-1 , 两交叠部分 8-1的两端分别连接， 其共同 端头再与芯片维修线 9电连接； 此时， 若断路发生在两段交叠部分 8-1之 间（也就是发生在阵列基板引线上），则维修 ;t早接只在阵列基板 20上进行， 从而可以避免在驱动芯片组件 7上进行焊接等维修操作， 降低因焊接损坏 驱动芯片组件 7的可能。
实施例三
如图 6所示， 本实施例的液晶面板具有与实施例一和实施例二的液晶 面板相似的结构， 区别在于本实施例针对液晶面板中数据驱动芯片组件与 阵列基板上的数据线之间的连接的， 因此维修线为数据引线维修线 18, 该 数据引线维修线 18与栅极引线（未示出）位于同一层中， 可由同一次构图 工序形成；该数据引线维修线 18位于数据引线 2下方并通过栅极绝缘层与 数据引线 2绝缘；其中数据引线维修线 18与驱动芯片组件 7上的芯片维修 线 9的电连接也可通过类似过孔 101、导电电极 11、导电胶 15的方式实现。 这里， 驱动芯片组件 7为数据驱动芯片组件。
显然地， 与实施例二类似， 本实施例中在阵列基板上的数据引线维修 线 18还可以包括两段与数据引线 2交叠但绝缘的交叠部分，两交叠部分的 两端分别连接， 其共同端头再与芯片维修线 9电连接。 此时， 若断路发生 在两段交叠部分之间（也就是发生在阵列基板引线上），则维修 ;t早接只在阵 列基板上进行，从而可以避免在数据驱动芯片组件上进行焊接等维修操作， 降低因焊接损坏数据驱动芯片组件的可能。
实施例四
如图 7所示， 本实施例的液晶面板具有与实施例一至实施例三的液晶 面板相似的结构， 其同时具有用于栅极引线的栅极引线维修线和用于数据 引线的数据引线维修线， 为实施例一与实施例三的组合。
阵列基板 20包括横向延伸的多条栅极引线 3与纵向延伸的多条数据弓 I 线 2在像素区域内交叉以限定按矩阵分布的像素阵列。 如图 7所示， 阵列 基板 20的左侧设置有多个驱动芯片组件 7用于驱动栅线 3; 阵列基板 20 的上侧设置有多个驱动芯片组件 7用于数据线 3。 每个驱动芯片组件 7具 有相应的驱动芯片 72、 芯片引线 12和芯片维修线 9。 在阵列基板 20上， 该栅极引线维修线 8与数据引线 2位于同一层中， 可由同一次构图工序形成；而数据引线维修线 18与栅极引线 3位于同一层 中， 可由同一次构图工序形成； 显然， 其中数据引线维修线 18与驱动数据 线的驱动芯片组件 7上的芯片维修线 9的电连接和栅极引线维修线 8与驱 动栅线的驱动芯片组件 7上的芯片维修线 9的电连接均可通过上述如图 4 所示的过孔 101、 导电电极 11、 导电胶 15的方式实现。
在实施例一至实施例四中， 驱动芯片组件 7可为薄膜芯片， 当然也可 为覆晶玻璃芯片等。
在实施例一至实施例四中， 在驱动芯片组件 7上的芯片维修线 9可为 一组或多组， 每组维修线 9可与一条或多条芯片引线 12交叠； 阵列基板 20上的阵列基板维修线 8或 18可为一组或多组，每组维修线 8或 18相应 地可与一条或多条栅线 3或数据线 2交叠。 该维修线 9、 8或 18可为单层 结构或复合层结构， 每层维修线可由选自铝、 铬、 钨、 钽、 钛、 钼、 铝镍 合金、钨钼合金中的任意材料制成。各引线（芯片引线 12和 /或数据引线 2 和 /或栅极引线 3 )也可具有类似上述维修线的层结构并由上述维修线的材 料制造。
显然， 在上述各实施例中， 栅极引线 3和 /或数据引线 2与芯片引线 12间的电连接可通过类似上述如图 4所示过孔 101、 导电电极 11、 各向异 性导电胶 15的结构实现，釆用这种电连接方式可使引线的电连接和维修线 的电连接在同一工艺步骤中实现，从而简化制造工艺。各导电电极 11优选 为由氧化铟锡或氧化铟辞或氧化铝辞制造的透明电极， 这样透明电极就可 与像素电极同时形成以简化工艺，当然导电电极 11也可为一般的金属电极 等。
本发明实施例的制造液晶面板的方法包括：
在阵列基板上形成阵列基板引线和阵列基板维修线， 其中阵列基板维 修线与阵列基板引线交叠但绝缘；
在驱动芯片组件上形成芯片引线和芯片维修线， 其中芯片维修线与芯 片引线交叠但绝缘；
使阵列基板维修线与芯片维修线形成电连接， 使阵列基板引线与芯片 引线形成电连接。 本发明实施例的制造液晶面板的方法能制得驱动芯片组件连接位置的 断路不良可维修的制造液晶面板。
下面， 将详细描述本发明实施例的制造液晶面板的方法的实施例。 实施例五
本发明实施例的一种制造液晶面板的方法， 包括以下过程。 在本实施 例中， 栅极引线 3作为阵列基板引线的示例， 栅极引线维修线 8作为阵列 基板维修线的示例。
过程一， 制造阵列基板 20, 其包括如下步骤。
步骤 1 , 在阵列基板的基底基板（例如玻璃基板）上沉积栅极金属层， 通过构图工艺在栅极金属层中形成栅极电极（未示出 )和如图 8所示的栅 极引线 3; 其中沉积方法可使用磁控溅射方法， 栅极金属层厚度在 1000至 7000人， 其材料通常为铝、 铬、 钨、 钽、 钛、 钼、 铝镍合金或钨钼合金等， 也可为多种上述材料的薄膜组成的多层结构， 而构图工艺可包括光刻工艺 和化学腐蚀工艺。
步骤 2, 在完成步骤 1的玻璃基板上沉积栅极绝缘层和非晶硅薄膜， 通过构图工艺，在与栅极引线 3位于同一层的栅极电极上形成半导体层（即 有源层） 图案， 将栅极引线 3位置的半导体层刻蚀掉； 其中可用化学汽相 沉积法淀积 1000到 6000人的栅极绝缘层和 1000到 6000人的非晶硅薄膜， 栅极绝缘层的材料通常是氮化硅， 也可为氧化硅和氮氧化硅等。 非晶硅薄 膜是形成的薄膜晶体管的有源层的示例。
步骤 3 , 在完成步骤 2的玻璃基板上沉积数据金属层， 通过构图工艺 在数据金属层中形成数据引线和栅极引线维修线 8, 得到如图 9所示的结 构（因数据引线的位置距离驱动芯片组件连接位置较远， 故未在图中标出）； 其中数据金属层的厚度在 1000到 7000人。这种方式可使数据引线和栅极引 线维修线 8同时形成， 从而简化工艺。
另外， 在另一个示例中， 可通过釆用半曝光工艺， 将步骤 3与步骤 2 合并为一个步骤 , 该半曝光工艺可使用半透光掩模板或狭缝掩模板等掩模 板。
步骤 4, 在完成步骤 3的玻璃基板上沉积保护层， 通过构图工艺在其 中形成过孔 10, 得到如图 10所示的结构； 其中， 保护层厚度在 1000到 6000人，其材料通常是氮化硅或二氧化硅，过孔 101位于栅极引线维修线 8 的末端。 同样，位于栅极引线 3末端的过孔 111也可在此步骤中同时形成， 从而简化工艺。
步骤 5, 在完成步骤 4的基板上沉积导电电极层 11 , 通过构图工艺， 形成位于上述栅极引线维修线 8的末端的导电电极，得到如图 11所示的结 构； 其中导电电极 11优选为透明电极，这样就可以与像素电极在一个步骤 中形成。 该透明电极通常为氧化铟锡、 氧化铟辞或氧化铝辞等， 其厚度在
100至 1000A之间。 同时，位于栅极引线 3末端的导电电极 11也可在此步 骤中同时形成， 从而简化工艺。
过程二， 制造驱动芯片组件（显然， 本过程也可与制造阵列基板的过 程同时进行或在其之前进行）， 包括如下步骤。 该实施例中， 该驱动芯片组 件用于驱动栅极引线。
步骤 6,在驱动芯片组件的芯片基板 71上沉积金属薄膜后通过构图工 艺制造芯片引线 12。 芯片基板 71可由聚酰亚胺树脂等制成， 沉积金属薄 膜可为先通过喷镀形成镍和铜的合金薄膜， 再电镀得到加厚的铜层， 而构 图工艺的示例包括光刻和化学腐蚀。 光刻包括在铜层上涂覆光致抗蚀剂后 曝光、 显影， 得到由耐腐蚀性抗蚀剂保护的图形。 化学腐蚀包括用蚀刻液 喷淋得到精细的线路图形，再去除抗蚀剂并进行防氧化处理得到芯片引线。
步骤 7, 在完成步骤 6的芯片基板上涂覆芯片绝缘层 16 (绝缘性抗蚀 膜）。
步骤 8, 如图 12所示， 再次沉积金属薄膜， 并用构图工艺形成芯片维 修线 9, 该芯片维修线 9与芯片引线 12通过芯片绝缘层 16隔开。
步骤 9,通过构图工艺在芯片引线 12末端上方的芯片绝缘层中制造过 孔， 以使芯片引线的末端暴露。
显然， 在制造驱动芯片组件的过程中， 也可先制造芯片维修线 9, 再 制造芯片绝缘层 16,之后制造芯片引线 12,最后在芯片维修线 9上方的芯 片绝缘层中开过孔 191 (如图 4所示）。
过程三， 将驱动芯片组件 7与阵列基板 20彼此连接， 包括如下步骤。 步骤 10, 在栅极引线维修线 8末端的过孔 101的导电电极 11以及栅 极引线 3末端的过孔 111的导电电极 11上涂敷各向异性导电胶。 步骤 11 , 将驱动芯片组件 7通过对位标记进行对准， 对准后通过压头 例如在 0.1至 0.4MPa的压强和 100至 200摄氏度的温度下，使栅极引线维 修线 8和芯片维修线 9以及栅极引线 3与芯片引线 12分别实现电连接，得 到如图 5所示的结构。
在各向异性导电胶 15中含有导电球 151(例如,金颗粒或石墨颗粒等 ), 在芯片维修线 9和栅极引线维修线 8压合后，导电球 151将两金属线导通； 同样， 栅极引线 3与芯片引线 12间的电连接也通过各向异性导电胶 15中 的导电球 151实现。
实施例六
本发明实施例的一种制造液晶面板的方法， 包括以下过程。 在本实施 例中， 数据引线作为阵列基板引线的示例， 数据引线维修线作为阵列基板 维修线的示例。
过程一， 制造阵列基板， 包括如下步骤。
步骤 1 , 在阵列基板的衬底基板（例如玻璃基板）上沉积栅极金属层， 通过构图工艺在栅极金属层中形成栅极电极、栅极引线和数据引线维修线。
步骤 2, 在完成步骤 1的玻璃基板上沉积栅极绝缘层和非晶硅薄膜， 通过构图工艺在栅极电极上形成半导体层图案， 将栅极弓 I线及数据引线维 修线位置的半导体层刻蚀掉。 非晶硅薄膜是形成的薄膜晶体管的有源层的 示例。
步骤 3 , 在完成步骤 2的玻璃基板上沉积数据金属层， 通过构图工艺 在数据金属层中形成数据引线。
步骤 4, 在完成步骤 3的玻璃基板上沉积保护层， 通过构图工艺在其 中形成位于数据？ )线维修线末端上方的过孔；
步骤 5, 在完成步骤 4的基板上沉积导电电极层， 通过构图工艺形成 位于数据引线维修线末端的过孔中的导电电极。
过程二， 制造驱动芯片组件， 包括如下步骤。 该实施例中， 该驱动芯 片组件用于驱动数据引线。
步骤 6, 在芯片基板上沉积金属薄膜后通过构图工艺制造芯片引线。 步骤 7 , 在驱动芯片组件上涂覆芯片绝缘层。
步骤 8, 再次沉积金属薄膜， 并用构图工艺形成芯片维修线。 步骤 9 ,通过构图工艺在芯片引线末端上方的芯片绝缘层中制造过孔。 过程三， 将驱动芯片组件与阵列基板彼此连接， 包括如下步骤。
步骤 10,在数据引线维修线末端的过孔的导电电极以及数据引线末端 上的过孔的导电电极上涂敷各向异性导电胶。
步骤 11 , 将驱动芯片组件通过对位标记对准， 通过压头使数据引线维 修线和芯片维修线实现电连接。
实施例七
本发明实施例的一种制造液晶面板的方法， 包括以下过程。 在本实施 例中， 栅极引线和数据引线作为阵列基板引线的示例， 栅极引线维修线和 数据引线维修线作为阵列基板维修线的示例。
过程一， 制造阵列基板， 包括如下步骤。
步骤 1 , 在阵列基板的玻璃基板上沉积栅极金属层， 通过构图工艺在 栅极金属层中形成栅极电极、 栅极引线和数据引线维修线；
步骤 2, 在完成步骤 1的玻璃基板上沉积栅极绝缘层和非晶硅薄膜， 通过构图工艺在栅极电极上形成半导体层图案， 将栅极引线和数据引线维 修线位置的半导体层刻蚀掉；
步骤 3 , 在完成步骤 2的玻璃基板上沉积数据金属层， 通过构图工艺 在数据金属层中形成数据引线和栅极引线维修线；
步骤 4, 在完成步骤 3的玻璃基板上沉积保护层， 通过构图工艺在其 中形成位于栅极引线维修线末端和数据引线维修线末端上方的过孔。
步骤 5, 在完成步骤 4的基板上沉积导电电极层， 通过构图工艺形成 位于数据引线维修线末端及栅极引线维修线末端的导电电极。
过程二， 制造驱动芯片组件， 包括如下步骤。 该实施例中， 分别形成 有用于驱动栅极引线的和驱动数据引线的驱动芯片组件。
步骤 6, 在芯片基板上沉积金属薄膜后通过构图工艺制造芯片引线。 步骤 7 , 在驱动芯片组件上涂覆芯片绝缘层。
步骤 8, 再次沉积金属薄膜， 并用构图工艺形成芯片维修线。
步骤 9 ,通过构图工艺在芯片引线末端上方的芯片绝缘层中制造过孔。 过程三， 将驱动芯片组件和阵列基板彼此连接， 包括如下步骤。
步骤 10,在数据引线维修线末端及栅极引线维修线末端的过孔的导电 电极上涂敷各向异性导电胶。
步骤 11 , 将驱动芯片组件通过对位标记进行对准， 通过压头使数据引 线维修线及栅极？ I线维修线分别与对应的驱动芯片组件的芯片维修线实现 电连接。
此外， 本发明实施例的维修液晶面板的驱动芯片组件连接位置的断路 不良的方法包括如下步骤。
首先， 确定驱动芯片组件连接位置的断路位置 17。
对断路位置 17 —侧的阵列基板维修线与阵列基板引线的交叠位置进 行； 1：早接以实现二者的电连接， 其中阵列基板维修线在焊接前与阵列基板引 线交叠但绝缘。
对断路位置 17另一侧的芯片维^ ί 线 9与芯片引线 12的交叠位置进行 焊接以实现二者的电连接，其中驱动芯片组件上对应的芯片引线 12与阵列 基板引线之间的电连接由于该断开位置 17而断开，而芯片维修线 9在焊接 前与芯片引线 12交叠但绝缘， 且芯片维修线 9与阵列基板维修线电连接。
下面将详细描述该维修方法的具体实施例。
实施例八
在该实施例中以栅极引线作为阵列基板引线的示例， 以栅极引线维修 线作为阵列基板维修线的示例。 显然地， 该实施例也适用于数据引线和数 据引线维修线。
如图 13所示，维修如实施例一所示的液晶面板的驱动芯片组件连接位 置的断路不良的方法包括：
首先， 通过检查工艺发现横向或纵向的亮线， 并确定亮线的坐标； 在 显 镜下通过已知的坐标查找到亮线对应的驱动芯片组件连接位置， 即芯 片引线 12和阵列基板引线 (此处以栅极引线 3为例）的连接位置； 确定驱 动芯片组件连接位置的断路位置 17。
之后 ,对位于断路位置一侧的芯片维修线 9与芯片引线 12的交叠位置 5用激光设备熔融进行焊接， 使芯片维修线 9与芯片引线 12实现电连接， 维修用的激光波长为 800至 lOOOnm, 能量为 100至 200nJ; 对位于断路位 置 17另一侧的栅极引线维修线 8与栅极引线 3的交叠位置 5也用激光设备 熔融进行焊接， 使栅极引线维修线 8与栅极引线 3实现电连接， 维修用的 激光波长为 800至 lOOOnm, 能量为 100至 500nJ; 焊接后， 栅极引线 3的 信号就可通过维修线 8、 9进行传递， 从而消除了断路 17造成的故障。
此外， 本发明实施例的另一种维修液晶面板的驱动芯片组件连接位置 的断路不良的方法包括以下步骤：
确定驱动芯片组件连接位置的断路位置 17 ;
当断路位置 17位于阵列基板引线上时， 对断路位置 17两侧的阵列基 板维修线的两段交叠部分 8-1与阵列基板引线的两交叠位置 5分别进行焊 接以实现阵列基板引线与阵列基板维修线的电连接。 阵列基板引线与驱动 芯片组件上对应的芯片引线 12之间的电连接由于该断开位置 17而断开， 阵列基板维修线的两段交叠部分 8-1 在焊接前与阵列基板引线交叠但绝 缘， 且两段交叠部分的两端分别连接， 连接后的共同端头再与驱动芯片组 件上的芯片维修线 9电连接，芯片维修线 9与芯片引线 12在; 1：早接前交叠但 绝缘；
当断路位置位于芯片引线上或位于芯片引线与阵列基板引线的电连接 位置时， 对断路位置一侧的阵列基板维修线的任一交叠部分与阵列基板引 线的交叠位置进行焊接以实现阵列基板引线与阵列基板维修线的电连接， 并对断路位置另一侧的芯片维修线与芯片引线的交叠位置进行焊接以实现 芯片维修线与芯片引线的电连接。
本发明实施例的方法可对液晶面板的驱动芯片组件连接位置的断路不 良进行维修， 从而减少废品， 降低成本。
下面将详细描述该维修方法的具体实施例。
实施例九
在该实施例中以栅极引线作为阵列基板引线的示例， 以栅极引线维修 线作为阵列基板维修线的示例。 显然地， 该实施例也适用于数据引线和数 据引线维修线。
维修如实施例二所示的液晶面板的驱动芯片组件连接位置的断路不良 的方法， 本实施例的维修方法与实施例八的维修方法类似， 区别在于需根 据断路位置 17的不同选择； t早接方法。
如图 14所示， 当断路位置 17在栅极引线 3上（也就是在栅极引线维 修线 8的两段交叠部分 8-1之间） 时， 对断路位置两侧的栅极引线 3与栅 极引线维修线 8的两段交叠部分 8-1的两个交叠位置 5分别进行； t早接而实 现维修； 这种情况下， 由于两次焊接均在阵列基板上进行， 故焊接过程中 不用调整激光熔融设备的参数，操作简便； 而且，在驱动芯片组件 7上（尤 其是薄膜芯片上）进行激光熔融易于烧坏驱动芯片组件 7, 本实施例的方 法可进行减少在驱动芯片组件 7上的; t早接， 从而降低在维修中损坏驱动芯 片组件 7的可能；
而当断路位置 17如图 15或图 16所示， 位于芯片引线 12上或位于芯 片引线 12与栅极引线 3的电连接位置时，则使用类似实施例八的方法进行 维修， 其中栅极引线维修线 8的交叠部分 8-1与栅极引线 3的交叠位置有 两个， 可对其中任意一个进行； t早接。
以上所述， 仅为本发明实施例的具体实施方式， 但本发明的保护范围并 不局限于此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可轻易想到变化或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发明 的保护范围应以权利要求的保护范围为准。

Claims

权利要求书
1、 一种液晶面板， 包括：
驱动芯片组件， 具有芯片引线和芯片维修线， 所述芯片维修线 与所述芯片引线交叠但绝缘；
阵列基板， 具有阵列基板引线和阵列基板维修线， 所述阵列基 板维修线与所述阵列基板引线交叠但绝缘；
其中所述驱动芯片组件安装到所述阵列基板上， 所述阵列基板 引线与对应的所述芯片引线电连接， 以及
所述芯片维修线的两端分别与对应的所述阵列基板维修线的 两端电连接。
2、 根据权利要求 1 所述的液晶面板， 其中所述阵列基板维修 线包括两段与所述阵列基板引线交叠但绝缘的交叠部分， 两段所述 交叠部分的位于所述阵列基板引线同一侧的两个端头分别连接， 连 接后的两个共同端头再分别与对应的所述芯片维修线的两端电连 接。
3、 根据权利要求 1 所述的液晶面板， 其中所述阵列基板引线 包括栅极引线， 所述阵列基板维修线包括栅极引线维修线， 所述栅 极引线维修线与所述栅极引线通过其间的栅极绝缘层而彼此绝缘。
4、 根据权利要求 1 所述的液晶面板， 其中所述阵列基板引线 包括数据引线， 所述阵列基板维修线包括数据引线维修线， 所述数 据引线维修线与所述数据引线通过其间的栅极绝缘层而彼此绝缘。
5、 根据权利要求 1 所述的液晶面板， 其中所述阵列基板引线 包括栅极引线和数据引线， 所述阵列基板维修线包括栅极引线维修 线和数据引线维修线； 所述栅极引线维修线与所述数据引线处于同 一层， 且与所述栅极引线通过栅极绝缘层而彼此绝缘； 所述数据引 线维修线与所述栅极引线处于同一层， 且与所述数据引线通过所述 栅极绝缘层而彼此绝缘。
6、 根据权利要求 1 所述的液晶面板， 其中所述驱动芯片组件 包括薄膜芯片或覆晶玻璃芯片。
7、 根据权利要求 1 所述的液晶面板， 其中所述芯片维修线与 一条或多条所述芯片引线相交叠， 所述阵列基板维修线与一条或多 条所述阵列基板引线相交叠。
8、 根据权利要求 1 所述的液晶面板， 其中所述驱动芯片组件 通过各向异性导电胶安装到所述阵列基板上， 所述阵列基板维修线 的末端有导电电极， 所述导电电极上有所述各向异性导电胶， 所述 各向异性导电胶与所述芯片维修线末端连接。
9、 根据权利要求 1 所述的液晶面板， 其中所述阵列基板维修 线和所述芯片维修线为单层结构或多个层的复合层结构。
10、 根据权利要求 10 所述的液晶面板， 其中所述单层结构或 复合层结构由选自铝、 铬、 钨、 钽、 钛、 钼、 铝镍合金、 钨钼合金 中的任意一种材料制成。
11、 一种制造液晶面板的方法， 包括以下步骤：
在阵列基板上形成阵列基板引线和阵列基板维修线， 其中所述 阵列基板维修线与所述阵列基板引线交叠但绝缘；
在驱动芯片组件上形成芯片引线和芯片维修线， 其中所述芯片 维修线与所述芯片引线交叠但绝缘；
将所述驱动芯片组件安装到所述阵列基板上， 使所述阵列基板 维修线的两端与对应的所述芯片维修线的两端形成电连接， 并且使 所述阵列基板引线与所述芯片引线形成电连接。
12、 根据权利要求 1 1 所述的制造液晶面板的方法， 其中所述 阵列基板引线包括栅极引线， 所述阵列基板维修线包括栅极引线维 修线， 其中所述在阵列基板上形成阵列基板引线和阵列基板维修线 的步骤包括：
在所述阵列基板上形成栅极引线金属层， 通过构图工艺由所述 栅极引线金属层形成栅极引线；
在所述阵列基板上形成栅极绝缘层；
在所述栅极绝缘层上形成数据引线金属层， 通过构图工艺由所 述数据引线金属层中同时形成数据引线和所述栅极引线维修线。
13、 根据权利要求 1 1 所述的制造液晶面板的方法， 其中所述 阵列基板引线包括数据引线， 所述阵列基板维修线包括数据引线维 修线， 其中所述在阵列基板上形成阵列基板引线和阵列基板维修线 的步骤包括：
在所述阵列基板上沉积栅极引线金属层， 通过构图工艺在所述 栅极引线金属层中同时形成栅极引线和所述数据引线维修线；
在所述阵列基板上沉积栅极绝缘层；
在所述栅极绝缘层上沉积数据引线金属层， 通过构图工艺在所 述数据引线金属层中同时形成所述数据引线。
14、 根据权利要求 1 1 所述的制造液晶面板的方法， 其中所述 在驱动芯片组件上形成芯片引线和芯片维修线的步骤包括：
在所述驱动芯片组件的基板上形成芯片引线金属层， 通过构图 工艺由所述芯片引线金属层形成所述芯片引线； 在所述驱动芯片组 件上形成芯片绝缘层； 在所述芯片绝缘层上形成芯片维修线金属层， 通过构图工艺由所述芯片维修线金属层形成所述芯片维修线。
15、 根据权利要求 1 1 所述的制造液晶面板的方法， 其中所述 在驱动芯片组件上形成芯片引线和芯片维修线的步骤包括：
在所述驱动芯片组件的基板上形成芯片维修线金属层， 通过构 图工艺由所述芯片维修线金属层形成所述芯片维修线； 在所述驱动 芯片组件上形成芯片绝缘层； 在所述芯片绝缘层上形成芯片引线金 属层， 通过构图工艺由所述芯片引线金属层形成所述芯片引线。
16、 根据权利要求 1 1 所述的制造液晶面板的方法， 其中使所 述阵列基板维修线和所述芯片维修线形成电连接的步骤包括：
通过各向异性导电胶将所述驱动芯片组件安装到所述阵列基 板上， 使所述芯片维修线与所述阵列基板维修线实现电连接。
17、 一种维修如权利要求 1所述的液晶面板的驱动芯片组件连 接位置的断路不良的方法， 包括以下步骤：
确定所述驱动芯片组件连接位置的断路位置；
对所述断路位置一侧的阵列基板维修线与阵列基板引线的交 叠位置进行焊接以实现二者的电连接；
对所述断路位置另一侧的芯片维修线与芯片引线的交叠位置 进行焊接以实现二者的电连接， 其中所述芯片引线与所述阵列基板 引线之间的电连接由于所述断路位置而断开。
18、 根据权利要求 17 所述的维修液晶面板的驱动芯片组件连 接位置的断路不良的方法， 其中所述焊接通过激光熔融实现。
19、 一种维修根据权利要求 2的液晶面板的驱动芯片组件连接 位置的断路不良的方法， 包括以下步骤：
确定所述驱动芯片组件连接位置的断路位置；
当所述断路位置位于阵列基板引线上时， 对所述断路位置两侧 的阵列基板维修线的两段交叠部分与阵列基板引线的两交叠位置分 别进行焊接以实现所述阵列基板引线与所述阵列基板维修线的电连 接； 其中， 所述阵列基板引线与驱动芯片组件上的芯片引线之间的 电连接由于上述断路位置而断开；
当所述断路位置位于所述芯片引线上或位于芯片引线与阵列 基板引线的电连接位置时， 对所述断路位置一侧的阵列基板维修线 的任一交叠部分与阵列基板引线的交叠位置进行焊接以实现所述阵 列基板引线与所述阵列基板维修线的电连接， 并对所述断路位置另 一侧的芯片维修线与芯片引线的交叠位置进行焊接以实现所述芯片 维修线与芯片引线的电连接。
20、 根据权利要求 19所述的维修液晶面板的驱动芯片组件连接位 置的断路不良的方法， 其中所述焊接通过激光熔融实现。
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