WO2021212579A1 - 阵列基板及其制造方法、显示装置 - Google Patents

阵列基板及其制造方法、显示装置 Download PDF

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WO2021212579A1
WO2021212579A1 PCT/CN2020/090401 CN2020090401W WO2021212579A1 WO 2021212579 A1 WO2021212579 A1 WO 2021212579A1 CN 2020090401 W CN2020090401 W CN 2020090401W WO 2021212579 A1 WO2021212579 A1 WO 2021212579A1
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layer
conductive
patterned
sub
conductive layer
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PCT/CN2020/090401
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English (en)
French (fr)
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赵斌
张鑫
肖军城
曹丹
刘俊领
胡小波
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/964,203 priority Critical patent/US20230154932A1/en
Publication of WO2021212579A1 publication Critical patent/WO2021212579A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • This application relates to the field of display technology, and in particular to an array substrate, a manufacturing method thereof, and a display device.
  • miniaturized light-emitting diodes have become one of the hotspots of display technology in the future.
  • miniaturized light-emitting diodes are more responsive Fast, high color gamut, high PPI, low energy consumption and other advantages, but its technical difficulties are many and the technology is complex, especially its key technology mass transfer technology, the miniaturization of light-emitting diode particles has become the technical bottleneck, while the sub-millimeter light-emitting diode (Mini- LED), as a product of the combination of miniaturized light-emitting diodes and backplanes, has the characteristics of high contrast and high color rendering performance comparable to organic light-emitting diodes.
  • Mini- LED sub-millimeter light-emitting diode
  • FIG. 1 it is a schematic diagram of a traditional Mini-LED backlight module.
  • the conventional sub-millimeter light emitting diode backlight module includes: a substrate 200; a gate 2011 and a first conductive member 2012 formed on the substrate 200; a gate insulating layer 202 covering the substrate 200, the gate 2011 and the first conductive member 2012; forming The active layer 203 provided on the gate insulating layer 202 and corresponding to the gate 2011; the source and drain electrodes (2041, 2042) formed on the active layer 203 and the conductive electrode 2043 on the gate insulating layer 202; covering the source and drain electrodes (2041, 2042) and the gate insulating layer 202 and the interlayer insulating layer 205 exposing the conductive electrode 2043; formed on the interlayer insulating layer 205 and passing through the interlayer insulating layer 205 and the via hole on the gate insulating layer 202 and The indium tin oxide layer 206 electrically connected to the first conductive member 2012; the light shielding layer 207 formed on the interlayer insulating layer 205.
  • the purpose of the present application is to provide an array substrate, a manufacturing method thereof, and a display device, so as to simplify the production process of the array substrate and the display device.
  • the present application provides a manufacturing method of an array substrate, the method includes the following steps:
  • first conductive layer Forming a first conductive layer on a substrate, patterning the first conductive layer by a first patterning process to obtain a first patterned conductive layer, the first patterned conductive layer including a gate and a first conductive member;
  • a second conductive layer is formed on the side of the semiconductor layer away from the substrate and in the via hole, and the second conductive layer and the semiconductor layer are patterned by a third patterning process to form an active layer and a second conductive layer.
  • Two conductive parts, source and drain electrodes and conductive electrodes, the second conductive part is electrically connected to the first conductive part through the via hole;
  • a black negative photoresist layer covering the second insulating layer is formed, and the second conductive member and the black negative photoresist layer corresponding to the conductive electrode are removed by a fourth patterning process to obtain a patterned black negative Photoresist layer;
  • the second insulating layer is a silicon nitride layer.
  • the thickness of the black negative photoresist layer is 0.5 micrometers to 200 micrometers, and the thickness of the second insulating layer is 600 angstroms to 2000 angstroms.
  • the dry etching removing the second conductive member and the second insulating layer corresponding to the conductive electrode includes the following steps:
  • Dry etching is used to etch and remove the second conductive member and the second insulating layer corresponding to the conductive electrode at an etching rate of 10,000 angstroms/min to 10500 angstroms/min.
  • the second conductive layer includes a first sub-conductive layer, a second sub-conductive layer, and a third sub-conductive layer, and the second sub-conductive layer is located between the first sub-conductive layer and the first sub-conductive layer.
  • the first sub-conductive layer is close to the substrate, the third sub-conductive layer is far away from the substrate, and the third sub-conductive layer and the first sub-conductive layer are
  • the preparation material is selected from any one of MoTiNi alloy, MoNbTa alloy, Mo, Ti and Ni, and the preparation material of the second sub-conductive layer is copper or copper alloy.
  • the preparation material of the third sub-conducting layer and the first sub-conducting layer is MoTiNi alloy or MoNbTa alloy, and the preparation material of the second sub-conducting layer is copper.
  • the manufacturing method further includes the following steps:
  • the sub-millimeter light emitting diode is connected to the conductive electrode, and the flip chip film is bound to the second conductive member.
  • a patterned semiconductor layer formed on a side of the first insulating layer away from the substrate, the patterned semiconductor layer including an active layer;
  • the second patterned conductive layer includes a second conductive member, a source and drain electrode, and a conductive electrode.
  • the second conductive member passes The via holes communicating on the first insulating layer and the patterned semiconductor layer are electrically connected to the first conductive member;
  • a second insulating layer covering the first insulating layer, the source and drain electrodes, the active layer and exposing the second conductive member and the conductive electrode;
  • a patterned black negative photoresist layer formed on the second insulating layer and exposing the second conductive element and the conductive electrode.
  • the second insulating layer is a silicon nitride layer.
  • the second patterned conductive layer includes a first sub-patterned conductive layer, a second sub-patterned conductive layer, and a third sub-patterned conductive layer, and the second sub-patterned conductive layer is located at the Between the first sub-patterned conductive layer and the third sub-patterned conductive layer, the first sub-patterned conductive layer is close to the substrate, and the third sub-patterned conductive layer is far away from the substrate.
  • the preparation materials of the third sub-patterned conductive layer and the first sub-patterned conductive layer are both MoTiNi alloy or MoNbTa alloy, and the preparation material of the second sub-patterned conductive layer is copper.
  • the thickness of the second insulating layer is 600 angstroms to 2000 angstroms.
  • a display device the display device includes an array substrate, and the array substrate includes:
  • a patterned semiconductor layer formed on a side of the first insulating layer away from the substrate, the patterned semiconductor layer including an active layer;
  • the second patterned conductive layer includes a second conductive member, a source and drain electrode, and a conductive electrode.
  • the second conductive member passes The via holes communicating on the first insulating layer and the patterned semiconductor layer are electrically connected to the first conductive member;
  • a second insulating layer covering the first insulating layer, the source and drain electrodes, the active layer and exposing the second conductive member and the conductive electrode;
  • a patterned black negative photoresist layer formed on the second insulating layer and exposing the second conductive element and the conductive electrode.
  • the second insulating layer is a silicon nitride layer.
  • the second patterned conductive layer includes a first sub-patterned conductive layer, a second sub-patterned conductive layer, and a third sub-patterned conductive layer, and the second sub-patterned conductive layer is located at the Between the first sub-patterned conductive layer and the third sub-patterned conductive layer, the first sub-patterned conductive layer is close to the substrate, and the third sub-patterned conductive layer is far away from the substrate.
  • the preparation materials of the third sub-patterned conductive layer and the first sub-patterned conductive layer are both MoTiNi alloy or MoNbTa alloy, and the preparation material of the second sub-patterned conductive layer is copper.
  • the thickness of the second insulating layer is 600 angstroms to 2000 angstroms.
  • the present application provides an array substrate, a manufacturing method thereof, and a display device.
  • the second insulating layer is etched by using a patterned black negative photoresist layer as an etching stop layer, so that the second insulating layer is used to transmit electrical signals and is in the same layer as the source and drain electrodes.
  • Two conductive elements are exposed.
  • the second conductive element replaces indium tin oxide in the traditional technology to electrically connect with the drive chip, reducing the process of forming indium tin oxide, and reducing the use of a photomask, simplifying the process, saving production costs, and improving production efficient.
  • the patterned black negative photoresist layer will not cause pollution to the etching equipment during the dry etching process of the second insulating layer as an etching stop layer, and the patterned black negative photoresist layer will be etched on the second insulating layer. There will be no deformation afterwards.
  • the thickness of the black negative photoresist layer and the thickness of the second insulating layer are optimized to ensure the effective thickness of the black negative photoresist layer after dry etching of the second insulating layer.
  • the material and composition of the second conductive layer are optimized to improve the oxidation resistance and conductivity of the second conductive member and the conductive electrode, and avoid the second conductive layer during the baking process of the patterning of the black negative photoresist layer.
  • the welding effect of light emitting diodes and conductive electrodes are oxidized, indium tin is welded to the conductive electrodes, and the conductivity of the second conductive layer is better than that of indium tin oxide, which is beneficial to reduce the impedance of the second conductive part and improve the signal Transmission capacity.
  • Figure 1 is a schematic diagram of a conventional sub-millimeter light-emitting diode backlight module
  • FIG. 2 is a flowchart of a manufacturing method of an array substrate according to an embodiment of the application
  • 3A-3G are schematic diagrams of the process of manufacturing the array substrate according to the flowchart shown in FIG. 2;
  • FIG. 4 is a schematic diagram of the patterned black negative photoresist layer after the second insulating layer is dry-etched.
  • FIG. 2 is a flowchart of a manufacturing method of an array substrate according to an embodiment of the application.
  • the manufacturing method of the array substrate includes the following steps:
  • a first conductive layer is formed on a substrate, and the first conductive layer is patterned by a first patterning process to obtain a first patterned conductive layer.
  • the first patterned conductive layer includes a gate and a first conductive member.
  • the entire surface of the first conductive layer is formed on the substrate 100, and the entire surface of the photoresist is coated on the first conductive layer.
  • the photoresist is exposed to the first mask and developed by the developer, it is removed by wet etching.
  • the first conductive layer not covered by the photoresist is removed from the remaining photoresist to obtain a first patterned conductive layer.
  • the first patterned conductive layer includes a gate electrode 1011 and a first conductive member 1012, as shown in FIG. 3A.
  • the first conductive layer includes a molybdenum layer and a copper layer sequentially disposed on the substrate 100.
  • the first insulating layer 102 is a gate insulating layer.
  • the material of the first insulating layer 102 is at least one of silicon oxide and silicon nitride.
  • the thickness of the first insulating layer 102 is 1000 angstroms to 15000 angstroms, such as 1500 angstroms, 2000 angstroms, 3000 angstroms, and 5000 angstroms, to protect the electrical insulation of the device.
  • S103 A semiconductor layer covering the first insulating layer is formed, and a via hole penetrating the first insulating layer and the semiconductor layer is formed by a second patterning process, and the via hole is provided corresponding to the first conductive member.
  • an amorphous silicon layer 1031 covering the first insulating layer 102 and an n-type doped amorphous silicon layer 1032 are sequentially formed, and an entire surface photoresist is formed on the n-type doped amorphous silicon 1032, and the photoresist passes through the second After the photomask is exposed and developed by the developer, the semiconductor layer and the first insulating layer 102 are dry-etched to form a via 103a penetrating the first insulating layer 102 and the semiconductor layer.
  • the via 103a is provided corresponding to the first conductive member 1012, such as Shown in Figure 3C.
  • the size of the via hole 103 a is 3 ⁇ m-30 ⁇ m, which facilitates the overlap between the second conductive member formed subsequently and the first conductive member 1012 through the via hole 103 a.
  • they are 5 micrometers, 10 micrometers, 15 micrometers, 20 micrometers, and 30 micrometers.
  • a second conductive layer is formed on the side of the semiconductor layer away from the substrate and in the via hole, and the second conductive layer and the semiconductor layer are patterned by a third patterning process to form an active layer, a second conductive member, source and drain electrodes, and The conductive electrode, the second conductive element is electrically connected with the first conductive element through the via hole.
  • a second conductive layer is formed on the entire surface of the n-type doped amorphous silicon layer 1032, a photoresist is formed on the surface of the second conductive layer, and the photoresist is exposed using a halftone gray-scale mask to define that the photoresist is fully retained Area, photoresist semi-reserved area, and photoresist removal area.
  • One photoresist fully reserved area corresponds to the first conductive member 1012 to facilitate subsequent patterning of the second conductive layer to form the second conductive member 1041, and a photoresist fully reserved area corresponds to the subsequent A region for binding the conductive electrode of the sub-millimeter light-emitting diode is formed.
  • a photoresist semi-reserved area corresponds to a part of the gate electrode 1011 to facilitate the subsequent formation of source and drain electrodes (1043, 1044).
  • the photoresist removal area is located in the photoresist semi-reserved area. Between the area and the photoresist completely reserved area.
  • the n-type doped amorphous silicon layer in the reserved area forms the source and drain electrodes (1043, 1044) and the active layer, as shown in FIG. 3D.
  • the second conductive layer includes a first sub-conductive layer, a second sub-conductive layer, and a third sub-conductive layer, the second sub-conductive layer is located between the first sub-conductive layer and the third sub-conductive layer, and the first sub-conductive layer is close to the substrate 100.
  • the third sub-conducting layer is far away from the substrate 100.
  • the preparation materials of the third sub-conducting layer and the first sub-conducting layer are selected from any one of MoTiNi alloy, MoNbTa alloy, Mo, Ti, and Ni.
  • the second sub-conducting layer is The preparation material is copper or copper alloy.
  • the second sub-conductive layer is made of copper or copper alloy, which improves the conductivity of the second conductive member 1041 and the conductive electrode 1042.
  • the preparation materials of the second conductive member 1041 are all metals, and the conductivity of the metal is better than that of indium tin oxide. The conductivity of the second conductive member 1041 is improved.
  • the second conductive member 1041 is provided on the same layer as the source and drain electrodes (1043, 1044). To bond the flip chip film.
  • the preparation material of the first sub-conductive layer is MoTiNi alloy or MoNbTa alloy, which on the one hand prevents the second sub-conductive layer from oxidizing, on the other hand, prevents the second sub-conductive layer from diffusing, or, the preparation of the first sub-conductive layer
  • the material of Mo can better prevent the diffusion of the second sub-conductive layer.
  • the preparation material of the third sub-conductive layer is MoTiNi alloy or MoNbTa alloy to avoid oxidation of the second sub-conductive layer.
  • the preparation material of the second sub-conductive layer is copper.
  • the thickness of the first sub-conductive layer is 50 angstroms-1000 angstroms, such as 200 angstroms, 400 angstroms, 600 angstroms, and 800 angstroms; the thickness of the third sub-conductive layer is 50 angstroms-1000 angstroms, such as 200 angstroms, 400 angstroms, 600 angstroms and 800 angstroms; the thickness of the second sub-conducting layer is 4000-6000 angstroms, for example, 4500 angstroms, the thickness of the first sub-conducting layer, the second sub-conducting layer, and the third sub-conducting layer are selected to satisfy the conductive electrode 1042 Good compatibility with solder paste is required.
  • S105 forming a second insulating layer covering the second conductive member, the source and drain electrodes, the active layer, the conductive electrode, and the first insulating layer.
  • the second insulating layer 105 covering the second conductive member 1041, the source and drain electrodes (1043, 1044), the conductive electrode 1042, and the first insulating layer 102 is formed by chemical vapor deposition, as shown in FIG. 3E.
  • the material of the second insulating layer 105 is silicon nitride.
  • the thickness of the second insulating layer is 600 angstroms to 2000 angstroms, such as 800 angstroms, 1000 angstroms, 1500 angstroms, or 1700 angstroms.
  • the second insulating layer 105 plays a role of electrical insulation, and on the other hand, it avoids the second insulating layer. Excessive thickness of 105 results in subsequent etching of the second insulating layer 105, resulting in failure of the patterned black negative photoresist layer.
  • S106 Form a black negative photoresist layer covering the second insulating layer, and use a fourth patterning process to remove the second conductive member and the black negative photoresist layer corresponding to the conductive electrode to obtain a patterned black negative Sexual photoresist layer.
  • the entire surface of the black negative photoresist layer 106 is coated on the second insulating layer 105, and the thickness of the black negative photoresist layer is 0.5 ⁇ m to 200 ⁇ m.
  • the black negative photoresist has better corrosion resistance and stability after exposure, so as to avoid the obvious loss of performance of the black negative photoresist during the dry etching process of the second insulating layer.
  • the fourth photomask is used to expose the black negative photoresist layer, and the unexposed part of the black negative photoresist layer is etched with a developer to obtain a patterned black negative photoresist layer, as shown in FIG. 3F.
  • the patterned black negative photoresist is used as the etching stop layer, and the second insulating layer is etched with a common etching atmosphere.
  • the etching atmosphere includes nitrogen trifluoride, oxygen and helium, and dry etching is used at a rate of 10000 angstroms/min-10500 angstroms/min.
  • the etching rate of min etches away the second conductive member and the second insulating layer corresponding to the conductive electrode, so that the second conductive member and the conductive electrode are exposed, as shown in FIG. 3G.
  • a sub-millimeter light emitting diode (not shown) is connected to the conductive electrode 1042, and a flip chip film (not shown) is bound to the second conductive member 1041.
  • the loss of the black negative photoresist layer due to dry etching of the second insulating layer is relatively small, which will not affect the patterned black negative The light-shielding property of the photoresist.
  • experiment 1 and experiment 2 are based on the average thickness of the five points of the BM before and after etching.
  • FIG. 4 is a schematic diagram of the patterned black negative photoresist layer after dry etching on the second insulating layer.
  • the pattern of the patterned black negative photoresist does not appear abnormal after being etched by the second insulating layer, indicating that the dry etching process of silicon nitride will not cause damage to the pattern of the patterned black negative photoresist.
  • the inventors have also verified through experiments that the patterned black negative photoresist will not pollute the dry etching equipment during the etching of the second insulating layer, so that the patterned black negative photoresist is used as the etching stop layer in the dry etching process.
  • the etching process is feasible, and the slope feet on the second insulating layer after etching the second insulating layer at an etching rate of 10,000 angstroms/min-10500 angstroms/min meet the requirements.
  • the application also provides a backlight module, the backlight module includes an array substrate, and the array substrate includes:
  • a patterned semiconductor layer formed on a side of the first insulating layer away from the substrate, the patterned semiconductor layer including an active layer;
  • the second patterned conductive layer includes a second conductive member, a source and drain electrode, and a conductive electrode.
  • the second conductive member passes through the first insulating layer and the patterned semiconductor
  • the via holes connected on the layer are electrically connected to the first conductive member; a second insulating layer covering the first insulating layer, the source and drain electrodes, the active layer and exposing the second conductive member and the conductive electrode;
  • a patterned black negative photoresist layer formed on the second insulating layer to expose the second conductive element and the conductive electrode.
  • the second insulating layer is a silicon nitride layer, and the thickness of the second insulating layer is 600 angstroms to 2000 angstroms.
  • the second patterned conductive layer includes a first sub-patterned conductive layer, a second sub-patterned conductive layer, and a third sub-patterned conductive layer.
  • the second sub-patterned conductive layer is located in the first sub-patterned conductive layer.
  • the first sub-patterned conductive layer is close to the substrate, the third sub-patterned conductive layer is far away from the substrate, the preparation of the third sub-patterned conductive layer and the first sub-patterned conductive layer
  • the material is MoTiNi alloy or MoNbTa alloy, and the preparation material of the second sub-patterned conductive layer is copper.
  • the sub-millimeter light emitting diode (Mini-LED) is connected to the conductive electrode by solder paste or conductive adhesive, the flip chip film is bound to the second conductive member, the flip chip film includes a flexible film and is arranged on the flexible film The driver chip.
  • the application also provides a display device, which includes the above-mentioned backlight module.

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Abstract

一种阵列基板及其制造方法、显示装置，通过以图案化黑色负性光阻层（106）作为蚀刻阻挡层蚀刻第二绝缘层（105），使得用于传输电信号且与源漏电极（1043/1044）同层的第二导电件（1041）显露，第二导电件（1041）替代传统技术中的氧化铟锡以与驱动芯片电性连接，减小形成氧化铟锡的制程，且减少使用一个光罩，简化制程，节约生产成本且提高生产效率。

Description

阵列基板及其制造方法、显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及其制造方法、显示装置。
背景技术
微型化发光二极管发展成未来显示技术的热点之一，和目前的液晶显示装置(Liquid Crystal Display，LCD)、有机发光二极管(Organic Light Emitting Diode，OLED)显示器件相比，微型化发光二极管具有反应快、高色域、高PPI、低能耗等优势，但其技术难点多且技术复杂，特别是其关键技术巨量转移技术、发光二极管颗粒微型化成为技术瓶颈，而亚毫米发光二极管(Mini-LED)作为微型化发光二极管与背板结合的产物，具有高对比度、高显色性能等可与有机发光二极管相媲美的特点，成本仅为有机发光二极管的60％左右，相对有机发光二极管更易实施，所以亚毫米发光二极管成为各大面板厂商布局热点。如图1所示，其为传统亚毫米发光二极管(Mini-LED)背光模组的示意图。传统亚毫米发光二极管背光模组包括：基板200；形成于基板200上的栅极2011以及第一导电件2012；覆盖基板200、栅极2011以及第一导电件2012的栅极绝缘层202；形成于栅极绝缘层202且对应栅极2011设置的有源层203；形成于有源层203上的源漏电极(2041，2042)以及栅极绝缘层202上的导电电极2043；覆盖源漏电极(2041，2042)以及栅极绝缘层202且使导电电极2043显露的层间绝缘层205；形成于层间绝缘层205上且通过层间绝缘层205以 及栅极绝缘层202上的过孔与第一导电件2012电连接的氧化铟锡层206；形成于层间绝缘层205上的遮光层207。传统亚毫米发光二极管背光模组存在制程繁多的缺点。
因此，有必要提出一种技术方案以解决传统亚毫米发光二极管存在制程繁多的问题。
技术问题
本申请的目的在于提供一种阵列基板及其制造方法、显示装置，以简化阵列基板及显示装置的生产制程。
技术解决方案
为实现上述目的，本申请提供一种阵列基板的制造方法，所述方法包括如下步骤：
于基板上形成第一导电层，利用第一次构图工艺图案化所述第一导电层得第一图案化导电层，所述第一图案化导电层包括栅极以及第一导电件；
形成覆盖所述第一图案化导电层以及所述基板的第一绝缘层；
形成覆盖所述第一绝缘层的半导体层，利用第二次构图工艺形成贯穿所述第一绝缘层以及所述半导体层的过孔，所述过孔对应所述第一导电件设置；
于所述半导体层远离所述基板的一侧以及所述过孔中形成第二导电层，利用第三次构图工艺图案化所述第二导电层以及所述半导体层，形成有源层、第二导电件、源漏电极以及导电电极，所述第二导电件通过所述过孔与所述第一导电件电连接；
形成覆盖所述第二导电件、源漏电极、所述有源层、导电电极以及所述第一绝缘层的第二绝缘层；
形成覆盖所述第二绝缘层的黑色负性光阻层，利用第四次构图工艺去除所述第二导电件以及所述导电电极对应的所述黑色负性光阻层，得图案化黑色负性光阻层；
以所述图案化黑色负性光阻层为蚀刻阻挡层，干法蚀刻去除所述第二导电件以及所述导电电极对应的所述第二绝缘层，得所述阵列基板。在上述阵列基板的制造方法中，所述第二绝缘层为氮化硅层。
在上述阵列基板的制造方法中，所述黑色负性光阻层的厚度为0.5微米-200微米，所述第二绝缘层的厚度为600埃-2000埃。
在上述阵列基板的制造方法中，所述干法蚀刻去除所述第二导电件以及所述导电电极对应的所述第二绝缘层包括如下步骤：
采用干法蚀刻以10000埃/min-10500埃/min的蚀刻速率蚀刻去除所述第二导电件以及所述导电电极对应的所述第二绝缘层。
在上述阵列基板的制造方法中，所述第二导电层包括第一子导电层、第二子导电层以及第三子导电层，所述第二子导电层位于所述第一子导电层和所述第三子导电层之间，所述第一子导电层靠近所述基板，所述第三子导电层远离所述基板，所述第三子导电层和所述第一子导电层的制备材料选自MoTiNi合金、MoNbTa合金、Mo、Ti以及Ni中的任意一种，所述第二子导电层的制备材料为铜或铜合金。
在上述阵列基板的制造方法中，所述第三子导电层和所述第一子导电层的制备材料为MoTiNi合金或MoNbTa合金，所述第二子导电层的 制备材料为铜。
在上述阵列基板的制造方法中，所述制造方法还包括如下步骤：
将亚毫米发光二极管连接在所述导电电极上，将覆晶薄膜绑定在所述第二导电件上。
一种阵列基板，所述阵列基板包括：
基板；
于所述基板上形成的第一图案化导电层，所述第一图案化导电层包括栅极以及第一导电件；
覆盖所述第一图案化导电层以及所述基板的第一绝缘层；
形成于所述第一绝缘层远离所述基板一侧的图案化半导体层，所述图案化半导体层包括有源层；
形成于所述图案化半导体层远离所述基板一侧的第二图案化导电层，所述第二图案化导电层包括第二导电件、源漏电极以及导电电极，所述第二导电件通过所述第一绝缘层和所述图案化半导体层上连通的过孔与所述第一导电件电性连接；
覆盖所述第一绝缘层、所述源漏电极、所述有源层且使所述第二导电件以及所述导电电极显露的第二绝缘层；
形成于所述第二绝缘层上且使所述第二导电件以及所述导电电极显露的图案化黑色负性光阻层。
在上述阵列基板中，所述第二绝缘层为氮化硅层。
在上述阵列基板中，所述第二图案化导电层包括第一子图案化导电层、第二子图案化导电层以及第三子图案化导电层，所述第二子图案 化导电层位于所述第一子图案导电层和所述第三子图案化导电层之间，所述第一子图案化导电层靠近所述基板，所述第三子图案化导电层远离所述基板，所述第三子图案化导电层和所述第一子图案化导电层的制备材料均为MoTiNi合金或MoNbTa合金，所述第二子图案化导电层的制备材料为铜。
在上述阵列基板中，所述第二绝缘层的厚度为600埃-2000埃。
一种显示装置，所述显示装置包括阵列基板，所述阵列基板包括：
基板；
于所述基板上形成的第一图案化导电层，所述第一图案化导电层包括栅极以及第一导电件；
覆盖所述第一图案化导电层以及所述基板的第一绝缘层；
形成于所述第一绝缘层远离所述基板一侧的图案化半导体层，所述图案化半导体层包括有源层；
形成于所述图案化半导体层远离所述基板一侧的第二图案化导电层，所述第二图案化导电层包括第二导电件、源漏电极以及导电电极，所述第二导电件通过所述第一绝缘层和所述图案化半导体层上连通的过孔与所述第一导电件电性连接；
覆盖所述第一绝缘层、所述源漏电极、所述有源层且使所述第二导电件以及所述导电电极显露的第二绝缘层；
形成于所述第二绝缘层上且使所述第二导电件以及所述导电电极显露的图案化黑色负性光阻层。
在上述显示装置中，所述第二绝缘层为氮化硅层。
在上述显示装置中，所述第二图案化导电层包括第一子图案化导电层、第二子图案化导电层以及第三子图案化导电层，所述第二子图案化导电层位于所述第一子图案导电层和所述第三子图案化导电层之间，所述第一子图案化导电层靠近所述基板，所述第三子图案化导电层远离所述基板，所述第三子图案化导电层和所述第一子图案化导电层的制备材料均为MoTiNi合金或MoNbTa合金，所述第二子图案化导电层的制备材料为铜。
在上述显示装置中，所述第二绝缘层的厚度为600埃-2000埃。
有益效果
本申请提供一种阵列基板及其制造方法、显示装置，通过以图案化黑色负性光阻层作为蚀刻阻挡层蚀刻第二绝缘层，使得用于传输电信号且与源漏电极同层的第二导电件显露，第二导电件替代传统技术中的氧化铟锡以与驱动芯片电性连接，减小形成氧化铟锡的制程，且减少使用一个光罩，简化制程，节约生产成本且提高生产效率。另外，经实验验证，图案化黑色负性光阻层作为蚀刻阻挡层在第二绝缘层干法蚀刻过程不会造成对蚀刻设备的污染，图案化黑色负性光阻层在第二绝缘层蚀刻后不会出现变形。
进一步地，对黑色负性光阻层的厚度以及第二绝缘层的厚度进行优选，以保证黑色负性光阻层在第二绝缘层干法蚀刻后的有效厚度。进一步地，对第二导电层的材料以及组成进行优选，提高第二导电件以及导电电极的抗氧化性以及导电性，避免在黑色负性光阻层制程图案化的烘烤制程中第二导电件以及导电电极氧化，铟锡焊接于导电电 极上的发光二极管的焊接效果，且第二导电层的导电性比氧化铟锡的导电性更好，有利于降低第二导电件的阻抗，提高信号的传输能力。
附图说明
图1为传统亚毫米发光二极管背光模组的示意图；
图2为本申请实施例阵列基板的制造方法的流程图；
图3A-3G为按照图2所示流程图制造阵列基板的过程示意图；
图4为图案化黑色负性光阻层在第二绝缘层经过干法蚀刻后的示意图。
本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图2，其为本申请实施例阵列基板的制造方法的流程图。阵列基板的制造方法包括如下步骤：
S101：于基板上形成第一导电层，利用第一次构图工艺图案化第一导电层得第一图案化导电层，第一图案化导电层包括栅极以及第一导电件。
具体地，于基板100上形成整面的第一导电层，于第一导电层上涂布整面的光阻，光阻经过第一光罩曝光以及显影液显影后，采用湿法蚀刻以去除光阻未覆盖的第一导电层，去除剩余的光阻，得第一图案化 导电层，第一图案化导电层包括栅极1011以及第一导电件1012，如图3A所示。第一导电层包括依次设置于基板100上的钼层以及铜层。
S102：形成覆盖第一图案化导电层以及基板的第一绝缘层。
具体地，采用化学气相沉积形成覆盖第一图案化导电层以及基板100的第一绝缘层102，如图3B所示。第一绝缘层102为栅极绝缘层。第一绝缘层102的制备材料为氧化硅以及氮化硅中的至少一种。第一绝缘层102的厚度为1000埃-15000埃，例如为1500埃、2000埃、3000埃以及5000埃，以起到保护器件的电性绝缘性。
S103：形成覆盖第一绝缘层的半导体层，利用第二次构图工艺形成贯穿第一绝缘层以及半导体层的过孔，过孔对应第一导电件设置。
具体地，依次形成覆盖第一绝缘层102的非晶硅层1031以及n型掺杂非晶硅层1032，于n型掺杂非晶硅1032上形成整面的光阻，光阻经过第二光罩曝光以及显影液显影后，经干法蚀刻半导体层以及第一绝缘层102，以形成贯穿第一绝缘层102以及半导体层的过孔103a，过孔103a对应第一导电件1012设置，如图3C所示。过孔103a的尺寸为3微米-30微米，有利于后续形成的第二导电件通过过孔103a与第一导电件1012之间实现搭接。例如为5微米、10微米、15微米、20微米以及30微米。
S104：于半导体层远离基板的一侧以及过孔中形成第二导电层，利用第三次构图工艺图案化第二导电层以及半导体层，形成有源层、第二导电件、源漏电极以及导电电极，第二导电件通过过孔与第一导电件电连接。
于n型掺杂非晶硅层1032上形成整面的第二导电层，于第二导电层的表面形成光阻，采用半色调灰阶掩模版对光阻进行曝光，以定义光阻全保留区、光阻半保留区以及光阻去除区，一个光阻全保留区对应第一导电件1012以便于后续第二导电层图案化后形成第二导电件1041，一个光阻全保留区对应后续形成用于绑定亚毫米发光二极管的导电电极的区域，一个光阻半保留区对应栅极1011的部分区域以便于后续形成源漏电极(1043，1044)，光阻去除区位于光阻半保留区以及光阻完全保留区之间。去除光阻去除区的光阻，采用湿法蚀刻对光阻去除区的第二导电层进去蚀刻，再采用干法蚀刻对光阻去除区的n型掺杂非晶硅层1032以及非晶硅层1031，形成第二导电件1041以及导电电极1042；再去除光阻半保留区的光阻，采用湿法蚀刻去除光阻半保留区的第二导电层，再采用干法蚀刻去除光阻半保留区的n型掺杂非晶硅层，形成源漏电极(1043，1044)以及有源层，如图3D所示。
第二导电层包括第一子导电层、第二子导电层以及第三子导电层，第二子导电层位于第一子导电层和第三子导电层之间，第一子导电层靠近基板100，第三子导电层远离基板100，第三子导电层和第一子导电层的制备材料选自MoTiNi合金、MoNbTa合金、Mo、Ti以及Ni中的任意一种，第二子导电层的制备材料为铜或铜合金。MoTiNi合金、MoNbTa合金、Mo、Ti以及Ni均具有良好的抗氧化性，可以避免第二导电件1041以及导电电极1042氧化。第二子导电层为铜或铜合金，提高第二导电件1041以及导电电极1042的导电性。第二导电件1041 的制备材料均为金属，金属导电性比氧化铟锡好，提高第二导电件1041的导电性，利用与源漏电极(1043，1044)同层设置的第二导电件1041以绑定覆晶薄膜。
第一子导电层的制备材料为MoTiNi合金或MoNbTa合金，一方面起到防止第二子导电层氧化的作用，另一方面避免第二子导电层发生扩散，或，第一子导电层的制备材料为Mo能更好地防止第二子导电层发生扩散。第三子导电层的制备材料为MoTiNi合金或MoNbTa合金，以避免第二子导电层氧化。第二子导电层的制备材料为铜。第一子导电层的厚度为50埃-1000埃，例如为200埃、400埃、600埃以及800埃；第三子导电层的厚度为50埃-1000埃，例如为200埃、400埃、600埃以及800埃；第二子导电层的厚度为4000埃-6000埃，例如为4500埃，第一子导电层、第二子导电层以及第三子导电层的厚度选自满足导电电极1042与锡膏具有良好融合性的要求。
S105：形成覆盖第二导电件、源漏电极、有源层、导电电极以及第一绝缘层的第二绝缘层。
采用化学气相沉积形成覆盖第二导电件1041、源漏电极(1043，1044)、导电电极1042以及第一绝缘层102的第二绝缘层105，如图3E所示。第二绝缘层105的制备材料为氮化硅。第二绝缘层的厚度为600埃-2000埃，例如为800埃、1000埃、1500埃、1700埃，一方面使得第二绝缘层105起到电性绝缘作用，另一方面避免第二绝缘层105过厚导致后续蚀刻第二绝缘层105导致图案化黑色负性光阻层失效。
S106：形成覆盖所述第二绝缘层的黑色负性光阻层，利用第四次构图工艺去除第二导电件以及所述导电电极对应的所述黑色负性光阻层，得图案化黑色负性光阻层。
于第二绝缘层105上涂布整面的黑色负性光阻层106，黑色负性光阻层的厚度为0.5微米-200微米。相对于普通光刻胶，黑色负性光阻在曝光后具有更好的耐腐蚀性以及稳定性，避免黑色负性光阻在第二绝缘层干法蚀刻过程中性能明显受损失。采用第四光罩对黑色负性光阻层进行曝光，采用显影液对黑色负性光阻层未曝光的部分进行蚀刻处理，得图案化黑色负性光阻层，如图3F所示。
S107：以图案化黑色负性光阻层为蚀刻阻挡层，干法蚀刻去除第二导电件以及导电电极对应的第二绝缘层，得阵列基板。
以图案化黑色负性光阻为蚀刻阻挡层，采用常见蚀刻气氛蚀刻第二绝缘层，例如蚀刻气氛包括三氟化氮、氧气以及氦气，采用干法蚀刻以10000埃/min-10500埃/min的蚀刻速率蚀刻去除第二导电件以及导电电极对应的第二绝缘层，使第二导电件以及导电电极显露，如图3G所示。将亚毫米发光二极管(未示出)连接在导电电极1042上，将覆晶薄膜(未示出)绑定在第二导电件1041上。
以下为图案化黑色负性光阻(Black Matrix，BM)作为蚀刻阻挡层的可行性实验的结果如下。
图案化黑色负性光阻损失量可行性结果如表1所示。
表1 图案化黑色负性光阻损失量可行性结果
Figure PCTCN2020090401-appb-000001
Figure PCTCN2020090401-appb-000002
由表1可知，每干法蚀刻1000埃氮化硅层，会损失200埃图案化黑色负性光阻。第二绝缘层的厚度为600埃-2000埃，黑色负性光阻的厚度为0.5微米-200微米，不会导致以图案化黑色负性光阻由于在第二绝缘层蚀刻后失效，剩余的图案化黑色负性光阻电性满足要求。特别是黑色负性光阻的厚度为1微米-1.5微米时，例如1.23微米时，由于干法蚀刻第二绝缘层损失的黑色负性光阻层相对较小，不会影响图案化黑色负性光阻的遮光性。
需要说明的是，实验1和实验2是以蚀刻前后BM的五个点的平均厚度。
图案化黑色负性光阻的图案正常验证如图4所示，其为图案化黑色负性光阻层在第二绝缘层经过干法蚀刻后的示意图。图案化黑色负性光阻的图案在经过第二绝缘层蚀刻后未出现异常，表明氮化硅的干法蚀刻过程不会对图案化黑色负性光阻的图案造成损伤。
此外，发明人还经过实验验证发现图案化黑色负性光阻在第二绝缘层蚀刻过程中不会对干法蚀刻设备造成污染，使得以图案化黑色负性光阻作为蚀刻阻挡层在干法蚀刻过程中具有可行性，且以10000埃 /min-10500埃/min的蚀刻速率蚀刻第二绝缘层后的第二绝缘层上的坡脚符合要求。
本申请还提供一种背光模组，背光模组包括阵列基板，阵列基板包括：
基板；
于基板上形成的第一图案化导电层，第一图案化导电层包括栅极以及第一导电件；
覆盖第一图案化导电层以及基板的第一绝缘层；
形成于第一绝缘层远离基板一侧的图案化半导体层，图案化半导体层包括有源层；
形成于图案化半导体层远离基板一侧的第二图案化导电层，第二图案化导电层包括第二导电件、源漏电极以及导电电极，第二导电件通过第一绝缘层和图案化半导体层上连通的过孔与第一导电件电性连接；覆盖第一绝缘层、源漏电极、有源层且使第二导电件以及导电电极显露的第二绝缘层；
形成于第二绝缘层上且使第二导电件以及导电电极显露的图案化黑色负性光阻层。
在本实施例中，第二绝缘层为氮化硅层，第二绝缘层的厚度为600埃-2000埃。
在本实施例中，第二图案化导电层包括第一子图案化导电层、第二子图案化导电层以及第三子图案化导电层，第二子图案化导电层位于第 一子图案化导电层和第三子图案化导电层之间，第一子图案化导电层靠近基板，第三子图案化导电层远离基板，第三子图案化导电层和第一子图案化导电层的制备材料为MoTiNi合金或MoNbTa合金，第二子图案化导电层的制备材料为铜。
在本实施例中，亚毫米发光二极管(Mini-LED)通过锡膏或者导电胶粘剂连接至导电电极，覆晶薄膜绑定在第二导电件上，覆晶薄膜包括柔性薄膜以及设置在柔性薄膜上的驱动芯片。
本申请还提供一种显示装置，显示装置包括上述背光模组。
以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (15)

  1. 一种阵列基板的制造方法，其中，所述方法包括如下步骤：
    于基板上形成第一导电层，利用第一次构图工艺图案化所述第一导电层得第一图案化导电层，所述第一图案化导电层包括栅极以及第一导电件；
    形成覆盖所述第一图案化导电层以及所述基板的第一绝缘层；
    形成覆盖所述第一绝缘层的半导体层，利用第二次构图工艺形成贯穿所述第一绝缘层以及所述半导体层的过孔，所述过孔对应所述第一导电件设置；
    于所述半导体层远离所述基板的一侧以及所述过孔中形成第二导电层，利用第三次构图工艺图案化所述第二导电层以及所述半导体层，形成有源层、第二导电件、源漏电极以及导电电极，所述第二导电件通过所述过孔与所述第一导电件电连接；
    形成覆盖所述第二导电件、源漏电极、所述有源层、导电电极以及所述第一绝缘层的第二绝缘层；
    形成覆盖所述第二绝缘层的黑色负性光阻层，利用第四次构图工艺去除所述第二导电件以及所述导电电极对应的所述黑色负性光阻层，得图案化黑色负性光阻层；
    以所述图案化黑色负性光阻层为蚀刻阻挡层，干法蚀刻去除所述第二导电件以及所述导电电极对应的所述第二绝缘层，得所述阵列基板。
  2. 根据权利要求1所述的阵列基板的制造方法，其中，所述第二绝缘层为氮化硅层。
  3. 根据权利要求1所述的阵列基板的制造方法，其中，所述黑色负性光阻层的厚度为0.5微米-200微米，所述第二绝缘层的厚度为600埃-2000埃。
  4. 根据权利要求1所述的阵列基板的制造方法，其中，所述干法蚀刻去除所述第二导电件以及所述导电电极对应的所述第二绝缘层包括如下步骤：
    采用干法蚀刻以10000埃/min-10500埃/min的蚀刻速率蚀刻去除所述第二导电件以及所述导电电极对应的所述第二绝缘层。
  5. 根据权利要求1所述的阵列基板的制造方法，其中，所述第二导电层包括第一子导电层、第二子导电层以及第三子导电层，所述第二子导电层位于所述第一子导电层和所述第三子导电层之间，所述第一子导电层靠近所述基板，所述第三子导电层远离所述基板。
  6. 根据权利要求5所述的阵列基板的制造方法，其中，所述第三子导电层和所述第一子导电层的制备材料为MoTiNi合金或MoNbTa合金，所述第二子导电层的制备材料为铜。
  7. 根据权利要求1所述的阵列基板的制造方法，其中，所述制造方法还包括如下步骤：
    将亚毫米发光二极管连接在所述导电电极上，将覆晶薄膜绑定在所述第二导电件上。
  8. 一种阵列基板，其中，所述阵列基板包括：
    基板；
    于所述基板上形成的第一图案化导电层，所述第一图案化导电层包括栅极以及第一导电件；
    覆盖所述第一图案化导电层以及所述基板的第一绝缘层；
    形成于所述第一绝缘层远离所述基板一侧的图案化半导体层，所述图案化半导体层包括有源层；
    形成于所述图案化半导体层远离所述基板一侧的第二图案化导电层，所述第二图案化导电层包括第二导电件、源漏电极以及导电电极，所述第二导电件通过所述第一绝缘层和所述图案化半导体层上连通的过孔与所述第一导电件电性连接；
    覆盖所述第一绝缘层、所述源漏电极、所述有源层且使所述第二导电件以及所述导电电极显露的第二绝缘层；
    形成于所述第二绝缘层上且使所述第二导电件以及所述导电电极显露的图案化黑色负性光阻层。
  9. 根据权利要求8所述的阵列基板，其中，所述第二绝缘层为氮化硅层。
  10. 根据权利要求8所述的阵列基板，其中，所述第二图案化导电层包括第一子图案化导电层、第二子图案化导电层以及第三子图案化导电层，所述第二子图案化导电层位于所述第一子图案导电层和所述第三子图案化导电层之间，所述第一子图案化导电层靠近所述基板，所述第三子图案化导电层远离所述基板，所述第三子图案化导电层和所 述第一子图案化导电层的制备材料均为MoTiNi合金或MoNbTa合金，所述第二子图案化导电层的制备材料为铜。
  11. 根据权利要求8所述的阵列基板，其中，所述第二绝缘层的厚度为600埃-2000埃。
  12. 一种显示装置，其中，所述显示装置包括阵列基板，所述阵列基板包括：
    基板；
    于所述基板上形成的第一图案化导电层，所述第一图案化导电层包括栅极以及第一导电件；
    覆盖所述第一图案化导电层以及所述基板的第一绝缘层；
    形成于所述第一绝缘层远离所述基板一侧的图案化半导体层，所述图案化半导体层包括有源层；
    形成于所述图案化半导体层远离所述基板一侧的第二图案化导电层，所述第二图案化导电层包括第二导电件、源漏电极以及导电电极，所述第二导电件通过所述第一绝缘层和所述图案化半导体层上连通的过孔与所述第一导电件电性连接；
    覆盖所述第一绝缘层、所述源漏电极、所述有源层且使所述第二导电件以及所述导电电极显露的第二绝缘层；
    形成于所述第二绝缘层上且使所述第二导电件以及所述导电电极显露的图案化黑色负性光阻层。
  13. 根据权利要求12所述的显示装置，其中，所述第二绝缘层为氮化硅层。
  14. 根据权利要求12所述的显示装置，其中，所述第二图案化导电层包括第一子图案化导电层、第二子图案化导电层以及第三子图案化导电层，所述第二子图案化导电层位于所述第一子图案导电层和所述第三子图案化导电层之间，所述第一子图案化导电层靠近所述基板，所述第三子图案化导电层远离所述基板，所述第三子图案化导电层和所述第一子图案化导电层的制备材料均为MoTiNi合金或MoNbTa合金，所述第二子图案化导电层的制备材料为铜。
  15. 根据权利要求12所述的显示装置，其中，所述第二绝缘层的厚度为600埃-2000埃。
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