WO2022111134A1 - 显示面板及其制备方法、显示装置 - Google Patents

显示面板及其制备方法、显示装置 Download PDF

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Publication number
WO2022111134A1
WO2022111134A1 PCT/CN2021/124659 CN2021124659W WO2022111134A1 WO 2022111134 A1 WO2022111134 A1 WO 2022111134A1 CN 2021124659 W CN2021124659 W CN 2021124659W WO 2022111134 A1 WO2022111134 A1 WO 2022111134A1
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Prior art keywords
light
emitting
patterns
pattern
base substrate
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PCT/CN2021/124659
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English (en)
French (fr)
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李彦松
刘月
毕娜
白珊珊
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京东方科技集团股份有限公司
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Priority to US17/922,557 priority Critical patent/US20230354641A1/en
Publication of WO2022111134A1 publication Critical patent/WO2022111134A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/352—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels the areas of the RGB subpixels being different
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/822—Cathodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80515—Anodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/875—Arrangements for extracting light from the devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/8791—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K59/8792—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. black layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/60—Forming conductive regions or layers, e.g. electrodes

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel, a method for manufacturing the display panel, and a display device including the display panel.
  • the more mainstream approach is the "low pixel density scheme", that is, reducing the pixel density of the under-screen camera display area to increase the gap between sub-pixels in the under-screen camera display area, thereby increasing the light transmittance.
  • the sparse pixel density in this area will cause the display to be different from the surrounding normal display area, reducing the look and feel. Therefore, how to improve the light transmittance of the display panel in the camera display area under the screen under the premise of ensuring no difference in display is a problem.
  • the purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art, and to provide a display panel, a manufacturing method of the display panel, and a display device including the display panel.
  • a display panel having a first area and a second area, the display panel comprising:
  • the light-emitting layer disposed on one side of the base substrate, the light-emitting layer includes a plurality of light-emitting patterns, and the orthographic projections of the plurality of light-emitting patterns on the base substrate do not overlap each other;
  • a plurality of transparent suppression patterns disposed on one side of the base substrate, and located between at least some of the adjacent light-emitting patterns, and the transparent suppression patterns are located in the first region, a plurality of the transparent suppression patterns Interval setting between patterns;
  • the first electrode is arranged on the side of the light-emitting layer away from the base substrate, a plurality of through holes are arranged on the first electrode, and the orthographic projection of the through holes on the base substrate is the same as that of all the through holes.
  • the orthographic projections of the transparent suppression pattern on the base substrate are coincident.
  • the pixel density of the first region is the same as the pixel density of the second region.
  • the display panel further includes:
  • planarization layer disposed on one side of the base substrate, and a first via hole is disposed on the planarization layer
  • a pixel definition layer is arranged on the side of the planarization layer away from the base substrate, and a third via hole and a fourth via hole are arranged on the pixel definition layer, and the third via hole is connected with the first via hole.
  • a via hole is connected;
  • the transparent suppression pattern is provided in the connected first via hole and the third via hole, and the light emitting pattern is provided in the fourth via hole.
  • the material of the transparent suppression pattern is a strong polar inorganic material or a strong polar organic material
  • the material of the first electrode is a conductive metal
  • the display panel further includes pixel units arranged in an array, and the pixel units include a first light-emitting pattern, a second light-emitting pattern, and two third light-emitting patterns, so The peripheral tangent of the pixel unit forms a rectangle;
  • the corners of two adjacent rectangles are arranged opposite to each other, and a plurality of the rectangles are arranged to form multiple rows, and the two adjacent rows are arranged in a staggered position; one of the transparent suppression patterns.
  • the transparent suppression pattern includes a middle region and four edge regions connected to the middle region, the middle region is circular, and the edge regions are elongated.
  • the first light-emitting patterns and the second light-emitting patterns are alternately arranged to form a first row, and the third light-emitting patterns are arranged to form a second row;
  • first row and the second row are alternately arranged, and the first direction and the second direction are perpendicular;
  • Two first light-emitting patterns and two second light-emitting patterns distributed in two adjacent rows and two columns form a virtual quadrilateral, and the third light-emitting pattern is located in the virtual quadrilateral;
  • the transparency suppression pattern is provided between two adjacent third light emitting patterns, and the transparency suppression pattern is provided between the adjacent first light emitting patterns and the second light emitting patterns.
  • the display panel further includes pixel units arranged in an array, and the pixel units include a first light-emitting pattern, a second light-emitting pattern, and two third light-emitting patterns.
  • the third light-emitting patterns are arranged in the second direction, the first light-emitting pattern and the second light-emitting pattern are arranged in the first direction, and the first light-emitting pattern and the second light-emitting pattern are located in on the center line of the line connecting the center points of the two third light-emitting patterns;
  • a plurality of the pixel units are arranged to form a row, the pixel units in two adjacent rows are arranged in dislocation, and the first direction and the second direction are perpendicular;
  • the transparency suppression pattern is disposed between the adjacent first light emitting patterns, the second light emitting patterns and the two third light emitting patterns in two adjacent rows.
  • the transparent suppression pattern is provided in an oval shape.
  • the first light-emitting pattern is a red light-emitting pattern
  • the second light-emitting pattern is a blue light-emitting pattern
  • the third light-emitting pattern is a green light-emitting pattern.
  • a display device including the display panel described in any one of the above.
  • a method for manufacturing a display panel comprising:
  • a base substrate is provided, the base substrate has a first region and a second region;
  • a light-emitting layer is formed on one side of the base substrate, the light-emitting layer includes a plurality of light-emitting patterns, and the orthographic projections of the plurality of light-emitting patterns on the base substrate do not overlap each other;
  • a plurality of transparent suppression patterns are formed, the transparent suppression patterns are located between at least part of the adjacent light-emitting patterns, and among the plurality of transparent suppression patterns interval setting;
  • a first electrode is formed on the side of the light-emitting layer away from the base substrate, and a plurality of through holes are formed on the first electrode, and the orthographic projection of the through holes on the base substrate is the same as that of all the through holes.
  • the orthographic projections of the transparent suppression pattern on the base substrate are coincident.
  • the preparation method further includes:
  • planarization layer on one side of the base substrate, and forming a first via hole on the planarization layer
  • a pixel definition layer is formed on the side of the planarization layer away from the base substrate, and a third via hole and a fourth via hole are formed on the pixel definition layer, and the third via hole is connected to the first via hole.
  • a via hole is connected;
  • the light emitting pattern is formed in the third via hole, and the transparent suppression pattern is formed in the connected first via hole and the third via hole.
  • a light-emitting layer is provided on one side of the base substrate, the light-emitting layer includes a plurality of light-emitting patterns, and the orthographic projections of the plurality of light-emitting patterns on the base substrate do not overlap each other;
  • a plurality of transparent suppression patterns are also arranged on one side of the base substrate, the transparent suppression patterns are located between at least partially adjacent light-emitting patterns, and the multiple transparent suppression patterns are arranged at intervals;
  • a first electrode is arranged on one side of the first electrode, and a plurality of through holes are arranged on the first electrode.
  • the density is the same as the pixel density of the normal display area, which will not cause display differences and can meet the display requirements of higher resolution; and multiple transparent suppression patterns are arranged at intervals, so that the first electrode is still connected as a whole, and will not affect the first electrode. Normal display of a zone.
  • FIG. 1 is a schematic structural diagram of an exemplary embodiment of a display panel of the present disclosure.
  • FIG. 2 is a schematic structural diagram of an exemplary embodiment of a pixel arrangement of the display panel in FIG. 1 .
  • FIG. 3 is a schematic view of the structure after the transparent suppression pattern is formed in FIG. 2 .
  • FIG. 4 is a schematic structural diagram of another exemplary embodiment of a pixel arrangement of the display panel in FIG. 1 .
  • FIG. 5 is a schematic view of the structure after forming the transparent suppression pattern in FIG. 4 .
  • FIG. 6 is a schematic structural diagram of still another exemplary embodiment of a pixel arrangement of the display panel in FIG. 1 .
  • FIG. 7 is a schematic view of the structure after forming the transparent suppression pattern in FIG. 6 .
  • FIG. 8 is a schematic flow chart of an exemplary embodiment of a method for fabricating a display panel of the present disclosure.
  • FIG. 9 is a schematic view of the structure after forming a pixel intervening layer in the manufacturing method of the display panel of the present disclosure.
  • FIG. 10 is a schematic view of the structure of a fine metal mask with openings.
  • FIG. 11 is a schematic diagram of the effect after the cathode is evaporated in the camera display area under the screen.
  • FIG. 12 is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure.
  • Planarization layer 51. First via hole; 52. Second via hole;
  • Light-emitting pattern 81. Red light-emitting pattern; 82. Blue light-emitting pattern; 83. Green light-emitting pattern; 84. Covering area of light-emitting material; 85. Actual light-emitting area;
  • Under-screen camera display area 142. Normal display area.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • This exemplary embodiment first provides a display panel.
  • the display panel has a first area and a second area.
  • the panel may include a base substrate 1, a light-emitting layer, a transparent suppression pattern 10 and a first electrode 9; the light-emitting layer is provided on one side of the base substrate 1, and the light-emitting layer includes a plurality of light-emitting patterns, and the plurality of light-emitting patterns are arranged on the base substrate 4.
  • the orthographic projections on 1 do not overlap each other; a plurality of transparent suppressing patterns 10 are arranged on one side of the base substrate 1 and are located between at least some adjacent light-emitting patterns, and the transparent suppressing patterns 10 are located in the first area, and the plurality of transparent suppressing patterns 10 are located in the first area.
  • the transparent suppression patterns 10 are arranged at intervals; the first electrode 9 is arranged on the side of the light-emitting layer away from the base substrate 1 , and a plurality of through holes 901 are arranged on the first electrode 9 .
  • the orthographic projection coincides with the orthographic projection of the transparent suppression pattern 10 on the base substrate 1 .
  • the first area can be used for off-screen camera display, fingerprint recognition, infrared camera and other functions.
  • the first area is the off-screen camera display area 141 used for off-screen camera display
  • the second area is the normal display area. 142 as an example to illustrate.
  • a plurality of transparent suppression patterns 10 are further provided on one side of the base substrate 1 in the camera display area 141 under the screen, and the transparent suppression patterns 10 are located between at least some adjacent light-emitting patterns.
  • a plurality of transparent suppression patterns 10 are arranged at intervals; a first electrode 9 is arranged on the side of the light-emitting layer away from the substrate substrate 1, and a plurality of through holes 901 are arranged on the first electrode 9, and the through holes 901 are located in the substrate
  • the orthographic projection on the substrate 1 coincides with the orthographic projection of the transparent suppression pattern 10 on the base substrate 1, that is, the first electrode 9 is not arranged on the transparent suppression pattern 10, so as to avoid the blocking of light by the first electrode 9 and improve the screen.
  • the light transmittance of the lower camera display area 141 can be increased under the premise of ensuring the light transmittance, so that the pixel density of the under screen camera display area 141 can be less than or equal to the normal display area 142.
  • the density will not cause display differences, and can meet the display requirements of higher resolution; and the plurality of transparent suppression patterns 10 are arranged at intervals, so that the first electrodes 9 are still connected as a whole, and will not affect the image display area 141 under the screen. normal display.
  • the base substrate 1 may be a glass substrate, of course, may also be a flexible substrate.
  • the base substrate 1 has an under-screen camera display area 141 and a normal display area 142 surrounding the under-screen camera display area 141 .
  • a camera can be arranged on one side of the base substrate 1 .
  • An organic film layer 2 is disposed on the opposite side of the base substrate 1 , that is, the organic film layer 2 is disposed on the opposite side of the base substrate 1 where the camera is disposed, and the material of the organic film layer 2 may be polyimide resin.
  • a barrier layer 3 is provided on the side of the organic film layer 2 away from the base substrate 1 .
  • An array substrate 4 is disposed on the side of the barrier layer 3 away from the base substrate 1.
  • the array substrate 4 may include a plurality of thin film transistors arranged in an array. Whether the sub-pixel is displayed.
  • the thin film transistor may include an insulating layer 41, a metal trace 42, a gate, a gate insulating layer (not shown in the figure due to the cutting position), an interlayer dielectric layer 43, and a source and drain 44, and the thin film transistor may be Top gate type, bottom gate type or double gate type, the specific structure of the thin film transistor is a mature technology, so it is not repeated here.
  • a planarization layer 5 is provided on the side of the array substrate 4 away from the base substrate 1 , and a first planarization layer 5 is provided on the planarization layer 5 .
  • a via hole 51 and a second via hole 52; a second electrode 7 is provided on the side of the planarization layer 5 away from the base substrate 1, the area of the second electrode 7 is small and is only provided in the pixel area, and the second electrode 7 It can be the anode 7 , and the second electrode 7 is connected to the thin film transistor through the second via hole 52 .
  • a planarization layer 5 is provided on the side of the array substrate 4 away from the base substrate 1, and a second via hole 52 is provided on the planarization layer 5; on the side of the planarization layer 5 away from the base substrate
  • One side of 1 is provided with a second electrode 7 , the second electrode 7 may be an anode 7 , and the second electrode 7 is connected to the thin film transistor through a second via hole 52 .
  • a pixel definition layer 6 is provided on the side of the planarization layer 5 and the second electrode 7 away from the base substrate 1 , and a third pixel definition layer 6 is provided on the pixel definition layer 6 . Via 61 and fourth via 62 .
  • the third via hole 61 communicates with the first via hole 51, that is, the orthographic projection of the third via hole 61 on the base substrate 1 coincides with the orthographic projection of the first via hole 51 on the base substrate 1; 61 and the first via hole 51 are not provided with thin film transistors and various traces, that is, the orthographic projection of the third via hole 61 on the base substrate 1 and the orthographic projection of the thin film transistor and various traces on the base substrate 1 Do not overlap each other to avoid thin film transistors and various traces affecting the light transmittance.
  • the fourth via hole 62 is connected to the second electrode 7 to expose the second electrode 7 .
  • a pixel definition layer 6 is provided on the side of the planarization layer 5 and the second electrode 7 away from the base substrate 1 , and a fourth via hole 62 is provided on the pixel definition layer 6 .
  • the fourth via hole 62 is connected to the second electrode 7 to expose the second electrode 7 .
  • the layout of thin film transistors and various wirings is not considered, because the light transmittance of the entire display panel is not considered in the normal display area 142.
  • a light-emitting pattern 8 is provided on the side of the second electrode 7 away from the base substrate 1 , and the light-emitting pattern 8 is formed in the fourth via hole 62 .
  • the orthographic projections on the base substrate 1 do not overlap each other, that is, a plurality of light-emitting patterns 8 are arranged at intervals, or two adjacent light-emitting patterns 8 are arranged co-edge or tangentially.
  • a light-emitting pattern 8 and a switch component controlling the light-emitting pattern 8 form a sub-pixel.
  • a plurality of light-emitting patterns 8 constitute a light-emitting layer.
  • the third via hole 61 and the first via hole 51 are provided with transparent suppression patterns 10 , and a plurality of transparent suppression patterns 10 are arranged at intervals;
  • the material is a strong polar inorganic material or a strong polar organic material, for example, Liq (8-hydroxyquinoline-lithium), Alq3 (8-hydroxyquinoline aluminum), LiF (lithium fluoride), the material is very sensitive to the metal magnesium Has a strong repulsive effect.
  • the first electrode 9 is not subsequently generated on the transparent suppression pattern 10 .
  • the transparency suppression pattern 10 is not provided.
  • the first light-emitting pattern is a red light-emitting pattern 81
  • the second light-emitting pattern is a blue light-emitting pattern 82
  • the third light-emitting pattern is a green light-emitting pattern 83 .
  • the light-emitting pattern is the coverage area 84 of the light-emitting material, and the actual area of the light-emitting area 85 is smaller than the area of the coverage area 84 of the light-emitting material.
  • the light emission pattern is set to be circular.
  • the blue light-emitting pattern 82 that emits blue light has the shortest lifetime among the red light-emitting pattern 81, the blue light-emitting pattern 82, and the green light-emitting pattern 83. Therefore, the blue light-emitting pattern 82 has a larger light-emitting area than the red light-emitting pattern 81 and the green light-emitting pattern 83, thereby avoiding the reduction of the lifespan of the OLED display, that is, the optimized pixel arrangement structure of the OLED display can provide a longer lifespan .
  • the light-emitting pattern can also be set to oval, rectangular, polygonal and other shapes.
  • the display panel includes pixel units arranged in an array, and the pixel units include a red light-emitting pattern 81 , a blue light-emitting pattern 82 and two green light-emitting patterns 83 in total.
  • Each of the four light-emitting patterns can be arranged in a circle, and two adjacent ones of the four light-emitting patterns are circumscribed to each other.
  • the peripheral tangent of the pixel unit forms a rectangle, so that the four light-emitting patterns are respectively located at the four corners of the rectangle, wherein the two green light-emitting patterns 83 are arranged oppositely, that is, the two green light-emitting patterns 83 are arranged at two opposite corners of the rectangle. part; a red light-emitting pattern 81 and a blue light-emitting pattern 82 are arranged oppositely. Since the area of the blue light-emitting pattern 82 is the largest, the area of the red light-emitting pattern 81 is second, and the red light-emitting pattern 81 and the blue light-emitting pattern 82 are arranged opposite to each other.
  • the peripheral tangent lines of the pixel unit are the two lines of the red light-emitting pattern 81 .
  • the tangent line and the two tangent lines of the blue light-emitting pattern 82 and the four tangent lines intersect to form a rectangle.
  • the corners of two adjacent rectangles are arranged opposite to each other, that is, the diagonals of the two adjacent rectangles are on a straight line, and a plurality of rectangles are arrayed to form multiple rows according to the above rules, and the two adjacent rows are arranged in a staggered position. , that is, the rectangle in one of the two adjacent rows is located within the included angle of the edge between the two adjacent rectangles in the other row.
  • the virtual centers of the rectangles of the five pixel units are arranged at the four corners and the center of the virtual large rectangle, wherein the virtual large rectangle is a square, and the side length of the virtual large rectangle is the size of two pixel pitches.
  • the pixel arrangement rule of the under-screen camera display area 141 and the pixel arrangement of the normal display area 142 The rules are the same, and therefore, the pixel arrangement rules of the normal display area 142 are not repeated here.
  • the pixel arrangement rule of the under-screen camera display area 141 and the pixel arrangement rule of the normal display area 142 may also be different, as long as the pixel density remains the same.
  • a transparency suppression pattern 10 is disposed between at least two adjacent pixel units. Since the space in the pixel unit is too small to accommodate the transparency suppression pattern 10, the transparency suppression pattern 10 is arranged between at least two adjacent pixel units.
  • the transparent suppression pattern 10 may include a middle region and four edge regions connected to the middle region, the middle region may be circular, the edge region may be elongated, and a rounded edge is provided at the connection between the middle region and the edge region Corner, make the transition between the middle area and the edge area smoothly; also set the rounded corner at the end of the long strip away from the middle area.
  • the middle area is located between four adjacent pixel units, and an edge area is located between two adjacent pixel units.
  • the transparency suppression pattern 10 can be arranged between two or three adjacent pixel units; the middle area can also be a square, a polygon, and the like, and the edge area can be an ellipse, a rectangle, and the like.
  • the light transmittance of the under-screen camera display area 141 can reach 38%.
  • the first light emitting patterns and the second light emitting patterns are alternately arranged to form a first row, and the third light emitting patterns are arranged to form a second row;
  • the first row and the second row are alternately arranged; that is, a plurality of red light-emitting patterns 81 and a plurality of blue light-emitting patterns 82 are alternately arranged in the first direction to form a plurality of first rows, that is, two adjacent red light-emitting patterns
  • a blue light-emitting pattern 82 is arranged between the light-emitting patterns 81, a red light-emitting pattern 81 is arranged between two adjacent blue light-emitting patterns 82, and the adjacent red light-emitting patterns 81 and blue light-emitting patterns 82 are arranged between A first gap is provided; a plurality of green light-emitting patterns 83 are arranged at intervals in the first direction to form a plurality of second rows, that is,
  • the adjacent red light-emitting patterns 81 and blue light-emitting patterns 82 in two adjacent first rows form a virtual quadrilateral
  • the green light-emitting pattern 83 is arranged in the center of the virtual quadrilateral.
  • the center line of the green light-emitting pattern 83 is collinear with the center line of the connection line between the blue light-emitting pattern 82 and the green light-emitting pattern 83, so that the plurality of red light-emitting patterns 81 and the plurality of blue light-emitting patterns 82 are still alternately arranged in the second direction
  • a plurality of first columns are formed, and a plurality of green light-emitting patterns 83 are still arranged at intervals in the second direction to form a plurality of second columns, and the second columns are located between two adjacent first columns.
  • the second direction and the first direction are substantially perpendicular to each other.
  • the vertical mentioned in the exemplary embodiments of the present disclosure is not completely vertical, but has a certain error, and the error range can be ⁇ 5°, that is, the two are perpendicular to each other, which refers to the sandwich between the two.
  • the angle is greater than or equal to 85° and less than or equal to 95°.
  • the five light-emitting patterns are located at the four corners and the center of the virtual small square, the four virtual small squares form a virtual large square, and the side length of the virtual large square is the size of two pixel pitches.
  • Each large virtual square contains eight complete glow patterns.
  • the pixel arrangement rule of the under-screen camera display area 141 and the pixel arrangement of the normal display area 142 The rules are the same, and therefore, the pixel arrangement rules of the normal display area 142 are not repeated here.
  • the pixel arrangement rule of the under-screen camera display area 141 and the pixel arrangement rule of the normal display area 142 may also be different, as long as the pixel density remains the same.
  • a transparent suppression pattern 10 is arranged between the adjacent red light-emitting patterns 81 and blue light-emitting patterns 82 , that is, a transparent suppression pattern 10 is arranged in the first gap.
  • a transparent suppression pattern 10, the transparent suppression pattern 10 is a first transparent suppression pattern; a transparent suppression pattern 10 is arranged between two adjacent green light-emitting patterns 83, that is, a transparent suppression pattern 10 is arranged in the second gap, and the transparent suppression pattern 10 is arranged in the second gap.
  • the suppression pattern 10 is a second transparent suppression pattern.
  • the transparent suppression patterns 10 provided at the two positions may both be elliptical.
  • the structure of the transparency suppression pattern 10 is not limited to the above description, for example, the transparency suppression pattern 10 can also be provided in various shapes such as polygon, circle, rectangle, waist circle, and the like.
  • the light transmittance of the under-screen camera display area 141 can reach 38.9%.
  • the display panel includes pixel units arranged in an array, and the pixel units include one red light-emitting pattern 81 , one blue light-emitting pattern 82 and two green light-emitting patterns 83 .
  • the pixel units include one red light-emitting pattern 81 , one blue light-emitting pattern 82 and two green light-emitting patterns 83 .
  • two green light-emitting patterns 83 are arranged in the second direction, and the two green light-emitting patterns 83 are arranged tangentially; a red light-emitting pattern 81 and a blue light-emitting pattern 82 are arranged in the first direction, and the red light-emitting pattern 83 is arranged in the first direction.
  • 81 and the blue light-emitting pattern 82 are arranged tangentially.
  • the red light-emitting pattern 81 and the blue light-emitting pattern 82 are located on the center line of the line connecting the center points of the two green light-emitting patterns 83 , that is, the center line of the red light-emitting pattern 81 and the blue light-emitting pattern 82 and the two green light-emitting patterns 83 .
  • the center lines of the lines connecting the center points are collinear, so that one red light-emitting pattern 81 , one blue light-emitting pattern 82 and two green light-emitting patterns 83 form a "T" shape.
  • the red light-emitting pattern 81 is closer to the green light-emitting pattern 83 than the blue light-emitting pattern 82 , and a gap may be provided between the red light-emitting pattern 81 and the green light-emitting pattern 83 .
  • the second direction and the first direction are substantially perpendicular to each other.
  • a plurality of pixel units are arranged in a first direction to form a row, a plurality of rows are arranged in a second direction, and the pixel units in two adjacent rows are arranged in dislocation, so that the center lines of the two green light-emitting patterns 83 in one row are adjacent to each other.
  • the center line of the line connecting the center point of the red light emitting pattern 81 and the center point of the blue light emitting pattern 82 in the other row is approximately collinear.
  • the arrangement of the pixel units is not limited to the above description.
  • the blue light-emitting pattern 82 may be closer to the green light-emitting pattern 83 than the red light-emitting pattern 81 , and the blue light-emitting pattern 82 and the green light-emitting pattern 83 may be arranged between them.
  • the side length of the small virtual square is the size of four pixel pitches. Each small virtual square contains eight complete luminous patterns. Four small virtual squares form a large virtual square.
  • the pixel arrangement rule of the under-screen camera display area 141 and the pixel arrangement of the normal display area 142 The rules are the same, and therefore, the pixel arrangement rules of the normal display area 142 are not repeated here.
  • the pixel arrangement rule of the under-screen camera display area 141 and the pixel arrangement rule of the normal display area 142 may also be different, as long as the pixel density remains the same.
  • the transparent suppression pattern 10 may be oval, the long axis ends of the transparent suppression pattern 10 are tangent to the two green light emitting patterns 83 , and the short axis ends of the transparent suppression pattern 10 are tangent to the red light emitting pattern 81 and the blue light emitting pattern 82 .
  • the structure of the transparency suppression pattern 10 is not limited to the above description, for example, the transparency suppression pattern 10 can also be provided in various shapes such as polygon, circle, rectangle, waist circle, and the like.
  • the light transmittance of the under-screen camera display area 141 can reach 36%.
  • a first electrode 9 is disposed on the side of the light-emitting layer away from the base substrate 1 .
  • the first electrode 9 can be a cathode 9 , and the material of the first electrode 9 is Is a conductive metal, specifically metal-modified magnesium.
  • the first electrode 9 is provided with a plurality of through holes 901, the number of the through holes 901 is the same as the number of the transparent suppression patterns 10, and the orthographic projection of the through holes 901 on the base substrate 1 is the same as the transparent suppression pattern 10 on the base substrate 1.
  • the orthographic projections coincide with each other, that is, the first electrode 9 is not provided on the side of the transparent suppression pattern 10 away from the base substrate 1 but a through hole 901 is formed to increase the light transmittance of the under-screen camera display area 141 .
  • the display panel may be a top emission type display panel or a bottom emission type display panel.
  • the first via hole 51 may not be provided on the planarization layer
  • the third via hole 61 may not be provided on the pixel definition layer
  • the transparency suppression pattern may be directly provided between the pixel definition layer.
  • a fifth via hole can also be provided on the insulating layer, the fifth via hole is in communication with the first via hole 51 and the third via hole 61, and a transparent suppression pattern is formed on the fifth via hole, the first via hole 51 and the third via hole 61.
  • the third via hole 61 or the third via hole 61 is only provided on the pixel definition layer, and the first via hole 51 is not provided on the planarization layer, and the transparency suppression pattern is formed in the third via hole 61 .
  • the present exemplary embodiment further provides a display device, and the display device may include the display panel described in any one of the above.
  • the display panel described in any one of the above. The specific structure of the display panel has been described in detail above, and therefore will not be repeated here.
  • the specific type of the display device is not particularly limited, and any type of display device commonly used in the art can be used, such as mobile devices such as mobile phones, wearable devices such as watches, VR devices, etc.
  • the specific use of the device should be selected accordingly, which will not be repeated here.
  • the display device also includes other necessary components and components, taking the display as an example, such as a casing, a circuit board, a power cord, etc.
  • the specific usage requirements will be supplemented accordingly, which will not be repeated here.
  • the beneficial effects of the display device provided by the exemplary embodiments of the present disclosure are the same as those of the display panel provided by the above-described exemplary embodiments, which will not be repeated here.
  • the present exemplary embodiment also provides a method for manufacturing a display panel.
  • the manufacturing method may include the following steps:
  • step S10 a base substrate 1 is provided, and the base substrate 1 has a first region and a second region.
  • Step S20 a light-emitting layer is formed on one side of the base substrate 1 , the light-emitting layer includes a plurality of light-emitting patterns, and the orthographic projections of the plurality of light-emitting patterns on the base substrate 1 do not overlap each other.
  • Step S30 forming a plurality of transparent suppression patterns 10 in the first region and on one side of the base substrate 1 , the transparent suppression patterns 10 are located between at least partially adjacent light-emitting patterns, and a plurality of transparent suppression patterns 10 are formed.
  • the transparent suppression patterns 10 are arranged at intervals.
  • Step S40 a first electrode 9 is formed on the side of the light-emitting layer away from the base substrate 1, and a plurality of through holes 901 are formed on the first electrode 9, and the through holes 901 are in the substrate
  • the orthographic projection on the base substrate 1 coincides with the orthographic projection of the transparent suppression pattern 10 on the base substrate 1 .
  • a base substrate 1 is provided.
  • the base substrate 1 has an under-screen camera display area 141 and a normal display area 142 surrounding the under-screen camera display area 141 .
  • An organic film layer 2 is formed on one side of the base substrate 1, and the organic film layer 2 is a flexible film layer to serve as the substrate of the array substrate (the base substrate 1 can be peeled off in the subsequent process to leave the organic film layer 2 as the substrate of the array substrate. flexible substrate).
  • a barrier layer 3 is formed on the side of the organic film layer 2 away from the base substrate 1, and the barrier layer 3 is used to block water vapor and impurity ions (such as excess H+, etc.) in the organic film layer 2 from affecting the subsequently formed semiconductor pattern (
  • a buffer layer (not shown in the figure) can also be formed on the side of the barrier layer 3 away from the base substrate 1, and the buffer layer can further block the water vapor and impurity ions in the organic film layer 2 and play the role of adding hydrogen ions to the subsequently formed semiconductor pattern.
  • An array substrate 4 is formed on the side of the barrier layer 3 away from the base substrate 1 ; the manufacturing method of the array substrate 4 adopts the method in the prior art, which will not be repeated here.
  • a planarization layer 5 is formed on the side of the array substrate away from the base substrate 1 by processes such as evaporation, deposition, sputtering, etc.; and the planarization layer 5 is etched to form a first via hole 51 and a second via hole 52, The first via hole 51 is only formed in the under-screen camera display area 141, and the second via hole 52 is formed on the entire display panel.
  • An anode material layer is formed on the side of the planarization layer 5 away from the base substrate 1 by processes such as evaporation, deposition, sputtering, etc., and the anode material layer is etched to form an anode 7 (second electrode 7).
  • a pixel definition layer 6 is formed on the side of the anode 7 and the planarization layer 5 away from the base substrate 1 by processes such as evaporation, deposition, sputtering, etc., and the pixel definition layer 6 is etched to form the third via hole 61 and the third via hole 61 .
  • Four via holes 62 the third via hole 61 communicates with the first via hole 51
  • the fourth via hole 62 communicates with the anode 7 (second electrode 7 ).
  • a plurality of light-emitting patterns 8 are formed by evaporating organic light-emitting materials through a RGB fine metal mask.
  • the plating material is a strong polar inorganic material or a strong polar organic material, which has been described in detail above, and will not be repeated here.
  • the cathode material was evaporated using an open mask, and the cathode material was metal-modified magnesium.
  • the metal magnesium will not form a film but form a through hole 901 where the transparent inhibition pattern 10 is formed to ensure that the film is formed.
  • the light transmittance of the camera display area 141 under the screen is improved; in the place where the transparent suppression pattern 10 is not formed, the metal magnesium can be completely formed into a film to form the cathode 9, so as to realize the evaporation of the cathode 9 in the light-emitting area and ensure the normal operation of the display panel.
  • an encapsulation layer 11 is formed on the side of the cathode 9 away from the base substrate 1 . It can be seen from the figure that the cathode 9 is not formed on the transparency suppressing pattern 10 of the under-screen camera display area 141, which improves the light transmittance of the under-screen camera display area 141.
  • the terms “a”, “an”, “the”, “the” and “at least one” are used to indicate the presence of one or more elements/components/etc.; the terms “comprising”, “including” and “Having” is used to indicate an open-ended inclusive meaning and to mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc.; the terms “first”, “secondary” “ and “Third” etc. are used only as markers, not as restrictions on the number of their objects.

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Abstract

本公开涉及显示技术领域，提出一种显示面板及其制备方法、显示装置。该显示面板具有第一区及第二区，该显示面板包括衬底基板、发光层、第一电极和多个透明抑制图案；发光层设于衬底基板的一侧，发光层包括多个发光图案，多个发光图案互不交叠；多个透明抑制图案设于衬底基板的一侧，并位于至少部分相邻的发光图案之间，且位于第一区，多个透明抑制图案之间间隔设置；第一电极设于发光层的远离衬底基板的一侧，第一电极上设置有多个通孔，通孔在衬底基板上的正投影与透明抑制图案在衬底基板上的正投影重合。该显示面板在透明抑制图案之上没有设置第一电极，避免第一电极对光线的遮挡，提高第一区的透光率。

Description

显示面板及其制备方法、显示装置
交叉引用
本公开要求于2020年11月30日提交的申请号为202011374922.0名称为“显示面板及其制备方法、显示装置”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示面板及显示面板的制备方法、包括该显示面板的显示装置。
背景技术
随着全面屏技术的发展，手机屏占比向着极致化的方向迈进，屏占比越高，视觉观感就越震撼。继刘海屏、水滴屏之后，又出现了“挖孔屏”，但这些并非真全面屏，对全面屏技术来说，要想达到满眼全是显示屏的效果。首要解决的问题就是前置摄像头的“隐藏”，因此显示屏下摄像才是终极解决方案，即做到如屏幕指纹技术一样，将前置摄像头真正“藏”起来。屏下摄像方案对屏下摄像显示区的显示屏的透光率提出一定要求，OLED(Organic Light-Emitting Diode，有机发光二极管)显示面板中真正透光的部分是发光二极管(子像素)间的缝隙部分。
目前，比较主流的做法是“低像素密度方案”，即降低屏下摄像显示区的像素密度，使屏下摄像显示区的子像素间的空隙增大，从而提升透光率。但是，该区域稀疏的像素密度会导致与周围正常显示区的显示有差异，降低观感，因此，如何在保证显示无差异的前提下，提高屏下摄像显示区的显示面板的透光率是一个难题。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
本公开的目的在于克服上述现有技术的不足，提供一种显示面板及显示面板的制备方法、包括该显示面板的显示装置。
根据本公开的一个方面，提供一种显示面板，具有第一区以及第二区，所述显示面板包括：
衬底基板；
发光层，设于所述衬底基板的一侧，所述发光层包括多个发光图案，所述多个发光图案在所述衬底基板上的正投影互不交叠；
多个透明抑制图案，设于所述衬底基板的一侧，并位于至少部分相邻的所述发光图案之间，且所述透明抑制图案位于所述第一区，多个所述透明抑制图案之间间隔设置；
第一电极，设于所述发光层的远离所述衬底基板的一侧，所述第一电极上设置有多个通孔，所述通孔在所述衬底基板上的正投影与所述透明抑制图案在所述衬底基板上的正投影重合。
在本公开的一种示例性实施例中，所述第一区的像素密度与所述第二区的像素密度相同。
在本公开的一种示例性实施例中，所述显示面板还包括：
平坦化层，设于所述衬底基板的一侧，所述平坦化层上设置有第一过孔；
像素定义层，设于所述平坦化层的远离所述衬底基板的一侧，所述像素定义层上设置有第三过孔和第四过孔，所述第三过孔与所述第一过孔连通；
所述透明抑制图案设置在连通的所述第一过孔和所述第三过孔内，所述发光图案设置在所述第四过孔内。
在本公开的一种示例性实施例中，所述透明抑制图案的材料是强极性无机材料或强极性有机材料，所述第一电极的材料是导电金属。
在本公开的一种示例性实施例中，所述显示面板还包括阵列排布的像素单元，所述像素单元包括一个第一发光图案、一个第二发光图案和两个第三发光图案，所述像素单元的外围切线形成矩形；
在第一方向上，相邻两个所述矩形的角部相对设置，且多个所述矩形排列形成多行，相邻两行错位设置；相邻至少两个所述像素单元之间 设置有一个所述透明抑制图案。
在本公开的一种示例性实施例中，所述透明抑制图案包括中间区域以及连接于所述中间区域的四个边缘区域，所述中间区域为圆形，所述边缘区域为长条形。
在本公开的一种示例性实施例中，
在第一方向上，第一发光图案和第二发光图案交替排列形成第一行，第三发光图案排列形成第二行；
在第二方向上，所述第一行和所述第二行交替排列，所述第一方向和所述第二方向垂直；
分布在相邻两行两列的两个第一发光图案和两个第二发光图案形成一个虚拟四边形，所述第三发光图案位于所述虚拟四边形中；
相邻两个所述第三发光图案之间设置有所述透明抑制图案，相邻的所述第一发光图案与所述第二发光图案之间设置有所述透明抑制图案。
在本公开的一种示例性实施例中，所述显示面板还包括阵列排布的像素单元，所述像素单元包括一个第一发光图案、一个第二发光图案和两个第三发光图案，两个所述第三发光图案在第二方向上排列，一个所述第一发光图案和一个所述第二发光图案在第一方向上排列，所述第一发光图案和所述第二发光图案位于两个所述第三发光图案的中心点的连线的中心线上；
在所述第一方向上，多个所述像素单元排列形成一行，相邻两行内的所述像素单元错位排列，所述第一方向和所述第二方向垂直；
在相邻两行的相邻所述第一发光图案、所述第二发光图案和两个所述第三发光图案之间设置有所述透明抑制图案。
在本公开的一种示例性实施例中，所述透明抑制图案设置为椭圆形。
在本公开的一种示例性实施例中，所述第一发光图案是红色发光图案，所述第二发光图案是蓝色发光图案，所述第三发光图案是绿色发光图案。
根据本公开的一个方面，提供一种显示装置，包括上述任意一项所述的显示面板。
根据本公开的一个方面，提供一种显示面板的制备方法，包括：
提供一衬底基板，所述衬底基板具有第一区以及第二区；
在所述衬底基板的一侧形成发光层，所述发光层包括多个发光图案，所述多个发光图案在所述衬底基板上的正投影互不交叠；
在所述第一区，且在所述衬底基板的一侧形成多个透明抑制图案，所述透明抑制图案位于至少部分相邻的所述发光图案之间，多个所述透明抑制图案之间间隔设置；
在所述发光层的远离所述衬底基板的一侧形成第一电极，并在所述第一电极上形成多个通孔，所述通孔在所述衬底基板上的正投影与所述透明抑制图案在所述衬底基板上的正投影重合。
在本公开的一种示例性实施例中，所述制备方法还包括：
在所述衬底基板的一侧形成平坦化层，并在所述平坦化层上形成第一过孔；
在所述平坦化层的远离所述衬底基板的一侧形成像素定义层，并在所述像素定义层上形成第三过孔和第四过孔，所述第三过孔与所述第一过孔连通；
所述发光图案形成在所述第三过孔内，所述透明抑制图案形成在连通的所述第一过孔和所述第三过孔内。
本公开的显示面板及其制备方法，在衬底基板的一侧设置有发光层，发光层包括多个发光图案，多个发光图案在衬底基板上的正投影互不交叠；在第一区，在衬底基板的一侧还设置有多个透明抑制图案，透明抑制图案位于至少部分相邻的发光图案之间，多个透明抑制图案之间间隔设置；在发光层的远离衬底基板的一侧设置有第一电极，第一电极上设置有多个通孔，通孔在衬底基板上的正投影与透明抑制图案在衬底基板上的正投影重合，即在透明抑制图案之上没有设置第一电极，从而避免第一电极对光线的遮挡，提高第一区的透光率，从而在保证透光率的前提下可以提高第一区的像素密度，使第一区的像素密度与正常显示区的像素密度相同，不会造成显示差异，可以满足较高分辨率的显示要求；而且多个透明抑制图案之间间隔设置，使第一电极还是连接成一体，不会影响第一区的正常显示。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解 释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开显示面板一示例实施方式的结构示意图。
图2是图1中的显示面板的像素排列一示例实施方式的结构示意图。
图3是在图2中形成透明抑制图案后的结构示意图。
图4是图1中的显示面板的像素排列另一示例实施方式的结构示意图。
图5是在图4中形成透明抑制图案后的结构示意图。
图6是图1中的显示面板的像素排列再一示例实施方式的结构示意图。
图7是在图6中形成透明抑制图案后的结构示意图。
图8是本公开显示面板的制备方法一示例实施方式的流程示意框图。
图9是本公开显示面板的制备方法中形成像素介定层后的结构示意图。
图10是具有开口的精细金属掩膜板的结构示意图。
图11是屏下摄像显示区蒸镀阴极后的效果示意图。
图12是本公开显示面板另一示例实施方式的结构示意图。
附图标记说明：
1、衬底基板；2、有机膜层；3、阻挡层；
4、阵列基板；41、绝缘层；42、金属走线；43、层间介电层；44、源漏极；
5、平坦化层；51、第一过孔；52、第二过孔；
6、像素介定层；61、第三过孔；62、第四过孔；
7、阳极(第二电极)；
8、发光图案；81、红色发光图案；82、蓝色发光图案；83、绿色发光图案；84、发光材料的覆盖区；85、实际发光区；
9、阴极(第一电极)；901、通孔；
10、透明抑制图案；11、封装层；12、精细金属掩膜板；13、开口；
141、屏下摄像显示区；142、正常显示区。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
本示例实施方式首先提供了一种显示面板，参照图1、图9和图12所示的本公开显示面板一示例实施方式的结构示意图，该显示面板具有第一区以及第二区，该显示面板可以包括衬底基板1、发光层、透明抑制图案10以及第一电极9；发光层设于衬底基板1的一侧，发光层包括多个发光图案，多个发光图案在4衬底基板1上的正投影互不交叠；多个透明抑制图案10设于衬底基板1的一侧，并位于至少部分相邻的发光图案之间，且透明抑制图案10位于第一区，多个透明抑制图案10之间间隔设置；第一电极9设于发光层的远离衬底基板1的一侧，第一电极9上设置有多个通孔901，通孔901在衬底基板1上的正投影与透明抑制图案10在衬底基板1上的正投影重合。
第一区可以用于屏下摄像显示，还可以用于指纹识别、红外摄像等功能，下面以第一区为用于屏下摄像显示的屏下摄像显示区141，第二区为正常显示区142为例进行说明。
本公开的显示面板及其制备方法，在屏下摄像显示区141，在衬底基板1的一侧还设置有多个透明抑制图案10，透明抑制图案10位于至少部分相邻的发光图案之间，多个透明抑制图案10之间间隔设置；在发光层的远离衬底基板1的一侧设置有第一电极9，第一电极9上设置有多个通孔901，通孔901在衬底基板1上的正投影与透明抑制图案10在衬底基 板1上的正投影重合，即在透明抑制图案10之上没有设置第一电极9，从而避免第一电极9对光线的遮挡，提高屏下摄像显示区141的透光率，从而可以在保证透光率的前提下提高屏下摄像显示区141的像素密度，使屏下摄像显示区141的像素密度小于或等于正常显示区142的像素密度，不会造成显示差异，可以满足较高分辨率的显示要求；而且多个透明抑制图案10之间间隔设置，使第一电极9还是连接成一体，不会影响屏下摄像显示区141的正常显示。
在本示例实施方式中，衬底基板1可以是玻璃基板，当然，也可以是柔性基板。衬底基板1具有屏下摄像显示区141以及围绕屏下摄像显示区141的正常显示区142。在屏下摄像显示区141，在衬底基板1的一侧可以设置摄像头。
在衬底基板1的相对另一侧设置有有机膜层2，即在衬底基板1设置摄像头的相对另一侧设置有机膜层2，有机膜层2的材质可以是聚酰亚胺树脂。在有机膜层2的远离衬底基板1的一侧设置有阻挡层3。在阻挡层3的远离衬底基板1的一侧设置有阵列基板4，阵列基板4可以包括多个阵列排布的薄膜晶体管，薄膜晶体管作为开关组件用于控制各个子像素的开关，即控制各个子像素是否进行显示。薄膜晶体管可以包括绝缘层41、金属走线42、栅极、栅绝缘层(由于剖切位置的缘故在图中未示出)、层间介电层43以及源漏极44，薄膜晶体管可以为顶栅型、底栅型或双栅型，薄膜晶体管的具体结构都是成熟技术，因此，在此不再赘述。
参照图9所示，在本示例实施方式中，在屏下摄像显示区141，在阵列基板4的远离衬底基板1的一侧设置有平坦化层5，在平坦化层5上设置有第一过孔51和第二过孔52；在平坦化层5的远离衬底基板1的一侧设置有第二电极7，第二电极7的面积较小只设置在像素区，第二电极7可以为阳极7，第二电极7通过第二过孔52与薄膜晶体管连接。
在正常显示区142，在阵列基板4的远离衬底基板1的一侧设置有平坦化层5，在平坦化层5上设置有第二过孔52；在平坦化层5的远离衬底基板1的一侧设置有第二电极7，第二电极7可以为阳极7，第二电极7通过第二过孔52与薄膜晶体管连接。
参照图9所示，在屏下摄像显示区141，在平坦化层5和第二电极7 的远离衬底基板1的一侧设置有像素定义层6，在像素定义层6上设置有第三过孔61和第四过孔62。第三过孔61与第一过孔51连通，即第三过孔61在衬底基板1上的正投影与第一过孔51在衬底基板1上的正投影重合；在第三过孔61和第一过孔51位置没有设置薄膜晶体管和各种走线，即第三过孔61在衬底基板1上的正投影与薄膜晶体管和各种走线在衬底基板1上的正投影互不交叠，避免薄膜晶体管和各种走线影响透光率。第四过孔62连通至第二电极7，使第二电极7裸露。
在正常显示区142，在平坦化层5和第二电极7的远离衬底基板1的一侧设置有像素定义层6，在像素定义层6上设置有第四过孔62。第四过孔62连通至第二电极7，使第二电极7裸露。在正常显示区142不用考虑薄膜晶体管和各种走线的布局，因为，在正常显示区142不用考虑整个显示面板的透光率。
参照图1所示，在屏下摄像显示区141，在第二电极7的远离衬底基板1的一侧设置有发光图案8，发光图案8形成在第四过孔62内，各个发光图案8在衬底基板1上的正投影互不交叠，即多个发光图案8之间是间隔设置，或相邻两个发光图案8之间是共边设置或相切设置的。一个发光图案8与控制该发光图案8的开关组件形成一个子像素。多个发光图案8组成发光层。
请继续参照图1所示，在屏下摄像显示区141，在第三过孔61和第一过孔51设置有透明抑制图案10，多个透明抑制图案10之间间隔设置；透明抑制图案10的材料是强极性无机材料或强极性有机材料，例如，Liq(8-羟基喹啉-锂)、Alq3(8-羟基喹啉铝)、LiF(氟化锂)，该材料对金属镁具有很强的排斥作用。使后续在透明抑制图案10之上不会生成第一电极9。
在正常显示区142，则没有设置透明抑制图案10。
下面对子像素的排列方式进行详细说明。
下述示例实施方式中，第一发光图案是红色发光图案81，第二发光图案是蓝色发光图案82，第三发光图案是绿色发光图案83。发光图案就是发光材料的覆盖区84，实际发光区85的面积比发光材料的覆盖区84的面积要小。在下述示例实施方式中，将发光图案设置为圆形的。发射 蓝光的蓝色发光图案82在红色发光图案81、蓝色发光图案82和绿色发光图案83中寿命最短。因此，蓝色发光图案82比红色发光图案81和绿色发光图案83的发光面积更大，从而避免了OLED显示器寿命的降低，也就是说，OLED显示器的优化的像素排列结构可以提供更长的寿命。发光图案还可以设置为椭圆形、矩形、多边形等等多种形状。
参照图2和图3所示，在该示例实施方式中，显示面板包括阵列排布的像素单元，像素单元包括一个红色发光图案81、一个蓝色发光图案82和两个绿色发光图案83共四个发光图案，该四个发光图案都可以设置为圆形，且该四个发光图案相邻的两个相互外切设置。像素单元的外围切线形成矩形，使四个发光图案分别位于矩形的四个角部，其中两个绿色发光图案83是相对设置的，即两个绿色发光图案83设置在矩形的相对的两个角部；一个红色发光图案81和一个蓝色发光图案82是相对设置的。由于蓝色发光图案82的面积最大，红色发光图案81的面积次之，而红色发光图案81和蓝色发光图案82是相对设置的，因此，像素单元的外围切线就是红色发光图案81的两条切线和蓝色发光图案82的两条切线，四条切线相交后形成矩形。在第一方向上，相邻两个矩形的角部相对设置，即相邻两个矩形的对角线在一条直线上，多个矩形按照上述规律阵列形成多行，相邻两行是错位设置的，即相邻两行中其中一行的矩形，位于另外一行的相邻两个矩形之间的边线的夹角内。
五个像素单元的矩形的虚拟中心又分别排列在虚拟大矩形的四角和中心处，其中虚拟大矩形为正方形，虚拟大矩形的边长为两个像素间距(pixel pitch)的大小。
在本示例实施方式中，为了避免设计上的不统一和制备工艺中各个辅助治具以及工艺流程上的不统一，屏下摄像显示区141的像素排布规律和正常显示区142的像素排布规律是相同的，因此，此处对正常显示区142的像素排布规律不再赘述。当然，在本公开的其他示例实施方式中，屏下摄像显示区141的像素排布规律和正常显示区142的像素排布规律也可以是不相同的，只要像素密度保持相同即可。
请继续参照图2和图3所示，在屏下摄像显示区141，相邻至少两个像素单元之间设置有一个透明抑制图案10。由于像素单元内空间较小无 法容纳透明抑制图案10，因此将透明抑制图案10设置在相邻至少两个像素单元之间。
具体地，透明抑制图案10可以包括中间区域以及连接于中间区域的四个边缘区域，中间区域可以为圆形，边缘区域可以为长条形，且在中间区域与边缘区域的连接处设置圆倒角，使中间区域与边缘区域圆滑过渡；在长条形的远离中间区域的一端也设置圆倒角。中间区域位于相邻的四个像素单元之间，一个边缘区域位于相邻的两个像素单元之间。当然，在边缘处，透明抑制图案10可以设置在相邻两个或三个像素单元之间；中间区域还可以为正方形、多边形等等，边缘区域可以为椭圆形、矩形等等。
在图2和图3所示的示例实施方式中，屏下摄像显示区141的透光率可以达到38％。
参照图4和图5所示，在该示例实施方式中，在第一方向上，第一发光图案和第二发光图案交替排列形成第一行，第三发光图案排列形成第二行；在第二方向上，第一行和第二行交替排列；即多个红色发光图案81与多个蓝色发光图案82在第一方向上交替排列形成多个第一行，即相邻的两个红色发光图案81之间设置有一个蓝色发光图案82，相邻的两个蓝色发光图案82之间设置有一个红色发光图案81，且相邻的红色发光图案81与蓝色发光图案82之间设置有第一间隙；多个绿色发光图案83在第一方向上间隔排列形成多个第二行，即相邻的两个绿色发光图案83之间设置有第二间隙；第二行位于相邻的两个第一行之间。
分布在相邻两行两列的两个第一发光图案和两个第二发光图案形成一个虚拟四边形，第三发光图案位于虚拟四边形中。具体为：相邻两个第一行的相邻红色发光图案81和蓝色发光图案82形成一个虚拟四边形，绿色发光图案83设于所述虚拟四边形的中心。绿色发光图案83的中心线与蓝色发光图案82和绿色发光图案83的连线的中心线共线，使多个红色发光图案81与多个蓝色发光图案82在第二方向上仍然交替排列形成多个第一列，多个绿色发光图案83在第二方向上仍然间隔排列形成多个第二列，第二列位于相邻的两个第一列之间。第二方向与第一方向大致相互垂直。
需要说明的是，在本公开示例实施方式中提到的垂直，并不是完全垂直，而是具有一定的误差，误差范围可以为±5°，即两者相互垂直是指两者之间的夹角大于等于85°且小于等于95°。
五个发光图案位于虚拟小正方形的四角和中心处，四个虚拟小正方形形成一个虚拟大正方形，虚拟大正方形的边长为两个像素间距(pixel pitch)的大小。每个虚拟大正方形中包含八个完整的发光图案。
在本示例实施方式中，为了避免设计上的不统一和制备工艺中各个辅助治具以及工艺流程上的不统一，屏下摄像显示区141的像素排布规律和正常显示区142的像素排布规律是相同的，因此，此处对正常显示区142的像素排布规律不再赘述。当然，在本公开的其他示例实施方式中，屏下摄像显示区141的像素排布规律和正常显示区142的像素排布规律也可以是不相同的，只要像素密度保持相同即可。
请继续参照图4和图5所示，在屏下摄像显示区141，相邻的红色发光图案81与蓝色发光图案82之间设置有一个透明抑制图案10，即在第一间隙内设置有透明抑制图案10，该透明抑制图案10为第一透明抑制图案；相邻两个绿色发光图案83之间设置有一个透明抑制图案10，即在第二间隙内设置有透明抑制图案10，该透明抑制图案10为第二透明抑制图案。两个位置设置的透明抑制图案10可以均是椭圆形。只是第一透明抑制图案的长轴沿第二方向设置，而第二透明抑制图案的长轴沿第一方向设置。另外，透明抑制图案10的结构不限于上述说明，例如，透明抑制图案10还可以设置为多边形、圆形、矩形、腰圆形等等多种形状。
在图4和图5所示的示例实施方式中，屏下摄像显示区141的透光率可以达到38.9％。
参照图6和图7所示，在该示例实施方式中，显示面板包括阵列排布的像素单元，像素单元包括一个红色发光图案81、一个蓝色发光图案82和两个绿色发光图案83。其中，两个绿色发光图案83在第二方向上排列，且两个绿色发光图案83相切设置；一个红色发光图案81和一个蓝色发光图案82在第一方向上排列，且该红色发光图案81和该蓝色发光图案82相切设置。红色发光图案81和蓝色发光图案82位于两个绿色发光图案83的中心点的连线的中心线上，即红色发光图案81和蓝色发 光图案82的中心线与两个绿色发光图案83的中心点的连线的中心线共线，使一个红色发光图案81、一个蓝色发光图案82和两个绿色发光图案83形成“T”字形。红色发光图案81相对于蓝色发光图案82更靠近绿色发光图案83，红色发光图案81与绿色发光图案83之间可以设置有间隙。第二方向与第一方向大致相互垂直。
多个像素单元在第一方向上排列形成一行，多行在第二方向上排列，且相邻两行内的像素单元错位排列，使其中一行中的两个绿色发光图案83的中心线与相邻另一行中的红色发光图案81的中心点和蓝色发光图案82的中心点的连线的中心线大致共线。
需要说明的是，像素单元的排列方式不限于上述说明，例如，可以是蓝色发光图案82相对于红色发光图案81更靠近绿色发光图案83，蓝色发光图案82与绿色发光图案83之间设置有间隙；还可以是，蓝色发光图案82与绿色发光图案83之间没有设置间隙，或红色发光图案81与绿色发光图案83之间没有设置间隙。
小虚拟正方形的边长为四个像素间距(pixel pitch)的大小。每个虚拟小正方形中包含八个完整的发光图案。四个小虚拟正方形形成一个大虚拟正方形。
在本示例实施方式中，为了避免设计上的不统一和制备工艺中各个辅助治具以及工艺流程上的不统一，屏下摄像显示区141的像素排布规律和正常显示区142的像素排布规律是相同的，因此，此处对正常显示区142的像素排布规律不再赘述。当然，在本公开的其他示例实施方式中，屏下摄像显示区141的像素排布规律和正常显示区142的像素排布规律也可以是不相同的，只要像素密度保持相同即可。
请继续参照图6和图7所示，在屏下摄像显示区141，在相邻两行的相邻红色发光图案81、蓝色发光图案82和两个绿色发光图案83之间设置有透明抑制图案10。透明抑制图案10可以是椭圆形，透明抑制图案10的长轴两端与两个绿色发光图案83相切，透明抑制图案10的短轴两端与红色发光图案81和蓝色发光图案82相切。另外，透明抑制图案10的结构不限于上述说明，例如，透明抑制图案10还可以设置为多边形、圆形、矩形、腰圆形等等多种形状。
在图6和图7所示的示例实施方式中，屏下摄像显示区141的透光率可以达到36％。
上面通过三个示例实施方式对像素的排列方式进行了详细说明，本领域技术人员可以理解的是，像素的排列方式不限于上述说明，只要在保证像素密度的情况下，能够设置更大面积的透明抑制图案10的像素的排列方式都是可行的，都属于本公开的保护范围。
请继续参照图1所示，在屏下摄像显示区141，在发光层的远离衬底基板1的一侧设置有第一电极9，第一电极9可以为阴极9，第一电极9的材料是导电金属，具体为金属改性镁。第一电极9上设置有多个通孔901，通孔901的数量与透明抑制图案10的数量相同，通孔901在衬底基板1上的正投影与透明抑制图案10在衬底基板1上的正投影重合，即在透明抑制图案10的远离衬底基板1的一侧没有设置第一电极9而是形成了通孔901，以增加屏下摄像显示区141的透光率。
该显示面板可以是顶发射型显示面板，也可以是底发射型显示面板。
另外，在本公开的其他示例实施方式中，可以在平坦化层上不设置第一过孔51，在像素定义层上不设置第三过孔61，直接将透明抑制图案设置在像素定义层之上；还可以在绝缘层上设置第五过孔，第五过孔与第一过孔51、第三过孔61是连通的，透明抑制图案形成在第五过孔、第一过孔51和第三过孔61内；或仅在像素定义层上设置第三过孔61，在平坦化层上不设置第一过孔51，透明抑制图案形成第三过孔61内。
进一步的，本示例实施方式还提供了一种显示装置，该显示装置可以包括上述任意一项所述的显示面板。显示面板的具体结构上述已经进行了详细说明，因此，此处不再赘述。
而该显示装置的具体类型不受特别的限制，本领域常用的显示装置类型均可，具体例如手机等移动装置、手表等可穿戴设备、VR装置等等，本领域技术人员可根据该显示设备的具体用途进行相应地选择，在此不再赘述。
需要说明的是，该显示装置除了显示面板以外，还包括其他必要的部件和组成，以显示器为例，具体例如外壳、电路板、电源线，等等，本领域技术人员可根据该显示装置的具体使用要求进行相应地补充，在 此不再赘述。
与现有技术相比，本公开示例实施方式提供的显示装置的有益效果与上述示例实施方式提供的显示面板的有益效果相同，在此不做赘述。
进一步的，本示例实施方式还提供了一种显示面板的制备方法，参照图8所示的本公开显示面板的制备方法的流程示意框图，该制备方法可以包括以下步骤：
步骤S10，提供一衬底基板1，所述衬底基板1具有第一区以及第二区。
步骤S20，在所述衬底基板1的一侧形成发光层，所述发光层包括多个发光图案，所述多个发光图案在所述衬底基板1上的正投影互不交叠。
步骤S30，在所述第一区，且在所述衬底基板1的一侧形成多个透明抑制图案10，所述透明抑制图案10位于至少部分相邻的所述发光图案之间，多个所述透明抑制图案10之间间隔设置。
步骤S40，在所述发光层的远离所述衬底基板1的一侧形成第一电极9，并在所述第一电极9上形成多个通孔901，所述通孔901在所述衬底基板1上的正投影与所述透明抑制图案10在所述衬底基板1上的正投影重合。
下面对显示面板的制备方法进行详细说明。
参照图9所示。
提供一衬底基板1，衬底基板1具有屏下摄像显示区141以及围绕屏下摄像显示区141的正常显示区142。
在衬底基板1的一侧形成有机膜层2，该有机膜层2为柔性膜层以作为阵列基板的衬底(后续工艺中可以将衬底基板1剥离以留下有机膜层2层作为柔性衬底)。在有机膜层2的远离衬底基板1的一侧形成阻挡层3，该阻挡层3用于阻隔有机膜层2中的水汽以及杂质离子(如过量的H+等)对后续形成的半导体图案(多晶硅有源层)的影响；还可以在阻挡层3的远离衬底基板1的一侧形成缓冲层(图中未示出)，缓冲层起到进一步阻隔有机膜层2中的水汽以及杂质离子的作用，并且起到为后续形成的半导体图案增加氢离子的作用。
在阻挡层3的远离衬底基板1的一侧形成阵列基板4；阵列基板4 的制备方法采用现有技术中的方法，在此不再赘述。
在阵列基板的远离衬底基板1的一侧通过蒸镀、沉积、溅射等工艺形成平坦化层5；并对平坦化层5进行刻蚀形成第一过孔51和第二过孔52，第一过孔51仅形成在屏下摄像显示区141，第二过孔52在整个显示面板上都有。
在平坦化层5的远离衬底基板1的一侧通过蒸镀、沉积、溅射等工艺形成阳极材料层，并对阳极材料层进行刻蚀形成阳极7(第二电极7)。
在阳极7和平坦化层5的远离衬底基板1的一侧通过蒸镀、沉积、溅射等工艺形成像素定义层6，并对像素定义层6进行刻蚀形成第三过孔61和第四过孔62，第三过孔61与所述第一过孔51连通，第四过孔62连通至阳极7(第二电极7)。
参照图1所示，然后，通过RGB精细金属掩膜板蒸镀有机发光材料形成多个发光图案8。
再使用图10所示的具有开口13的精细金属掩膜板12对屏下摄像显示区141的非发光区进行蒸镀，开口13的形状、位置与透明抑制图案10的形状、位置一致，蒸镀材料为强极性无机材料或强极性有机材料，上述已经进行了详细说明，在此不再赘述。
最后，使用开放式掩膜板蒸镀阴极材料，阴极材料是金属改性镁。参照图11所示，由于强极性无机材料或强极性有机材料能有效抑制金属改性镁的成膜，透明抑制图案10形成的地方金属镁不会成膜而是形成通孔901，保证了屏下摄像显示区141的透光性；在透明抑制图案10未成膜的地方金属镁可以完全成膜形成阴极9，实现发光区域的阴极9蒸镀，保证显示面板正常工作。
参照图12所示，在阴极9的远离衬底基板1的一侧形成封装层11。从图中可以得到在屏下摄像显示区141的透明抑制图案10之上没有形成阴极9，提高了屏下摄像显示区141的透光率。
上述所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中，如有可能，各实施例中所讨论的特征是可互换的。在上面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案 而没有所述特定细节中的一个或更多，或者可以采用其它的方法、组件、材料等。在其它情况下，不详细示出或描述公知结构、材料或者操作以避免模糊本公开的各方面。
本说明书中使用“约”“大约”的用语通常表示在一给定值或范围的20％之内，较佳是10％之内，且更佳是5％之内。在此给定的数量为大约的数量，意即在没有特定说明的情况下，仍可隐含“约”“大约”“大致”“大概”的含义。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。其他相对性的用语，例如“高”“低”“顶”“底”等也作具有类似含义。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
本说明书中，用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包含”、“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
应可理解的是，本公开不将其应用限制到本说明书提出的部件的详细结构和布置方式。本公开能够具有其他实施方式，并且能够以多种方式实现并且执行。前述变形形式和修改形式落在本公开的范围内。应可理解的是，本说明书公开和限定的本公开延伸到文中和/或附图中提到或明显的两个或两个以上单独特征的所有可替代组合。所有这些不同的组合构成本公开的多个可替代方面。本说明书所述的实施方式说明了已知用于实现本公开的最佳方式，并且将使本领域技术人员能够利用本公开。

Claims (13)

  1. 一种显示面板，具有第一区以及第二区，其中，所述显示面板包括：
    衬底基板；
    发光层，设于所述衬底基板的一侧，所述发光层包括多个发光图案，所述多个发光图案在所述衬底基板上的正投影互不交叠；
    多个透明抑制图案，设于所述衬底基板的一侧，并位于至少部分相邻的所述发光图案之间，且所述透明抑制图案位于所述第一区，多个所述透明抑制图案之间间隔设置；
    第一电极，设于所述发光层的远离所述衬底基板的一侧，所述第一电极上设置有多个通孔，所述通孔在所述衬底基板上的正投影与所述透明抑制图案在所述衬底基板上的正投影重合。
  2. 根据权利要求1所述的显示面板，其中，所述第一区的像素密度与所述第二区的像素密度相同。
  3. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    平坦化层，设于所述衬底基板的一侧，所述平坦化层上设置有第一过孔；
    像素定义层，设于所述平坦化层的远离所述衬底基板的一侧，所述像素定义层上设置有第三过孔和第四过孔，所述第三过孔与所述第一过孔连通；
    所述透明抑制图案设置在连通的所述第一过孔和所述第三过孔内，所述发光图案设置在所述第四过孔内。
  4. 根据权利要求1所述的显示面板，其中，所述透明抑制图案的材料是强极性无机材料或强极性有机材料，所述第一电极的材料是导电金属。
  5. 根据权利要求1所述的显示面板，其中，所述显示面板还包括阵列排布的像素单元，所述像素单元包括一个第一发光图案、一个第二发光图案和两个第三发光图案，所述像素单元的外围切线形成矩形；
    在第一方向上，相邻两个所述矩形的角部相对设置，且多个所述矩形排列形成多行，相邻两行错位设置；相邻至少两个所述像素单元之间 设置有一个所述透明抑制图案。
  6. 根据权利要求5所述的显示面板，其中，所述透明抑制图案包括中间区域以及连接于所述中间区域的四个边缘区域，所述中间区域为圆形，所述边缘区域为长条形。
  7. 根据权利要求1所述的显示面板，其中，
    在第一方向上，第一发光图案和第二发光图案交替排列形成第一行，第三发光图案排列形成第二行；
    在第二方向上，所述第一行和所述第二行交替排列，所述第一方向和所述第二方向垂直；
    分布在相邻两行两列的两个所述第一发光图案和两个所述第二发光图案形成一个虚拟四边形，所述第三发光图案位于所述虚拟四边形中；
    相邻两个所述第三发光图案之间设置有所述透明抑制图案，相邻的所述第一发光图案与所述第二发光图案之间设置有所述透明抑制图案。
  8. 根据权利要求1所述的显示面板，其中，所述显示面板还包括阵列排布的像素单元，所述像素单元包括一个第一发光图案、一个第二发光图案和两个第三发光图案，两个所述第三发光图案在第二方向上排列，一个所述第一发光图案和一个所述第二发光图案在第一方向上排列，所述第一发光图案和所述第二发光图案位于两个所述第三发光图案的中心点的连线的中心线上；
    在所述第一方向上，多个所述像素单元排列形成一行，相邻两行内的所述像素单元错位排列，所述第一方向和所述第二方向垂直；
    在相邻两行的相邻所述第一发光图案、所述第二发光图案和两个所述第三发光图案之间设置有所述透明抑制图案。
  9. 根据权利要求7或8所述的显示面板，其中，所述透明抑制图案设置为椭圆形。
  10. 根据权利要求5～8任意一项所述的显示面板，其中，所述第一发光图案是红色发光图案，所述第二发光图案是蓝色发光图案，所述第三发光图案是绿色发光图案。
  11. 一种显示装置，其中，包括权利要求1～9任意一项所述的显示面板。
  12. 一种显示面板的制备方法，其中，包括：
    提供一衬底基板，所述衬底基板具有第一区以及第二区；
    在所述衬底基板的一侧形成发光层，所述发光层包括多个发光图案，所述多个发光图案在所述衬底基板上的正投影互不交叠；
    在所述第一区，且在所述衬底基板的一侧形成多个透明抑制图案，所述透明抑制图案位于至少部分相邻的所述发光图案之间，多个所述透明抑制图案之间间隔设置；
    在所述发光层的远离所述衬底基板的一侧形成第一电极，并在所述第一电极上形成多个通孔，所述通孔在所述衬底基板上的正投影与所述透明抑制图案在所述衬底基板上的正投影重合。
  13. 根据权利要求12所述的显示面板的制备方法，其中，所述制备方法还包括：
    在所述衬底基板的一侧形成平坦化层，并在所述平坦化层上形成第一过孔；
    在所述平坦化层的远离所述衬底基板的一侧形成像素定义层，并在所述像素定义层上形成第三过孔和第四过孔，所述第三过孔与所述第一过孔连通；
    所述发光图案形成在所述第三过孔内，所述透明抑制图案形成在连通的所述第一过孔和所述第三过孔内。
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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11832473B2 (en) 2019-06-26 2023-11-28 Oti Lumionics Inc. Optoelectronic device including light transmissive regions, with light diffraction characteristics
CN117500334A (zh) 2019-06-26 2024-02-02 Oti照明公司 包括具有光衍射特征的光透射区域的光电设备
CN112382651A (zh) * 2020-11-30 2021-02-19 京东方科技集团股份有限公司 显示面板及其制备方法、显示装置
JP2023553379A (ja) 2020-12-07 2023-12-21 オーティーアイ ルミオニクス インコーポレーテッド 核形成抑制被膜及び下地金属被膜を用いた導電性堆積層のパターニング
CN113327961A (zh) * 2021-05-21 2021-08-31 武汉华星光电技术有限公司 Oled显示面板及其制备方法、oled显示装置
WO2023024086A1 (zh) * 2021-08-27 2023-03-02 京东方科技集团股份有限公司 显示基板及显示装置
CN117396037A (zh) * 2022-02-14 2024-01-12 武汉华星光电半导体显示技术有限公司 显示面板及移动终端
CN115207248B (zh) * 2022-07-15 2024-01-19 武汉华星光电半导体显示技术有限公司 显示面板及显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170077209A1 (en) * 2015-09-11 2017-03-16 Samsung Display Co., Ltd. Organic light-emitting diode display and method of manufacturing the same
CN110010665A (zh) * 2019-03-27 2019-07-12 武汉华星光电半导体显示技术有限公司 Oled显示面板
CN110391254A (zh) * 2019-07-16 2019-10-29 武汉华星光电半导体显示技术有限公司 一种显示面板及其制备方法、显示装置
CN110783485A (zh) * 2019-09-24 2020-02-11 昆山国显光电有限公司 透光显示面板、显示面板、制作方法、显示装置
CN111223886A (zh) * 2018-11-27 2020-06-02 北京小米移动软件有限公司 显示屏及电子设备
CN111863892A (zh) * 2020-07-13 2020-10-30 武汉华星光电半导体显示技术有限公司 显示装置及其制备方法
CN112382651A (zh) * 2020-11-30 2021-02-19 京东方科技集团股份有限公司 显示面板及其制备方法、显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170077209A1 (en) * 2015-09-11 2017-03-16 Samsung Display Co., Ltd. Organic light-emitting diode display and method of manufacturing the same
CN111223886A (zh) * 2018-11-27 2020-06-02 北京小米移动软件有限公司 显示屏及电子设备
CN110010665A (zh) * 2019-03-27 2019-07-12 武汉华星光电半导体显示技术有限公司 Oled显示面板
CN110391254A (zh) * 2019-07-16 2019-10-29 武汉华星光电半导体显示技术有限公司 一种显示面板及其制备方法、显示装置
CN110783485A (zh) * 2019-09-24 2020-02-11 昆山国显光电有限公司 透光显示面板、显示面板、制作方法、显示装置
CN111863892A (zh) * 2020-07-13 2020-10-30 武汉华星光电半导体显示技术有限公司 显示装置及其制备方法
CN112382651A (zh) * 2020-11-30 2021-02-19 京东方科技集团股份有限公司 显示面板及其制备方法、显示装置

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