WO2022110650A1 - 一种显示基板、显示装置 - Google Patents

一种显示基板、显示装置 Download PDF

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Publication number
WO2022110650A1
WO2022110650A1 PCT/CN2021/092096 CN2021092096W WO2022110650A1 WO 2022110650 A1 WO2022110650 A1 WO 2022110650A1 CN 2021092096 W CN2021092096 W CN 2021092096W WO 2022110650 A1 WO2022110650 A1 WO 2022110650A1
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Prior art keywords
light
sub
circuit
signal line
substrate
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Application number
PCT/CN2021/092096
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English (en)
French (fr)
Inventor
王洪润
徐攀
李昌峰
张慧
张舜航
侯凯
刘立伟
林允植
Original Assignee
京东方科技集团股份有限公司
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Priority to US17/762,334 priority Critical patent/US12033573B2/en
Publication of WO2022110650A1 publication Critical patent/WO2022110650A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate and a display device.
  • Organic Light-Emitting Diode (English: Organic Light-Emitting Diode, OLED) display devices are widely used in various fields due to their advantages of high brightness, low power consumption, fast response, high definition, good flexibility and high luminous efficiency.
  • the OLED display device includes a plurality of sub-pixels, each sub-pixel includes a pixel driving circuit and a light-emitting element, and the pixel driving circuit is used for driving the light-emitting element to emit light. Since all pixel driving circuits in an OLED display device are distributed on the substrate in an array, subject to factors such as line width, line spacing and via size, the number of pixel driving circuits in a certain area is limited, which makes it difficult to achieve High resolution OLED display device.
  • the purpose of the present disclosure is to provide a display substrate and a display device.
  • a first aspect of the present disclosure provides a display substrate including a base and a plurality of sub-pixels disposed on the base, each sub-pixel including a light-emitting element;
  • the plurality of sub-pixels are divided into a plurality of sub-pixel groups, the sub-pixel group includes at least two sub-pixels, and the at least two sub-pixels multiplex the same pixel driving circuit, and the pixel driving circuit includes:
  • At least two light-emitting control signal lines at least part of each light-emitting control signal line extends along a first direction, at least two light-emitting control signal lines are arranged along a second direction, and the second direction intersects the first direction ;
  • a compensation driving sub-circuit the output end of the compensation driving sub-circuit is used for outputting a driving signal
  • At least two light-emitting control sub-circuits correspond to the at least two light-emitting elements included in the at least two sub-pixels, the at least two light-emitting control sub-circuits and the at least two light-emitting elements Corresponding control signal lines, each of the light-emitting control sub-circuits is respectively coupled with the output end of the compensation driving sub-circuit, the corresponding light-emitting element and the corresponding light-emitting control signal line; each of the light-emitting control sub-circuits is used for Under the control of the corresponding light-emitting control signal line, the connection between the output end of the compensation driving sub-circuit and the corresponding light-emitting element is controlled to be turned on or off.
  • the pixel driving circuit further includes:
  • a reference signal line at least a portion of the reference signal line extends along the first direction
  • a first reset signal line at least part of the first reset signal line extends along the first direction
  • the compensation driving sub-circuit includes:
  • the first end of the driving sub-circuit is coupled to the power line, and the second end of the driving sub-circuit serves as the output end of the compensation driving sub-circuit;
  • the first end of the storage sub-circuit is coupled to the control end of the driving sub-circuit, and the second end of the storage sub-circuit is coupled to the second end of the driving sub-circuit;
  • a first reset sub-circuit respectively coupled to the first reset signal line, the reference signal line and the control terminal of the driving sub-circuit
  • the data writing sub-circuit is respectively coupled to the gate line, the data line and the control terminal of the driving sub-circuit.
  • the at least two light-emitting control signal lines include a first light-emitting control signal line and a second light-emitting control signal line;
  • the at least two light-emitting control sub-circuits include a first light-emitting control sub-circuit and a second light-emitting control sub-circuit.
  • the at least two light-emitting elements include a first light-emitting element and a second light-emitting element;
  • the first light-emitting control sub-circuit is respectively connected with the second end of the driving sub-circuit, the first light-emitting control signal line is coupled with the first light-emitting element;
  • the second light-emitting control sub-circuit is respectively connected with the At the second end of the driving sub-circuit, the second light-emitting control signal line is coupled to the second light-emitting element.
  • the first lighting control sub-circuit includes a first transistor
  • the second lighting control sub-circuit includes a second transistor
  • the driving sub-circuit includes a driving transistor
  • the storage sub-circuit includes a storage capacitor
  • the gate of the driving transistor is multiplexed as the first plate of the storage capacitor
  • the second electrode plate of the storage capacitor is located on the side of the first electrode plate facing away from the substrate, and the second electrode plate is coupled to the second electrode of the driving transistor;
  • the first electrode of the first transistor is coupled to the second electrode of the driving transistor, and the second electrode of the first transistor is coupled to the first light-emitting element;
  • the first electrode of the second transistor is coupled to the second electrode plate, and the second electrode of the second transistor is coupled to the second light emitting element.
  • the first transistor includes a first active pattern, and the first active pattern extends along the second direction; the first end of the first active pattern and the second end of the driving transistor pole coupling; the second end of the first active pattern is coupled with the first light emitting element;
  • the second pole plate includes a main body portion and an extension portion
  • an orthographic projection of the body portion on the substrate at least partially overlaps an orthographic projection of the gate of the driving transistor on the substrate;
  • the extension portion extends along the second direction, and the orthographic projection of the extension portion on the substrate is respectively related to the orthographic projection of the first light-emitting control signal line on the substrate and the second light-emitting control signal line. Orthographic projections of the signal lines on the substrate overlap.
  • the second transistor includes a second active pattern, at least a part of the second active pattern extends along the second direction, and the first end of the second active pattern is connected to the extending portion coupling, the second end of the second active pattern is coupled with the second light-emitting element;
  • the pixel driving circuit further includes:
  • an initialization signal line at least a portion of the initialization signal line extends along the first direction
  • the second reset signal line at least a part of the second reset signal line extends along the first direction; the first reset signal line, the gate line, the first light-emitting control signal line, the second The light-emitting control signal line and the second reset signal line are sequentially arranged along the second direction;
  • the second reset sub-circuit is respectively coupled to the second reset signal line, the initialization signal line and the extension part.
  • the second reset sub-circuit includes a fifth transistor, the fifth transistor includes a fifth active pattern, and the fifth active pattern extends along the second direction;
  • the first end of the fifth active pattern is coupled to the extension part, and the orthographic projection of the first end of the fifth active pattern on the substrate is located where the second light-emitting control signal line is located. between the orthographic projection on the substrate and the orthographic projection of the second reset signal line on the substrate.
  • the fifth active pattern and the initialization signal line form an integral structure.
  • the orthographic projection of the first reset signal line on the substrate is located between the orthographic projection of the reference signal line on the substrate and the orthographic projection of the grid line on the substrate;
  • the first reset sub-circuit includes a third transistor, the third transistor includes a third active pattern, the third active pattern extends along the second direction, and a first end of the third active pattern coupled with the reference signal line, the orthographic projection of the second end of the third active pattern on the substrate, the orthographic projection of the first reset signal line on the substrate and the gate line between orthographic projections on the substrate.
  • the gate line includes a gate main body part and two gate protrusion parts, the gate main body part extends along the first direction, the two gate protrusion parts are spaced apart along the first direction, and the two gate protrusions are located between the gate body and the first reset signal line;
  • the data writing sub-circuit includes a fourth transistor, the fourth transistor includes a fourth active pattern, the fourth active pattern extends along the first direction, and the fourth active pattern is on the substrate. orthographic projections, respectively overlapping the orthographic projections of the two gate protrusions on the substrate;
  • the first end of the fourth active pattern is coupled to the data line, and the second end of the fourth active pattern is coupled to the second end of the third active pattern.
  • the pixel driving circuit includes a conductive connection portion, at least a part of the conductive connection portion extends along the second direction, and the orthographic projection of the conductive connection portion on the substrate is where the gate line is located. Orthographic overlap on the base;
  • the first end of the conductive connection portion is coupled to the second end of the third active pattern, and the second end of the conductive connection portion is coupled to the control end of the driving sub-circuit.
  • a second aspect of the present disclosure provides a display device including the above-mentioned display substrate.
  • the at least two light-emitting control signal lines in the display substrate include a first light-emitting control signal line and a second light-emitting control signal line;
  • the at least two light-emitting control sub-circuits include a first light-emitting control sub-circuit and a second light-emitting control sub-circuit a sub-circuit;
  • at least two light-emitting elements include a first light-emitting element and a second light-emitting element;
  • the plurality of pixel driving circuits included in the plurality of sub-pixel groups in the display substrate are distributed in an array, and the plurality of pixel driving circuits are divided into a plurality of rows of pixel driving circuits arranged along the second direction, and each row of pixel driving circuits
  • the first light-emitting control signal lines in the pixel driving circuit are sequentially coupled, and the second light-emitting control signal lines in each row of pixel driving circuits are sequentially coupled;
  • the display device further includes: a gate drive circuit located in a peripheral area of the display substrate, the gate drive circuit includes a plurality of first shift register units and a plurality of second shift register units; the plurality of first shift register units The shift register units are in one-to-one correspondence with the plurality of rows of pixel driving circuits, and the plurality of second shift register units are in one-to-one correspondence with the multi-row pixel driving circuits;
  • the output end of the first shift register unit is coupled to the first light-emitting control signal line in the corresponding row of pixel driving circuits, and the output end of the second shift register unit is coupled to the first light emission control signal line in the corresponding row of pixel driving circuits.
  • the two light-emitting control signal lines are coupled.
  • FIG. 1 is a schematic layout diagram of a pixel driving circuit provided by an embodiment of the present disclosure
  • Fig. 2 is the schematic diagram of the active layer in Fig. 1;
  • FIG. 3 is a schematic diagram of the first gate metal layer in FIG. 1;
  • FIG. 4 is a schematic diagram of the second gate metal layer in FIG. 1;
  • FIG. 5 is a schematic diagram of the first source-drain metal layer in FIG. 1;
  • FIG. 6 is a first basic structural diagram of a pixel driving circuit provided by an embodiment of the present disclosure.
  • FIG. 7 is a first specific structural diagram of a pixel driving circuit provided by an embodiment of the present disclosure.
  • FIG. 8 is a second basic structural diagram of a pixel driving circuit provided by an embodiment of the present disclosure.
  • FIG. 9 is a second specific structural diagram of a pixel driving circuit provided by an embodiment of the present disclosure.
  • FIG. 10 is a working timing diagram of a pixel driving circuit within one frame of display time provided by an embodiment of the present disclosure
  • FIG. 11 is a working timing diagram in a signal writing period provided by an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of a gate driving circuit provided by an embodiment of the present disclosure.
  • An embodiment of the present disclosure provides a display substrate, including a base and a plurality of sub-pixels disposed on the base, each of the sub-pixels including a light-emitting element;
  • the plurality of sub-pixels are divided into a plurality of sub-pixel groups, the sub-pixel group includes at least two sub-pixels, and the at least two sub-pixels multiplex the same pixel driving circuit, and the pixel driving circuit includes:
  • At least two light-emitting control signal lines at least part of each light-emitting control signal line extends along a first direction, at least two light-emitting control signal lines are arranged along a second direction, and the second direction intersects the first direction ;
  • a compensation driving sub-circuit the output end of the compensation driving sub-circuit is used for outputting a driving signal
  • At least two light-emitting control sub-circuits correspond to the at least two light-emitting elements included in the at least two sub-pixels, the at least two light-emitting control sub-circuits and the at least two light-emitting elements Corresponding control signal lines, each of the light-emitting control sub-circuits is respectively coupled with the output end of the compensation driving sub-circuit, the corresponding light-emitting element and the corresponding light-emitting control signal line; each of the light-emitting control sub-circuits is used for Under the control of the corresponding light-emitting control signal line, the connection between the output end of the compensation driving sub-circuit and the corresponding light-emitting element is controlled to be turned on or off.
  • the at least two light-emitting control sub-circuits are in one-to-one correspondence with at least two light-emitting elements included in the at least two sub-pixels, and the at least two light-emitting control sub-circuits are associated with the at least two light-emitting control signals. Lines correspond one by one.
  • the light-emitting element includes an anode and a cathode disposed opposite to each other, and an organic light-emitting material layer located between the anode and the cathode.
  • each sub-pixel group includes at least two adjacent sub-pixels along the first direction.
  • each sub-pixel group includes at least two sub-pixels adjacent along the second direction.
  • each sub-pixel group includes a plurality of sub-pixels, and the plurality of sub-pixels include sub-pixels adjacent to the first direction and sub-pixels adjacent to the second direction.
  • each sub-pixel included in the sub-pixel group multiplexes the same pixel driving circuit.
  • the first direction includes a horizontal direction
  • the second direction includes a vertical direction
  • the compensation driving sub-circuit is used to generate a current signal for driving the light-emitting element to emit light.
  • only one light-emitting control sub-circuit of the at least two light-emitting control sub-circuits can control the compensation driving sub-circuit to be turned on.
  • the connection between the output end of the compensation drive sub-circuit and the corresponding light-emitting element, and the remaining light-emitting control sub-circuits are controlled to disconnect the connection between the output end of the compensation drive sub-circuit and the corresponding light-emitting element.
  • a plurality of light-emitting control sub-circuits can control the compensation driving sub-circuit to be turned on.
  • the connection between the output terminal and the corresponding light-emitting element can control the compensation driving sub-circuit to be turned on.
  • At least two sub-pixels can multiplex a pixel driving circuit, and the pixel driving circuit can independently control each of the at least two sub-pixels to include:
  • the light-emitting elements of the present disclosure emit light independently or at the same time. Therefore, the display substrate provided by the embodiment of the present disclosure can realize high-resolution display under the condition that a limited number of pixel driving circuits are arranged.
  • the pixel driving circuit further includes:
  • a reference signal line 31 at least a part of the reference signal line 31 extends along the first direction
  • a first reset signal line 32 at least a part of the first reset signal line 32 extends along the first direction;
  • a gate line 33 at least part of the gate line 33 extends along the first direction
  • a power cord 38 at least a portion of which extends in the second direction;
  • a data line 39 at least part of the data line 39 extends along the second direction;
  • the compensation driving sub-circuit includes:
  • the driving sub-circuit 10 the first end of the driving sub-circuit 10 is coupled to the power line 38, and the second end of the driving sub-circuit 10 is used as the output end of the compensation driving sub-circuit;
  • a storage sub-circuit 11 the first terminal of the storage sub-circuit 11 is coupled to the control terminal of the driving sub-circuit 10, and the second terminal of the storage sub-circuit 11 is coupled to the second terminal of the driving sub-circuit 10 catch;
  • the first reset sub-circuit 12 is respectively coupled to the first reset signal line 32, the reference signal line 31 and the control terminal of the driving sub-circuit 10;
  • the data writing sub-circuit 13 is respectively coupled to the gate line 33 , the data line 39 and the control terminal of the driving sub-circuit 10 .
  • the reference signal line 31 is used to provide the reference signal Vref, and the reference signal Vref is a DC signal.
  • the orthographic projection of the reference signal line 31 on the substrate, the orthographic projection of the first reset signal line 32 on the substrate, and the orthographic projection of the gate line 33 on the substrate are along the The second directions are arranged in sequence.
  • the power lines 38 and the data lines 39 are arranged along the first direction.
  • the power line 38 and the data line 39 are provided in the same layer and the same material.
  • the illustrated power supply line 38 provides a positive power supply signal ELVDD and the cathode of the light emitting element receives a negative power supply signal ELVSS.
  • the first reset sub-circuit 12 and the driving sub-circuit 10 are arranged along the second direction.
  • the orthographic projection of the driving sub-circuit 10 on the substrate the orthographic projection of the storage sub-circuit 11 on the substrate, and the orthographic projection of the first reset sub-circuit 12 on the substrate.
  • the projections are located between the orthographic projection of the power line 38 on the substrate and the orthographic projection of the data line 39 on the substrate.
  • the at least two light-emitting control signal lines include a first light-emitting control signal line 34 and a second light-emitting control signal line 35 ; the at least two light-emitting control signal lines
  • the control sub-circuit includes a first light-emitting control sub-circuit 15 and a second light-emitting control sub-circuit 16; the at least two light-emitting elements include a first light-emitting element EL1 and a second light-emitting element EL2;
  • the first light-emitting control sub-circuit 15 is respectively coupled to the second end of the driving sub-circuit 10, the first light-emitting control signal line 34 and the first light-emitting element EL1;
  • the second light-emitting control sub-circuit 16 are respectively coupled to the second end of the driving sub-circuit 10, the second light-emitting control signal line 35 and the second light-emitting element EL2.
  • the first light-emitting control signal line 34 and the second light-emitting control signal line 35 both extend along the first direction, and the first light-emitting control signal line 34 and the second light-emitting control signal line 35 are arranged along the second direction.
  • the organic light-emitting material layer of the first light-emitting element EL1 and the organic light-emitting material layer of the second light-emitting element EL2 are arranged along the first direction; or the organic light-emitting material layer of the first light-emitting element EL1 and the organic light-emitting material layers of the second light-emitting element EL2 are arranged along the second direction.
  • the first light-emitting control sub-circuit 15 can be controlled to turn on or off the connection between the second end of the driving sub-circuit 10 and the first light-emitting element EL1 under the control of the first light-emitting control signal line 34 .
  • the second light-emitting control sub-circuit 16 can control the connection between the second end of the driving sub-circuit 10 and the second light-emitting element EL2 under the control of the second light-emitting control signal line 35 . Connection.
  • the first light-emitting control sub-circuit 15 controls the connection between the second end of the driving sub-circuit 10 and the corresponding first light-emitting element EL1
  • the second light-emitting control The sub-circuit 16 controls the connection between the second end of the driving sub-circuit 10 and the corresponding first light-emitting element EL1 to be turned on.
  • the display time of one frame is divided into a first half frame and a second half frame, and the first half frame and the second half frame both include a signal writing period P11 and a light emitting period P12 .
  • the compensation driving sub-circuit completes the process of writing and compensating the gray scale corresponding to the first light-emitting element EL1.
  • the first light-emitting control sub-circuit 15 controls the connection between the output end of the compensation driving sub-circuit and the corresponding first light-emitting element EL1.
  • the second light-emitting control sub-circuit 16 controls to disconnect the output end of the compensation driving sub-circuit and the corresponding The connection between the second light-emitting elements EL2 prevents the second light-emitting elements EL2 from emitting light.
  • the compensation driving sub-circuit completes the process of writing and compensating the gray scale corresponding to the second light-emitting element EL2.
  • the first light-emitting control sub-circuit 15 controls to disconnect the output end of the compensation driving sub-circuit and the corresponding first light-emitting element EL1
  • the second light-emitting control sub-circuit 16 controls to turn on the output end of the compensation driving sub-circuit and the The connection between the corresponding second light-emitting elements EL2 enables the second light-emitting elements EL2 to emit light.
  • each sub-pixel group includes N sub-pixels
  • N is an integer greater than or equal to 2
  • the display time of each frame can be divided into N sub-frames, and gray-scale writing can be implemented for the corresponding light-emitting elements in each sub-frame. , compensation and display process.
  • the grayscale writing and signal compensation vias corresponding to each subframe can achieve non-interference with each other, thereby realizing independent control of the N light-emitting elements.
  • N sub-pixels can share one pixel driving circuit, so that time-sharing display or simultaneous display of each sub-pixel can be realized, and it is avoided that each pixel is provided with an independent pixel driving circuit, which greatly improves the performance of the pixel.
  • the first lighting control sub-circuit 15 includes a first transistor T1
  • the second lighting control sub-circuit 16 includes a second transistor T2
  • the drive sub-circuit 10 includes a drive transistor DTFT
  • the storage sub-circuit 11 includes a storage capacitor Cst
  • the gate g of the driving transistor DTFT is multiplexed as the first plate Cst1 of the storage capacitor Cst;
  • the second electrode plate Cst2 of the storage capacitor Cst is located on the side of the first electrode plate Cst1 facing away from the substrate, and the second electrode plate Cst2 is coupled to the second electrode of the driving transistor DTFT;
  • the first electrode of the first transistor T1 is coupled to the second electrode of the driving transistor DTFT, and the second electrode of the first transistor T1 is coupled to the first light-emitting element EL1;
  • the first electrode of the second transistor T2 is coupled to the second electrode plate Cst2, and the second electrode of the second transistor T2 is coupled to the second light emitting element EL2.
  • the driving transistor DTFT includes a driving active pattern 56, and the driving active pattern 56 includes a portion extending along the first direction and a portion extending along the second direction,
  • the orthographic projection of the driving active pattern 56 on the substrate partially overlaps the orthographic projection of the gate of the driving transistor DTFT on the substrate, and the first end of the driving active pattern 56 serves as the The first electrode of the driving transistor DTFT, the second end of the driving active pattern 56 serves as the second electrode of the driving transistor DTFT, and the orthographic projection of the first end of the driving active pattern 56 on the substrate is the same as the The orthographic projection of the power line 38 on the substrate overlaps, and at the overlap, the first end of the driving active pattern 56 is coupled with the power line 38 through the first via 21 , and the driver has The second terminal of the source pattern 56 is coupled to the first terminal of the first transistor T1.
  • the orthographic projection of the second end of the driving active pattern 56 on the substrate overlaps with the orthographic projection of the second plate Cst2 on the substrate.
  • the second end of the driving active pattern 56 is coupled to the second electrode plate Cst2 through the second via hole 22 .
  • the first transistor T1 includes a first active pattern 51 , and the first active pattern 51 extends along the second direction ;
  • the first end of the first active pattern 51 is coupled to the second pole of the driving transistor DTFT;
  • the second end of the first active pattern 51 is coupled to the first light-emitting element EL1;
  • the first active pattern 51 extends along the second direction, and the orthographic projection of the first active pattern 51 on the substrate and the first light-emitting control signal line 34 are on the substrate.
  • the first electrode, the second end of the first active pattern 51 serves as the second electrode of the first transistor T1.
  • neither the first end nor the second end of the first active pattern 51 overlaps with the first light emission control signal 34 .
  • the first end of the first active pattern 51 and the second end of the driving active pattern 56 form an integral structure.
  • the second end of the first active pattern 51 is coupled to the anode of the first light-emitting element EL1 through the third via hole 23 .
  • the second electrode plate Cst2 includes a main body portion Cst21 and an extension portion Cst22 ;
  • the orthographic projection of the main body portion Cst21 on the substrate at least partially overlaps the orthographic projection of the gate electrode of the driving transistor DTFT on the substrate;
  • the extension portion Cst22 extends along the second direction, and the orthographic projection of the extension portion Cst22 on the substrate is respectively the orthographic projection of the first light-emitting control signal line 34 on the substrate and the orthographic projection of the first light-emitting control signal line 34 on the substrate.
  • the orthographic projections of the two light-emitting control signal lines 35 on the substrate overlap.
  • the main body portion and the extension portion Cst22 are formed as an integral structure.
  • the main body part is block-shaped
  • the extension part Cst22 is strip-shaped
  • the orthographic projection of the second end of the driving active pattern 56 on the substrate overlaps with the orthographic projection of the main body portion Cst21 on the substrate, where the driving has The second end of the source pattern 56 is coupled to the body portion Cst21 through the second via hole 22 .
  • the orthographic projection of one end of the extension portion Cst22 away from the main body portion on the substrate is located in the orthographic projection of the second light-emitting control signal line 35 on the substrate and the second reset signal line 36 between orthographic projections on the substrate.
  • the second transistor T2 includes a second active pattern 52 , and at least part of the second active pattern 52 extends along the second direction , the first end of the second active pattern 52 is coupled to the extension portion Cst22, and the second end of the second active pattern 52 is coupled to the second light-emitting element EL2;
  • the second active graphics 52 are shape.
  • the second active pattern 52 includes a first part and a second part of an integral structure, the first part extends along the second direction, the second part extends along the first direction, the The orthographic projection of the first portion on the substrate overlaps the orthographic projection portion of the second light emission control signal line 35 on the substrate.
  • the first end of the second active pattern 52 serves as the first pole of the second transistor T2, and the second end of the second active pattern 52 serves as the second end of the second transistor T2. pole.
  • the orthographic projection of the first end of the second active pattern 52 on the substrate overlaps with the orthographic projection of the extending portion Cst22 on the substrate, and at the overlap, the second active pattern
  • the first end of the pattern 52 is coupled to the extending portion Cst22 through the fourth via hole 24 .
  • the second end of the second active pattern 52 is coupled to the anode of the second light emitting element EL2 through the fifth via hole 25 .
  • the orthographic projection of the second end of the second active pattern 52 on the substrate the orthographic projection of the second light-emitting control signal line 35 on the substrate and the second reset signal line 36 between orthographic projections on the substrate.
  • the pixel driving circuit further includes:
  • an initialization signal line 37 at least a part of the initialization signal line 37 extends along the first direction;
  • the second reset signal line 36 at least a part of the second reset signal line 36 extends along the first direction; the first reset signal line 32, the gate line 33, the first light emission control signal line 34 , the second light-emitting control signal line 35 and the second reset signal line 36 are sequentially arranged along the second direction;
  • the second reset sub-circuit 14 is respectively coupled to the second reset signal line 36 , the initialization signal line 37 and the extension portion Cst22 .
  • the initialization signal line 37 is used to provide the reference signal Vref with a fixed potential.
  • the initialization signal line 37 is provided in the same layer and material as the active pattern in each transistor.
  • the initialization signal line 37 and the gate line 33 are provided in the same layer and material.
  • the initialization signal line 37 and the second plate Cst2 of the storage capacitor Cst are provided in the same layer and the same material.
  • the orthographic projection of the second reset signal line 36 on the substrate the orthographic projection of the second light-emitting control signal line 35 on the substrate, and the initialization signal line 37 on the substrate between the orthographic projections on.
  • the second reset sub-circuit 14 can control the connection between the initialization signal line 37 and the extension portion Cst22 to be turned on or off under the control of the second reset signal line 36 .
  • the second reset sub-circuit 14 includes a fifth transistor T5 , and the fifth transistor T5 includes a fifth active pattern 55 , so the fifth active pattern 55 extends along the second direction;
  • the first end of the fifth active pattern 55 is coupled to the extension portion Cst22, and the orthographic projection of the first end of the fifth active pattern 55 on the substrate is located in the second light-emitting control signal Between the orthographic projection of the line 35 on the substrate and the orthographic projection of the second reset signal line 36 on the substrate.
  • the orthographic projection of the fifth active pattern 55 on the substrate overlaps the orthographic projection of the second reset signal line 36 on the substrate.
  • One end serves as the second pole of the fifth transistor T5
  • the second end of the fifth active pattern 55 serves as the first pole of the fifth transistor T5.
  • the orthographic projection of the first end of the fifth active pattern 55 on the substrate overlaps with the orthographic projection of the extending portion Cst22 on the substrate.
  • the first ends of the five active patterns 55 are coupled to the extending portion Cst22 through the sixth via hole 26 .
  • the fifth active pattern 55 and the initialization signal line 37 are arranged to form an integrated structure.
  • the above arrangement enables the fifth active pattern 55 and the initialization signal line 37 to be formed in the same patterning process, which effectively simplifies the manufacturing process of the display substrate and reduces the manufacturing cost.
  • the orthographic projection of the first reset signal line 32 on the substrate is located on the substrate of the reference signal line 31 between the orthographic projection of and the orthographic projection of the grid line 33 on the substrate;
  • the first reset sub-circuit 12 includes a third transistor T3, the third transistor T3 includes a third active pattern 53, the third active pattern 53 extends along the second direction, and the third active pattern 53 extends along the second direction.
  • the first end of the pattern 53 is coupled to the reference signal line 31, and the orthographic projection of the second end of the third active pattern 53 on the substrate is located on the substrate of the first reset signal line 32. between the orthographic projection on and the orthographic projection of the grid lines 33 on the substrate.
  • the orthographic projection of the third active pattern 53 on the substrate partially overlaps the orthographic projection of the first reset signal line 32 on the substrate.
  • the first end of the third active pattern 53 serves as the first pole of the third transistor T3
  • the second end of the third active pattern 53 serves as the second pole of the third transistor T3
  • the The orthographic projection of the first end of the third active pattern 53 on the substrate overlaps with the orthographic projection of the reference signal line 31 on the substrate.
  • the third active pattern The first end of 53 is coupled to the reference signal line 31 through the seventh via hole 27 .
  • the gate line 33 includes a gate main body part 331 and two gate protrusion parts 332 , and the gate main body part 331 is along the first gate part 331 . extending in the first direction, the two gate protrusions 332 are arranged at intervals along the first direction, and the two gate protrusions 332 are located between the gate body portion 331 and the first reset signal line 32;
  • the data writing sub-circuit 13 includes a fourth transistor T4, the fourth transistor T4 includes a fourth active pattern 54, the fourth active pattern 54 extends along the first direction, and the fourth active pattern 54
  • the orthographic projections on the substrate respectively overlap with the orthographic projections of the two gate protrusions 332 on the substrate;
  • the first end of the fourth active pattern 54 is coupled to the data line 39 , and the second end of the fourth active pattern 54 is coupled to the second end of the third active pattern 53 .
  • the gate main body part 331 and the two gate protrusion parts 332 are formed as an integral structure.
  • the gate protrusions 332 extend along the second direction.
  • the orthographic projection of the two gate protrusions 332 on the substrate the orthographic projection of the gate body portion 331 on the substrate and the first reset signal line 32 on the substrate between the orthographic projections.
  • the two gate protrusions 332 are multiplexed as gates of the fourth transistor T4, and the fourth transistor T4 has a double gate structure.
  • the fourth transistor T4 may also be formed in a common structure with only one gate.
  • the first end of the fourth active pattern 54 serves as the first pole of the fourth transistor T4, and the second end of the fourth active pattern 54 serves as the second end of the fourth transistor T4. pole.
  • the orthographic projection of the first end of the fourth active pattern 54 on the substrate overlaps with the orthographic projection of the data line 39 on the substrate, where the first end of the fourth active pattern 54 overlaps.
  • the first ends of the four active patterns 54 are coupled to the data line 39 through the eighth via hole 28 .
  • the second end of the fourth active pattern 54 and the second end of the third active pattern 53 form an integral structure.
  • the third active pattern 53 and the fourth active pattern 54 are jointly formed into an L shape.
  • first transistor T1 the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the driving transistor DTFT are various, Exemplarily, NMOS transistors are used.
  • the working process of the pixel driving circuit during the signal writing period is as follows:
  • the third transistor T3 is turned on, and the gate of the driving transistor DTFT (ie point g) is turned on. ) write the reference signal Vref; under the control of the second reset signal G2 written in the second reset signal line 36, the fifth transistor T5 is turned on, and the initialization is written to the source of the driving transistor DTFT (ie, the s point). Signal Vint.
  • the voltage of the reference signal Vref is higher than the voltage of the initialization signal Vint, the driving transistor DTFT is turned on, and the voltage at the s point rises.
  • the Vth bit drives the transistor.
  • the pixel driving circuit includes a conductive connection part 40 , at least a part of the conductive connection part 40 extends along the second direction, and the conductive connection part 40 is in the second direction.
  • the orthographic projection on the substrate partially overlaps the orthographic projection of the grid line 33 on the substrate;
  • the first end of the conductive connection portion 40 is coupled to the second end of the third active pattern 53 , and the second end of the conductive connection portion 40 is coupled to the control end of the driving sub-circuit 10 .
  • the orthographic projection of the first end of the conductive connection portion 40 on the substrate overlaps with the orthographic projection of the second end of the third active pattern 53 on the substrate, and at the overlap, The first end of the conductive connection portion 40 is coupled to the second end of the third active pattern 53 through the ninth via hole 29 .
  • the orthographic projection of the second end of the conductive connection part 40 on the substrate overlaps with the orthographic projection of the gate of the driving transistor DTFT on the substrate, and the second end of the conductive connection part 40 overlaps with the orthographic projection of the gate of the driving transistor DTFT on the substrate.
  • the gate of the driving transistor DTFT is coupled through the tenth via hole 20 .
  • the orthographic projection of the conductive connection portion 40 on the substrate does not overlap with the orthographic projection of the second electrode plate Cst2 on the substrate.
  • the display substrate includes an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, and an interlayer that are sequentially stacked along a direction away from the substrate.
  • the active layer is used to form the active pattern included in each transistor, and the signal line 37 is initialized;
  • the first gate metal layer is used to form the first reset signal line 32, the gate, so the first light-emitting control signal line 34, the second light-emitting control signal line 35 and the second reset signal line 36;
  • the second gate metal layer is used to form the reference signal line 31, the second pole plate Cst2 and some conductive connection parts 40 ;
  • the first source-drain metal layer is used to form the power supply line 38 , the data line 39 and some conductive connection parts 40 .
  • the first via hole 21 to the tenth via hole 20 can penetrate one or more film layers.
  • the second electrode of the first transistor T1 and the second electrode of the second transistor T2 may pass through the connection portion (such as the markers 41 and 41) formed by the second gate metal layer and the first source-drain metal layer. 42), and the corresponding via hole, which is coupled with the anode of the corresponding light-emitting element.
  • the layout space can be effectively utilized, and the resolution of the display substrate can be maximized.
  • Embodiments of the present disclosure also provide a display device including the display substrate provided by the above embodiments.
  • the display substrate provided by the above embodiment at least two sub-pixels can be multiplexed with a pixel driving circuit, and the pixel driving circuit can independently control the light-emitting elements included in each of the at least two sub-pixels to emit light independently or simultaneously. Therefore, , the display substrate provided by the above-mentioned embodiments can realize high-resolution display under the circumstance that a limited number of pixel driving circuits are arranged.
  • the display device provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when including the above-mentioned display substrate, which will not be repeated here.
  • the display device may be any product or component with a display function, such as a TV, a monitor, a digital photo frame, a mobile phone, and a tablet computer.
  • the at least two light-emitting control signal lines in the display substrate include a first light-emitting control signal line 34 and a second light-emitting control signal line 35 ;
  • the at least two light-emitting control sub-circuits include the first light-emitting control sub-circuit 15 and a second light-emitting control sub-circuit 16;
  • at least two light-emitting elements include a first light-emitting element EL1 and a second light-emitting element EL2;
  • the plurality of pixel driving circuits included in the plurality of sub-pixel groups in the display substrate are distributed in an array, and the plurality of pixel driving circuits are divided into a plurality of rows of pixel driving circuits arranged along the second direction, and each row of pixel driving circuits
  • the first light-emitting control signal lines 34 in each row are coupled in sequence
  • the second light-emitting control signal lines 35 in each row of pixel driving circuits are coupled in sequence;
  • the display device further includes: a gate drive circuit located in a peripheral area of the display substrate, the gate drive circuit includes a plurality of first shift register units and a plurality of second shift register units; the plurality of first shift register units The shift register units are in one-to-one correspondence with the plurality of rows of pixel driving circuits, and the plurality of second shift register units are in one-to-one correspondence with the multi-row pixel driving circuits;
  • the output terminal of the first shift register unit is coupled to the first light-emitting control signal line 34 in the corresponding row of pixel driving circuits, and the output terminal of the second shift register unit is coupled to the corresponding row of pixel driving circuits in the pixel driving circuit.
  • the second lighting control signal line 35 is coupled.
  • a plurality of sub-pixel groups includes a plurality of pixel driving circuits distributed in an array, and the plurality of pixel driving circuits can be divided into a plurality of rows of pixel driving circuits and a plurality of columns of pixel driving circuits.
  • the plurality of rows of pixel driving circuits are arranged in sequence along the second direction, and each row of pixel driving circuits includes a plurality of pixel driving circuits arranged along the first direction.
  • the plurality of columns of pixel driving circuits are arranged in sequence along the first direction, and each column of pixel driving circuits includes a plurality of pixel driving circuits arranged along the second direction.
  • the reference signal lines 31 are sequentially coupled to form an integrated structure
  • the first reset signal lines 32 are sequentially coupled to form an integrated structure
  • the gate lines 33 are sequentially coupled to form an integrated structure
  • the first light-emitting control signal lines 34 are sequentially coupled to form an integrated structure
  • the second light-emitting control signal lines 35 are sequentially coupled to form an integrated structure
  • the second reset signal lines 36 are sequentially coupled to form an integrated structure
  • the initialization signal lines 37 are sequentially coupled to form an integrated structure.
  • the power lines 38 are sequentially coupled to form an integrated structure
  • the data lines 39 are sequentially coupled to form an integrated structure.
  • the gate driving circuit includes a plurality of first shift register units EM1GOA and a plurality of second shift register units EM2GOA; the plurality of first shift register units and the There is a one-to-one correspondence between the multiple rows of pixel driving circuits, and the multiple second shift register units are in one-to-one correspondence with the multiple rows of pixel driving circuits;
  • the first light-emitting control signal line 34 of the second shift register unit is coupled to the second light-emitting control signal line 35 in the corresponding row of pixel driving circuits.
  • the gate driving circuit includes a plurality of third shift register units G3GOA, the plurality of third shift register units are in one-to-one correspondence with the plurality of rows of pixel driving circuits, and the third shift register units The output terminal of the unit is coupled to the gate line 33 in the corresponding row of pixel driving circuits.
  • the gate driving circuit includes a plurality of fourth shift register units G1GOA, the plurality of fourth shift register units are in one-to-one correspondence with the plurality of rows of pixel driving circuits, and the fourth shift register units The output terminal of the unit is coupled to the first reset signal line 32 in the corresponding row of pixel driving circuits.
  • the gate driving circuit includes a plurality of fifth shift register units G2GOA, the plurality of fifth shift register units are in one-to-one correspondence with the plurality of rows of pixel driving circuits, and the fifth shift register units The output terminal of the unit is coupled to the second reset signal line 36 in the corresponding row of pixel driving circuits.
  • a shift register unit corresponding to a row of pixel driving circuits may be arranged on one side of the display substrate, that is, to realize single-side driving; or a shift register unit corresponding to a row of pixel driving circuits may also be arranged on the display substrate. Opposite sides, that is, to achieve double-sided driving.
  • the gate driving circuit includes N first shift register units EM1GOA, and the N first shift register units EM1GOA are cascaded, that is, the output of the N-1th first shift register unit EM1GOA.
  • the terminal is coupled to the first light-emitting control signal line 34 in the corresponding row of pixel driving circuits, and the output terminal of the N-1th first shift register unit EM1GOA is also connected to the input of the Nth first shift register unit EM1GOA at the same time.
  • the signal terminal is coupled to the input signal terminal of the N-1th first shift register unit EM1GOA simultaneously to the first light-emitting control signal line 34 in the corresponding row of pixel driving circuits and the Nth first shift register unit EM1GOA Write the first light emission control signal.
  • the plurality of second shift register units EM2GOA, the plurality of third shift register units G3GOA, the plurality of fourth shift register units G1GOA, and the plurality of fifth shift register units G2GOA also satisfy the above-mentioned requirements.
  • the cascading relationship is not repeated here.
  • an embodiment of the present disclosure further provides a pixel driving circuit for driving at least two light-emitting elements to emit light, and the pixel driving circuit includes:
  • the first terminal of the driving sub-circuit 10 is coupled to the first level signal input terminal;
  • a storage sub-circuit 11 the first terminal of the storage sub-circuit 11 is coupled to the control terminal of the driving sub-circuit 10, and the second terminal of the storage sub-circuit 11 is coupled to the second terminal of the driving sub-circuit 10 catch;
  • the first reset sub-circuit 12 is respectively coupled to the first reset signal input terminal, the reference signal input terminal and the control terminal of the driving sub-circuit 10;
  • the data writing sub-circuit 13 is respectively coupled to the scan signal input terminal, the data signal input terminal and the control terminal of the driving sub-circuit 10; and,
  • At least two light-emitting control sub-circuits the at least two light-emitting control sub-circuits are in one-to-one correspondence with the at least two light-emitting elements, and the at least two light-emitting control sub-circuits are in one-to-one correspondence with at least two control signal output terminals;
  • Each of the light-emitting control sub-circuits is respectively coupled to the second end of the driving sub-circuit 10, the corresponding control signal output end and the corresponding light-emitting element; each of the light-emitting control sub-circuits is used for the corresponding control signal Under the control of the output terminal, the connection between the second terminal of the driving sub-circuit 10 and the corresponding light-emitting element is controlled to be turned on or off.
  • the at least two light-emitting elements include a first light-emitting element EL1 and a second light-emitting element EL2; the at least two control signal output ends include a first control signal output end and a second control signal output end;
  • the at least two lighting control sub-circuits include a first lighting control sub-circuit 15 and a second lighting control sub-circuit 16;
  • the first light-emitting control sub-circuit 15 is respectively coupled to the second end of the driving sub-circuit 10, and the first control signal output end is coupled to the first light-emitting element EL1; Under the control of the output terminal, the connection between the second terminal of the driving sub-circuit 10 and the first light-emitting element EL1 is controlled to be turned on or off;
  • the second light-emitting control sub-circuit 16 is respectively coupled to the second end of the driving sub-circuit 10, and the second control signal output end is coupled to the second light-emitting element EL2; Under the control of the output terminal, the connection between the second terminal of the driving sub-circuit 10 and the second light-emitting element EL2 is controlled to be turned on or off.
  • the first light-emitting control sub-circuit 15 includes a first transistor T1, the gate of the first transistor T1 is coupled to the first control signal output terminal, the The first electrode of the first transistor T1 is coupled to the second end of the driving sub-circuit 10 , and the second electrode of the first transistor T1 is coupled to the first light emitting element EL1 .
  • the second lighting control sub-circuit 16 includes a second transistor T2, the gate of the second transistor T2 is coupled to the second control signal output terminal, the The first electrode of the second transistor T2 is coupled to the second end of the driving sub-circuit 10, and the second electrode of the second transistor T2 is coupled to the second light emitting element EL2.
  • the driving sub-circuit 10 includes a driving transistor DTFT, and a first electrode of the driving transistor DTFT is coupled to the first level signal input terminal;
  • the storage sub-circuit 11 includes a storage capacitor Cst, the first plate Cst1 of the storage capacitor Cst is coupled to the gate of the driving transistor DTFT, and the second plate Cst2 of the storage capacitor Cst is connected to the driving transistor.
  • the second pole of the DTFT is coupled;
  • the first reset sub-circuit 12 includes a third transistor T3, the gate of the third transistor T3 is coupled to the first reset signal input terminal, and the first electrode of the third transistor T3 is connected to the reference signal the input terminal is coupled, and the second pole of the third transistor T3 is coupled to the gate of the driving transistor DTFT;
  • the data writing sub-circuit 13 includes a fourth transistor T4, the gate of the fourth transistor T4 is coupled to the scan signal input terminal, and the first pole of the fourth transistor T4 is coupled to the data signal input terminal The second electrode of the fourth transistor T4 is coupled to the gate of the driving transistor DTFT.
  • the pixel driving circuit further includes:
  • the second reset sub-circuit 14 is respectively coupled to the second reset signal input end, the initialization signal input end and the second end of the driving sub-circuit 10; under the control of the second reset signal input end, the control leads Turn on or off the connection between the input terminal of the initialization signal and the second terminal of the driving sub-circuit 10 .
  • the second reset sub-circuit 14 includes a fifth transistor T5, the gate of the fifth transistor T5 is coupled to the second reset signal input terminal, the first The first electrode of the fifth transistor T5 is coupled to the input terminal of the initialization signal, and the second electrode of the fifth transistor T5 is coupled to the second end of the driving sub-circuit 10 .
  • Embodiments of the present disclosure also provide a driving method for a pixel driving circuit, wherein, for driving the pixel driving circuit provided in the above-mentioned embodiments, the driving method includes:
  • At least two control signal output ends respectively control the corresponding at least two light-emitting control sub-circuits, so that each light-emitting control sub-circuit controls to turn on or off the second end of the driving sub-circuit 10 and the corresponding light-emitting control sub-circuits. connections between components.
  • the at least two light-emitting elements include a first light-emitting element EL1 and a second light-emitting element EL2; the at least two control signal output ends include a first control signal output end and a second control signal output end; the The at least two lighting control sub-circuits include a first lighting control sub-circuit 15 and a second lighting control sub-circuit 16;
  • the first light-emitting control sub-circuit 15 controls the connection between the second end of the driving sub-circuit 10 and the first light-emitting element EL1 under the control of the first control signal output end under the control of the second control signal output end
  • the second light-emitting control sub-circuit 16 controls to disconnect the connection between the second end of the driving sub-circuit 10 and the second light-emitting element EL2;
  • the first light-emitting control sub-circuit 15 controls to disconnect the connection between the second end of the driving sub-circuit 10 and the first light-emitting element EL1
  • the second light-emitting control sub-circuit 16 controls the connection between the second end of the driving sub-circuit 10 and the second light-emitting element EL2.

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Abstract

提供了一种显示基板、显示装置。显示基板中多个子像素划分为多个子像素组，子像素组包括至少两个子像素，至少两个子像素复用同一个像素驱动电路，像素驱动电路中的至少两个发光控制子电路（15，16）与至少两个子像素中包括的至少两个发光元件（EL1，EL2）对应，至少两个发光控制子电路（15，16）与至少两条发光控制信号线（34，35）对应，每个发光控制子电路（15，16）分别与补偿驱动子电路的输出端，对应的发光元件（EL1，EL2）和对应的发光控制信号线（34，35）耦接；每个发光控制子电路（15，16）用于在对应的发光控制信号线（34，35）的控制下，控制导通或断开补偿驱动子电路的输出端和对应的发光元件（EL1，EL2）之间的连接。

Description

一种显示基板、显示装置
相关申请的交叉引用
本申请主张在2020年11月24日在中国提交的中国专利申请号No.202011329916.3的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板、显示装置。
背景技术
有机发光二极管(英文：Organic Light-Emitting Diode，简称：OLED)显示装置以其亮度高、功耗低、响应快、清晰度高、柔性好和发光效率高等优点被广泛应用在各个领域。
OLED显示装置包括多个子像素，每个子像素均包括像素驱动电路和发光元件，像素驱动电路用于驱动发光元件发光。由于OLED显示装置中的全部像素驱动电路呈阵列分布在基底，因此，受制于线宽、线距及过孔大小等因素，在一定区域内，布局像素驱动电路的数量受限，从而导致难以实现高分辨率的OLED显示装置。
发明内容
本公开的目的在于提供一种显示基板、显示装置。
为了实现上述目的，本公开提供如下技术方案：
本公开的第一方面提供一种显示基板，包括基底和设置于所述基底上的多个子像素，每个子像素均包括发光元件；
所述多个子像素划分为多个子像素组，所述子像素组包括至少两个子像素，所述至少两个子像素复用同一个像素驱动电路，所述像素驱动电路包括：
至少两条发光控制信号线，每条所述发光控制信号线的至少部分沿第一方向延伸，至少两条发光控制信号线沿第二方向排列，所述第二方向与所述第一方向相交；
补偿驱动子电路，所述补偿驱动子电路的输出端用于输出驱动信号；
至少两个发光控制子电路，所述至少两个发光控制子电路与所述至少两个子像素中包括的至少两个发光元件对应，所述至少两个发光控制子电路与所述至少两条发光控制信号线对应，每个所述发光控制子电路分别与所述补偿驱动子电路的输出端，对应的发光元件和对应的发光控制信号线耦接；每个所述发光控制子电路用于在对应的发光控制信号线的控制下，控制导通或断开所述补偿驱动子电路的输出端和对应的发光元件之间的连接。
可选的，所述像素驱动电路还包括：
基准信号线，所述基准信号线的至少部分沿第一方向延伸；
第一复位信号线，所述第一复位信号线的至少部分沿第一方向延伸；
栅线，所述栅线的至少部分沿所述第一方向延伸；
电源线，所述电源线的至少部分沿第二方向延伸；以及，
数据线，所述数据线的至少部分沿所述第二方向延伸；
所述补偿驱动子电路包括：
驱动子电路，所述驱动子电路的第一端与所述电源线耦接，所述驱动子电路的第二端作为所述补偿驱动子电路的输出端；
存储子电路，所述存储子电路的第一端与所述驱动子电路的控制端耦接，所述存储子电路的第二端与所述驱动子电路的第二端耦接；
第一复位子电路，分别与第一复位信号线，基准信号线和所述驱动子电路的控制端耦接；
数据写入子电路，分别与栅线，数据线和所述驱动子电路的控制端耦接。
可选的，所述至少两条发光控制信号线包括第一发光控制信号线和第二发光控制信号线；所述至少两个发光控制子电路包括第一发光控制子电路和第二发光控制子电路；所述至少两个发光元件包括第一发光元件和第二发光元件；
所述第一发光控制子电路分别与所述驱动子电路的第二端，所述第一发光控制信号线和所述第一发光元件耦接；所述第二发光控制子电路分别与所述驱动子电路的第二端，所述第二发光控制信号线和所述第二发光元件耦接。
可选的，所述第一发光控制子电路包括第一晶体管，所述第二发光控制 子电路包括第二晶体管，所述驱动子电路包括驱动晶体管；所述存储子电路包括存储电容；
所述驱动晶体管的栅极复用为所述存储电容的第一极板；
所述存储电容的第二极板位于所述第一极板背向所述基底的一侧，所述第二极板与所述驱动晶体管的第二极耦接；
所述第一晶体管的第一极与所述驱动晶体管的第二极耦接，所述第一晶体管的第二极与第一发光元件耦接；
所述第二晶体管的第一极与所述第二极板耦接，所述第二晶体管的第二极与所述第二发光元件耦接。
可选的，所述第一晶体管包括第一有源图形，所述第一有源图形沿所述第二方向延伸；所述第一有源图形的第一端与所述驱动晶体管的第二极耦接；所述第一有源图形的第二端与所述第一发光元件耦接；
所述第一有源图形的第二端在所述基底上的正投影，位于所述第一发光控制信号线在所述基底上的正投影和所述第二发光控制信号线在所述基底上的正投影之间。
可选的，所述第二极板包括主体部和延伸部；
所述主体部在所述基底上的正投影与所述驱动晶体管的栅极在所述基底上的正投影至少部分交叠；
所述延伸部沿所述第二方向延伸，所述延伸部在所述基底上的正投影，分别与所述第一发光控制信号线在所述基底上的正投影和所述第二发光控制信号线在所述基底上的正投影交叠。
可选的，所述第二晶体管包括第二有源图形，所述第二有源图形的至少部分沿所述第二方向延伸，所述第二有源图形的第一端与所述延伸部耦接，所述第二有源图形的第二端与所述第二发光元件耦接；
所述第二有源图形的第一端在所述基底上的正投影，位于所述第一发光控制信号线在所述基底上的正投影和所述第二发光控制信号线在所述基底上的正投影之间。
可选的，所述像素驱动电路还包括：
初始化信号线，所述初始化信号线的至少部分沿所述第一方向延伸；
第二复位信号线，所述第二复位信号线的至少部分沿所述第一方向延伸；所述第一复位信号线，所述栅线，所述第一发光控制信号线，所述第二发光控制信号线和所述第二复位信号线沿所述第二方向依次排列；
第二复位子电路，分别与第二复位信号线，初始化信号线和所述延伸部耦接。
可选的，所述第二复位子电路包括第五晶体管，所述第五晶体管包括第五有源图形，所述第五有源图形沿所述第二方向延伸；
所述第五有源图形的第一端与所述延伸部耦接，所述第五有源图形的第一端在所述基底上的正投影，位于所述第二发光控制信号线在所述基底上的正投影和所述第二复位信号线在所述基底上的正投影之间。
可选的，所述第五有源图形与所述初始化信号线形成为一体结构。
可选的，所述第一复位信号线在所述基底上的正投影，位于所述基准信号线在所述基底上的正投影和所述栅线在所述基底上的正投影之间；
所述第一复位子电路包括第三晶体管，所述第三晶体管包括第三有源图形，所述第三有源图形沿所述第二方向延伸，所述第三有源图形的第一端与所述基准信号线耦接，所述第三有源图形的第二端在所述基底上的正投影，位于所述第一复位信号线在所述基底上的正投影和所述栅线在所述基底上的正投影之间。
可选的，所述栅线包括栅主体部和两个栅突出部，所述栅主体部沿所述第一方向延伸，所述两个栅突出部沿所述第一方向间隔设置，所述两个栅突出部位于所述栅主体部和所述第一复位信号线之间；
所述数据写入子电路包括第四晶体管，所述第四晶体管包括第四有源图形，所述第四有源图形沿第一方向延伸，所述第四有源图形在所述基底上的正投影，分别与两个栅突出部在所述基底上的正投影交叠；
所述第四有源图形的第一端与所述数据线耦接，所述第四有源图形的第二端与所述第三有源图形的第二端耦接。
可选的，所述像素驱动电路包括导电连接部，所述导电连接部的至少部分沿所述第二方向延伸，所述导电连接部在所述基底上的正投影与所述栅线在所述基底上的正投影交叠；
所述导电连接部的第一端与所述第三有源图形的第二端耦接，所述导电连接部的第二端与所述驱动子电路的控制端耦接。
基于上述显示基板的技术方案，本公开的第二方面提供一种显示装置，包括上述显示基板。
可选的，所述显示基板中至少两条发光控制信号线包括第一发光控制信号线和第二发光控制信号线；至少两个发光控制子电路包括第一发光控制子电路和第二发光控制子电路；至少两个发光元件包括第一发光元件和第二发光元件；
所述显示基板中的多个子像素组中包括的多个像素驱动电路呈阵列分布，所述多个像素驱动电路划分为沿所述第二方向排列的多行像素驱动电路，每行像素驱动电路中的第一发光控制信号线依次耦接，每行像素驱动电路中的第二发光控制信号线依次耦接；
所述显示装置还包括：位于显示基板的周边区域的栅极驱动电路，所述栅极驱动电路包括多个第一移位寄存器单元和多个第二移位寄存器单元；所述多个第一移位寄存器单元与所述多行像素驱动电路一一对应，所述多个第二移位寄存器单元与所述多行像素驱动电路一一对应；
所述第一移位寄存器单元的输出端与对应的一行像素驱动电路中的第一发光控制信号线耦接，所述第二移位寄存器单元的输出端与对应的一行像素驱动电路中的第二发光控制信号线耦接。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为本公开实施例提供的像素驱动电路的布局示意图；
图2为图1中有源层的示意图；
图3为图1中第一栅金属层的示意图；
图4为图1中第二栅金属层的示意图；
图5为图1中第一源漏金属层的示意图；
图6为本公开实施例提供的像素驱动电路的第一基本结构图；
图7为本公开实施例提供的像素驱动电路的第一具体结构图；
图8为本公开实施例提供的像素驱动电路的第二基本结构图；
图9为本公开实施例提供的像素驱动电路的第二具体结构图；
图10为本公开实施例提供的一帧显示时间内像素驱动电路的工作时序图；
图11为本公开实施例提供的信号写入时段内的工作时序图；
图12为本公开实施例提供的栅极驱动电路的示意图。
具体实施方式
为了进一步说明本公开实施例提供的显示基板、显示装置，下面结合说明书附图进行详细描述。
本公开实施例提供了一种显示基板，包括基底和设置于所述基底上的多个子像素，每个子像素均包括发光元件；
所述多个子像素划分为多个子像素组，所述子像素组包括至少两个子像素，所述至少两个子像素复用同一个像素驱动电路，所述像素驱动电路包括：
至少两条发光控制信号线，每条所述发光控制信号线的至少部分沿第一方向延伸，至少两条发光控制信号线沿第二方向排列，所述第二方向与所述第一方向相交；
补偿驱动子电路，所述补偿驱动子电路的输出端用于输出驱动信号；
至少两个发光控制子电路，所述至少两个发光控制子电路与所述至少两个子像素中包括的至少两个发光元件对应，所述至少两个发光控制子电路与所述至少两条发光控制信号线对应，每个所述发光控制子电路分别与所述补偿驱动子电路的输出端，对应的发光元件和对应的发光控制信号线耦接；每个所述发光控制子电路用于在对应的发光控制信号线的控制下，控制导通或断开所述补偿驱动子电路的输出端和对应的发光元件之间的连接。
示例性的，所述至少两个发光控制子电路与所述至少两个子像素中包括的至少两个发光元件一一对应，所述至少两个发光控制子电路与所述至少两 条发光控制信号线一一对应。
示例性的，所述发光元件包括相对设置的阳极和阴极，以及位于所述阳极和所述阴极之间的有机发光材料层。
示例性的，每个子像素组中包括沿所述第一方向相邻的至少两个子像素。
示例性的，每个子像素组中包括沿所述第二方向相邻的至少两个子像素。
示例性的，每个子像素组中包括多个子像素，所述多个子像素包括沿所述第一方向相邻的子像素和沿所述第二方向相邻的子像素。
示例性的，所述子像素组中包括的各子像素复用同一个像素驱动电路。
示例性的，所述第一方向包括水平方向，所述第二方向包括竖直方向。
示例性的，所述补偿驱动子电路用于产生驱动发光元件发光的电流信号。
示例性的，在同一时段，在所述至少两条发光控制信号线的控制下，所述至少两个发光控制子电路中，仅有一个发光控制子电路能够控制导通所述补偿驱动子电路的输出端和对应的发光元件之间的连接，其余发光控制子电路均控制断开所述补偿驱动子电路的输出端和对应的发光元件之间的连接。
示例性的，在同一时段，在所述至少两条发光控制信号线的控制下，所述至少两个发光控制子电路中，有多个发光控制子电路能够控制导通所述补偿驱动子电路的输出端和对应的发光元件之间的连接。
根据上述显示基板的具体结构可知，本公开实施例提供的显示基板中，至少两个子像素能够复用一个像素驱动电路，且该像素驱动电路能够独立控制所述至少两个子像素中各子像素包括的发光元件独立发光或同时发光，因此，本公开实施例提供的显示基板，能够在布局有限数量的像素驱动电路的情况下，实现高分辨率的显示。
如图1～图6、图8所示，在一些实施例中，所述像素驱动电路还包括：
基准信号线31，所述基准信号线31的至少部分沿第一方向延伸；
第一复位信号线32，所述第一复位信号线32的至少部分沿第一方向延伸；
栅线33，所述栅线33的至少部分沿所述第一方向延伸；
电源线38，所述电源线38的至少部分沿第二方向延伸；以及，
数据线39，所述数据线39的至少部分沿所述第二方向延伸；
所述补偿驱动子电路包括：
驱动子电路10，所述驱动子电路10的第一端与所述电源线38耦接，所述驱动子电路10的第二端作为所述补偿驱动子电路的输出端；
存储子电路11，所述存储子电路11的第一端与所述驱动子电路10的控制端耦接，所述存储子电路11的第二端与所述驱动子电路10的第二端耦接；
第一复位子电路12，分别与第一复位信号线32，基准信号线31和所述驱动子电路10的控制端耦接；
数据写入子电路13，分别与栅线33，数据线39和所述驱动子电路10的控制端耦接。
示例性的，所述基准信号线31用于提供基准信号Vref，该基准信号Vref为直流信号。
示例性的，所述基准信号线31在所述基底上的正投影，所述第一复位信号线32在所述基底上的正投影以及所述栅线33在所述基底上的正投影沿所述第二方向依次排列。
示例性的，所述电源线38与所述数据线39沿所述第一方向排列。
示例性的，所述电源线38与所述数据线39同层同材料设置。
示例性的，所示电源线38提供正电源信号ELVDD，发光元件的阴极接收负电源信号ELVSS。
示例性的，所述第一复位子电路12与所述驱动子电路10沿所述第二方向排列。
示例性的，所述驱动子电路10在所述基底上的正投影，所述存储子电路11在所述基底上的正投影，以及所述第一复位子电路12在所述基底上的正投影，均位于所述电源线38在所述基底上的正投影与所述数据线39在所述基底上的正投影之间。
如图1～图6、图8所示，在一些实施例中，所述至少两条发光控制信号线包括第一发光控制信号线34和第二发光控制信号线35；所述至少两个发光控制子电路包括第一发光控制子电路15和第二发光控制子电路16；所述至少两个发光元件包括第一发光元件EL1和第二发光元件EL2；
所述第一发光控制子电路15分别与所述驱动子电路10的第二端，所述 第一发光控制信号线34和所述第一发光元件EL1耦接；所述第二发光控制子电路16分别与所述驱动子电路10的第二端，所述第二发光控制信号线35和所述第二发光元件EL2耦接。
示例性的，所述第一发光控制信号线34和所述第二发光控制信号线35均沿所述第一方向延伸，所述第一发光控制信号线34和所述第二发光控制信号线35沿所述第二方向排列。
示例性的，所述第一发光元件EL1的有机发光材料层和所述第二发光元件EL2的有机发光材料层沿所述第一方向排列；或者所述第一发光元件EL1的有机发光材料层和所述第二发光元件EL2的有机发光材料层沿所述第二方向排列。
所述第一发光控制子电路15能够在所述第一发光控制信号线34的控制下，控制导通或断开所述驱动子电路10的第二端与所述第一发光元件EL1之间的连接。所述第二发光控制子电路16能够在所述第二发光控制信号线35的控制下，控制导通或断开所述驱动子电路10的第二端与所述第二发光元件EL2之间的连接。
示例性的，在同一显示时段，所述第一发光控制子电路15控制导通所述驱动子电路10的第二端与对应的第一发光元件EL1之间的连接，所述第二发光控制子电路16控制导通所述驱动子电路10的第二端与对应的第一发光元件EL1之间的连接。
示例性的，如图10所示，将一帧显示时间分为前半帧和后半帧，所述前半帧和所述后半帧均包括信号写入时段P11和发光时段P12。在前半帧中的信号写入时段，所述补偿驱动子电路完成对应第一发光元件EL1的灰阶写入和补偿的过程。在前半帧中的发光时段，在第一发光控制信号线34的控制下，所述第一发光控制子电路15控制导通所述补偿驱动子电路的输出端与对应的第一发光元件EL1之间的连接，使所述第一发光元件EL1发光；在第二发光控制信号线35的控制下，所述第二发光控制子电路16控制断开所述补偿驱动子电路的输出端与对应的第二发光元件EL2之间的连接，使所述第二发光元件EL2不发光。
在后半帧中的信号写入时段，所述补偿驱动子电路完成对应第二发光元 件EL2的灰阶写入和补偿的过程。在后半帧中的发光时段，在第一发光控制信号线34的控制下，所述第一发光控制子电路15控制断开所述补偿驱动子电路的输出端与对应的第一发光元件EL1之间的连接，使所述第一发光元件EL1不发光；在第二发光控制信号线35的控制下，所述第二发光控制子电路16控制导通所述补偿驱动子电路的输出端与对应的第二发光元件EL2之间的连接，使所述第二发光元件EL2发光。
需要说明，当每个子像素组包括N个子像素时，N为大于或等于2的整数，可以将每一帧显示时间划分为N个子帧，在每个子帧对对应的发光元件实现灰阶写入，补偿和显示的过程。在将每一帧显示时间划分为N个子帧时，每个子帧对应的灰阶写入和信号补偿过孔能够实现互不干扰，从而实现对N个发光元件的独立控制。
上述实施例提供的显示基板中，N个子像素可以共用一个像素驱动电路，实现各子像素的分时显示或同时显示，避免了每个像素都设置独立的像素驱动电路，从而很好的提高了显示基板中像素驱动电路的布局空间利用率。
如图1～图5、图7和图9所示，在一些实施例中，所述第一发光控制子电路15包括第一晶体管T1，所述第二发光控制子电路16包括第二晶体管T2，所述驱动子电路10包括驱动晶体管DTFT；所述存储子电路11包括存储电容Cst；
所述驱动晶体管DTFT的栅极g复用为所述存储电容Cst的第一极板Cst1；
所述存储电容Cst的第二极板Cst2位于所述第一极板Cst1背向所述基底的一侧，所述第二极板Cst2与所述驱动晶体管DTFT的第二极耦接；
所述第一晶体管T1的第一极与所述驱动晶体管DTFT的第二极耦接，所述第一晶体管T1的第二极与第一发光元件EL1耦接；
所述第二晶体管T2的第一极与所述第二极板Cst2耦接，所述第二晶体管T2的第二极与所述第二发光元件EL2耦接。
示例性的，如图2所示，所述驱动晶体管DTFT包括驱动有源图形56，所述驱动有源图形56包括沿所述第一方向延伸的部分和沿所述第二方向延伸的部分，所述驱动有源图形56在所述基底上的正投影与所述驱动晶体管 DTFT的栅极在所述基底上的正投影部分交叠，所述驱动有源图形56的第一端作为所述驱动晶体管DTFT的第一极，所述驱动有源图形56的第二端作为驱动晶体管DTFT的第二极，所述驱动有源图形56的第一端在所述基底上的正投影与所述电源线38在所述基底上的正投影交叠，在该交叠处，所述驱动有源图形56的第一端与所述电源线38通过第一过孔21耦接，所述驱动有源图形56的第二端与所述第一晶体管T1的第一极耦接。
示例性的，所述驱动有源图形56的第二端在所述基底上的正投影与所述第二极板Cst2在所述基底上的正投影交叠，在该交叠处，所述驱动有源图形56的第二端与所述第二极板Cst2通过第二过孔22耦接。
如图1、图2、图7和图9所示，在一些实施例中，所述第一晶体管T1包括第一有源图形51，所述第一有源图形51沿所述第二方向延伸；所述第一有源图形51的第一端与所述驱动晶体管DTFT的第二极耦接；所述第一有源图形51的第二端与所述第一发光元件EL1耦接；
所述第一有源图形51的第二端在所述基底上的正投影，位于所述第一发光控制信号线34在所述基底上的正投影和所述第二发光控制信号线35在所述基底上的正投影之间。
示例性的，所述第一有源图形51沿所述第二方向延伸，所述第一有源图形51在所述基底上的正投影与所述第一发光控制信号线34在所述基底上的正投影部分交叠，所述第一发光控制信号线34复用为所述第一晶体管T1的栅极，所述第一有源图形51的第一端作为所述第一晶体管T1的第一极，所述第一有源图形51的第二端作为所述第一晶体管T1的第二极。
示例性的，所述第一有源图形51的第一端和第二端均不与所述第一发光控制信号34线交叠。
示例性的，所述第一有源图形51的第一端与所述驱动有源图形56的第二端形成为一体结构。
示例性的，所述第一有源图形51的第二端通过第三过孔23与所述第一发光元件EL1的阳极耦接。
如图1、图3、图4所示，在一些实施例中，所述第二极板Cst2包括主体部Cst21和延伸部Cst22；
所述主体部Cst21在所述基底上的正投影与所述驱动晶体管DTFT的栅极在所述基底上的正投影至少部分交叠；
所述延伸部Cst22沿所述第二方向延伸，所述延伸部Cst22在所述基底上的正投影，分别与所述第一发光控制信号线34在所述基底上的正投影和所述第二发光控制信号线35在所述基底上的正投影交叠。
示例性的，所述主体部和所述延伸部Cst22形成为一体结构。
示例性的，所述主体部为块状，所述延伸部Cst22为条状。
示例性的，所述驱动有源图形56的第二端在所述基底上的正投影与所述主体部Cst21在所述基底上的正投影交叠，在该交叠处，所述驱动有源图形56的第二端与所述主体部Cst21通过第二过孔22耦接。
示例性的，所述延伸部Cst22远离所述主体部的一端在所述基底上的正投影，位于所述第二发光控制信号线35在所述基底上的正投影和第二复位信号线36在所述基底上的正投影之间。
如图1、图2、图4所示，在一些实施例中，所述第二晶体管T2包括第二有源图形52，所述第二有源图形52的至少部分沿所述第二方向延伸，所述第二有源图形52的第一端与所述延伸部Cst22耦接，所述第二有源图形52的第二端与所述第二发光元件EL2耦接；
所述第二有源图形52的第一端在所述基底上的正投影，位于所述第一发光控制信号线34在所述基底上的正投影和所述第二发光控制信号线35在所述基底上的正投影之间。
示例性的，所述第二有源图形52呈
Figure PCTCN2021092096-appb-000001
形。
示例性的，所述第二有源图形52包括一体结构的第一部分和第二部分，所述第一部分沿所述第二方向延伸，所述第二部分沿所述第一方向延伸，所述第一部分在所述基底上的正投影与所述第二发光控制信号线35在所述基底上的正投影部分交叠。
示例性的，所述第二有源图形52的第一端作为所述第二晶体管T2的第一极，所述第二有源图形52的第二端作为所述第二晶体管T2的第二极。所述第二有源图形52的第一端在所述基底上的正投影，与所述延伸部Cst22在所述基底上的正投影交叠，在该交叠处，所述第二有源图形52的第一端与所 述延伸部Cst22通过第四过孔24耦接。所述第二有源图形52的第二端与所述第二发光元件EL2的阳极通过第五过孔25耦接。
示例性的，所述第二有源图形52的第二端在所述基底上的正投影，位于所述第二发光控制信号线35在所述基底上的正投影和第二复位信号线36在所述基底上的正投影之间。
如图1～图3、图6和图8所示，在一些实施例中，所述像素驱动电路还包括：
初始化信号线37，所述初始化信号线37的至少部分沿所述第一方向延伸；
第二复位信号线36，所述第二复位信号线36的至少部分沿所述第一方向延伸；所述第一复位信号线32，所述栅线33，所述第一发光控制信号线34，所述第二发光控制信号线35和所述第二复位信号线36沿所述第二方向依次排列；
第二复位子电路14，分别与第二复位信号线36，初始化信号线37和所述延伸部Cst22耦接。
示例性的，所述初始化信号线37用于提供具有固定电位的基准信号Vref。
示例性的，所述初始化信号线37与各晶体管中的有源图形同层同材料设置。
示例性的，所述初始化信号线37与所述栅线33同层同材料设置。
示例性的，所述初始化信号线37与存储电容Cst的第二极板Cst2同层同材料设置。
示例性的，所述第二复位信号线36在所述基底上的正投影，位于所述第二发光控制信号线35在所述基底上的正投影和所述初始化信号线37在所述基底上的正投影之间。
所述第二复位子电路14能够在所述第二复位信号线36的控制下，控制导通或断开所述初始化信号线37与所述延伸部Cst22之间的连接。
如图1～图3、图7和图9所示，在一些实施例中，所述第二复位子电路14包括第五晶体管T5，所述第五晶体管T5包括第五有源图形55，所述第五有源图形55沿所述第二方向延伸；
所述第五有源图形55的第一端与所述延伸部Cst22耦接，所述第五有源图形55的第一端在所述基底上的正投影，位于所述第二发光控制信号线35在所述基底上的正投影和所述第二复位信号线36在所述基底上的正投影之间。
示例性的，所述第五有源图形55在所述基底上的正投影与所述第二复位信号线36在所述基底上的正投影交叠，所述第五有源图形55的第一端作为所述第五晶体管T5的第二极，所述第五有源图形55的第二端作为所述第五晶体管T5的第一极。
示例性的，所述第五有源图形55的第一端在所述基底上的正投影与所述延伸部Cst22在所述基底上的正投影交叠，在该交叠处，所述第五有源图形55的第一端与所述延伸部Cst22通过第六过孔26耦接。
如图2所示，在一些实施例中，设置所述第五有源图形55与所述初始化信号线37形成为一体结构。
上述设置方式使得所述第五有源图形55与所述初始化信号线37能够在同一次构图工艺中形成，有效简化了显示基板的制作流程，降低了制作成本。
如图1～图3、图7和图9所示，在一些实施例中，所述第一复位信号线32在所述基底上的正投影，位于所述基准信号线31在所述基底上的正投影和所述栅线33在所述基底上的正投影之间；
所述第一复位子电路12包括第三晶体管T3，所述第三晶体管T3包括第三有源图形53，所述第三有源图形53沿所述第二方向延伸，所述第三有源图形53的第一端与所述基准信号线31耦接，所述第三有源图形53的第二端在所述基底上的正投影，位于所述第一复位信号线32在所述基底上的正投影和所述栅线33在所述基底上的正投影之间。
示例性的，所述第三有源图形53在所述基底上的正投影与所述第一复位信号线32在所述基底上的正投影部分交叠。所述第三有源图形53的第一端作为所述第三晶体管T3的第一极，所述第三有源图形53的第二端作为所述第三晶体管T3的第二极，所述第三有源图形53的第一端在所述基底上的正投影，与所述基准信号线31在所述基底上的正投影交叠，在该交叠处，所述第三有源图形53的第一端与所述基准信号线31通过第七过孔27耦接。
如图1～图3、图7和图9所示，在一些实施例中，所述栅线33包括栅主体部331和两个栅突出部332，所述栅主体部331沿所述第一方向延伸，所述两个栅突出部332沿所述第一方向间隔设置，所述两个栅突出部332位于所述栅主体部331和所述第一复位信号线32之间；
所述数据写入子电路13包括第四晶体管T4，所述第四晶体管T4包括第四有源图形54，所述第四有源图形54沿第一方向延伸，所述第四有源图形54在所述基底上的正投影，分别与两个栅突出部332在所述基底上的正投影交叠；
所述第四有源图形54的第一端与所述数据线39耦接，所述第四有源图形54的第二端与所述第三有源图形53的第二端耦接。
示例性的，所述栅主体部331和所述两个栅突出部332形成为一体结构。
示例性的，所述栅突出部332沿所述第二方向延伸。
示例性的，所述两个栅突出部332在所述基底上的正投影，位于所述栅主体部331在所述基底上的正投影和所述第一复位信号线32在所述基底上的正投影之间。
示例性的，所述两个栅突出部332复用为所述第四晶体管T4的栅极，所述第四晶体管T4为双栅结构。
示例性的，所述第四晶体管T4也可以形成为普通的只有一个栅极的结构。
示例性的，所述第四有源图形54的第一端作为所述第四晶体管T4的第一极，所述第四有源图形54的第二端作为所述第四晶体管T4的第二极。
示例性的，所述第四有源图形54的第一端在所述基底上的正投影与所述数据线39在所述基底上的正投影交叠，在该交叠处，所述第四有源图形54的第一端与所述数据线39通过第八过孔28耦接。
示例性的，所述第四有源图形54的第二端与所述第三有源图形53的第二端形成为一体结构。
示例性的，所述第三有源图形53和所述第四有源图形54共同形成为L形。
需要说明，所述第一晶体管T1、所述第二晶体管T2、所述第三晶体管 T3、所述第四晶体管T4、所述第五晶体管T5和所述驱动晶体管DTFT的具体类型多种多样，示例性的，均选用NMOS晶体管。
当所述像素驱动电路包括：所述第一晶体管T1、所述第二晶体管T2、所述第三晶体管T3、所述第四晶体管T4、所述第五晶体管T5和所述驱动晶体管DTFT时，如图11所示，所述像素驱动电路在信号写入时段的工作过程如下：
在所述信号写入时段的P111阶段，在所述第一复位信号线32写入的第一复位信号G1的控制下，第三晶体管T3导通，向驱动晶体管DTFT的栅极(即g点)写入基准信号Vref；在所述第二复位信号线36写入的第二复位信号G2的控制下，第五晶体管T5导通，向驱动晶体管DTFT的源极(即s点)写入初始化信号Vint。
在所述信号写入时段的P112阶段，基准信号Vref的电压高于初始化信号Vint的电压，驱动晶体管DTFT导通，s点电压上升，当s点电压上升到Vref-Vth时，Vth位驱动晶体管DTFT的阈值电压，驱动晶体管DTFT的Vgs-Vth＝0，Vgs为驱动晶体管DTFT的栅极和源极之间的电压差值，从而驱动晶体管DTFT截止。
在所述信号写入时段的P113阶段，在栅线33写入的扫描信号G3的控制下，第四晶体管T4导通，将数据线39传输的数据信号DA写入g点，由于存储电容Cst和OLED本身固有电容Coled的耦合作用，s点电压变化为Vref-Vth+a(Vdata-Vref)，其中a＝C1/(C1+Coled)，C1为存储电容Cst的容值，Vdata为数据信号DA的电压值。流经驱动晶体管DTFT的最终驱动电流为I＝k*(Vgs-Vth)^2＝k*[(1-a)*(Vdata-Vref)]^2，驱动电流大小与Vth无关，从而实现Vth的补偿。
如图1和图5所示，在一些实施例中，所述像素驱动电路包括导电连接部40，所述导电连接部40的至少部分沿所述第二方向延伸，所述导电连接部40在所述基底上的正投影与所述栅线33在所述基底上的正投影部分交叠；
所述导电连接部40的第一端与所述第三有源图形53的第二端耦接，所述导电连接部40的第二端与所述驱动子电路10的控制端耦接。
示例性的，所述导电连接部40的第一端在所述基底上的正投影与第三有 源图形53的第二端在所述基底上的正投影交叠，在该交叠处，所述导电连接部40的第一端与第三有源图形53的第二端通过第九过孔29耦接。所述导电连接部40的第二端在所述基底上的正投影与所述驱动晶体管DTFT的栅极在所述基底上的正投影交叠，所述导电连接部40的第二端与所述驱动晶体管DTFT的栅极通过第十过孔20耦接。
示例性的，所述导电连接部40在所述基底上的正投影与所述第二极板Cst2在所述基底上的正投影不交叠。
需要说明，所述显示基板包括沿远离所述基底的方向，依次层叠设置的有源层、第一栅绝缘层、第一栅金属层、第二栅绝缘层、第二栅金属层、层间绝缘层、第一源漏金属层和平坦层等。
示例性的，所述有源层用于形成各晶体管包括的有源图形，初始化信号线37；所述第一栅金属层用于形成所述第一复位信号线32，所述栅极，所述第一发光控制信号线34、所述第二发光控制信号线35和所述第二复位信号线36；所述第二栅金属层用于形成所述基准信号线31，所述第二极板Cst2和一些导电连接部40；所述第一源漏金属层用于形成所述电源线38，所述数据线39和一些导电连接部40。
需要说明，所述第一过孔21至所述第十过孔20能够贯穿一层或多层膜层。
所述第一晶体管T1的第二极和所述第二晶体管T2的第二极，可以通过由所述第二栅金属层和所述第一源漏金属层形成的连接部(如标记41和42)，以及对应的过孔，与对应的发光元件的阳极耦接。
上述实施例提供的显示基板中，在采用上述布局方式时，能够有效利用布局空间，实现显示基板的分辨率最大化。
本公开实施还提供了一种显示装置，包括上述实施例提供的显示基板。
上述施例提供的显示基板中，至少两个子像素能够复用一个像素驱动电路，且该像素驱动电路能够独立控制所述至少两个子像素中各子像素包括的发光元件独立发光或同时发光，因此，上述实施例提供的显示基板，能够在布局有限数量的像素驱动电路的情况下，实现高分辨率的显示。
本公开实施例提供的显示装置在包括上述显示基板时同样具有上述有益 效果，此处不再赘述。
需要说明的是，所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。
在一些实施例中，所述显示基板中至少两条发光控制信号线包括第一发光控制信号线34和第二发光控制信号线35；至少两个发光控制子电路包括第一发光控制子电路15和第二发光控制子电路16；至少两个发光元件包括第一发光元件EL1和第二发光元件EL2；
所述显示基板中的多个子像素组中包括的多个像素驱动电路呈阵列分布，所述多个像素驱动电路划分为沿所述第二方向排列的多行像素驱动电路，每行像素驱动电路中的第一发光控制信号线34依次耦接，每行像素驱动电路中的第二发光控制信号线35依次耦接；
所述显示装置还包括：位于显示基板的周边区域的栅极驱动电路，所述栅极驱动电路包括多个第一移位寄存器单元和多个第二移位寄存器单元；所述多个第一移位寄存器单元与所述多行像素驱动电路一一对应，所述多个第二移位寄存器单元与所述多行像素驱动电路一一对应；
所述第一移位寄存器单元的输出端与对应的一行像素驱动电路中的第一发光控制信号线34耦接，所述第二移位寄存器单元的输出端与对应的一行像素驱动电路中的第二发光控制信号线35耦接。
示例性的，所述显示基板中，多个子像素组中包括多个像素驱动电路呈阵列分布，所述多个像素驱动电路能够划分为多行像素驱动电路和多列像素驱动电路。
所述多行像素驱动电路沿所述第二方向依次排列，每行像素驱动电路均包括沿所述第一方向排列的多个像素驱动电路。所述多列像素驱动电路沿所述第一方向依次排列，每列像素驱动电路均包括沿所述第二方向排列的多个像素驱动电路。
在同一行像素驱动电路中，所述基准信号线31依次耦接形成为一体结构，所述第一复位信号线32依次耦接形成为一体结构，所述栅线33依次耦接形成为一体结构，所述第一发光控制信号线34依次耦接形成为一体结构，所述第二发光控制信号线35依次耦接形成为一体结构，所述第二复位信号线 36依次耦接形成为一体结构，所述初始化信号线37依次耦接形成为一体结构。
在同一列像素驱动电路中，所述电源线38依次耦接形成为一体结构，所述数据线39依次耦接形成为一体结构。
如图12所示，示例性的，所述栅极驱动电路包括多个第一移位寄存器单元EM1GOA和多个第二移位寄存器单元EM2GOA；所述多个第一移位寄存器单元与所述多行像素驱动电路一一对应，所述多个第二移位寄存器单元与所述多行像素驱动电路一一对应；所述第一移位寄存器单元的输出端与对应的一行像素驱动电路中的第一发光控制信号线34耦接，所述第二移位寄存器单元的输出端与对应的一行像素驱动电路中的第二发光控制信号线35耦接。
示例性的，所述栅极驱动电路包括多个第三移位寄存器单元G3GOA，所述多个第三移位寄存器单元与所述多行像素驱动电路一一对应，所述第三移位寄存器单元的输出端与对应的一行像素驱动电路中的栅线33耦接。
示例性的，所述栅极驱动电路包括多个第四移位寄存器单元G1GOA，所述多个第四移位寄存器单元与所述多行像素驱动电路一一对应，所述第四移位寄存器单元的输出端与对应的一行像素驱动电路中的第一复位信号线32耦接。
示例性的，所述栅极驱动电路包括多个第五移位寄存器单元G2GOA，所述多个第五移位寄存器单元与所述多行像素驱动电路一一对应，所述第五移位寄存器单元的输出端与对应的一行像素驱动电路中的第二复位信号线36耦接。
示例性的，对应一行像素驱动电路的一种移位寄存器单元可以设置在显示基板的一侧，即实现单侧驱动；或者对应一行像素驱动电路的一种移位寄存器单元也可以设置在显示基板相对的两侧，即实现双侧驱动。
示例性的，所述栅极驱动电路包括N个第一移位寄存器单元EM1GOA，所述N个第一移位寄存器单元EM1GOA级联，即第N-1个第一移位寄存器单元EM1GOA的输出端与对应的一行像素驱动电路中的第一发光控制信号线34耦接，第N-1个第一移位寄存器单元EM1GOA的输出端还同时与第N个第一移位寄存器单元EM1GOA的输入信号端耦接，第N-1个第一移位寄 存器单元EM1GOA同时向对应的一行像素驱动电路中的第一发光控制信号线34，以及第N个第一移位寄存器单元EM1GOA的输入信号端写入第一发光控制信号。
同样的，所述多个第二移位寄存器单元EM2GOA，所述多个第三移位寄存器单元G3GOA，多个第四移位寄存器单元G1GOA，多个第五移位寄存器单元G2GOA也均满足上述级联关系，此处不再赘述。
如图6所示，本公开实施例还提供了一种像素驱动电路，用于驱动至少两个发光元件发光，所述像素驱动电路包括：
驱动子电路10，所述驱动子电路10的第一端与第一电平信号输入端耦接；
存储子电路11，所述存储子电路11的第一端与所述驱动子电路10的控制端耦接，所述存储子电路11的第二端与所述驱动子电路10的第二端耦接；
第一复位子电路12，分别与第一复位信号输入端，基准信号输入端和所述驱动子电路10的控制端耦接；
数据写入子电路13，分别与扫描信号输入端，数据信号输入端和所述驱动子电路10的控制端耦接；以及，
至少两个发光控制子电路，所述至少两个发光控制子电路与所述至少两个发光元件一一对应，所述至少两个发光控制子电路与至少两个控制信号输出端一一对应；每个所述发光控制子电路分别与所述驱动子电路10的第二端，对应的控制信号输出端和对应的发光元件耦接；每个所述发光控制子电路用于在对应的控制信号输出端的控制下，控制导通或断开所述驱动子电路10的第二端与对应的发光元件之间的连接。
在一些实施例中，所述至少两个发光元件包括第一发光元件EL1和第二发光元件EL2；所述至少两个控制信号输出端包括第一控制信号输出端和第二控制信号输出端；所述至少两个发光控制子电路包括第一发光控制子电路15和第二发光控制子电路16；
所述第一发光控制子电路15分别与所述驱动子电路10的第二端，所述第一控制信号输出端和所述第一发光元件EL1耦接；用于在所述第一控制信号输出端的控制下，控制导通或断开所述驱动子电路10的第二端与所述第一 发光元件EL1之间的连接；
所述第二发光控制子电路16分别与所述驱动子电路10的第二端，所述第二控制信号输出端和所述第二发光元件EL2耦接；用于在所述第二控制信号输出端的控制下，控制导通或断开所述驱动子电路10的第二端与所述第二发光元件EL2之间的连接。
如图7所示，在一些实施例中，所述第一发光控制子电路15包括第一晶体管T1，所述第一晶体管T1的栅极与所述第一控制信号输出端耦接，所述第一晶体管T1的第一极与所述驱动子电路10的第二端耦接，所述第一晶体管T1的第二极与所述第一发光元件EL1耦接。
如图7所示，在一些实施例中，所述第二发光控制子电路16包括第二晶体管T2，所述第二晶体管T2的栅极与所述第二控制信号输出端耦接，所述第二晶体管T2的第一极与所述驱动子电路10的第二端耦接，所述第二晶体管T2的第二极与所述第二发光元件EL2耦接。
如图7所示，在一些实施例中，所述驱动子电路10包括驱动晶体管DTFT，所述驱动晶体管DTFT的第一极与所述第一电平信号输入端耦接；
所述存储子电路11包括存储电容Cst，所述存储电容Cst的第一极板Cst1与所述驱动晶体管DTFT的栅极耦接，所述存储电容Cst的第二极板Cst2与所述驱动晶体管DTFT的第二极耦接；
所述第一复位子电路12包括第三晶体管T3，所述第三晶体管T3的栅极与所述第一复位信号输入端耦接，所述第三晶体管T3的第一极与所述基准信号输入端耦接，所述第三晶体管T3的第二极与所述驱动晶体管DTFT的栅极耦接；
所述数据写入子电路13包括第四晶体管T4，所述第四晶体管T4的栅极与所述扫描信号输入端耦接，所述第四晶体管T4的第一极与所述数据信号输入端耦接，所述第四晶体管T4的第二极与所述驱动晶体管DTFT的栅极耦接。
如图8所示，在一些实施例中，所述像素驱动电路还包括：
第二复位子电路14，分别与第二复位信号输入端，初始化信号输入端和所述驱动子电路10的第二端耦接；用于在所述第二复位信号输入端的控制下，控制导通或断开所述初始化信号输入端与所述驱动子电路10的第二端之 间的连接。
如图9所示，在一些实施例中，所述第二复位子电路14包括第五晶体管T5，所述第五晶体管T5的栅极与所述第二复位信号输入端耦接，所述第五晶体管T5的第一极与所述初始化信号输入端耦接，所述第五晶体管T5的第二极与所述驱动子电路10的第二端耦接。
本公开实施例还提供了一种像素驱动电路的驱动方法，其中，用于驱动上述实施例提供的像素驱动电路，所述驱动方法包括：
在发光阶段，至少两个控制信号输出端分别控制对应的至少两个发光控制子电路，以使各发光控制子电路控制导通或断开所述驱动子电路10的第二端与对应的发光元件之间的连接。
在一些实施例中，至少两个发光元件包括第一发光元件EL1和第二发光元件EL2；所述至少两个控制信号输出端包括第一控制信号输出端和第二控制信号输出端；所述至少两个发光控制子电路包括第一发光控制子电路15和第二发光控制子电路16；
在第一发光阶段，所述第一发光控制子电路15在所述第一控制信号输出端的控制下，控制导通所述驱动子电路10的第二端与所述第一发光元件EL1之间的连接；所述第二发光控制子电路16在所述第二控制信号输出端的控制下，控制断开所述驱动子电路10的第二端与所述第二发光元件EL2之间的连接；
在第二发光阶段，所述第一发光控制子电路15在所述第一控制信号输出端的控制下，控制断开所述驱动子电路10的第二端与所述第一发光元件EL1之间的连接；所述第二发光控制子电路16在所述第二控制信号输出端的控制下，控制导通所述驱动子电路10的第二端与所述第二发光元件EL2之间的连接。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属 领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”、“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种显示基板，包括基底和设置于所述基底上的多个子像素，每个子像素均包括发光元件；
    所述多个子像素划分为多个子像素组，所述子像素组包括至少两个子像素，所述至少两个子像素复用同一个像素驱动电路，所述像素驱动电路包括：
    至少两条发光控制信号线，每条所述发光控制信号线的至少部分沿第一方向延伸，至少两条发光控制信号线沿第二方向排列，所述第二方向与所述第一方向相交；
    补偿驱动子电路，所述补偿驱动子电路的输出端用于输出驱动信号；
    至少两个发光控制子电路，所述至少两个发光控制子电路与所述至少两个子像素中包括的至少两个发光元件对应，所述至少两个发光控制子电路与所述至少两条发光控制信号线对应，每个所述发光控制子电路分别与所述补偿驱动子电路的输出端，对应的发光元件和对应的发光控制信号线耦接；每个所述发光控制子电路用于在对应的发光控制信号线的控制下，控制导通或断开所述补偿驱动子电路的输出端和对应的发光元件之间的连接。
  2. 根据权利要求1所述的显示基板，其中，所述像素驱动电路还包括：
    基准信号线，所述基准信号线的至少部分沿第一方向延伸；
    第一复位信号线，所述第一复位信号线的至少部分沿第一方向延伸；
    栅线，所述栅线的至少部分沿所述第一方向延伸；
    电源线，所述电源线的至少部分沿第二方向延伸；以及，
    数据线，所述数据线的至少部分沿所述第二方向延伸；
    所述补偿驱动子电路包括：
    驱动子电路，所述驱动子电路的第一端与所述电源线耦接，所述驱动子电路的第二端作为所述补偿驱动子电路的输出端；
    存储子电路，所述存储子电路的第一端与所述驱动子电路的控制端耦接，所述存储子电路的第二端与所述驱动子电路的第二端耦接；
    第一复位子电路，分别与第一复位信号线，基准信号线和所述驱动子电路的控制端耦接；
    数据写入子电路，分别与栅线，数据线和所述驱动子电路的控制端耦接。
  3. 根据权利要求2所述的显示基板，其中，所述至少两条发光控制信号线包括第一发光控制信号线和第二发光控制信号线；所述至少两个发光控制子电路包括第一发光控制子电路和第二发光控制子电路；所述至少两个发光元件包括第一发光元件和第二发光元件；
    所述第一发光控制子电路分别与所述驱动子电路的第二端，所述第一发光控制信号线和所述第一发光元件耦接；所述第二发光控制子电路分别与所述驱动子电路的第二端，所述第二发光控制信号线和所述第二发光元件耦接。
  4. 根据权利要求3所述的显示基板，其中，所述第一发光控制子电路包括第一晶体管，所述第二发光控制子电路包括第二晶体管，所述驱动子电路包括驱动晶体管；所述存储子电路包括存储电容；
    所述驱动晶体管的栅极复用为所述存储电容的第一极板；
    所述存储电容的第二极板位于所述第一极板背向所述基底的一侧，所述第二极板与所述驱动晶体管的第二极耦接；
    所述第一晶体管的第一极与所述驱动晶体管的第二极耦接，所述第一晶体管的第二极与第一发光元件耦接；
    所述第二晶体管的第一极与所述第二极板耦接，所述第二晶体管的第二极与所述第二发光元件耦接。
  5. 根据权利要求4所述的显示基板，其中，所述第一晶体管包括第一有源图形，所述第一有源图形沿所述第二方向延伸；所述第一有源图形的第一端与所述驱动晶体管的第二极耦接；所述第一有源图形的第二端与所述第一发光元件耦接；
    所述第一有源图形的第二端在所述基底上的正投影，位于所述第一发光控制信号线在所述基底上的正投影和所述第二发光控制信号线在所述基底上的正投影之间。
  6. 根据权利要求4所述的显示基板，其中，所述第二极板包括主体部和延伸部；
    所述主体部在所述基底上的正投影与所述驱动晶体管的栅极在所述基底上的正投影至少部分交叠；
    所述延伸部沿所述第二方向延伸，所述延伸部在所述基底上的正投影，分别与所述第一发光控制信号线在所述基底上的正投影和所述第二发光控制信号线在所述基底上的正投影交叠。
  7. 根据权利要求6所述的显示基板，其中，所述第二晶体管包括第二有源图形，所述第二有源图形的至少部分沿所述第二方向延伸，所述第二有源图形的第一端与所述延伸部耦接，所述第二有源图形的第二端与所述第二发光元件耦接；
    所述第二有源图形的第一端在所述基底上的正投影，位于所述第一发光控制信号线在所述基底上的正投影和所述第二发光控制信号线在所述基底上的正投影之间。
  8. 根据权利要求6所述的显示基板，其中，所述像素驱动电路还包括：
    初始化信号线，所述初始化信号线的至少部分沿所述第一方向延伸；
    第二复位信号线，所述第二复位信号线的至少部分沿所述第一方向延伸；所述第一复位信号线，所述栅线，所述第一发光控制信号线，所述第二发光控制信号线和所述第二复位信号线沿所述第二方向依次排列；
    第二复位子电路，分别与第二复位信号线，初始化信号线和所述延伸部耦接。
  9. 根据权利要求8所述的显示基板，其中，所述第二复位子电路包括第五晶体管，所述第五晶体管包括第五有源图形，所述第五有源图形沿所述第二方向延伸；
    所述第五有源图形的第一端与所述延伸部耦接，所述第五有源图形的第一端在所述基底上的正投影，位于所述第二发光控制信号线在所述基底上的正投影和所述第二复位信号线在所述基底上的正投影之间。
  10. 根据权利要求9所述的显示基板，其中，所述第五有源图形与所述初始化信号线形成为一体结构。
  11. 根据权利要求2所述的显示基板，其中，所述第一复位信号线在所述基底上的正投影，位于所述基准信号线在所述基底上的正投影和所述栅线在所述基底上的正投影之间；
    所述第一复位子电路包括第三晶体管，所述第三晶体管包括第三有源图 形，所述第三有源图形沿所述第二方向延伸，所述第三有源图形的第一端与所述基准信号线耦接，所述第三有源图形的第二端在所述基底上的正投影，位于所述第一复位信号线在所述基底上的正投影和所述栅线在所述基底上的正投影之间。
  12. 根据权利要求11所述的显示基板，其中，所述栅线包括栅主体部和两个栅突出部，所述栅主体部沿所述第一方向延伸，所述两个栅突出部沿所述第一方向间隔设置，所述两个栅突出部位于所述栅主体部和所述第一复位信号线之间；
    所述数据写入子电路包括第四晶体管，所述第四晶体管包括第四有源图形，所述第四有源图形沿第一方向延伸，所述第四有源图形在所述基底上的正投影，分别与两个栅突出部在所述基底上的正投影交叠；
    所述第四有源图形的第一端与所述数据线耦接，所述第四有源图形的第二端与所述第三有源图形的第二端耦接。
  13. 根据权利要求12所述的显示基板，其中，所述像素驱动电路包括导电连接部，所述导电连接部的至少部分沿所述第二方向延伸，所述导电连接部在所述基底上的正投影与所述栅线在所述基底上的正投影交叠；
    所述导电连接部的第一端与所述第三有源图形的第二端耦接，所述导电连接部的第二端与所述驱动子电路的控制端耦接。
  14. 一种显示装置，包括如权利要求1～13中任一项所述的显示基板。
  15. 根据权利要求14所述的显示装置，其中，所述显示基板中至少两条发光控制信号线包括第一发光控制信号线和第二发光控制信号线；至少两个发光控制子电路包括第一发光控制子电路和第二发光控制子电路；至少两个发光元件包括第一发光元件和第二发光元件；
    所述显示基板中的多个子像素组中包括的多个像素驱动电路呈阵列分布，所述多个像素驱动电路划分为沿所述第二方向排列的多行像素驱动电路，每行像素驱动电路中的第一发光控制信号线依次耦接，每行像素驱动电路中的第二发光控制信号线依次耦接；
    所述显示装置还包括：位于显示基板的周边区域的栅极驱动电路，所述栅极驱动电路包括多个第一移位寄存器单元和多个第二移位寄存器单元；所 述多个第一移位寄存器单元与所述多行像素驱动电路一一对应，所述多个第二移位寄存器单元与所述多行像素驱动电路一一对应；
    所述第一移位寄存器单元的输出端与对应的一行像素驱动电路中的第一发光控制信号线耦接，所述第二移位寄存器单元的输出端与对应的一行像素驱动电路中的第二发光控制信号线耦接。
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