WO2022100756A1 - 一种芯片端口状态检测电路、芯片及通信终端 - Google Patents

一种芯片端口状态检测电路、芯片及通信终端 Download PDF

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WO2022100756A1
WO2022100756A1 PCT/CN2021/130951 CN2021130951W WO2022100756A1 WO 2022100756 A1 WO2022100756 A1 WO 2022100756A1 CN 2021130951 W CN2021130951 W CN 2021130951W WO 2022100756 A1 WO2022100756 A1 WO 2022100756A1
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pmos transistor
twenty
nmos transistor
drain
transistor
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PCT/CN2021/130951
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English (en)
French (fr)
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王永寿
高晨阳
林升
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上海唯捷创芯电子技术有限公司
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Priority to JP2023529971A priority Critical patent/JP2023549413A/ja
Priority to KR1020237020352A priority patent/KR20230117734A/ko
Priority to EP21891276.4A priority patent/EP4246156A1/en
Publication of WO2022100756A1 publication Critical patent/WO2022100756A1/zh
Priority to US18/318,040 priority patent/US20230288500A1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/66—Testing of connections, e.g. of plugs or non-disconnectable joints
    • G01R31/68—Testing of releasable connections, e.g. of terminals mounted on a printed circuit board
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31703—Comparison aspects, e.g. signature analysis, comparators
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R15/00—Details of measuring arrangements of the types provided for in groups G01R17/00 - G01R29/00, G01R33/00 - G01R33/26 or G01R35/00
    • G01R15/04—Voltage dividers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/145—Indicating the presence of current or voltage
    • G01R19/155—Indicating the presence of voltage
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16566—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533
    • G01R19/16576—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533 comparing DC or AC voltage with one threshold
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
    • G01R19/257—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques using analogue/digital converters of the type with comparison of different reference values with the value of voltage or current, e.g. using step-by-step method
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31704—Design for test; Design verification
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31713—Input or output interfaces for test, e.g. test pins, buffers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31718—Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31721—Power aspects, e.g. power supplies for test circuits, power saving during test
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
    • H04W88/02—Terminal devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the invention relates to a chip port state detection circuit, and also relates to an integrated circuit chip including the chip port state detection circuit and a corresponding communication terminal, belonging to the technical field of integrated circuits.
  • multiple identical chips are usually distinguished by detecting the state of a port or ports of a chip, and then outputting different chip IDs according to different port states to provide identification to corresponding communication terminals.
  • the port of each chip includes three states, namely the pull-up state, the pull-down state and the floating state. Since the communication terminal identification chip is the first operation on the chip, and the chip port status may change during the application process, the detection of the chip port status needs to be fast, low power consumption and real-time detection.
  • the primary technical problem to be solved by the present invention is to provide a chip port state detection circuit.
  • Another technical problem to be solved by the present invention is to provide a chip including a chip port state detection circuit and a corresponding communication terminal.
  • the present invention adopts the following technical scheme:
  • a chip port state detection circuit including a port detection conversion circuit, a reference voltage generation circuit, a first comparator, a second comparator, a dynamic bias current generation circuit, and a chip ID judgment circuit; the port detection conversion circuit, the reference voltage generation circuit and the dynamic bias current generation circuit are respectively connected to the first comparator and the second comparator, the first comparator and the first comparator Two comparators are respectively connected to the chip ID judgment circuit;
  • the port detection conversion circuit is connected to the port to be detected of the chip, so as to convert the state of the to-be-detected port into a corresponding voltage, which are respectively output to the first comparator and the second comparator; the first comparison The second comparator receives the input reference voltage provided by the reference voltage generation circuit, compares the voltage output by the port detection conversion circuit with the input reference voltage, and outputs the output to the chip ID judgment circuit A logic signal, the chip ID judging circuit outputs the chip ID corresponding to the state of the port to be detected according to the logic signal, so as to distinguish multiple identical chips.
  • the port detection and conversion circuit includes, but is not limited to, a first resistor and a second resistor; the first resistor and the second resistor are connected in series, and the connection between the first resistor and the second resistor is The connection point is connected to the port to be detected on the chip.
  • the reference voltage generating circuit includes but is not limited to a third resistor, a fourth resistor and a fifth resistor; the third resistor, the fourth resistor and the fifth resistor are connected in series, the third resistor The resistor, the fourth resistor, and the fifth resistor divide the power supply voltage to obtain a high-potential reference voltage and a low-potential reference voltage, respectively.
  • the first comparator includes a first comparison unit and a first shaping driving unit, and the first comparison unit is connected to the first shaping driving unit;
  • the second comparator includes a second comparison unit and a second shaping driving unit, and the second comparison unit is connected to the second shaping driving unit.
  • the first comparison unit includes but is not limited to a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, a fourth NMOS tube, a fifth PMOS tube and a sixth PMOS tube;
  • the gate of the first NMOS tube is connected to the high-potential reference voltage output end of the reference voltage generating circuit;
  • the drain of the first NMOS tube, the The drain of the first PMOS transistor, the gate of the second PMOS transistor, the drain and gate of the third PMOS transistor, and the gate of the fourth PMOS transistor are connected to each other;
  • the gate of the NMOS transistor is connected to the port detection conversion circuit; the drain of the second NMOS transistor, the drain of the second PMOS transistor, the gate of the first PMOS transistor, and the drain of the fifth PMOS transistor
  • the drain and the gate and the gate of the sixth PMOS transistor are connected to each other; the sources of the
  • the second comparison unit includes but is not limited to the thirteenth PMOS transistor, the fourteenth PMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, the twelfth NMOS transistor, the The fifteenth PMOS tube, the sixteenth PMOS tube, the thirteenth NMOS tube and the fourteenth NMOS tube; the gate of the fourteenth PMOS tube is connected to the low-potential reference voltage output end of the reference voltage generating circuit; the The drain of the fourteenth PMOS transistor, the drain of the tenth NMOS transistor, the gate of the ninth NMOS transistor, the drain and gate of the thirteenth NMOS transistor, and the fourteenth NMOS transistor. The gates of the thirteenth PMOS transistors are connected to each other; the gate of the thirteenth PMOS transistor is connected to the port detection conversion circuit; the drain of the thirteenth PMOS transistor, the drain of the ninth NMOS transistor, the drain of the The gate of the ten NMOS transistors, the drain and gate of the eleventh
  • the source of the transistor is respectively connected to the second current bias terminal of the dynamic bias current generating circuit; the drain of the twelfth NMOS transistor, the drain and gate of the fifteenth PMOS transistor and the The gates of the sixteen PMOS transistors are connected to each other; the drain of the sixteenth PMOS transistor, the drain of the fourteenth NMOS transistor and the input end of the second shaping driving unit are connected to each other; The source electrodes of the fifteenth PMOS transistor and the sixteenth PMOS transistor are respectively connected to the power supply voltage, the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, and the twelfth NMOS transistor The source electrodes of the transistor, the thirteenth NMOS transistor and the fourteenth NMOS transistor are respectively grounded.
  • the dynamic bias current generating circuit includes a start-up unit, the low-power consumption and low-current generation unit, and the low-voltage and high-current generation unit; the start-up unit is connected to the low-power consumption and low-current generation unit ; The low power consumption and small current generating unit is connected with the low voltage and high current generating unit.
  • the low power consumption and small current generation unit includes a self-bias current generation module, a current mirror module and a switch enabling module; the self-bias current generation module is respectively connected to the startup unit and the current mirror module, the current mirror module is connected to the switch enabling module.
  • the self-bias current generating module includes a twentieth NMOS transistor, a twenty-first NMOS transistor, a sixth resistor, a twentieth PMOS transistor, a twenty-first PMOS transistor, and a twenty-second PMOS transistor.
  • the drain of the twentieth NMOS transistor is respectively connected to one end of the sixth resistor, the gate of the twenty-first NMOS transistor and the start-up unit; the gate of the twentieth NMOS transistor, the gate of the twentieth NMOS transistor, the The other end of the six resistors, the drain of the twentieth PMOS transistor, and the current mirror module are connected to each other, the gate of the twentieth PMOS transistor, the startup unit, and the twenty-first PMOS.
  • the gate and drain of the transistor, the drain of the twenty-second PMOS transistor, the drain of the twenty-first NMOS transistor, and the current mirror module are connected to each other, and the twentieth PMOS transistor,
  • the twenty-second PMOS transistor, the twenty-first PMOS transistor, and the source are respectively connected to a power supply voltage, and the sources of the twentieth NMOS transistor and the twenty-first NMOS transistor are grounded respectively.
  • the low-voltage and high-current generating unit includes a twenty-fifth PMOS transistor, a twenty-sixth PMOS transistor, a twenty-sixth PMOS transistor, a twenty-fourth NMOS transistor, a twenty-fifth NMOS transistor, and a twenty-fifth NMOS transistor.
  • the drain of the twenty-fifth PMOS transistor is connected to the drain of the twenty-fourth PMOS transistor, the gate of the twenty-fifth PMOS transistor, the second The gate and drain of the sixteen PMOS transistors and the drain of the twenty-fifth NMOS transistor are connected to each other, the gate of the twenty-fifth NMOS transistor, the gate of the twenty-sixth NMOS transistor and the drain, the gate of the twenty-fourth NMOS transistor, and one end of the seventh resistor are connected to each other, and the drain of the twenty-fourth NMOS transistor is connected to the drain of the twenty-third NMOS transistor.
  • the other end of the seventh resistor is connected to the drain of the twenty-sixth PMOS transistor, the twenty-fifth PMOS transistor, the twenty-sixth PMOS transistor, the twenty-sixth PMOS transistor.
  • the sources are respectively connected to the power supply voltage, and the sources of the twenty-fourth NMOS transistor and the twenty-fifth NMOS transistor are respectively grounded.
  • an integrated circuit chip including the above-mentioned chip port state detection circuit.
  • a communication terminal including the above-mentioned chip port state detection circuit.
  • the state of the port to be detected is converted into a corresponding voltage through the port detection conversion circuit, and output to the first comparator and the second comparator respectively and the corresponding voltage.
  • a logic signal is output to the chip ID judgment circuit to obtain the chip ID corresponding to the state of the port to be detected of the chip, so that the communication terminal can identify the chip and distinguish multiple identical chips.
  • the dynamic bias current generating circuit provides the first comparator and the second comparator with a bias current and a static operating point respectively from the start of the establishment of the power supply voltage to before the establishment of the power supply voltage is completed and after the establishment of the power supply voltage is completed.
  • the state of the to-be-detected port of the chip is detected, which satisfies the requirement of fast detection of the to-be-detected port of the chip, and can meet the requirements of static low power consumption and real-time detection of the chip port state detection circuit.
  • FIG. 1 is a schematic block diagram of a chip port state detection circuit provided by an embodiment of the present invention.
  • FIGS. 2a to 2c are respectively circuit diagrams of an embodiment of a port detection conversion circuit in a chip port state detection circuit provided by an embodiment of the present invention
  • FIG. 3 is a circuit diagram of an embodiment of a reference voltage generating circuit in a chip port state detection circuit provided by an embodiment of the present invention
  • 4a is a circuit diagram of an embodiment of a first comparator in a chip port state detection circuit provided by an embodiment of the present invention
  • 4b is a circuit diagram of an embodiment of a second comparator in a chip port state detection circuit provided by an embodiment of the present invention
  • FIG. 5 is a circuit diagram of an embodiment of a dynamic bias current generating circuit in a chip port state detection circuit provided by an embodiment of the present invention.
  • an embodiment of the present invention provides a chip port state detection circuit, including a port detection conversion circuit 101, a reference voltage generation circuit 102, a first comparator 103, a second comparator 104, a dynamic bias current
  • the generation circuit 105, the chip ID judgment circuit 108, the port detection conversion circuit 101, the reference voltage generation circuit 102 and the dynamic bias current generation circuit 105 are respectively connected to the first comparator 103 and the second comparator 104, the first comparator 103 and the The two comparators 104 are respectively connected to the chip ID judging circuit 108 .
  • the port detection conversion circuit 101 is connected to the port to be detected of the chip to convert the state of the port to be detected into a corresponding voltage, which are respectively output to the first comparator 103 and the second comparator 104, the first comparator 103, the second comparator
  • the device 104 uses the voltage VH and the voltage VL provided by the reference voltage generating circuit 102 as the input reference voltage, and after comparing the voltage output by the port detection conversion circuit 101 with the input reference voltage, it outputs a logic signal to the chip ID judgment circuit 108 .
  • the chip ID judging circuit outputs the chip ID corresponding to the state of the to-be-detected port of the chip, so that the communication terminal can identify the chip and distinguish multiple identical chips.
  • the port detection conversion circuit 101 is composed of a first resistor R1 and a second resistor R2 connected in series, but not limited thereto. Connect the port to be detected Vpin of the chip to the connection point between the first resistor R1 and the second resistor R2, the other end of the first resistor R1 is connected to the power supply voltage VDD, and the other end of the second resistor is connected to the ground.
  • the three states (pull-up state, pull-down state and floating state) of the to-be-detected port of the chip are converted into corresponding three different voltages through the voltage dividing action of the first resistor R1 and the second resistor R2.
  • the potential of the port to be detected Vpin in the floating state is obtained by dividing the power supply voltage VDD through the first resistor R1 and the second resistor R2, that is, Among them, appropriate resistance values of the first resistor R1 and the second resistor R2 need to be selected to compromise power consumption and layout area.
  • the reference voltage generating circuit 102 is composed of a third resistor R3 , a fourth resistor R4 and a fifth resistor R5 connected in series, but not limited thereto.
  • the third resistor R3, the fourth resistor R4 and the fifth resistor R5 divide the power supply voltage VDD to obtain a high-potential reference voltage VH and a low-potential reference voltage VL, respectively, and output them to the first comparator 103 and the second comparator correspondingly 104 as the input reference voltage.
  • the first comparator 103 includes a first comparison unit 1030 and a first shaping driving unit 1031 , and the first comparison unit 1030 is connected to the first shaping driving unit 1031 .
  • the first comparison unit 1030 includes a first NMOS transistor 401, a second NMOS transistor 402, a first PMOS transistor 403, a second PMOS transistor 404, a third PMOS transistor 405, a fourth PMOS transistor 406, a third NMOS transistor 408, a fourth The NMOS transistor 410, the fifth PMOS transistor 411 and the sixth PMOS transistor 412, but not limited to this; the connection relationship between the parts of the first comparison unit 1030 is as follows: the gate of the first NMOS transistor 401 is connected to the reference voltage generating circuit 102 High potential reference voltage output terminal, the drain of the first NMOS transistor 401, the drain of the first PMOS transistor 403, the gate of the second PMOS transistor 404, the drain and gate of the third PMOS transistor 405, and the fourth PMOS transistor The gates of
  • the first current bias terminal Ibias_N, the drain of the fourth PMOS transistor 406, the drain and gate of the third NMOS transistor 408, and the gate of the fourth NMOS transistor 410 are connected to each other, and the drain of the fourth NMOS transistor 410 is connected to each other.
  • the drain of the sixth PMOS transistor 412 and the input terminal of the first shaping driving unit 1031 are connected to each other, the first PMOS transistor 403, the second PMOS transistor 404, the third PMOS transistor 405, the fourth PMOS transistor 406, the fifth
  • the sources of the PMOS transistor 411 and the sixth PMOS transistor 412 are respectively connected to the power supply voltage, and the sources of the third NMOS transistor 408 and the fourth NMOS transistor 410 are respectively grounded.
  • the working principle of the first comparator 103 is as follows: when the voltage corresponding to the state of the port Vpin to be detected and output by the port detection conversion circuit 101 received by the first comparator 103 is greater than the high-potential reference voltage VH provided by the reference voltage generation circuit 102, the current The current through the second NMOS transistor 402 is greater than the current of the first NMOS transistor 401, and the first PMOS transistor 403 is turned on, so that the drain voltage of the third PMOS transistor 405 is pulled up.
  • the third PMOS transistor 405 and the fourth PMOS transistor The transistor 406, the third NMOS transistor 408 and the fourth NMOS transistor 410 are in an off state, while the fifth PMOS transistor 411 and the sixth PMOS transistor 412 are in an on state, and after the eleventh PMOS transistor 415 and the seventh NMOS transistor 416, the first The inverters formed by the twelve PMOS transistors 417 and the eighth NMOS transistor 418 are connected in series to obtain the shaping driving effect of the first shaping driving unit 1031 , so that the first comparator 103 outputs a high level through the voltage output terminal Vout_A.
  • the current flowing through the second NMOS transistor 402 is smaller than the A current of the NMOS transistor 401, the second PMOS transistor 404 is turned on, and the drain voltage of the fifth PMOS transistor 411 is pulled up. At this time, the fifth PMOS transistor 411 and the sixth PMOS transistor 412 are in an off state, while the third PMOS transistor 412 is in an off state.
  • the shaping driving function of the first shaping driving unit 1031 is obtained by connecting the inverters formed respectively in series, so that the first comparator 103 outputs a low level through the voltage output terminal Vout_A.
  • the ninth PMOS transistor 407, the fifth PMOS transistor 411 and the sixth PMOS transistor 412 are connected between the gates of the third PMOS transistor 405 and the fourth PMOS transistor 406.
  • the tenth PMOS transistor 413 is connected between the gates
  • the fifth NMOS transistor 409 is connected between the gates of the third NMOS transistor 408 and the fourth NMOS transistor 410, the drains of the fourth NMOS transistor 410 and the sixth PMOS transistor 412 and the
  • the sixth NMOS transistor 414 is connected between the input ends of a shaping driving unit 1031; wherein, the ninth PMOS transistor 407, the tenth PMOS transistor 413, the fifth NMOS transistor 409 and the sixth NMOS transistor 414 are respectively used as enabling control transistors, through
  • the gate of each enable control transistor receives an enable control signal to control the functionality of the first comparator 103 to be turned on and off.
  • the second comparator 104 includes a second comparison unit 1040 and a second shaping driving unit 1041 , and the second comparison unit 1040 is connected to the second shaping driving unit 1041 .
  • the second comparison unit 1040 includes a thirteenth PMOS transistor 501, a fourteenth PMOS transistor 502, a ninth NMOS transistor 503, a tenth NMOS transistor 504, an eleventh NMOS transistor 505, a twelfth NMOS transistor 506, and a fifteenth PMOS transistor tube 508 , the sixteenth PMOS tube 510 , the thirteenth NMOS tube 511 and the fourteenth NMOS tube 513 , but not limited to this;
  • the connection relationship between the parts of the second comparison unit 1030 is as follows: The gate is connected to the low-potential reference voltage output terminal of the reference voltage generating circuit 102 , the drain of the fourteenth PMOS transistor 502 , the drain of the tenth NMOS transistor 504 , the gate of the ninth NMOS transistor 503 ,
  • the gates of the sixteen PMOS transistors 510 are connected to each other, the drain of the sixteenth PMOS transistor 510, the drain of the fourteenth NMOS transistor 513 and the input terminal of the second shaping driving unit 1041 are connected to each other.
  • the fifteenth The sources of the PMOS transistor 508 and the sixteenth PMOS transistor 510 are respectively connected to the power supply voltage, the ninth NMOS transistor 503 , the tenth NMOS transistor 504 , the eleventh NMOS transistor 505 , the twelfth NMOS transistor 506 , and the thirteenth NMOS transistor 511 and the source of the fourteenth NMOS transistor 513 are grounded respectively.
  • the working principle of the first comparator 103 is as follows: when the voltage corresponding to the state of the port Vpin to be detected and output by the port detection conversion circuit 101 received by the second comparator 104 is greater than the low-level reference voltage VL provided by the reference voltage generation circuit 102, the current The current passing through the fourteenth PMOS transistor 502 is greater than the current of the thirteenth PMOS transistor 501, and the ninth NMOS transistor 503 is turned on, so that the drain voltage of the eleventh NMOS transistor 505 is pulled up.
  • the eleventh NMOS transistor 505 , the twelfth NMOS transistor 506 , the fifteenth PMOS transistor 508 , and the sixteenth PMOS transistor 510 are in the off state, while the thirteenth NMOS transistor 511 and the fourteenth NMOS transistor 513 are in the on state, after the seventeenth PMOS transistor 515, the fifteenth NMOS transistor 516, the eighteenth PMOS transistor 517 and the sixteenth NMOS transistor 518, respectively, are connected in series to obtain the shaping driving effect of the second shaping driving unit 1041, so that the second comparator 104 passes The voltage output terminal Vout_B outputs a low level.
  • the current flowing through the fourteenth PMOS transistor 502 is less than The current of the thirteenth PMOS transistor 501, the tenth NMOS transistor 504 is turned on, and the drain voltage of the thirteenth NMOS transistor 511 is pulled up. At this time, the thirteenth NMOS transistor 511 and the fourteenth NMOS transistor 513 are in the off state.
  • the eleventh NMOS transistor 505 , the twelfth NMOS transistor 506 , the fifteenth PMOS transistor 508 , and the sixteenth PMOS transistor 510 are in a conducting state.
  • the inverters formed by the eight PMOS transistors 517 and the sixteenth NMOS transistor 518 are connected in series to obtain the shaping driving effect of the second shaping driving unit 1041, so that the second comparator 104 outputs a high level through the voltage output terminal Vout_B.
  • a nineteenth PMOS transistor 509 is connected between the gates of the fifteenth PMOS transistor 508 and the gates of the sixteenth PMOS transistor 510, the eleventh NMOS transistor 505 and the tenth
  • the seventeenth NMOS transistor 507 is connected between the gates of the two NMOS transistors 506, the eighteenth NMOS transistor 512 is connected between the gates of the thirteenth NMOS transistor 511 and the fourteenth NMOS transistor 513, and the sixteenth PMOS transistor 510 is connected to
  • the nineteenth NMOS transistor 514 is connected between the drain of the fourteenth NMOS transistor 513 and the input terminal of the second shaping driving unit 1041 .
  • the nineteenth PMOS transistor 509, the seventeenth NMOS transistor 507, the eighteenth NMOS transistor 512 and the nineteenth NMOS transistor 514 are respectively used as enable control transistors, and the enable control signals are received through the gates of the enable control transistors. , to control the functionality of the second comparator 104 to be turned on and off.
  • the first comparator 103 and the second comparator 104 output different logic signals, and the logic signals are the voltages of the first comparator 103 and the second comparator 104 High or low level output at the output.
  • the first comparator 103 When the port to be detected of the chip is in the pull-up state, the first comparator 103 outputs a high level, and the second comparator 104 outputs a low level; when the port to be detected of the chip is in a pull-down state, the first comparator 103 outputs Low level, the second comparator 104 outputs a high level; when the port to be detected of the chip is in a floating state, the first comparator 103 outputs a low level, and the second comparator 104 outputs a low level.
  • the different logic signals output by the first comparator 103 and the second comparator 104 are output to the chip ID judgment circuit 108, and the chip ID judgment circuit 108 is based on the pre-designed logic signals output by the first comparator 103 and the second comparator 104 and the chip ID.
  • the corresponding relationship between the IDs, the logic signals actually output by the first comparator 103 and the second comparator 104 are judged, and the chip ID of each chip applied to the same communication terminal is determined, so as to realize the chip port status and chip ID.
  • the chip ID includes but is not limited to a chip product ID, an operator ID, and the like.
  • the chip ID judging circuit 108 may be composed of several logical AND gates, logical NOT gates, logical OR gate circuits, and the like.
  • the port will correspond to three chip IDs, that is, three identical chips are allowed in the same application environment; then, if more identical chips are required in the same application environment, Then, the number of ports to be detected by the chip can be determined according to the number of required chips, and each port to be detected can be respectively connected to the port detection conversion circuit of the port state detection circuit of the chip. For example, if five identical chips are required in the same application environment, the chip needs to have two ports to be detected which are respectively connected to the port detection conversion circuit.
  • the dynamic bias current generating circuit 105 is used to provide bias current for the first comparator 103 and the second comparator 104, so that the first comparator 103 and the second comparator 104 can work normally.
  • the dynamic bias current generating circuit 105 includes a starting unit 1050, a low-power and low-current generating unit 1051, and a low-voltage and high-current generating unit 1052; the starting unit 1050 is connected to the low-power and low-current generating unit 1051, and the The low-consumption current generating unit 1051 is connected to the low-voltage high-current generating unit 1052 .
  • the low-power and low-current generating unit 1051 and the low-voltage and high-current generating unit 1052 respectively receive a high-level enable control signal
  • the low-power and low-current generating unit 1051 is in an on state
  • the low-voltage and high-current generating unit 1052 is in an off state , to provide bias current for the first comparator 103 and the second comparator 104 after the power supply voltage is established, so as to meet the requirements of the chip port state detection circuit for static low power consumption and real-time detection.
  • the low-voltage and high-current generating unit 1052 and the low-power and low-current generating unit 1051 respectively receive the low-level enable control signal, the low-voltage and high-current generating unit 1052 is in an on state, and the low-power and low-current generating unit 1051 is in an off state , provide bias current for the first comparator 103 and the second comparator 104 before the power supply voltage is established until the establishment is completed, so as to ensure that the detection of the port status to be detected of the chip is completed before the communication terminal recognizes the chip, and the detection of the status of the chip to be detected is satisfied Requirements for fast port detection.
  • the low power consumption and small current generation unit 1051 includes a self-bias current generation module 10510, a current mirror module 10511 and a switch enable module 10512; the self-bias current generation module 10510 is respectively connected to the startup unit 1050 and the current mirror module 10511, the current mirror module 10511 is connected to the switch enabling module 10512.
  • the self-bias current generating module 10510 includes a twentieth NMOS transistor 607 , a twenty-first NMOS transistor 609 , a sixth resistor 608 , a twentieth PMOS transistor 610 , a twenty-first PMOS transistor 611 , and a twenty-second PMOS transistor 612
  • the specific connection relationship is as follows: the drain of the twentieth NMOS tube 607 is respectively connected to one end of the sixth resistor 608, the gate of the twenty-first NMOS tube 609 and the start-up unit 1050, the gate of the twentieth NMOS tube 607, the The other end of the six resistors 608 , the drain of the twentieth PMOS transistor 610 and the current mirror module 10511 are connected to each other, the gate of the twentieth PMOS transistor 610 , the startup unit 1050 , and the gate of the twenty-first PMOS transistor 611 and the drain, the drain of the twenty-second PMOS transistor 612, the drain of the twenty-first NMOS transistor 609, and the current mirror module 105
  • the twenty-second PMOS transistor 610, the twenty-second PMOS transistor 612, The sources of the twenty-first PMOS transistors 611 and 611 are respectively connected to the power supply voltage, and the sources of the twenty-first NMOS transistor 607 and the twenty-first NMOS transistor 609 are respectively grounded.
  • the current mirror module 10511 includes a twenty-third PMOS transistor 613 and a twenty-second NMOS transistor 615 ; the gate of the twenty-third PMOS transistor 613 , the gate of the twentieth PMOS transistor 610 , and a start-up unit. 1050.
  • the gate and drain of the twenty-first PMOS transistor 611, the drain of the twenty-second PMOS transistor 612, and the drain of the twenty-first NMOS transistor 609 are connected to each other, and the twenty-third PMOS transistor 613 is connected to each other.
  • the drain is connected to the switch enabling module 10512 , the source of the twenty-third PMOS transistor 613 is connected to the power supply voltage, the gate of the twenty-second NMOS transistor 615 , the gate of the twentieth NMOS transistor 607 , and the other side of the sixth resistor 608 .
  • One end and the drain of the twentieth PMOS transistor 610 are connected to each other, the drain of the twenty-second NMOS transistor 615 is connected to the switch enabling module 10512 , and the source of the twenty-second NMOS transistor 615 is grounded.
  • the switch enabling module 10512 includes a twenty-fourth PMOS transistor 614 and a twenty-third NMOS transistor 616 ; the source of the twenty-fourth PMOS transistor 614 is connected to the drain of the twenty-third PMOS transistor 613 , The drain of the twenty-fourth PMOS transistor 614 is connected to the low-voltage and high-current generating unit 1052 to form the first current bias terminal Ibias_N of the dynamic bias current generating circuit 105, and the source of the twenty-third NMOS transistor 616 is connected to the twenty-third The drains of the two NMOS transistors 615 and the drain of the twenty-third NMOS transistor 616 are connected to the low-voltage and high-current generating unit 1052 to form the second current bias terminal Ibias_P of the dynamic bias current generating circuit 105 .
  • the low-voltage and high-current generating unit 1052 includes a twenty-fifth PMOS transistor 617 , a twenty-sixth PMOS transistor 618 , a twenty-sixth PMOS transistor 619 , a twenty-fourth NMOS transistor 620 , and a twenty-fifth NMOS transistor 620 .
  • the drain of the twenty-fifth PMOS transistor 617 is connected to the drain of the twenty-fourth PMOS transistor 614, the gate of the twenty-fifth PMOS transistor 617, the gate and the drain of the twenty-sixth PMOS transistor 618
  • the gate and the drain of the twenty-fifth NMOS transistor 621 are connected to each other, the gate of the twenty-fifth NMOS transistor 621, the gate and drain of the twenty-sixth NMOS transistor 622, and the gate of the twenty-fourth NMOS transistor 620
  • the gate and one end of the seventh resistor 623 are connected to each other, the drain of the twenty-fourth NMOS transistor 620 is connected to the drain of the twenty-third NMOS transistor 616, and the other end of the seventh resistor 623 is connected to the twenty-sixth PMOS transistor
  • the start-up unit 1050 is used to make the low-power consumption and low-current generating unit 1051 start normally, avoiding the degeneracy point to ensure that it is stable at the required output point.
  • the startup unit 1050 includes a twenty-seventh NMOS transistor 601 , a twenty-eighth NMOS transistor 602 , a twenty-ninth NMOS transistor 603 , a twenty-seventh PMOS transistor 605 , a twenty-eighth PMOS transistor 606 and an eighth resistor 604 .
  • the specific connections are as follows: the gate of the twenty-seventh NMOS transistor 601, the gate of the twenty-eighth NMOS transistor 602, the gate and drain of the twenty-ninth NMOS transistor 603, and one end of the eighth resistor 604 are connected to each other.
  • the drain of the twenty-seventh NMOS transistor 601 is connected to the source of the twenty-eighth NMOS transistor 602
  • the drain of the twenty-eighth NMOS transistor 602 is connected to the source of the twenty-ninth NMOS transistor 603
  • the other end of the eighth resistor 604 They are respectively connected to the drain of the twenty-seventh PMOS transistor 605, the gate of the twenty-eighth PMOS transistor 606, the gate of the twenty-seventh PMOS transistor 605, the gate of the twenty-third PMOS transistor 613, and the twenty-eighth PMOS transistor 613.
  • the gate of the transistor 610, the gate and drain of the twenty-first PMOS transistor 611, the drain of the twenty-second PMOS transistor 612, and the drain of the twenty-first NMOS transistor 609 are connected to each other, and the twenty-eighth
  • the drain of the PMOS transistor 606 is the drain of the twentieth NMOS transistor 607 , one end of the sixth resistor 608 , the gate of the twenty-first NMOS transistor 609 , the twenty-seventh PMOS transistor 605 and the twenty-eighth PMOS transistor 606 , respectively.
  • the sources of the NMOS transistors 601 are respectively connected to the power supply voltage, and the source electrodes of the twenty-seventh NMOS transistor 601 are grounded.
  • the working principle of the dynamic bias current generating circuit 105 is as follows: when the enable control signal is at a low level, that is, before the power supply voltage is established until the establishment is completed, the twenty-second PMOS transistor 612 is turned on, and the twenty-fourth PMOS transistor is turned on. 614 and the twenty-third NMOS transistor 616 are respectively turned off, so that the low power consumption and small current generation unit 1051 is turned off.
  • the self-bias current generation module 10510 of the low power consumption and small current generation unit 1051 is in a closed state, so that the first The comparator 103 and the second comparator 104 provide the bias current and the static operating point, and the twenty-sixth PMOS transistor 619 is turned on, so that the low-voltage and high-current generating unit 1052 is turned on, through the twenty-sixth PMOS transistor 619, the seventh The resistor 623 and the twenty-sixth NMOS transistor 622 generate a bias current, which is copied by the twenty-fourth NMOS transistor 620 on the one hand and provides the first comparator 103 with a bias current from the first current bias terminal Ibias_N and At the static operating point, on the other hand, the bias current is copied by the twenty-fifth NMOS transistor 621 and mirrored by the twenty-fifth PMOS transistor 617 and the twenty-sixth PMOS transistor 618, and the bias current from the second current bias terminal Ibias_P is The second comparator
  • the enable control signal is at a high level, that is, after the power supply voltage is established, the twenty-sixth PMOS transistor 619 is turned off, so that the low-voltage and high-current generating unit 1052 is in an off state. At this time, the low-voltage and high-current generating unit 1052 cannot
  • the bias current and the static operating point are provided for the first comparator 103 and the second comparator 104, while the twenty-second PMOS transistor 612 is turned off, the twenty-fourth PMOS transistor 614 and the twenty-third NMOS transistor 616 are respectively turned on,
  • the low-power and low-current generating unit 1051 is turned on, and the self-biasing current generating module 10510 uses The principle of generating a bias current, the bias current is mirrored by the twenty-third PMOS transistor 613 and the twenty-second NMOS transistor 615, respectively, and then passes through the twenty-fourth PMOS transistor 614 and the twenty-third NMOS transistor 616 from the corresponding
  • the current bias terminal provides
  • the twenty-seventh NMOS transistor 601 , the twenty-eighth NMOS transistor 602 , the twenty-ninth NMOS transistor 603 , the twenty-seventh PMOS transistor 605 and the eighth NMOS transistor 605 of the unit 1050 are activated.
  • the branch of the resistor 604 generates current, so that the gate voltage of the twenty-eighth PMOS transistor 606 is pulled down and turned on, thereby enabling the low-power consumption and small current generating unit 1051 to start normally, avoiding the degeneracy point.
  • chip port state detection circuit provided by the embodiment of the present invention may be used in an integrated circuit chip.
  • the specific structure of the chip port state detection circuit in the integrated circuit chip will not be described in detail here.
  • the above chip port state detection circuit can also be used in a communication terminal as an important part of the detection circuit.
  • the communication terminal mentioned here refers to the computer equipment that can be used in the mobile environment and supports various communication standards such as GSM, EDGE, TD_SCDMA, TDD_LTE, FDD_LTE, etc., including mobile phones, notebook computers, tablet computers, car computers, etc.
  • GSM Global System for Mobile communications
  • EDGE TD_SCDMA
  • TDD_LTE Time Division Duplex
  • FDD_LTE Frequency Division Duplex
  • the technical solutions provided by the embodiments of the present invention are also applicable to other situations where the detection circuit is applied, such as a communication base station.
  • the state of the port to be detected is converted into a corresponding voltage through the port detection conversion circuit, which are respectively output to the first comparator and the second comparator, and After comparing the corresponding input reference voltages, a logic signal is output to the chip ID judging circuit to obtain the chip ID corresponding to the state of the port to be detected on the chip, so that the communication terminal can identify the chip and distinguish multiple identical chips.
  • the dynamic bias current generating circuit provides the first comparator and the second comparator with a bias current and a static operating point respectively from the start of the establishment of the power supply voltage to before the establishment of the power supply voltage is completed and after the establishment of the power supply voltage is completed.
  • the state of the to-be-detected port of the chip is detected, which satisfies the requirement of fast detection of the to-be-detected port of the chip, and can meet the requirements of static low power consumption and real-time detection of the chip port state detection circuit.

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Abstract

本发明公开了一种芯片端口状态检测电路、芯片及通信终端。该芯片端口状态检测电路通过端口检测转换电路将待检测端口的状态转换为相应的电压，分别输出到第一比较器和第二比较器，与相应的输入参考电压进行比较后，向芯片ID判断电路输出逻辑信号，得到与芯片待检测端口状态对应的芯片ID，以区分出多颗相同的芯片。另一方面，通过动态偏置电流产生电路在电源电压开始建立到建立完成之前和在电源电压建立完成之后分别为第一比较器和第二比较器提供偏置电流以及静态工作点，不仅实现在通信终端识别芯片之前对芯片的待检测端口状态完成检测，满足对芯片待检测端口快速检测的要求，而且可以满足芯片端口状态检测电路静态低功耗且实时检测的要求。

Description

一种芯片端口状态检测电路、芯片及通信终端 技术领域
本发明涉及一种芯片端口状态检测电路，同时也涉及包括该芯片端口状态检测电路的集成电路芯片及相应的通信终端，属于集成电路技术领域。
背景技术
随着集成电路集成度的不断增加，以及芯片应用环境不断的多样化，对芯片端口状态检测技术提出了新的要求。例如在同一个通信终端中，需要应用到多颗相同芯片时，该通信终端就需要识别出每一颗相同的芯片。
现有技术中，通常通过检测芯片某一个端口或多个端口的状态，然后根据不同的端口状态输出不同的芯片ID以提供给相应的通信终端识别，从而区分多颗相同的芯片。
每一颗芯片的端口包括三种状态，即拉高状态，拉低状态和悬空状态。由于通信终端识别芯片是对芯片进行的第一步操作，并且芯片端口状态有可能在应用过程中发生变化，因此对芯片端口状态的检测需要做到速度快、低功耗和实时检测。
发明内容
本发明所要解决的首要技术问题在于提供一种芯片端口状态检测电路。
本发明所要解决的另一技术问题在于提供一种包括芯片端口状态检测电路的芯片及相应的通信终端。
为了实现上述目的，本发明采用下述的技术方案：
根据本发明实施例的第一方面，提供一种芯片端口状态检测电路，包括端口检测转换电路、参考电压产生电路、第一比较器、第二比较器、动态偏置电流产生电路和芯片ID判断电路；所述端口检测转换电路、所述参考电压产生电路及所述动态偏置电流产生电路分别连接所述第一比较器和所述第二比较器，所述第一比较器和所述第二比较器分别连接所述芯片ID判断电路；
所述端口检测转换电路连接芯片的待检测端口，实现将所述待检测端口的状态转换为相应的电压，分别输出到所述第一比较器和所述第二比较器；所述第一比较器、所述第二比较器接收所述参考电压产生电路提供的输入参考电压，并将所述端口检测转换电路输出的电压与所述输入参考电压进行比较后，向所述芯片ID判断电路输出逻辑信号，所述芯片ID判断电路根据该逻辑信号输出与所述待检测端口状态对应的芯片ID，以区分多颗相同的芯片。
其中较优地，所述端口检测转换电路包括但不限于第一电阻和第二电阻；所述第一电阻和所述第二电阻串联，并且所述第一电阻和所述第二电阻之间的连接点接入芯片的待检测端口。
其中较优地，所述参考电压产生电路包括但不限于第三电阻、第四电阻和第五电阻；所述第三电阻、所述第四电阻和所述第五电阻串联，所述第三电阻、所述第四电阻和所述第五电阻对电源电压进行分压，分别得到高电位参考电压和低电位参考电压。
其中较优地，所述第一比较器包括第一比较单元和第一整形驱动单元，所述第一比较单元连接所述第一整形驱动单元；
所述第二比较器包括第二比较单元和第二整形驱动单元，所述第二比较单元连接所述第二整形驱动单元。
其中较优地，所述第一比较单元包括但不限于第一NMOS管、第二NMOS管、第一PMOS管、第二PMOS管、第三PMOS管、第四PMOS管、第三NMOS管、第四NMOS管、第五PMOS管和第六PMOS管；所述第一NMOS管的栅极连接所述参考电压产生电路的高电位参考电压输出端；所述第一NMOS管的漏极、所述第一PMOS管的漏极、所述第二PMOS管的栅极、所述第三PMOS管的漏极和栅极以及所述第四PMOS管的栅极之间相互连接；所述第二NMOS管的栅极连接所述端口检测转换电路；所述第二NMOS管的漏极、所述第二PMOS管的漏极、所述第一PMOS管的栅极、所述第五PMOS管的漏极和栅极以及所述第六PMOS管的栅极之间相互连接；所述第一NMOS管与所述第二NMOS管的源极分别连接所述动态偏置电流产生电路的第一电流偏置端；所述第四PMOS管的漏极、所述第三NMOS管的漏极和栅极以及所述第四NMOS管的栅极之间相互连接；所述第四NMOS管的漏极、所述第六PMOS管的漏极以及 所述第一整形驱动单元的输入端之间相互连接；所述第一PMOS管、所述第二PMOS管、所述第三PMOS管、所述第四PMOS管、所述第五PMOS管和所述第六PMOS管的源极分别连接电源电压，所述第三NMOS管与所述第四NMOS管的源极分别接地。
其中较优地，所述第二比较单元包括但不限于第十三PMOS管、第十四PMOS管、第九NMOS管、第十NMOS管、第十一NMOS管、第十二NMOS管、第十五PMOS管、第十六PMOS管、第十三NMOS管和第十四NMOS管；所述第十四PMOS管的栅极连接所述参考电压产生电路的低电位参考电压输出端；所述第十四PMOS管的漏极、所述第十NMOS管的漏极、所述第九NMOS管的栅极、所述第十三NMOS管的漏极和栅极以及所述第十四NMOS管的栅极之间相互连接；所述第十三PMOS管的栅极连接所述端口检测转换电路；所述第十三PMOS管的漏极、所述第九NMOS管的漏极、所述第十NMOS管的栅极、所述第十一NMOS管的漏极和栅极以及所述第十二NMOS管的栅极之间相互连接；所述第十三PMOS管与所述第十四PMOS管的源极分别连接所述动态偏置电流产生电路的第二电流偏置端；所述第十二NMOS管的漏极、所述第十五PMOS管的漏极和栅极以及所述第十六PMOS管的栅极之间相互连接；所述第十六PMOS管的漏极、所述第十四NMOS管的漏极以及所述第二整形驱动单元的输入端之间相互连接；所述第十五PMOS管与所述第十六PMOS管的源极分别连接电源电压，所述第九NMOS管、所述第十NMOS管、所述第十一NMOS管、所述第十二NMOS管、所述第十三NMOS管和所述第十四NMOS管的源极分别接地。
其中较优地，所述动态偏置电流产生电路包括启动单元、所述低功耗小电流产生单元和所述低电压大电流产生单元；所述启动单元连接所述低功耗小电流产生单元；所述低功耗小电流产生单元和所述低电压大电流产生单元相连接。
其中较优地，所述低功耗小电流产生单元包括自偏置电流产生模块、电流镜像模块和开关使能模块；所述自偏置电流产生模块分别连接所述启动单元和所述电流镜像模块，所述电流镜像模块连接所述开关使能模块。
其中较优地，所述自偏置电流产生模块包括第二十NMOS管、第二 十一NMOS管、第六电阻、第二十PMOS管、第二十一PMOS管、第二十二PMOS管；所述第二十NMOS管的漏极分别连接所述第六电阻的一端、所述第二十一NMOS管的栅极以及启动单元；所述第二十NMOS管的栅极、所述第六电阻的另一端、所述第二十PMOS管的漏极、所述电流镜像模块之间相互连接，所述第二十PMOS管的栅极、所述启动单元、所述第二十一PMOS管的栅极和漏极、所述第二十二PMOS管的漏极、所述第二十一NMOS管的漏极、所述电流镜像模块之间相互连接，所述第二十PMOS管、所述第二十二PMOS管、所述第二十一PMOS管、所述的源极分别连接电源电压，所述第二十NMOS管与所述第二十一NMOS管的源极分别接地。
其中较优地，所述低电压大电流产生单元包括第二十五PMOS管、第二十六PMOS管、第二十六PMOS管、第二十四NMOS管、第二十五NMOS管、第二十六NMOS管和第七电阻，所述第二十五PMOS管的漏极连接所述第二十四PMOS管的漏极，所述第二十五PMOS管的栅极、所述第二十六PMOS管的栅极与漏极、所述第二十五NMOS管的漏极之间相互连接，所述第二十五NMOS管的栅极、所述第二十六NMOS管的栅极和漏极、所述第二十四NMOS管的栅极、所述第七电阻的一端之间相互连接，所述第二十四NMOS管的漏极连接所述第二十三NMOS管的漏极，所述第七电阻的另一端连接所述第二十六PMOS管的漏极，所述第二十五PMOS管、所述第二十六PMOS管、所述第二十六PMOS管的源极分别连接电源电压，所述第二十四NMOS管、所述第二十五NMOS管的源极分别接地。
根据本发明实施例的第二方面，提供一种集成电路芯片，包括上述的芯片端口状态检测电路。
根据本发明实施例的第三方面，提供一种通信终端，包括上述的芯片端口状态检测电路。
本发明实施例提供的芯片端口状态检测电路、芯片及通信终端，一方面通过端口检测转换电路将待检测端口的状态转换为相应的电压，分别输出到第一比较器和第二比较器与相应的输入参考电压进行比较后，向芯片ID判断电路输出逻辑信号，得到与芯片的待检测端口状态对应的芯片ID，以便于通信终端对芯片进行识别，以区分出多颗 相同的芯片。另一方面，通过动态偏置电流产生电路在电源电压开始建立到建立完成之前以及在电源电压建立完成之后分别为第一比较器和第二比较器提供偏置电流以及静态工作点，不仅实现在通信终端识别芯片之前对芯片的待检测端口状态完成检测，满足对芯片待检测端口快速检测的要求，而且可以满足芯片端口状态检测电路静态低功耗且实时检测的要求。
附图说明
图1为本发明实施例提供的芯片端口状态检测电路的原理框图；
图2a～图2c分别为本发明实施例提供的芯片端口状态检测电路中，端口检测转换电路实施例电路图；
图3为本发明实施例提供的芯片端口状态检测电路中，参考电压产生电路实施例电路图；
图4a为本发明实施例提供的芯片端口状态检测电路中，第一比较器实施例电路图；
图4b为本发明实施例提供的芯片端口状态检测电路中，第二比较器实施例电路图；
图5为本发明实施例提供的芯片端口状态检测电路中，动态偏置电流产生电路实施例电路图。
具体实施方式
下面结合附图和具体实施例对本发明的技术内容做进一步的详细说明。
为了应对芯片端口状态在应用过程中发生变化，保证在芯片端口检测过程中满足速度快、低功耗和实时检测的要求，实现精准地区分通信终端中的多颗相同的芯片。如图1所示，本发明实施例中提供了一种芯片端口状态检测电路，包括端口检测转换电路101、参考电压产生电路102、第一比较器103、第二比较器104、动态偏置电流产生电路105和芯片ID判断电路108，端口检测转换电路101、参考电压产生电路102及动态偏置电流产生电路105分别连接第一比较器103和第二比较器104，第一比较器103和第二比较器104分别连接芯片ID判断电路108。
将端口检测转换电路101连接芯片的待检测端口，实现将待检测 端口的状态转换为相应的电压，分别输出到第一比较器103和第二比较器104，第一比较器103、第二比较器104以参考电压产生电路102提供的电压VH和电压VL作为输入参考电压，并将端口检测转换电路101输出的电压与所述的输入参考电压进行比较后，向芯片ID判断电路108输出逻辑信号。根据该逻辑信号，芯片ID判断电路输出与芯片的待检测端口状态对应的芯片ID，以便通信终端对芯片进行识别，区分出多颗相同的芯片。
如图2a～图2c所示，端口检测转换电路101由第一电阻R1和第二电阻R2串联组成，但不仅局限于此。将芯片的待检测端口Vpin接在第一电阻R1和第二电阻R2之间的连接点，第一电阻R1另一端连接到电源电压VDD，第二电阻的另一端连接到地。通过第一电阻R1和第二电阻R2的分压作用实现将芯片待检测端口的三种状态(拉高状态，拉低状态和悬空状态)转换为对应的三种不同电压。
具体地说，当芯片的待检测端口为拉高状态时，如图2a所示，处于拉高状态下的待检测端口Vpin的电位是电源电压VDD，即
Figure PCTCN2021130951-appb-000001
当芯片的待检测端口为拉低状态时，如图2b所示，处于拉低状态下的待检测端口Vpin的电位是地，即Vpin＝0。当芯片的待检测端口为悬空状态时，如图2c所示，处于悬空状态下的待检测端口Vpin的电位是电源电压VDD经过第一电阻R1和第二电阻R2分压得到，即
Figure PCTCN2021130951-appb-000002
其中，需要选择第一电阻R1和第二电阻R2的合适阻值以折中功耗和版图面积。
如图3所示，参考电压产生电路102由第三电阻R3、第四电阻R4和第五电阻R5串联组成，但不仅局限于此。第三电阻R3、第四电阻R4和第五电阻R5对电源电压VDD进行分压，分别得到高电位参考电压VH和低电位参考电压VL，并对应输出到第一比较器103和第二比较器104作为输入参考电压。其中，高电位参考电压
Figure PCTCN2021130951-appb-000003
低电位参考电压
Figure PCTCN2021130951-appb-000004
如图4a所示，第一比较器103包括第一比较单元1030和第一整形驱动单元1031，第一比较单元1030连接第一整形驱动单元1031。 第一比较单元1030包括第一NMOS管401、第二NMOS管402、第一PMOS管403、第二PMOS管404、第三PMOS管405、第四PMOS管406、第三NMOS管408、第四NMOS管410、第五PMOS管411和第六PMOS管412，但不仅局限于此；第一比较单元1030各部分之间连接关系如下：第一NMOS管401的栅极连接参考电压产生电路102的高电位参考电压输出端，第一NMOS管401的漏极、第一PMOS管403的漏极、第二PMOS管404的栅极、第三PMOS管405的漏极和栅极以及第四PMOS管406的栅极之间相互连接，第二NMOS管402的栅极连接端口检测转换电路101，第二NMOS管402的漏极、第二PMOS管404的漏极、第一PMOS管403的栅极、第五PMOS管411的漏极和栅极以及第六PMOS管412的栅极之间相互连接，第一NMOS管401与第二NMOS管402的源极分别连接动态偏置电流产生电路105的第一电流偏置端Ibias_N,第四PMOS管406的漏极、第三NMOS管408的漏极和栅极以及第四NMOS管410的栅极之间相互连接，第四NMOS管410的漏极、第六PMOS管412的漏极以及第一整形驱动单元1031的输入端之间相互连接，第一PMOS管403、第二PMOS管404、第三PMOS管405、第四PMOS管406、第五PMOS管411和第六PMOS管412的源极分别连接电源电压，第三NMOS管408与第四NMOS管410的源极分别接地。
第一比较器103的工作原理如下：当第一比较器103接收的端口检测转换电路101输出的与待检测端口Vpin状态对应的电压大于参考电压产生电路102提供的高电位参考电压VH时，流过第二NMOS管402的电流大于第一NMOS管401的电流，第一PMOS管403导通，使得第三PMOS管405的漏极电压被拉高，此时第三PMOS管405、第四PMOS管406、第三NMOS管408与第四NMOS管410处于截止状态，而第五PMOS管411和第六PMOS管412处于导通状态，经过第十一PMOS管415和第七NMOS管416、第十二PMOS管417和第八NMOS管418分别组成的反相器经串联得到的第一整形驱动单元1031的整形驱动作用，使得第一比较器103通过电压输出端Vout_A输出高电平。
当第一比较器103接收的端口检测转换电路101输出的与待检测端口Vpin状态对应的电压小于参考电压产生电路102提供的高电位参考电压VH时，流过第二NMOS管402的电流小于第一NMOS管401的电 流，第二PMOS管404导通，第五PMOS管411的漏极电压被拉高，此时第五PMOS管411和第六PMOS管412处于截止状态，而第三PMOS管405、第四PMOS管406、第三NMOS管408与第四NMOS管410处于导通状态，经过第十一PMOS管415和第七NMOS管416、第十二PMOS管417和第八NMOS管418分别组成的反相器经串联得到的第一整形驱动单元1031的整形驱动作用，使得第一比较器103通过电压输出端Vout_A输出低电平。
为了控制第一比较器103功能性的开启和关闭，在第三PMOS管405与第四PMOS管406的栅极之间接入第九PMOS管407，第五PMOS管411和第六PMOS管412的栅极之间接入第十PMOS管413，第三NMOS管408与第四NMOS管410的栅极之间接入第五NMOS管409，第四NMOS管410与第六PMOS管412的漏极和第一整形驱动单元1031的输入端之间接入第六NMOS管414；其中，第九PMOS管407、第十PMOS管413、第五NMOS管409和第六NMOS管414分别作为使能控制管，通过各使能控制管的栅极接收使能控制信号，以控制第一比较器103功能性的开启和关闭。
如图4b所示，第二比较器104包括第二比较单元1040和第二整形驱动单元1041，第二比较单元1040连接第二整形驱动单元1041。第二比较单元1040包括第十三PMOS管501、第十四PMOS管502、第九NMOS管503、第十NMOS管504、第十一NMOS管505、第十二NMOS管506、第十五PMOS管508、第十六PMOS管510、第十三NMOS管511和第十四NMOS管513，但不仅局限于此；第二比较单元1030各部分之间连接关系如下：第十四PMOS管502的栅极连接参考电压产生电路102的低电位参考电压输出端，第十四PMOS管502的漏极、第十NMOS管504的漏极、第九NMOS管503的栅极、第十三NMOS管511的漏极和栅极以及第十四NMOS管513的栅极之间相互连接；第十三PMOS管501的栅极连接端口检测转换电路101，第十三PMOS管501的漏极、第九NMOS管503的漏极、第十NMOS管504的栅极、第十一NMOS管505的漏极和栅极以及第十二NMOS管506的栅极之间相互连接，第十三PMOS管501与第十四PMOS管502的源极分别连接动态偏置电流产生电路105的第二电流偏置端Ibias_P,第十二NMOS管506的漏极、 第十五PMOS管508的漏极和栅极以及第十六PMOS管510的栅极之间相互连接，第十六PMOS管510的漏极、第十四NMOS管513的漏极以及第二整形驱动单元1041的输入端之间相互连接，第十五PMOS管508与第十六PMOS管510的源极分别连接电源电压，第九NMOS管503、第十NMOS管504、第十一NMOS管505、第十二NMOS管506、第十三NMOS管511和第十四NMOS管513的源极分别接地。
第一比较器103的工作原理如下：当第二比较器104接收的端口检测转换电路101输出的与待检测端口Vpin状态对应的电压大于参考电压产生电路102提供的低电位参考电压VL时，流过第十四PMOS管502的电流大于第十三PMOS管501的电流，第九NMOS管503导通，使得第十一NMOS管505的漏极电压被拉高，此时第十一NMOS管505、第十二NMOS管506、第十五PMOS管508、第十六PMOS管510处于截止状态，而第十三NMOS管511和第十四NMOS管513处于导通状态，经过第十七PMOS管515和第十五NMOS管516、第十八PMOS管517和第十六NMOS管518分别组成的反相器经串联得到的第二整形驱动单元1041的整形驱动作用，使得第二比较器104通过电压输出端Vout_B输出低电平。
当第二比较器104接收的端口检测转换电路101输出的与待检测端口Vpin状态对应的电压小于参考电压产生电路102提供的低电位参考电压VL时，流过第十四PMOS管502的电流小于第十三PMOS管501的电流，第十NMOS管504导通，第十三NMOS管511的漏极电压被拉高，此时第十三NMOS管511和第十四NMOS管513处于截止状态，而第十一NMOS管505、第十二NMOS管506、第十五PMOS管508、第十六PMOS管510处于导通状态，经过第十七PMOS管515和第十五NMOS管516、第十八PMOS管517和第十六NMOS管518分别组成的反相器经串联得到的第二整形驱动单元1041的整形驱动作用，使得第二比较器104通过电压输出端Vout_B输出高电平。
为了控制第二比较器104功能性的开启和关闭，在第十五PMOS管508与第十六PMOS管510的栅极之间接入第十九PMOS管509，第十一NMOS管505与第十二NMOS管506的栅极之间接入第十七NMOS管507，第十三NMOS管511与第十四NMOS管513的栅极之间接入第十八NMOS 管512，第十六PMOS管510与第十四NMOS管513的漏极和第二整形驱动单元1041的输入端之间接入第十九NMOS管514。其中，第十九PMOS管509、第十七NMOS管507、第十八NMOS管512和第十九NMOS管514分别作为使能控制管，通过各使能控制管的栅极接收使能控制信号，以控制第二比较器104功能性的开启和关闭。
由于不同的芯片的待检测端口状态对应不同的电压，进而对应第一比较器103和第二比较器104输出不同的逻辑信号，该逻辑信号即为第一比较器103和第二比较器104电压输出端输出的高电平或低电平。当芯片的待检测端口为拉高状态时，第一比较器103输出高电平，第二比较器104输出低电平；当芯片的待检测端口为拉低状态时，第一比较器103输出低电平，第二比较器104输出高电平；当芯片的待检测端口为悬空状态时，第一比较器103输出低电平，第二比较器104输出低电平。
第一比较器103和第二比较器104输出的不同逻辑信号输出到芯片ID判断电路108，芯片ID判断电路108根据预先设计的第一比较器103和第二比较器104输出的逻辑信号与芯片ID的对应关系，对第一比较器103和第二比较器104实际输出的逻辑信号进行判断，确定出同一个通信终端中应用到的每颗芯片的芯片ID，从而实现芯片端口状态和芯片ID一一对应，以便于通信终端识别出每一颗相同的芯片。其中，芯片ID包括但不限于芯片产品ID、运营商ID等。
在本发明的一个实施例中，芯片ID判断电路108可以由若干个逻辑与门、逻辑非门、逻辑或门电路等组成。此外，由于芯片的一个端口对应有三种状态，因此该端口会对应有三个芯片ID，即在同一个应用环境中允许有三颗相同芯片；那么，如果在同一应用环境中需要更多的相同芯片，则可以根据所需芯片的数量，确定芯片所需检测的端口数量，并将每个待检测端口分别连接本芯片端口状态检测电路的端口检测转换电路即可。例如，在同一应用环境中需要五颗相同的芯片，则该芯片需要有两个待检测端口分别连接到端口检测转换电路。
动态偏置电流产生电路105，用于为第一比较器103和第二比较器104提供偏置电流，使第一比较器103和第二比较器104可以正常工作。如图5所示，动态偏置电流产生电路105包括启动单元1050、 低功耗小电流产生单元1051和低电压大电流产生单元1052；启动单元1050连接低功耗小电流产生单元1051，低功耗小电流产生单元1051连接低电压大电流产生单元1052。
当低功耗小电流产生单元1051和低电压大电流产生单元1052分别接收高电平使能控制信号时，低功耗小电流产生单元1051处于开启状态，低电压大电流产生单元1052处于关闭状态，实现在电源电压建立完成之后为第一比较器103和第二比较器104提供偏置电流，以满足芯片端口状态检测电路静态低功耗且实时检测的要求。
当低电压大电流产生单元1052和低功耗小电流产生单元1051分别接收低电平使能控制信号时，低电压大电流产生单元1052处于开启状态，低功耗小电流产生单元1051处于关闭状态，在电源电压开始建立到建立完成之前为第一比较器103和第二比较器104提供偏置电流，以确保在通信终端识别芯片之前对芯片的待检测端口状态完成检测，满足对芯片待检测端口快速检测的要求。
如图5所示，低功耗小电流产生单元1051包括自偏置电流产生模块10510、电流镜像模块10511和开关使能模块10512；自偏置电流产生模块10510分别连接启动单元1050和电流镜像模块10511，电流镜像模块10511连接开关使能模块10512。自偏置电流产生模块10510包括第二十NMOS管607、第二十一NMOS管609、第六电阻608、第二十PMOS管610、第二十一PMOS管611、第二十二PMOS管612；具体连接关系如下：第二十NMOS管607的漏极分别连接第六电阻608的一端、第二十一NMOS管609的栅极以及启动单元1050，第二十NMOS管607的栅极、第六电阻608的另一端、第二十PMOS管610的漏极、电流镜像模块10511之间相互连接，第二十PMOS管610的栅极、启动单元1050、第二十一PMOS管611的栅极和漏极、第二十二PMOS管612的漏极、第二十一NMOS管609的漏极、电流镜像模块10511之间相互连接，第二十PMOS管610、第二十二PMOS管612、第二十一PMOS管611、的源极分别连接电源电压，第二十NMOS管607与第二十一NMOS管609的源极分别接地。
如图5所示，电流镜像模块10511包括第二十三PMOS管613和第二十二NMOS管615；第二十三PMOS管613的栅极、第二十PMOS管610 的栅极、启动单元1050、第二十一PMOS管611的栅极和漏极、第二十二PMOS管612的漏极、第二十一NMOS管609的漏极之间相互连接，第二十三PMOS管613的漏极连接开关使能模块10512，第二十三PMOS管613的源极连接电源电压，第二十二NMOS管615的栅极、第二十NMOS管607的栅极、第六电阻608的另一端、第二十PMOS管610的漏极之间相互连接，第二十二NMOS管615的漏极连接开关使能模块10512，第二十二NMOS管615的源极接地。
如图5所示，开关使能模块10512包括第二十四PMOS管614和第二十三NMOS管616；第二十四PMOS管614的源极连接第二十三PMOS管613的漏极，第二十四PMOS管614的漏极连接低电压大电流产生单元1052后构成动态偏置电流产生电路105的第一电流偏置端Ibias_N，第二十三NMOS管616的源极连接第二十二NMOS管615的漏极，第二十三NMOS管616的漏极连接低电压大电流产生单元1052后构成动态偏置电流产生电路105的第二电流偏置端Ibias_P。
如图5所示，低电压大电流产生单元1052包括第二十五PMOS管617、第二十六PMOS管618、第二十六PMOS管619、第二十四NMOS管620、第二十五NMOS管621、第二十六NMOS管622和第七电阻623。具体连接关系如下：第二十五PMOS管617的漏极连接第二十四PMOS管614的漏极，第二十五PMOS管617的栅极、第二十六PMOS管618的栅极与漏极、第二十五NMOS管621的漏极之间相互连接，第二十五NMOS管621的栅极、第二十六NMOS管622的栅极和漏极、第二十四NMOS管620的栅极、第七电阻623的一端之间相互连接，第二十四NMOS管620的漏极连接第二十三NMOS管616的漏极，第七电阻623的另一端连接第二十六PMOS管619的漏极，第二十五PMOS管617、第二十六PMOS管618、第二十六PMOS管619的源极分别连接电源电压，第二十四NMOS管620、第二十五NMOS管621的源极分别接地。
如图5所示，启动单元1050，用于使得低功耗小电流产生单元1051正常启动，避开简并点，以保证其在所需输出点稳定。该启动单元1050包括第二十七NMOS管601、第二十八NMOS管602、第二十九NMOS管603、第二十七PMOS管605、第二十八PMOS管606和第八电阻604。具体连接如下：第二十七NMOS管601的栅极、第二十八NMOS管602 的栅极、第二十九NMOS管603的栅极和漏极以及第八电阻604的一端相互连接，第二十七NMOS管601的漏极连接第二十八NMOS管602的源极，第二十八NMOS管602的漏极连接第二十九NMOS管603的源极，第八电阻604的另一端分别连接第二十七PMOS管605的漏极、第二十八PMOS管606的栅极，第二十七PMOS管605的栅极、第二十三PMOS管613的栅极、第二十PMOS管610的栅极、第二十一PMOS管611的栅极和漏极、第二十二PMOS管612的漏极、第二十一NMOS管609的漏极之间相互连接，第二十八PMOS管606的漏极分别第二十NMOS管607的漏极、第六电阻608的一端、第二十一NMOS管609的栅极，第二十七PMOS管605与第二十八PMOS管606的源极分别连接电源电压，第二十七NMOS管601的的源极接地。
动态偏置电流产生电路105的工作原理如下：当使能控制信号为低电平时，也就是在电源电压开始建立到建立完成之前，第二十二PMOS管612导通，第二十四PMOS管614与第二十三NMOS管616分别截止，使得低功耗小电流产生单元1051关闭，此时低功耗小电流产生单元1051的自偏置电流产生模块10510处于关闭状态，进而无法为第一比较器103和第二比较器104提供偏置电流以及静态工作点，而第二十六PMOS管619导通，使得低电压大电流产生单元1052开启，通过第二十六PMOS管619、第七电阻623以及第二十六NMOS管622产生偏置电流，该偏置电流一方面通过第二十四NMOS管620复制并从第一电流偏置端Ibias_N为第一比较器103提供偏置电流以及静态工作点，该偏置电流另一方面通过第二十五NMOS管621复制，并通过第二十五PMOS管617与第二十六PMOS管618镜像后，从第二电流偏置端Ibias_P为第二比较器104提供偏置电流以及静态工作点，从而确保在通信终端识别芯片之前对芯片的待检测端口状态完成检测，满足对芯片待检测端口快速检测的要求。
当使能控制信号为高电平时，也就是在电源电压建立完成之后，第二十六PMOS管619截止，使得低电压大电流产生单元1052处于关闭状态，此时低电压大电流产生单元1052无法为第一比较器103和第二比较器104提供偏置电流以及静态工作点，而第二十二PMOS管612截止，第二十四PMOS管614与第二十三NMOS管616分别导通，使得 低功耗小电流产生单元1051开启，此时自偏置电流产生模块10510利用
Figure PCTCN2021130951-appb-000005
的原理产生偏置电流，该偏置电流分别通过第二十三PMOS管613和第二十二NMOS管615镜像后，通过第二十四PMOS管614与第二十三NMOS管616从相应的电流偏置端为第一比较器103提供偏置电流以及静态工作点，以满足本芯片端口状态检测电路静态低功耗且实时检测的要求。其中，当使能控制信号为高电平时，启动单元1050的第二十七NMOS管601、第二十八NMOS管602、第二十九NMOS管603、第二十七PMOS管605和第八电阻604支路产生电流，使得第二十八PMOS管606的栅极电压被拉低导通，进而使得低功耗小电流产生单元1051正常启动，避开简并点。
另外，本发明实施例提供的芯片端口状态检测电路可以被用在集成电路芯片中。对于该集成电路芯片中芯片端口状态检测电路的具体结构，在此不再一一详述。
上述芯片端口状态检测电路还可以被用在通信终端中，作为检测电路的重要组成部分。这里所说的通信终端是指可以在移动环境中使用，支持GSM、EDGE、TD_SCDMA、TDD_LTE、FDD_LTE等多种通信制式的计算机设备，包括移动电话、笔记本电脑、平板电脑、车载电脑等。此外，本发明实施例提供的技术方案也适用于其他检测电路应用的场合，例如通信基站等。
本发明实施例提供的芯片端口状态检测电路、芯片及通信终端，一方面通过端口检测转换电路将待检测端口的状态转换为相应的电压，分别输出到第一比较器和第二比较器，与相应的输入参考电压进行比较后，向芯片ID判断电路输出逻辑信号，得到与芯片待检测端口状态对应的芯片ID，以便于通信终端对芯片进行识别，以区分出多颗相同的芯片。另一方面，通过动态偏置电流产生电路在电源电压开始建立到建立完成之前和在电源电压建立完成之后分别为第一比较器和第二比较器提供偏置电流以及静态工作点，不仅实现在通信终端识别芯片之前对芯片的待检测端口状态完成检测，满足对芯片待检测端口快速检测的要求，而且可以满足芯片端口状态检测电路静态低功耗且实时检测的要求。
以上对本发明所提供的芯片端口状态检测电路、芯片及通信终端 进行了详细的说明。对本领域的一般技术人员而言，在不背离本发明实质内容的前提下对它所做的任何显而易见的改动，都将属于本发明专利权的保护范围。

Claims (12)

  1. 一种芯片端口状态检测电路，其特征在于包括端口检测转换电路、参考电压产生电路、第一比较器、第二比较器、动态偏置电流产生电路和芯片ID判断电路；所述端口检测转换电路、所述参考电压产生电路及所述动态偏置电流产生电路分别连接所述第一比较器和所述第二比较器，所述第一比较器和所述第二比较器分别连接所述芯片ID判断电路；
    所述端口检测转换电路连接芯片的待检测端口，实现将所述待检测端口的状态转换为相应的电压，分别输出到所述第一比较器和所述第二比较器；所述第一比较器、所述第二比较器接收所述参考电压产生电路提供的输入参考电压，并将所述端口检测转换电路输出的电压与所述输入参考电压进行比较后，向所述芯片ID判断电路输出逻辑信号，所述芯片ID判断电路根据该逻辑信号输出与所述待检测端口状态对应的芯片ID，以区分多颗相同的芯片。
  2. 如权利要求1所述的芯片端口状态检测电路，其特征在于：
    所述端口检测转换电路包括但不限于第一电阻和第二电阻；所述第一电阻和所述第二电阻串联，并且所述第一电阻和所述第二电阻之间的连接点接入芯片的待检测端口。
  3. 如权利要求1所述的芯片端口状态检测电路，其特征在于：
    所述参考电压产生电路包括但不限于第三电阻、第四电阻和第五电阻；所述第三电阻、所述第四电阻和所述第五电阻串联，所述第三电阻、所述第四电阻和所述第五电阻对电源电压进行分压，分别得到高电位参考电压和低电位参考电压。
  4. 如权利要求1所述的芯片端口状态检测电路，其特征在于：
    所述第一比较器包括第一比较单元和第一整形驱动单元，所述第一比较单元连接所述第一整形驱动单元；
    所述第二比较器包括第二比较单元和第二整形驱动单元，所述第二比较单元连接所述第二整形驱动单元。
  5. 如权利要求4所述的芯片端口状态检测电路，其特征在于：
    所述第一比较单元包括但不限于第一NMOS管、第二NMOS管、第 一PMOS管、第二PMOS管、第三PMOS管、第四PMOS管、第三NMOS管、第四NMOS管、第五PMOS管和第六PMOS管；所述第一NMOS管的栅极连接所述参考电压产生电路的高电位参考电压输出端；所述第一NMOS管的漏极、所述第一PMOS管的漏极、所述第二PMOS管的栅极、所述第三PMOS管的漏极和栅极以及所述第四PMOS管的栅极之间相互连接；所述第二NMOS管的栅极连接所述端口检测转换电路，所述第二NMOS管的漏极、所述第二PMOS管的漏极、所述第一PMOS管的栅极、所述第五PMOS管的漏极和栅极以及所述第六PMOS管的栅极之间相互连接；所述第一NMOS管与所述第二NMOS管的源极分别连接所述动态偏置电流产生电路的第一电流偏置端；所述第四PMOS管的漏极、所述第三NMOS管的漏极和栅极以及所述第四NMOS管的栅极之间相互连接；所述第四NMOS管的漏极、所述第六PMOS管的漏极以及所述第一整形驱动单元的输入端之间相互连接；所述第一PMOS管、所述第二PMOS管、所述第三PMOS管、所述第四PMOS管、所述第五PMOS管和所述第六PMOS管的源极分别连接电源电压，所述第三NMOS管与所述第四NMOS管的源极分别接地。
  6. 如权利要求4所述的芯片端口状态检测电路，其特征在于：
    所述第二比较单元包括但不限于第十三PMOS管、第十四PMOS管、第九NMOS管、第十NMOS管、第十一NMOS管、第十二NMOS管、第十五PMOS管、第十六PMOS管、第十三NMOS管和第十四NMOS管；所述第十四PMOS管的栅极连接所述参考电压产生电路的低电位参考电压输出端；所述第十四PMOS管的漏极、所述第十NMOS管的漏极、所述第九NMOS管的栅极、所述第十三NMOS管的漏极和栅极以及所述第十四NMOS管的栅极之间相互连接；所述第十三PMOS管的栅极连接所述端口检测转换电路；所述第十三PMOS管的漏极、所述第九NMOS管的漏极、所述第十NMOS管的栅极、所述第十一NMOS管的漏极和栅极以及所述第十二NMOS管的栅极之间相互连接；所述第十三PMOS管与所述第十四PMOS管的源极分别连接所述动态偏置电流产生电路的第二电流偏置端；所述第十二NMOS管的漏极、所述第十五PMOS管的漏极和栅极以及所述第十六PMOS管的栅极之间相互连接；所述第十六PMOS管的漏极、所述第十四NMOS管的漏极以及所述第二整形驱动单元的输 入端之间相互连接；所述第十五PMOS管与所述第十六PMOS管的源极分别连接电源电压，所述第九NMOS管、所述第十NMOS管、所述第十一NMOS管、所述第十二NMOS管、所述第十三NMOS管和所述第十四NMOS管的源极分别接地。
  7. 如权利要求1所述的芯片端口状态检测电路，其特征在于：
    所述动态偏置电流产生电路包括启动单元、所述低功耗小电流产生单元和所述低电压大电流产生单元；所述启动单元连接所述低功耗小电流产生单元；所述低功耗小电流产生单元和所述低电压大电流产生单元相连接。
  8. 如权利要求7所述的芯片端口状态检测电路，其特征在于：
    所述低功耗小电流产生单元包括自偏置电流产生模块、电流镜像模块和开关使能模块，所述自偏置电流产生模块分别连接所述启动单元和所述电流镜像模块，所述电流镜像模块连接所述开关使能模块。
  9. 如权利要求8所述的芯片端口状态检测电路，其特征在于：
    所述自偏置电流产生模块包括第二十NMOS管、第二十一NMOS管、第六电阻、第二十PMOS管、第二十一PMOS管、第二十二PMOS管；所述第二十NMOS管的漏极分别连接所述第六电阻的一端、所述第二十一NMOS管的栅极以及启动单元，所述第二十NMOS管的栅极、所述第六电阻的另一端、所述第二十PMOS管的漏极、所述电流镜像模块之间相互连接，所述第二十PMOS管的栅极、所述启动单元、所述第二十一PMOS管的栅极和漏极、所述第二十二PMOS管的漏极、所述第二十一NMOS管的漏极、所述电流镜像模块之间相互连接，所述第二十PMOS管、所述第二十二PMOS管、所述第二十一PMOS管、所述的源极分别连接电源电压，所述第二十NMOS管与所述第二十一NMOS管的源极分别接地。
  10. 如权利要求8所述的芯片端口状态检测电路，其特征在于：
    所述低电压大电流产生单元包括第二十五PMOS管、第二十六PMOS管、第二十六PMOS管、第二十四NMOS管、第二十五NMOS管、第二十六NMOS管和第七电阻，所述第二十五PMOS管的漏极连接所述第二十四PMOS管的漏极，所述第二十五PMOS管的栅极、所述第二十六PMOS管的栅极与漏极、所述第二十五NMOS管的漏极之间相互连接，所述第 二十五NMOS管的栅极、所述第二十六NMOS管的栅极和漏极、所述第二十四NMOS管的栅极、所述第七电阻的一端之间相互连接，所述第二十四NMOS管的漏极连接所述第二十三NMOS管的漏极，所述第七电阻的另一端连接所述第二十六PMOS管的漏极，所述第二十五PMOS管、所述第二十六PMOS管、所述第二十六PMOS管的源极分别连接电源电压，所述第二十四NMOS管、所述第二十五NMOS管的源极分别接地。
  11. 一种集成电路芯片，其特征在于包括权利要求1～10中任意一项所述的芯片端口状态检测电路。
  12. 一种通信终端，其特征在于包括权利要求1～10中任意一项所述的芯片端口状态检测电路。
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CN115334300A (zh) * 2022-08-09 2022-11-11 慷智集成电路(上海)有限公司 一种线路故障检测模块及车载视频传输芯片
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