WO2022099764A1 - 碳化硅器件 - Google Patents

碳化硅器件 Download PDF

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Publication number
WO2022099764A1
WO2022099764A1 PCT/CN2020/130599 CN2020130599W WO2022099764A1 WO 2022099764 A1 WO2022099764 A1 WO 2022099764A1 CN 2020130599 W CN2020130599 W CN 2020130599W WO 2022099764 A1 WO2022099764 A1 WO 2022099764A1
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silicon carbide
source
layer
type
gate
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PCT/CN2020/130599
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English (en)
French (fr)
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龚轶
刘磊
刘伟
王睿
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苏州东微半导体股份有限公司
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Priority to JP2021569955A priority Critical patent/JP7350373B2/ja
Priority to KR1020217042701A priority patent/KR102572266B1/ko
Priority to US17/614,259 priority patent/US20230275134A1/en
Publication of WO2022099764A1 publication Critical patent/WO2022099764A1/zh

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Definitions

  • the present application belongs to the technical field of semiconductor devices, for example, relates to a silicon carbide device.
  • Silicon carbide has many characteristics different from traditional silicon semiconductor materials. Its energy band gap is 2.8 times that of silicon, and its dielectric breakdown field strength is 5.3 times that of silicon. Therefore, in the field of high-voltage power devices, silicon carbide devices can be used compared to silicon materials. Thinner epitaxial layers to reach the same withstand voltage level as conventional silicon devices, while having lower on-resistance. At present, the main problem of using silicon carbide to fabricate trench power devices is that a large electric field will be applied to the gate dielectric layer in the gate trench during the operation of the device, which makes the gate easily broken down and affects the device. pressure resistance.
  • the present application provides a silicon carbide device, so as to reduce the risk of gate breakdown and improve the withstand voltage of the device.
  • the application provides a silicon carbide device, including:
  • a silicon carbide substrate comprising a first n-type silicon carbide layer, a second n-type silicon carbide layer, a p-type silicon carbide layer and a third n-type silicon carbide layer stacked in sequence;
  • gate trenches and source trenches that are located in the silicon carbide substrate and are alternately spaced, the bottom of the gate trench and the bottom of the source trench are both located in the second n-type silicon carbide within the layer;
  • a gate located in the gate trench, the gate is isolated from the second n-type silicon carbide layer by a first insulating layer, the gate is separated from the p-type semiconductor layer and the p-type semiconductor layer by a second insulating layer the third n-type semiconductor layer is isolated;
  • a source located in the source trench the source is connected to the p-type silicon carbide layer and the third n-type silicon carbide layer, the source is connected to the source through a third insulating layer the second n-type silicon carbide layer isolation at the location of the sidewall of the trench;
  • a p-type well region located within the second n-type silicon carbide layer and located at the bottom of the source trench, where the p-type well region and the source are located at the bottom of the source trench connected.
  • the depth of the gate trench is the same as the depth of the source trench.
  • the width of the source trench is greater than the width of the gate trench.
  • the thickness of the first insulating layer is greater than the thickness of the second insulating layer.
  • the first insulating layer is at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide and hafnium oxide.
  • the second insulating layer is at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide and hafnium oxide.
  • the third insulating layer is at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide and hafnium oxide.
  • the gate is at least one of conductive polysilicon, titanium, nickel, copper, aluminum, silver, gold, titanium nitride and tungsten.
  • the source is at least one of conductive polysilicon, titanium, nickel, copper, aluminum, silver, gold, titanium nitride and tungsten.
  • the p-type well region under the source trench can increase the electric field near the bottom of the source trench, limit the highest electric field to the pn junction at the bottom of the source trench, and protect the gate trench
  • the gate inside is not easily broken down, and the withstand voltage of the device is improved;
  • a first insulating layer with a larger thickness is used in the lower part of the gate trench, which can further protect the gate from being broken down.
  • FIG. 1 is a schematic cross-sectional structure diagram of an embodiment of a silicon carbide device provided by the present application.
  • FIG. 1 is a schematic cross-sectional structure diagram of an embodiment of a silicon carbide device provided by the present application.
  • the silicon carbide device of the present application includes a silicon carbide substrate 20, and the silicon carbide substrate 20 includes first n layers stacked in sequence. type silicon carbide layer 21, second n-type silicon carbide layer 22, p-type silicon carbide layer 23 and third n-type silicon carbide layer 24, the first n-type silicon carbide layer 21 serves as the n-type drain region of the silicon carbide device.
  • the gate trenches 41 and the source trenches 42 are located in the silicon carbide substrate 20 and are alternately spaced, and the bottoms of the gate trenches 41 and the source trenches 42 are both located in the second n-type silicon carbide layer 22 .
  • the number of gate trenches 41 and source trenches 42 is determined by the specifications of the designed silicon carbide device. Only one gate trench 41 and two source trenches 42 are exemplarily shown in the embodiments of the present application. .
  • the depth of the gate trench 41 and the depth of the source trench 42 may be the same, and thus, the gate trench 41 and the source trench 42 may be simultaneously formed in the same etching process.
  • the p-type silicon carbide layer 23 between the gate trench 41 and the source trench 42 can serve as the p-type body region of the silicon carbide device, and the third n between the gate trench 41 and the source trench 42 Type silicon carbide layer 24 may serve as an n-type source region of a silicon carbide device.
  • the gate 27 located in the gate trench 41, the gate 27 is isolated from the second n-type silicon carbide layer 22 by the first insulating layer 26, and the material of the first insulating layer 26 can be silicon oxide, silicon nitride, oxynitride At least one of silicon, aluminum oxide and hafnium oxide, and the material of the gate 27 can be at least one of conductive polysilicon, titanium, nickel, copper, aluminum, silver, gold, titanium nitride and tungsten; the gate 27
  • the second insulating layer 28 is isolated from the p-type silicon carbide layer 23 and the third n-type silicon carbide layer 24.
  • the material of the second insulating layer 28 can be among silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide and hafnium oxide. At least one of them can also be other insulating mediums with high dielectric constant.
  • the thickness of the first insulating layer 26 may be the same as that of the second insulating layer 28 , and the material of the first insulating layer 26 may be the same as the material of the second insulating layer 28 , whereby the first insulating layer 26 may be the same as the second insulating layer 28 . Formed in the same manufacturing process step; the thickness of the first insulating layer 26 may also be greater than the thickness of the second insulating layer 28 , which can protect the gate electrode 27 in the gate trench 41 from being easily broken down.
  • the material of the third insulating layer 30 can be at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide and hafnium oxide, and the material of the source electrode 29 can be conductive polysilicon, titanium, nickel, copper, aluminum, At least one of silver, gold, titanium nitride and tungsten.
  • the material of the third insulating layer 30 may be the same as that of the first insulating layer 26 , so that the third insulating layer 30 and the first insulating layer 26 may be formed in the same manufacturing process step, thereby simplifying the manufacturing process of the silicon carbide device.
  • the width of the source trench 42 may be greater than that of the gate trench 41 , so that the first insulating layer 26 in the gate trench 41 can be more easily formed, so as to simplify the manufacturing process of the silicon carbide device of the present application.
  • a p-type well region 31 located in the second n-type silicon carbide layer 22 and located at the bottom position of the source trench 42 is connected to the source electrode 29 at the bottom position of the source trench 42 .
  • the p-type well region 31 and the second n-type silicon carbide layer 22 form a pn junction structure, increase the electric field near the bottom of the source trench, and limit the highest electric field in the silicon carbide device to the pn junction below the source trench 42 , the gate 27 in the protection gate trench 41 is not easily broken down, and the withstand voltage of the device is improved.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本申请公开了一种碳化硅器件，包括：位于所述碳化硅衬底内且交替间隔设置的栅极沟槽和源极沟槽；位于栅极沟槽的栅极，栅极通过第一绝缘层与第二n型碳化硅层隔离，栅极通过第二绝缘层与p型半导体层和第三n型半导体层隔离；位于源极沟槽内的源极，源极与p型碳化硅层和第三n型碳化硅层连接，源极通过第三绝缘层与源极沟槽的侧壁位置处的第二n型碳化硅层隔离；位于第二n型碳化硅层内且位于源极沟槽底部位置处的p型阱区，p型阱区与源极在源极沟槽的底部位置相连接。本申请可以降低栅极被击穿的风险，并提高碳化硅器件的耐压。

Description

碳化硅器件
本申请要求在2020年11月16日提交中国专利局、申请号为202011280134.5的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请属于半导体器件技术领域，例如涉及一种碳化硅器件。
背景技术
碳化硅具有不同于传统硅半导体材料的诸多特点，其能带间隙为硅的2.8倍,绝缘击穿场强为硅的5.3倍,因此在高压功率器件领域，碳化硅器件可以使用相对于硅材料更薄的外延层来到达传统硅器件相同的耐压水平，同时拥有更低的导通电阻。目前，利用碳化硅制备沟槽功率器件的主要问题在于，在器件运行时会有很大的电场施加在栅极沟槽内的栅介质层上，这使得栅极容易被击穿，影响了器件的耐压。
发明内容
本申请提供一种碳化硅器件，以降低栅极被击穿的风险，提高器件的耐压。
本申请提供了一种碳化硅器件，包括：
碳化硅衬底，所述碳化硅衬底包括依次层叠的第一n型碳化硅层、第二n型碳化硅层、p型碳化硅层和第三n型碳化硅层；
位于所述碳化硅衬底内且交替间隔设置的栅极沟槽和源极沟槽，所述栅极沟槽的底部和所述源极沟槽的底部均位于所述第二n型碳化硅层内；
位于所述栅极沟槽内的栅极，所述栅极通过第一绝缘层与所述第二n型碳化硅层隔离，所述栅极通过第二绝缘层与所述p型半导体层和所述第三n型半导体层隔离；
位于所述源极沟槽内的源极，所述源极与所述p型碳化硅层和所述第三n型碳化硅层连接，所述源极通过第三绝缘层与所述源极沟槽的侧壁位置处的所述第二n型碳化硅层隔离；
位于所述第二n型碳化硅层内且位于所述源极沟槽的底部位置处的p型阱区，所述p型阱区与所述源极在所述源极沟槽的底部位置相连接。
可选的，所述栅极沟槽的深度与所述源极沟槽的深度相同。
可选的，所述源极沟槽的宽度大于所述栅极沟槽的宽度。
可选的，所述第一绝缘层的厚度大于所述第二绝缘层的厚度。
可选的，所述第一绝缘层为氧化硅、氮化硅、氮氧化硅、氧化铝和氧化铪中的至少一种。
可选的，所述第二绝缘层为氧化硅、氮化硅、氮氧化硅、氧化铝和氧化铪中的至少一种。
可选的，所述第三绝缘层为氧化硅、氮化硅、氮氧化硅、氧化铝和氧化铪中的至少一种。
可选的，所述栅极为导电性多晶硅、钛、镍、铜、铝、银、金、氮化钛和钨中的至少一种。
可选的，所述源极为导电性多晶硅、钛、镍、铜、铝、银、金、氮化钛和钨中的至少一种。
本申请的碳化硅器件，首先，源极沟槽下方的p型阱区可以增加源极沟槽底部附近的电场，把最高电场限定在源极沟槽底部的pn结处，保护栅极沟槽内的栅极不容易被击穿，并提高器件的耐压；其次，栅极沟槽的下部内采用更大厚度的第一绝缘层，可以进一步保护栅极不容易被击穿。
附图说明
图1是本申请提供的碳化硅器件的一个实施例的剖面结构示意图。
具体实施方式
以下将结合本申请实施例中的附图，完整地描述本申请的技术方案。应当理解，本申请所使用的诸如“具有”、“包含”以及“包括”等术语并不配出一个或多个其它元件或其组合的存在。同时，为清楚地说明本申请的具体实施方式，说明书附图中所列示意图，放大了本申请所述的层和区域的厚度，且所列图形大小并不代表实际尺寸。
图1是本申请提供的碳化硅器件的一个实施例的剖面结构示意图，如图1所示，本申请的碳化硅器件包括碳化硅衬底20，碳化硅衬底20包括依次层叠的第一n型碳化硅层21、第二n型碳化硅层22、p型碳化硅层23和第三n型碳化硅层24，第一n型碳化硅层21作为碳化硅器件的n型漏区。
位于碳化硅衬底20内且交替间隔设置的栅极沟槽41和源极沟槽42，栅极沟槽41的底部和源极沟槽42的底部均位于第二n型碳化硅层22内。栅极沟槽41和源极沟槽42的数量由所设计的碳化硅器件的规格确定，本申请实施例中仅示例性的示出了一个栅极沟槽41和两个源极沟槽42。栅极沟槽41的深度与源极沟槽42的深度可以相同，由此，栅极沟槽41和源极沟槽42可以在同一步刻蚀工艺中同时形成。
位于栅极沟槽41和源极沟槽42之间的p型碳化硅层23可以作为碳化硅器件的p型体区，位于栅极沟槽41和源极沟槽42之间的第三n型碳化硅层24可以作为碳化硅器件的n型源区。
位于栅极沟槽41内的栅极27，栅极27通过第一绝缘层26与第二n型碳化硅层22隔离，第一绝缘层26的材料可以为氧化硅、氮化硅、氮氧化硅、氧化铝和氧化铪中的至少一种，栅极27的材料可以为导电性多晶硅、钛、镍、铜、铝、银、金、氮化钛和钨中的至少一种；栅极27通过第二绝缘层28与p型碳化硅层23、第三n型碳化硅层24隔离，第二绝缘层28的材料可以为氧化硅、氮化硅、氮氧化硅、氧化铝和氧化铪中的至少一种，也可以为其它高介电常数的绝缘介质。第一绝缘层26的厚度可以与第二绝缘层28的厚度相同，并且第 一绝缘层26的材料与第二绝缘层28的材料相同，由此第一绝缘层26可以与第二绝缘层28在同一制造工艺步骤中形成；第一绝缘层26的厚度也可以大于第二绝缘层28的厚度，这可以保护栅极沟槽41内的栅极27不容易被击穿。
位于源极沟槽42内的源极29，源极29与p型碳化硅层23和第三n型碳化硅层24连接，源极29通过第三绝缘层30与源极沟槽42的侧壁位置处的第二n型碳化硅层22隔离。第三绝缘层30的材料可以为氧化硅、氮化硅、氮氧化硅、氧化铝和氧化铪中的至少一种，源极29的材料可以为导电性多晶硅、钛、镍、铜、铝、银、金、氮化钛和钨中的至少一种。第三绝缘层30的材料可以与第一绝缘层26的材料相同，如此，第三绝缘层30和第一绝缘层26可在同一制造工艺步骤中形成，进而简化碳化硅器件的制备工艺。
源极沟槽42的宽度可以大于栅极沟槽41的宽度，这样可以更加容易的形成栅极沟槽41内的第一绝缘层26，以简化本申请的碳化硅器件的制造工艺。
位于第二n型碳化硅层22内且位于源极沟槽42的底部位置处的p型阱区31，p型阱区31与源极29在源极沟槽42的底部位置相连接。p型阱区31与第二n型碳化硅层22形成pn结结构，增加源极沟槽底部附近的电场，将碳化硅器件的内的最高电场限定在源极沟槽42下方的pn结处，保护栅极沟槽41内的栅极27不容易被击穿，并提高器件的耐压。

Claims (9)

  1. 碳化硅器件，包括：
    碳化硅衬底，所述碳化硅衬底包括依次层叠的第一n型碳化硅层、第二n型碳化硅层、p型碳化硅层和第三n型碳化硅层；
    位于所述碳化硅衬底内且交替间隔设置的栅极沟槽和源极沟槽，所述栅极沟槽的底部和所述源极沟槽的底部均位于所述第二n型碳化硅层内；
    位于所述栅极沟槽内的栅极，所述栅极通过第一绝缘层与所述第二n型碳化硅层隔离，所述栅极通过第二绝缘层与所述p型半导体层和所述第三n型半导体层隔离；
    位于所述源极沟槽内的源极，所述源极与所述p型碳化硅层和所述第三n型碳化硅层连接，所述源极通过第三绝缘层与所述源极沟槽的侧壁位置处的所述第二n型碳化硅层隔离；
    位于所述第二n型碳化硅层内且位于所述源极沟槽的底部位置处的p型阱区，所述p型阱区与所述源极在所述源极沟槽的底部位置相连接。
  2. 如权利要求1所述的碳化硅器件，其中，所述栅极沟槽的深度与所述源极沟槽的深度相同。
  3. 如权利要求1所述的碳化硅器件，其中，所述源极沟槽的宽度大于所述栅极沟槽的宽度。
  4. 如权利要求1所述的碳化硅器件，其中，所述第一绝缘层的厚度大于所述第二绝缘层的厚度。
  5. 如权利要求1所述的碳化硅器件，其中，所述第一绝缘层的材料为氧化硅、氮化硅、氮氧化硅、氧化铝和氧化铪中的至少一种。
  6. 如权利要求1所述的碳化硅器件，其中，所述第三绝缘层的材料为氧化硅、氮化硅、氮氧化硅、氧化铝和氧化铪中的至少一种。
  7. 如权利要求1所述的碳化硅器件，其中，所述第二绝缘层的材料为氧化硅、氮化硅、氮氧化硅、氧化铝和氧化铪中的至少一种。
  8. 如权利要求1所述的碳化硅器件，其中，所述栅极的材料为导电性多晶 硅、钛、镍、铜、铝、银、金、氮化钛和钨中的至少一种。
  9. 如权利要求1所述的碳化硅器件，其中，所述源极的材料为导电性多晶硅、钛、镍、铜、铝、银、金、氮化钛和钨中的至少一种。
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