CN105609409B - 在底部分上选择性地具有厚电介质的沟槽 - Google Patents

在底部分上选择性地具有厚电介质的沟槽 Download PDF

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CN105609409B
CN105609409B CN201510783169.3A CN201510783169A CN105609409B CN 105609409 B CN105609409 B CN 105609409B CN 201510783169 A CN201510783169 A CN 201510783169A CN 105609409 B CN105609409 B CN 105609409B
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trench
dielectric
dielectric layer
gate
sidewalls
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CN105609409A (zh
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河原秀明
杨红
C·B·科措恩
熊宇飞
刘云龙
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Texas Instruments Inc
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Texas Instruments Inc
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本申请案涉及在底部分上选择性地具有厚电介质的沟槽。一种制造半导体装置的方法(100)包含：蚀刻(101)具有顶表面的半导体衬底以形成具有侧壁及从所述顶表面延伸到所述半导体衬底中的底表面的沟槽。第一电介质材料的电介质衬里形成(102)于所述沟槽的所述底表面及侧壁上以给所述沟槽加衬里。第二电介质材料的第二电介质层经沉积(103)以至少局部填充所述沟槽。所述第二电介质层经局部蚀刻(104)以从所述沟槽的上部分选择性地移除所述第二电介质层，同时保存所述沟槽的下部分上的所述第二电介质层。使用提供至少是半导体的导电性的导电性的填充材料填充(105)所述沟槽。

Description

在底部分上选择性地具有厚电介质的沟槽
技术领域
揭示的实施例涉及用于半导体装置的电介质地填充的加衬里的沟槽结构。
背景技术
一些沟槽结构包含填充有掺杂半导体或电导体的电介质衬里。对于某些使用，举例来说，当沟槽用于沟槽场型金属氧化物半导体场效应晶体管(MOSFET)或沟槽栅型MOSFET(两者都在较大的操作电压下操作)时，所述电介质衬里需要支持较大的电场强度。维持用于此类沟槽结构的较高击穿电压的一种方式是增加电介质衬里的厚度或使用相对高折射率衬里材料。
发明内容
提供此发明内容以便以简化形式引入揭示的概念的简要选择，在下文包含提供的图式的具体实施方式中进一步描述揭示的概念的简要选择。此发明内容不希望限制所主张的标的物的范围。
揭示的实施例认识到，对于电介质地加衬里的沟槽结构，尽管增加电介质衬里的厚度或使用相对高折射率衬里材料会升高沟槽电介质可维持的操作电压，但对于一些装置存在折衷。举例来说，对于沟槽栅型MOSFET及沟槽场板型平面栅MOSFET，在击穿电压与归因于沟槽电介质衬里与衬底材料(举例来说，硅)之间的电荷平衡的导通状态电阻之间存在折衷。通常，对于电荷平衡改进，减小的电介质(举例来说，氧化物)厚度为优选的，但可尤其在沟槽底部拐角处引起可靠性或高E场问题。增加的电介质厚度可减小此类风险，但引入保持用于合适击穿电压的电荷平衡的难题。揭示的沟槽结构包含仅在沟槽的底部处包括第一电介质材料(举例来说，氧化硅)第二电介质材料(举例来说，SiN)两者的常规电介质沟槽衬里以仅在沟槽的底部处增加总电介质厚度。
附图说明
现在将参考不一定按比例绘制的附图，其中：
图1为展示根据实例实施例的用于制造半导体装置的实例方法中的步骤的流程图，所述方法包含形成在其底部分上选择性地具有厚电介质的沟槽。
图2A为常规沟槽场板FET的横截面部分。
图2B为根据实例实施例的包含在其底部分上选择性地具有厚电介质的沟槽的揭示的沟槽场板FET的横截面部分。
图2C为根据实例实施例的包含在经过外延层延伸到下层衬底中的其底部分上选择性地具有厚电介质的揭示的沟槽场板FET的横截面部分。
图2D为常规沟槽栅FET的横截面部分。
图2E为根据实例实施例的包含在其底部分上选择性地具有厚电介质的沟槽的揭示的沟槽栅FET的横截面部分。
图3A描绘根据实例实施例的包含多个晶体管单元的实例沟槽栅MOSFET的横截面视图，所述晶体管单元各自包含在其底部分上选择性地具有厚电介质的揭示的沟槽。
图3B描绘根据实例实施例的包含多个有源晶体管单元的实例平面栅沟槽MOSFET的横截面视图，所述有源晶体管单元各自包含在其底部分上选择性地具有厚电介质的揭示的沟槽。
具体实施方式
参考图式描述实例实施例，其中相同参考数字用以标示类似或等效元件。说明的动作或事件的次序不应被认为具限制性，因为一些动作或事件可以不同次序及/或与其它动作或事件同时发生。此外，可无需一些说明的动作或事件来实施根据本发明的方法。
图1为展示根据本发明的实例实施例的用于制造半导体装置的实例方法100中的步骤的流程图，其包含形成在其底部分上选择性地具有厚电介质的沟槽。步骤101包括蚀刻具有顶表面的半导体衬底以形成具有侧壁及从所述顶表面延伸到所述半导体衬底中的底表面的沟槽。所述衬底可为块状半导体(举例来说，硅或包括硅)上的外延层，但也可为单独的块状半导体。沟槽深度大体上为从2μm到50μm。
步骤102包括在沟槽的底表面及侧壁上形成包括第一电介质材料的电介质衬里以给所述沟槽加衬里。可例如通过低压化学气相沉积(LPCVD))使电介质衬里热生长或沉积。
步骤103包括沉积包括第二电介质材料的第二电介质层以至少局部填充沟槽。沟槽填充任选地为完整沟槽填充。第二电介质材料一般具有k值≥5。氮化硅为第二电介质材料的实例，其它实例包含SiON、SiC或其它电介质材料(例如HfO2、ZrO2、Al2O3及HfSiO3)。
步骤104包括局部蚀刻第二电介质层以从沟槽的上部分选择性地移除第二电介质层，同时保留沟槽的下部分上的第二电介质层。湿或干(举例来说，等离子)处理可用于此蚀刻回过程，且通常不需要掩蔽图案。不具有第二电介质层的沟槽的上部分的长度大体上≥具有第二电介质层的沟槽的下部分的长度。不具有第二电介质层的上部分与具有第二电介质层的下部分的典型长度比率>10:1。
步骤105包括使用提供至少是半导体的导电性的导电性的填充材料填充沟槽。在半导体填充材料的情况下，可稍后在过程中掺杂所述半导体。填充材料的实例包含多晶硅及硅化物(例如硅化钨)。填充材料通常经沉积且接着经平面化以(例如)通过化学机械研磨(CMP)移除过多的填充材料。接着完成制造过程，包含植入、掩蔽水平、沉积及形成栅极、源极、漏极、互连件及接合垫的扩散，及钝化。
图2A为形成于n+衬底196上的外延半导体层(外延层)180上的常规沟槽场板FET的横截面部分。所展示的FET包含在外延层180的顶表面180a上的栅电介质271上的栅电极270。展示硅化物层272在栅电极270上，当栅电极270包括多晶硅时通常将存在硅化物层272。展示FET之上的外延层180的表面180a覆盖有电介质膜190。展示沟槽包含包括由填充物材料170填充的第一电介质材料的电介质衬里140。展示源极250及本体区域260形成于外延层180中。展示源极金属层195接触源极250、本体区域260及填充物材料170。
图2B为根据实例实施例的包含在其底部分上选择性地具有厚电介质的沟槽的揭示的沟槽场板FET的横截面部分。展示包括第二电介质材料的第二电介质层141仅在沟槽的下部分上。再次展示源极金属层195接触源极250、本体区域260及填充物材料170。
图2C为根据实例实施例的包含在经过外延层180延伸到下层衬底196中的其底部分上选择性地具有厚电介质的沟槽的揭示的沟槽场板FET的横截面部分。再次展示源极金属层195接触源极250、本体区域260及填充物材料170。
图2D为常规沟槽栅FET的横截面部分。展示FET包含填充物材料170作为其栅电极及电介质衬里140作为其栅电介质层。展示源极150及本体区域160形成于外延层180中。展示源极金属层195接触源极150及本体区域160。尽管下文描述的图2D或图2E中未展示，但通过另一金属(或多晶硅)图案经过图3A中展示的在填充物材料170之上的电介质膜190中切割的通孔接触填充物材料170。
图2E为根据实例实施例的包含在其底部分上选择性地具有厚电介质的沟槽的揭示的沟槽栅FET的横截面部分。展示包括第二电介质材料的第二电介质层141仅在沟槽的下部分上。
图3A描绘根据实例实施例的展示为包含各自包含在其底部分上选择性地具有厚电介质的沟槽的多个晶体管单元(单元)110的n沟道装置(NMOS)的实例沟槽栅MOSFET 300(沟槽栅MOSFET 300)的横截面视图。尽管文本中通常描述为NMOS装置，但揭示的MOSFET装置也可为PMOS。此外，在实际的装置中，可能存在并联电连接的成百上千个单元。展示的单元110中的任一者的沟槽部分可用于沟槽隔离结构、场板或作为给定半导体装置的沟槽电容器。尽管图3A中未展示，但提供栅接触件及到栅接触件的金属连接件以提供到单元110的栅电极170的电接触。
沟槽栅MOSFET 100形成于衬底196(展示为n+衬底，其提供在其上具有提供n-漏极漂移区域的n-外延半导体层180的装置的漏极)上。n+衬底196/半导体层180可包括硅；替代地，n+衬底196/外延半导体层180可包括其它半导体材料，例如锗、碳化硅、氮化镓、砷化镓等等。p-掺杂本体区域160形成于半导体层180中，其中n+掺杂源极区域150形成于本体区域160内的半导体层180的表面180a处。
导体填充的电介质衬里的栅沟槽170/140为相应单元110提供栅结构。使用包括用作栅电介质的第一电介质材料的电介质膜140(或衬里)给栅沟槽壁加衬里。所述沟槽在其底部上选择性地包含由展示的第二电介质层141提供的厚电介质。在此实施例中，电介质膜140可为二氧化硅。替代地，电介质膜140可包括其它电介质材料，例如氮化硅或其它电介质。电介质衬里的沟槽填充有多晶硅或其它导电材料(例如钨)以形成单元110的栅电极170。
可从外延半导体层180的表面180a蚀刻栅沟槽。在此实施例中，可与图案步骤及接着蚀刻步骤同时处理五个描绘的栅沟槽。在此实施例中的沟槽栅MOSFET 300可由用于常规沟槽MOSFET的过程流形成，例如包含离子植入或掺杂剂扩散以形成本体区域160及源区域150。
展示半导体层180的表面180a覆盖有电介质膜190。在此实施例中，电介质膜190可包括氧化硅或氧氮化硅。替代地，电介质膜190可包括如半导体装置制造领域中已知的其它电介质材料。
如图3A中展示，单元110还包含源极/本体接触孔112，源极/本体接触孔112由穿过源极区域150的栅沟槽与本体区域160之间的半导体层180的顶表面180a形成。尽管图3A中展示源极/本体接触孔112延伸到半导体层180中，但揭示的实施例还包含具有平面源极/本体接触件的选项。
一旦使用展示为源极金属层195的电导体填充，接触孔112就将源极区域150短接到单元110中的每一者的本体区域160。源极金属层195可更通常为任何导电材料(例如钨或掺杂多晶硅)，所述电导体材料在操作中通常为接地。
展示图3A中的沟槽栅MOSFET 300的n+衬底196的背侧196a覆盖有单独的金属膜197。此金属膜197形成到n+衬底196的低电阻欧姆接触，其提供漏极区域，其在操作中连接到Vds。替代地，可省略金属膜197且n+衬底196的背侧196a可替代地安装到引线框的裸片垫。有源晶体管单元110的栅电极170由连接到装置封装的栅电极端子的另一金属或掺杂多晶元件(未展示)分别系在一起。
当沟槽栅MOSFET 300为增强装置时，假如装置在栅极与源极之间被适当偏置，反沟道形成于源极区域150与漏极漂移区域180'之间的台面区域中，邻近给沟槽壁加衬里的电介质膜140。当在源极端子与漏极端子之间建立适当电势差时，电流垂直流过沟道。如果使用n型掺杂剂(PMOS)更重度掺杂本体区域时，通过空穴将电流载运穿过沟道；如果使用p型掺杂剂(NMOS)更重度掺杂本体区域(如图3A中展示)。
图3B描绘根据实例实施例的包含各自包含在其底部分上选择性地具有厚电介质的沟槽的多个晶体管单元(单元)210的实例平面栅沟槽MOSFET装置350(平面栅沟槽MOSFET350)的简化横截面视图。平面栅沟槽MOSFET 350包含具有由电介质衬里140(包括在沟槽的底部上选择性地具有由展示的第二电介质层141提供的厚电介质的第一电介质材料)加衬里的多晶硅填充物240的电介质衬里的沟槽以在单元210的栅堆叠的两侧上提供场板(有时称为“RESURF沟槽”)。展示单元210具有包括栅电介质271上的栅电极270的栅堆叠。尽管图3B中未展示，但栅接触件及金属连接件经提供以提供到单元210的栅电极270的电接触。n+掺杂源极区域250在栅堆叠与沟槽之间的半导体层180的顶表面180a上，且衬底196被展示为n+衬底，所述n+衬底为在其上具有提供漏极漂移区域180'的外延层180的装置提供漏极。尽管针对单元210中的每一者展示单一栅，但相应单元210也可具有分裂双栅。在此实施例中的平面栅沟槽MOSFET 350可通过用于常规MOSFET的过程流形成，例如包含离子植入或扩散以形成p掺杂本体区域260及源极区域250。
表面180a包含其上的电介质层190。在此实施例中，电介质膜材料可为二氧化硅。替代地，电介质膜190可包括其它电介质材料，例如氮化硅或其它电介质。展示源极金属层195接触电介质衬里的沟槽中的多晶硅填充物240以及邻近的源极250及本体区域260。
有源晶体管单元210的栅电极270由通常连接到装置封装的栅极端子的另一金属或多晶硅元件单独系在一起。当平面栅沟槽MOSFET 350为增强装置时，假如装置被适当偏置，则反沟道形成于栅极270之下的本体区域260中。当在源极与漏极之间建立电场梯度时，电流流过沟道。如果使用n型掺杂剂(PMOS)更重度掺杂本体区域，则通过空穴将电流载运穿过沟道；如果使用p型掺杂剂(NMOS)更重度掺杂本体区域，则通过电子将电流载运穿过沟道。
揭示的沟槽结构的优点包含在不降低沟槽的底部处的可靠性或高E场问题的情况下增强特定导通电阻(Rsp)-击穿电压(BV)折衷的电荷平衡。作为实例，对于沟槽场MOSFET，输出电容(Coss)可减小大于20％而无Rsp、BV或阈值电压(Vt)中的任何性能降低。对于沟槽栅FET，揭示的沟槽减小栅极到漏极电荷(Qgd)50％，且Coss可减小10％，同时保持相同的Rsp、BV及Vt范围。
此外，揭示的沟槽增加沟槽栅FET的衬底(举例来说，硅)与填充材料(举例来说，多晶硅)之间的完整性，且提高沟槽底部处的沟槽电容器的操作电压(Vop)，在沟槽底部处由于更高电E场而通常关注可靠性。如上文注意，揭示的沟槽还可用于隔离沟槽，举例来说，用于浅沟槽隔离(STI)及深沟槽隔离。
揭示的实施例可用以形成半导体裸片，所述半导体裸片可被集成到多种组合件流中以形成多种不同装置及相关产品。所述半导体裸片可包含其中的各种元件及/或其上的各种层(包含势垒层、电介质层、装置结构、有源元件及无源元件(包含源极区域、漏极区域、位线、基极、发射极、集电极、导线、导电通孔等等))。此外，所述半导体裸片可由多种过程构成，包含双极、绝缘栅双极晶体管(IGBT)、CMOS、BiCMOS及MEMS。
本发明涉及的所属领域的技术人员将了解，在所主张的发明的范围内，许多其它实施例及实施例的变化为可能的，且在不背离本发明的范围的情况下可对所描述的实施例作出进一步添加、删除、替代及修改。

Claims (14)

1.一种制造半导体装置的方法，其包括：
蚀刻具有顶表面的半导体衬底以形成具有侧壁及从所述顶表面延伸到所述半导体衬底中的底表面的沟槽；
形成包括在所述沟槽的所述底表面及所述侧壁上的第一电介质材料的电介质衬里以给所述沟槽加衬里；
在形成所述电介质衬里之后，在所述电介质衬里上沉积包括第二电介质材料的第二电介质层以至少局部填充所述沟槽；
局部蚀刻所述第二电介质层以从所述沟槽的上部分选择性地移除所述第二电介质层，同时保留在所述沟槽的下部分上的所述第二电介质层，并且同时保留在所述沟槽的所述上部分和所述沟槽的所述下部分中的所述电介质衬里；以及
使用提供至少是半导体的导电性的导电性的填充材料填充所述沟槽，其中所述电介质衬里给所述沟槽中的所述填充材料加衬里。
2.根据权利要求1所述的方法，其中所述沟槽的所述上部分的长度大于或等于(≥)所述沟槽的所述下部分的长度。
3.根据权利要求1所述的方法，其中所述沟槽为与平面栅金属氧化物半导体场效应晶体管MOSFET相关联的场板，其中所述平面栅与所述场板相分离。
4.根据权利要求1所述的方法，其中所述沟槽为用于沟槽栅金属氧化物半导体场效应晶体管MOSFET的沟槽栅。
5.根据权利要求1所述的方法，其中所述沟槽为用于所述半导体装置的沟槽隔离结构。
6.根据权利要求1所述的方法，其中所述沟槽为用于所述半导体装置的沟槽电容器。
7.根据权利要求1所述的方法，其中所述半导体衬底包括块状衬底材料上的外延层，且其中所述沟槽延伸到所述块状衬底材料中。
8.根据权利要求1所述的方法，其中所述第二电介质材料具有k值≥5。
9.一种用于构造半导体装置的方法，其包括：
蚀刻半导体衬底以形成沟槽，所述沟槽具有侧壁及底表面；
形成包括在所述沟槽的所述底表面及所述侧壁上的第一电介质材料的电介质衬里以给所述沟槽加衬里；
在形成所述电介质衬里之后，在所述电介质衬里上沉积包括第二电介质材料的第二电介质层以至少局部填充所述沟槽；以及
局部蚀刻所述第二电介质层以从所述沟槽的上部分选择性地移除所述第二电介质层，同时保留在所述沟槽的下部分上的所述第二电介质层，其中在局部填充所述沟槽之后所述电介质衬里在所述第二电介质层的顶表面之上沿着所述沟槽的所述侧壁延伸；以及
在所述电介质衬里在所述第二电介质层的所述顶表面之上沿着所述沟槽的所述侧壁延伸的同时，使用多晶硅填充所述沟槽，其中所述电介质衬里给所述沟槽中的所述多晶硅加衬里。
10.根据权利要求9所述的方法，其中所述沟槽为与平面栅金属氧化物半导体场效应晶体管MOSFET相关联的场板，其中所述平面栅与所述场板相分离。
11.根据权利要求9所述的方法，其中所述沟槽为用于沟槽栅金属氧化物半导体场效应晶体管MOSFET的沟槽栅。
12.根据权利要求9所述的方法，其中所述沟槽为用于所述半导体装置的沟槽隔离结构。
13.根据权利要求9所述的方法，其中所述沟槽为用于所述半导体装置的沟槽电容器。
14.一种用于构造半导体装置的方法，其包括：
通过以下步骤形成沟槽场板：
蚀刻半导体衬底以形成沟槽，所述沟槽具有侧壁及底表面；
形成包括在所述沟槽的所述底表面及所述侧壁上的第一电介质材料的电介质衬里以给所述沟槽加衬里；
沉积包括第二电介质材料的第二电介质层以至少局部填充所述沟槽；
局部蚀刻所述第二电介质层以从所述沟槽的上部分选择性地移除所述第二电介质层，同时保留在所述沟槽的下部分上的所述第二电介质层，其中在局部蚀刻之后所述电介质衬里在所述第二电介质层的顶表面之上沿着所述沟槽的所述侧壁延伸；以及
在所述电介质衬里在所述第二电介质层的所述顶表面之上沿着所述沟槽的所述侧壁延伸的同时，使用多晶硅填充所述沟槽，其中所述电介质衬里给所述沟槽中的所述多晶硅加衬里；以及
在栅电介质上形成栅电极，所述栅电介质在所述半导体衬底的顶表面上，其中在所述栅电极和所述沟槽中的所述多晶硅之间存在空间。
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