WO2022098107A1 - Procédé de fabrication d'un trou d'interconnexion traversant le silicium ne comprenant pas de vides - Google Patents

Procédé de fabrication d'un trou d'interconnexion traversant le silicium ne comprenant pas de vides Download PDF

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Publication number
WO2022098107A1
WO2022098107A1 PCT/KR2021/015859 KR2021015859W WO2022098107A1 WO 2022098107 A1 WO2022098107 A1 WO 2022098107A1 KR 2021015859 W KR2021015859 W KR 2021015859W WO 2022098107 A1 WO2022098107 A1 WO 2022098107A1
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Prior art keywords
silicon
hole
etch
stop layer
electrode
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PCT/KR2021/015859
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English (en)
Korean (ko)
Inventor
서수정
이세원
김윤식
윤주봉
임천
배규태
Original Assignee
성균관대학교산학협력단
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Publication of WO2022098107A1 publication Critical patent/WO2022098107A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]

Definitions

  • the present invention relates to a method of manufacturing a through-silicon electrode capable of electrically connecting multilayer semiconductor devices by providing an electrode penetrating through a silicon substrate.
  • a method of forming a through-hole in a silicon substrate through an etching process and then filling the through-hole with a metal through a plating process is mainly applied.
  • a method of manufacturing a through-silicon electrode includes a first step of forming an etch-stop layer on a lower surface of a silicon substrate; a second step of forming a through hole in the silicon substrate through a photolithography process; a third step of sequentially forming a metal layer and a protective layer on the lower surface of the etch-stop layer and then removing a portion of the etch-stop layer corresponding to the through hole; and a fourth step of forming a via electrode in the through hole by growing a plating film filling the inside of the through hole from the metal layer through an electrolytic plating process.
  • the etch-stop layer may be formed of silicon oxide or silicon nitride.
  • the etch-stop layer is formed by oxidizing the silicon substrate to form a silicon oxide film on the entire surface of the silicon substrate, and then removing portions of the silicon oxide film on the upper surface and the side surface of the silicon substrate.
  • the etch-stop layer may remain during the second step.
  • a photoresist layer may be formed on the lower surface of the etch stop layer during the second step.
  • the metal layer may be formed of a metal having electrical conductivity and have a thickness of about 2000 to 10000 ⁇ .
  • the metal layer may be formed through an electroless plating process or a sputtering process.
  • the etch-stop layer may be formed of silicon oxide.
  • a portion of the etch-stop layer corresponding to the through-hole is removed by injecting a buffered oxide etchant (BOE) into the through-hole. can do.
  • BOE buffered oxide etchant
  • the via electrode may be formed by growing an electrolytic plating layer of copper inside the through hole.
  • the via electrode may directly contact the silicon substrate in the through hole.
  • a method of manufacturing a through-silicon electrode includes a first step of forming an etch-stop layer on a lower surface of a silicon substrate; a second step of forming a through hole in the silicon substrate through a photolithography process; a third step of forming a silicon oxide film on the inner surface of the through hole and the upper surface of the silicon substrate; a fourth step of sequentially forming a metal layer and a protective layer on the lower surface of the etch-stop layer and then removing a portion of the etch-stop layer corresponding to the through hole; and a fifth step of forming a via electrode in the through hole by growing a plating film filling the inside of the through hole from the metal layer through an electrolytic plating process.
  • the etch-stop layer may be formed of silicon oxide, and in this case, the silicon oxide layer may be formed to have a greater thickness than the etch-stop layer.
  • the etch stop layer may be formed to a thickness of 1000 to 2000 ⁇ , and the silicon oxide layer may be formed to a thickness of 5000 to 40000 ⁇ .
  • the silicon oxide layer may remain inside the through hole and on the upper surface of the silicon substrate during the fourth step.
  • the fifth step comprises: forming the via electrode by growing a plating film filling the inside of the through hole from the metal layer through an electrolytic plating process; removing the remaining portions of the protective film, the metal layer, and the etch-stop layer formed on the lower surface of the silicon substrate; and removing the via electrode portion protruding from the upper surface of the silicon substrate.
  • the silicon oxide layer formed on the upper surface of the silicon substrate may remain while the via electrode portion protruding from the upper surface of the silicon substrate is removed.
  • the silicon oxide layer formed on the top surface of the silicon substrate may be removed together.
  • the silicon oxide layer may remain between the via electrode and the silicon substrate in the through hole.
  • the via electrode is formed by growing an electrolytic plating film from the metal layer covering the entire area of the through-hole, the formation of a void in the via electrode can be prevented.
  • the via electrode when the via electrode is formed in a state in which the silicon oxide film remains inside the through hole, the insulating property between the silicon substrate and the via electrode can be improved, and as a result, restrictions on the material of the silicon substrate are reduced. can be reduced
  • FIG. 1 is a flowchart illustrating a method of manufacturing a through-silicon electrode according to an embodiment of the present invention.
  • 2A to 2E are process diagrams for explaining a method of manufacturing the TSV shown in FIG. 1 .
  • FIG. 3 is a flowchart illustrating a method of manufacturing a through-silicon electrode according to another embodiment of the present invention.
  • 4A to 4F are process diagrams for explaining the method of manufacturing the TSV shown in FIG. 3 .
  • FIG. 1 is a flowchart illustrating a method of manufacturing a silicon through-electrode according to a first embodiment of the present invention
  • FIGS. 2A to 2E are process diagrams for explaining the method of manufacturing the silicon through-electrode shown in FIG. 1 .
  • the first step of forming the etch-stop layer 120 on the lower surface of the silicon substrate 110 the first step of forming the etch-stop layer 120 on the lower surface of the silicon substrate 110 .
  • S110 a second step (S120) of forming a through hole 111 in the silicon substrate 110 through a photolithography process;
  • step (S130) After sequentially forming the metal layer 140 and the protective layer 150 on the lower surface of the etch stop layer 120 , a third part of the etch stop layer 120 corresponding to the through hole 111 is removed.
  • the etch-stop layer 120 may be formed to cover the lower surface of the surfaces of the silicon substrate 110, and function as an etch-stop layer in the subsequent photolithography process. It may be formed of a material that can be
  • the etch stop layer 120 may be formed of silicon oxide or silicon nitride.
  • the etch-stop layer 120 when the etch-stop layer 120 is formed of silicon oxide, as shown in FIG. 2A , the silicon substrate 110 is oxidized to form silicon on the entire surface of the silicon substrate 110 . After the oxide film 120a is formed, the etch stop layer 120 can be formed by removing the portion of the silicon oxide film 120a on the upper surface and the side surface of the silicon substrate 110 using a buffered oxide etchant (BOE) or the like. there is.
  • BOE buffered oxide etchant
  • the etch-stop layer 120 may be formed by forming a silicon oxide film only on the lower surface of the silicon substrate 110 by a method such as PECVD.
  • the etch stop layer 120 may be formed to a thickness of about 1000 to 2000 ⁇ .
  • a through hole 111 may be formed in the silicon substrate 110 through a photolithography process using the photoresist pattern 130a as a mask.
  • the etch-stop layer 120 is not etched, and may remain under the through-hole 111 .
  • a photoresist film 130b is formed on the lower surface of the etch-stop layer 120 . can be further formed.
  • the photoresist pattern 130a and the photoresist layer 130b may be removed.
  • the metal layer 140 for electrolytic plating on the lower surface of the etch stop layer 120 and a protective layer for protecting the metal layer 140 ( 150) may be sequentially formed, and then a portion corresponding to the through hole 111 of the etch-stop layer 120 may be removed.
  • the metal layer 140 may be formed of a metal having electrical conductivity to a thickness of about 2000 to 10000 ⁇ , and the formation method thereof is not particularly limited.
  • the metal layer 140 may be formed through an electroless plating process or a sputtering process.
  • the metal layer 140 when the metal layer 140 is formed through an electroless plating process, an electroless plating seed layer is formed on the lower surface of the etch stop layer 120 and then the seed layer is formed.
  • An electroless plating film can be formed through the reduction reaction used.
  • the metal layer 140 may be formed of copper (Cu).
  • a polymer or photoresist material is formed on the lower surface of the metal layer 140 .
  • the reporting layer 140 may be formed to a thickness of about 70 to 100 ⁇ m.
  • a buffered oxide etchant (BOE) or the like is injected into the through-hole 111 to form the through-hole ( 111) can be removed.
  • a coating film is grown from the surface of the metal layer 140 through an electroplating process to form a via electrode 160 filling the through hole 111. can do.
  • the via electrode 160 may be formed of copper (Cu).
  • the silicon through-electrode is formed by removing the remaining portions of the protective film 150 , the metal layer 140 , and the etch-stop layer 120 formed on the lower surface of the silicon substrate 110 through physical processing or chemical etching process.
  • a portion of the via electrode 1260 protruding from the upper surface of the silicon substrate 110 may be additionally removed through physical processing or a chemical etching process.
  • the via electrode 160 may directly contact the silicon substrate 110 inside the through hole 111 . Accordingly, in order to prevent a current leaking from the via electrode 160 to the silicon substrate 110 , the silicon substrate 110 may be formed of a silicon material having a relatively high resistance.
  • FIG. 3 is a flowchart illustrating a method of manufacturing a silicon through electrode according to a second exemplary embodiment of the present invention
  • FIGS. 4A to 4F are process diagrams for explaining the method of manufacturing the silicon through electrode shown in FIG. 3 .
  • the first step of forming the etch-stop layer 220 on the lower surface of the silicon substrate 210 is (S210); a second step (S220) of forming a through hole 211 in the silicon substrate 210 through a photolithography process; a third step (S230) of forming a silicon oxide layer 225 on the inner surface of the through hole 211 and the upper surface of the silicon substrate 210; After sequentially forming a metal layer 240 and a protective layer 250 on the lower surface of the etch stop layer 220 , a fourth portion of the etch stop layer 220 corresponding to the through hole 211 is removed step (S240); and forming a via electrode 260 filling the inside of the through hole 211 from the metal layer 240 through an electroplating process (S440).
  • the first step ( S210 ) and the second step ( S220 ) are through silicon according to the first embodiment of the present invention described with reference to FIGS. 1 and 2A to 2E . Since the first step ( S110 ) and the second step ( S120 ) of the electrode manufacturing method are substantially the same, respectively, overlapping detailed descriptions thereof will be omitted.
  • an inner surface of the through hole 211 and an upper surface of the silicon substrate 210 are oxidized by oxidizing the exposed surface of the silicon substrate 210 .
  • the silicon oxide layer 225 may be formed thereon.
  • the silicon oxide layer 225 when the etch-stop layer 220 is formed of silicon oxide, the silicon oxide layer 225 may be formed to have a greater thickness than the etch-stop layer 220 . In this case, even after removing the portion of the etch-stop layer 220 corresponding to the through-hole 211 in the fourth step (S240), the inner surface of the through-hole 211 and the silicon substrate 210 The silicon oxide layer 225 may remain on the upper surface, and as a result, the insulating property between the via electrode 260 and the silicon substrate 210 may be improved.
  • the silicon substrate 210 may be formed of not only a silicon material having a relatively high resistance value but also a silicon material having a relatively low resistance value.
  • the silicon oxide layer 225 when the etch-stop layer 220 is formed of silicon oxide, the silicon oxide layer 225 may be formed to have a thickness equal to or smaller than that of the etch-stop layer 220 .
  • a scallop is inevitably formed on the wall surface of the through hole 211 .
  • the etch stop layer 220 is formed on the wall surface of the through hole 211 .
  • the silicon oxide layer 225 may be formed to a thickness of about 5000 to 40,000 ⁇ .
  • the fourth step (S240) is substantially the same as the third step (S130) of the method for manufacturing a through-silicon electrode according to the first embodiment of the present invention described with reference to FIGS. 1 and 2A to 2E. A redundant detailed description thereof will be omitted, and differences will be mainly described.
  • a buffered oxide etchant (BOE) or the like is injected into the through-hole 211 to the through-hole ( The portion corresponding to 211 may be removed, and in this case, as described above, since the thickness of the silicon oxide layer 225 is thicker than that of the etch-stop layer 220 , the portion corresponding to the through hole 211 may be removed. Even when the etch-stop layer 220 is completely removed, the silicon oxide layer 225 may remain on the inner surface of the through hole 211 and the upper surface of the silicon substrate 210 .
  • BOE buffered oxide etchant
  • the fifth step (S250) is substantially the same as the fourth step (S140) of the method for manufacturing a through-silicon electrode according to the first embodiment of the present invention described with reference to FIGS. 1 and 2A to 2E. A redundant detailed description thereof will be omitted, and differences will be mainly described.
  • the via electrode 260 formed on the top surface of the silicon substrate 210 is removed.
  • the silicon oxide layer 225 may remain.
  • the via electrode 260 portion protruding from the top surface of the silicon substrate 210 is removed through physical processing or chemical etching process, the silicon oxide film formed on the top surface of the silicon substrate 210 . (225) may be removed.
  • the via electrode 260 is disposed inside the through-hole 211 . It may not be in direct contact with the silicon substrate 110 . Accordingly, since insulation between the via electrode 260 and the silicon substrate 210 is secured by the silicon oxide film 225 , the silicon substrate 210 is not only a silicon material having a relatively high resistance value, but also relatively It may be formed of a silicon material having a low resistance value.
  • the via electrode is formed by growing an electrolytic plating film from the metal layer covering the entire area of the through-hole, the formation of a void in the via electrode can be prevented.
  • the via electrode when the via electrode is formed in a state in which the silicon oxide film remains inside the through hole, the insulating property between the silicon substrate and the via electrode can be improved, and as a result, restrictions on the material of the silicon substrate are reduced. can be reduced

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Est divulgué un procédé de fabrication d'un trou d'interconnexion traversant le silicium. Un procédé de fabrication d'un trou d'interconnexion traversant le silicium comprend : une première étape consistant à former une couche d'arrêt de gravure sur une surface inférieure d'un substrat de silicium ; une deuxième étape consistant à former un orifice traversant sur le substrat de silicium par l'intermédiaire d'un processus de gravure photographique ; une troisième étape consistant à retirer une partie de la couche d'arrêt de gravure correspondant à l'orifice traversant après la formation séquentielle d'une couche métallique et d'une couche protectrice sur une surface inférieure de la couche d'arrêt de gravure ; et une étape consistant à former une électrode de trou d'interconnexion à l'intérieur de l'orifice traversant en développant un film de placage remplissant l'orifice traversant à partir de la couche métallique par l'intermédiaire d'un processus d'électrodéposition.
PCT/KR2021/015859 2020-11-05 2021-11-04 Procédé de fabrication d'un trou d'interconnexion traversant le silicium ne comprenant pas de vides WO2022098107A1 (fr)

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KR10-2020-0146528 2020-11-05
KR1020200146528A KR102442256B1 (ko) 2020-11-05 2020-11-05 보이드가 없는 실리콘 관통전극의 제조방법

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Citations (6)

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JP2008532319A (ja) * 2005-03-02 2008-08-14 エンデヴコ コーポレイション 接合部分離バイア
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JP2009218302A (ja) * 2008-03-09 2009-09-24 Fujikura Ltd 半導体基板の電解めっき方法および電解めっき装置
JP2012253227A (ja) * 2011-06-03 2012-12-20 Shinko Electric Ind Co Ltd 配線基板及びその製造方法
JP2014095104A (ja) * 2012-11-07 2014-05-22 Toppan Printing Co Ltd めっきによる貫通孔の銅充填方法
JP2015153978A (ja) * 2014-02-18 2015-08-24 キヤノン株式会社 貫通配線の作製方法

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JP2007049103A (ja) * 2005-08-05 2007-02-22 Zycube:Kk 半導体チップおよびその製造方法、ならびに半導体装置
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JP5608605B2 (ja) * 2010-11-05 2014-10-15 新光電気工業株式会社 配線基板の製造方法
KR101239430B1 (ko) * 2011-07-22 2013-03-06 성균관대학교산학협력단 전해 연마를 이용한 기판의 평탄화 방법 및 이를 포함하는 반도체 소자의 제조 방법

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008532319A (ja) * 2005-03-02 2008-08-14 エンデヴコ コーポレイション 接合部分離バイア
KR20090013417A (ko) * 2007-08-01 2009-02-05 삼성전자주식회사 반도체 패키지, 이를 이용한 웨이퍼 스택 패키지 및 이의제조방법
JP2009218302A (ja) * 2008-03-09 2009-09-24 Fujikura Ltd 半導体基板の電解めっき方法および電解めっき装置
JP2012253227A (ja) * 2011-06-03 2012-12-20 Shinko Electric Ind Co Ltd 配線基板及びその製造方法
JP2014095104A (ja) * 2012-11-07 2014-05-22 Toppan Printing Co Ltd めっきによる貫通孔の銅充填方法
JP2015153978A (ja) * 2014-02-18 2015-08-24 キヤノン株式会社 貫通配線の作製方法

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