WO2022095484A1 - 半导体结构的形成方法及半导体结构 - Google Patents

半导体结构的形成方法及半导体结构 Download PDF

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Publication number
WO2022095484A1
WO2022095484A1 PCT/CN2021/103874 CN2021103874W WO2022095484A1 WO 2022095484 A1 WO2022095484 A1 WO 2022095484A1 CN 2021103874 W CN2021103874 W CN 2021103874W WO 2022095484 A1 WO2022095484 A1 WO 2022095484A1
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dummy
area
forming
substrate
functional
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PCT/CN2021/103874
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English (en)
French (fr)
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刘志拯
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长鑫存储技术有限公司
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Priority to US17/604,477 priority Critical patent/US20230101884A1/en
Publication of WO2022095484A1 publication Critical patent/WO2022095484A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76892—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0335—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

Definitions

  • the present disclosure relates to, but is not limited to, a method of forming a semiconductor structure and a semiconductor structure.
  • a plurality of pseudo-functional structures arranged at intervals are provided on one side of the functional structure to solve the problem of irregular patterns at the edge of the functional structure due to the optical proximity effect. Connection, the stability of a single pseudo-functional structure is not enough, and it is easy to deform, which will cause adverse effects on the semiconductor structure.
  • Embodiments of the present disclosure provide a method for forming a semiconductor structure and a semiconductor structure, which are beneficial to solve the problem of unstable pseudo-function structure.
  • a first aspect of the present disclosure provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a center region and dummy regions located on opposite outer sides of edges in a first direction of the center region, the center region including forming area and cutting areas located on opposite two outer sides of the edge of the forming area in the second direction; forming a plurality of core posts at intervals on the substrate, the core posts located in the central area spanning the forming area and the cutting area, each of the dummy areas is formed with at least one of the core pillars; an initial mask layer surrounding and covering the sidewalls of the core pillars is formed on the substrate; the initial mask layer is used to form several spaced-apart mask spacers in the forming area, and the initial mask layer in the dummy area is reserved as a ring-shaped spacer; the central area and the core column of the dummy area; using the mask spacer as a mask to etch a substrate to form a plurality of functional structures, and to use the annular
  • the process step of removing the initial mask layer located in the cutting area includes: forming a pattern layer covering the dummy area and the initial mask layer of the forming area masking layer, and exposing the initial masking layer in the cutting area; using the pattern layer as a mask, etching and removing the initial masking layer in the cutting area.
  • the length of the stem located in the dummy area is shorter than the length of the stem located in the central area; the positive direction of the formed pattern layer on the substrate is The shape of the projection is a rectangle.
  • the core column located in the dummy area and the core column located in the central area have the same length and are flush with end surfaces; the pattern layer is formed on the substrate
  • the shape of the orthographic projection is I-shaped.
  • the stem is removed first, and then the initial mask layer in the trimmed area is removed.
  • the initial mask layer located in the trimming region is removed first, and then the stem is removed.
  • the stem is removed using a wet etching process.
  • the substrate includes a substrate and an initial bit line layer on the substrate; and etching the substrate using the mask spacer as a mask includes: etching the initial bit line layer a bit line layer to form the functional structure, and the functional structure is a bit line structure; etching the substrate with the annular spacer as a mask, including: etching the initial bit line layer to form the dummy functional structure , the dummy function structure is a dummy bit line structure.
  • a second aspect of the present disclosure provides a semiconductor structure, comprising: a substrate including a central region and dummy regions located on opposite sides of the central region; and a plurality of spaced apart functional structures, the functional structures are located on all of the central regions. on the base of the central area; a pseudo-functional structure, the pseudo-functional structure is located on the base of the dummy area, and the pseudo-functional structure is a ring structure.
  • the pseudo-functional structure is a rectangular ring structure.
  • a plurality of the functional structures are arranged in parallel along a first direction; and along the first direction, the thickness of the functional structures is greater than or equal to the thickness of the dummy functional structures.
  • the functional structure extends along a second direction, and along the second direction, the length of the pseudo-functional structure is less than or equal to the length of the functional structure.
  • the pseudo-functional structure includes a first side, a second side, a third side, and a fourth side connected in sequence, and the first side and the first side are The three sides are opposite to each other, and the first side and the third side are parallel to the functional structure.
  • the functional structure is a bit line structure or a word line structure
  • the dummy functional structure is a dummy bit line structure or a dummy word line structure.
  • a dummy functional structure is formed on both sides of the functional structure, and the dummy functional structure is a ring structure, and the irregular edge pattern of the formed semiconductor structure caused by the optical proximity effect is located in the dummy functional structure. It will not affect the functional structure, and the ring-shaped pseudo-functional structure is stable and firm, and is not easily deformed.
  • the length of the core column in the dummy area is shorter than that in the central area, and the orthographic shape of the formed graphic layer on the substrate is a rectangle.
  • the cutting area is removed in the subsequent etching. In the step of the initial mask layer, the formation of the pattern layer as a mask is simpler, and the etching step is more convenient to carry out.
  • FIG. 1 is a schematic structural diagram corresponding to a step of forming a core column on a substrate of a semiconductor structure
  • FIG. 2 is a schematic structural diagram corresponding to a step of forming an initial mask layer on a substrate of a semiconductor structure
  • FIG. 3 is a schematic structural diagram corresponding to steps of forming a functional structure of a semiconductor structure
  • FIG. 4 is a schematic structural diagram of the substrate of the semiconductor structure provided in the first embodiment of the present disclosure from a top view;
  • FIG. 5 is a schematic structural diagram of the substrate of the semiconductor structure provided by the first embodiment of the present disclosure from a front view;
  • FIG. 6 is a schematic structural diagram corresponding to a step of forming a stem on a substrate of the semiconductor structure provided by the first embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram corresponding to a step of forming an initial mask layer on a substrate of the semiconductor structure provided in the first embodiment of the present disclosure
  • FIG. 8 is a schematic structural diagram corresponding to the step of removing the stem of the semiconductor structure provided by the first embodiment of the present disclosure
  • FIG. 9 is a schematic structural diagram corresponding to the step of forming a pattern layer of the semiconductor structure provided in the first embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram corresponding to the steps of forming a mask spacer and an annular spacer of the semiconductor structure provided in the first embodiment of the present disclosure
  • FIG. 11 is a schematic structural diagram corresponding to the steps of forming a functional structure and a pseudo-functional structure of the semiconductor structure provided in the first embodiment of the present disclosure
  • FIG. 12 is a schematic structural diagram corresponding to a step of forming a stem on a substrate of the semiconductor structure provided by the second embodiment of the present disclosure
  • FIG. 13 is a schematic structural diagram corresponding to a step of forming an initial mask layer on a substrate of the semiconductor structure provided by the second embodiment of the present disclosure
  • FIG. 14 is a schematic structural diagram corresponding to the step of removing the stem of the semiconductor structure provided by the second embodiment of the present disclosure.
  • 15 is a schematic structural diagram corresponding to a step of forming a pattern layer of the semiconductor structure provided by the second embodiment of the present disclosure.
  • 16 is a schematic structural diagram corresponding to a step of forming a mask spacer and an annular spacer of the semiconductor structure provided by the second embodiment of the present disclosure
  • 17 is a schematic structural diagram corresponding to steps of forming a functional structure and a pseudo-functional structure of the semiconductor structure provided by the second embodiment of the present disclosure.
  • 1 to 3 are schematic structural diagrams corresponding to each step in a method for forming a semiconductor structure.
  • the stem 130 is formed on the substrate 100 .
  • an initial mask layer 140 surrounding and covering the sidewalls of the stem 130 is formed on the substrate 100 .
  • the initial mask layer 140 is an annular structure surrounding the stem 130 .
  • the stem 130 and part of the initial mask layer 140 are removed to form spaced mask spacers, and the mask spacers are used as masks to form spaced functional structures 161 , which may be bit lines. .
  • the material at the edge where the functional structure 161 is formed is different from the material of the functional structure 161.
  • the optical proximity effect will lead to irregular patterns at the edge of the formed functional structure 161.
  • the structure at the edge of the functional structure is not as expected.
  • the technical solution of the first aspect of the present disclosure provides a method for forming a semiconductor structure, forming a ring-shaped pseudo-functional structure while forming a functional structure, while eliminating the adverse effects caused by the optical proximity effect on the functional structure, while ensuring the pseudo-functional structure. stability.
  • FIGS. 4 and 6 to 11 are schematic structural diagrams corresponding to each step of a method for forming a semiconductor structure provided by the first embodiment of the present disclosure
  • FIGS. 4 and 6 to 11 are schematic top-view structural diagrams
  • FIG. 5 is a view of FIG. 4 along the direction AA1 Schematic cross-section of the cut.
  • a substrate 200 is provided.
  • the substrate 200 includes a central area 210 and dummy areas 220 located on opposite sides of the edge in the first direction of the central area 210 .
  • the cutting areas 211 on the opposite two outer sides of the two-direction edge.
  • the central area 210 is a functional area of the semiconductor structure, and a functional structure is formed in the central area 210 in the subsequent process;
  • the dummy area 220 is a protection area of the semiconductor structure, and a dummy functional structure is formed in the dummy area 220 in the subsequent process to protect the functional structure
  • the central area 210 is further divided into a forming area 212 and a cutting area 211. In the subsequent process of forming the functional structure, the structure located in the cutting area 211 is to be removed to form a functional structure that better meets the requirements of the semiconductor structure.
  • the substrate 200 includes a substrate 202 and an initial bit line layer 201 .
  • the substrate 202 can be a silicon substrate, a germanium substrate, a silicon germanium substrate, or a silicon-on-insulator substrate, etc.; the initial bit line layer 201 includes one or more conductive layers on the substrate 202, and the initial bit line The material of the layer 201 includes one or more of polysilicon, tungsten metal, copper metal, aluminum metal, gold metal, or silver metal.
  • the initial bit line layer 201 may further include one or more conductive layers and insulating layers, such as one or more of silicon nitride, silicon dioxide, and the like.
  • the substrate may include a substrate and an initial word line layer; the substrate may include any one of an initial word line layer or an initial bit line layer.
  • a plurality of spaced posts 230 are formed on the substrate 200 , and the posts 230 located in the central area 210 (refer to FIG. 4 ) span the forming area 212 (refer to FIG. 4 ) and the cutting area 211 (refer to FIG. 4 ) , each dummy region 220 (see FIG. 4 ) is formed with at least one stem 230 .
  • the stems 230 in different regions are formed at the same time, and the materials of the stems 230 in different regions are the same, which simplifies the process steps.
  • the material of the stem 230 is different from that of the substrate 200, and may be amorphous silicon or amorphous carbon.
  • the method for forming the stem 230 may be a double-layer patterning process, in which the stem film layer is formed first, and then the stem 230 is formed by etching.
  • the stem 230 may serve as a core layer for forming an initial mask layer subsequently.
  • the length of the stem 230 located in the dummy region 220 is shorter than the length of the stem 230 located in the central region 210 (see FIG. 4 ).
  • the length of the stem 230 located in the dummy area 220 is not only shorter than the length of the stem 230 located in the central area 210 (refer to FIG. 4 ), but also the end of the stem 230 located in the dummy area 220 has no Exceeding the end of the stem 230 located in the central region 210, so the initial mask layer is formed around the stem 230, and then when part of the initial mask layer is removed, the orthographic projection of the shape of the pattern layer used as a mask on the substrate 200 Being rectangular, the shape of the graphic layer is simple and easy to form, which simplifies the process steps.
  • an initial mask layer 240 surrounding and covering the sidewalls of the stem 230 is formed on the substrate 200 .
  • the method for forming the initial mask layer 240 can be a self-aligned patterning method, using the stem 230 as the core layer, forming an initial mask on the core layer, and then removing the top and surrounding areas of the stem 230 by a maskless etching process.
  • the initial mask only the initial mask surrounding the sidewall of the stem 230 is reserved as the initial mask layer 240 .
  • the material of the initial mask layer 240 is different from the material of the stem 230 and the substrate 200, and can be silicon nitride, silicon oxide or titanium oxide, but not limited thereto.
  • the initial mask layer 240 surrounding the sidewalls of the stem 230 of the dummy area 220 (refer to FIG. 4 ) is at least located in the dummy area 220 , and is located at the initial mask layer of the dummy area 220 in the first direction.
  • the thickness of the film layer 240 is equal to the thickness of the initial mask layer 240 located in the central region 210 .
  • the thickness of the initial mask layer located in the dummy region is greater than the thickness of the initial mask layer located in the central region, and the greater the thickness of the initial mask layer in the dummy region, the initial The greater the thickness of the pseudo-functional structure formed by the mask layer as a mask, the greater the thickness of the pseudo-functional structure, the better the stability of the pseudo-functional structure.
  • the stems 230 located in the dummy area 220 (refer to FIG. 4 ) and the central area 210 (refer to FIG. 4 ) are removed first, and then the initial mask located in the cut area 211 (refer to FIG. 4 ) is removed Layer 240.
  • the initial mask layer in the trimming area is removed first, and then the stem is removed.
  • a wet etching process may be used to remove the stem 230 .
  • the stem can also be removed by a dry etching process.
  • the initial mask layer 240 located in the cutting area 211 is removed to form a plurality of spaced mask sidewall strips 241 located in the forming area 212 (refer to FIG. 4 ), and the mask sidewall strips 241 located in the forming area 212 (refer to FIG. 4 ) remain
  • the initial mask layer 240 of the dummy region 220 serves as the annular spacer 242 .
  • the dummy area is formed by the annular spacer 242, and the substrate 200 is etched by using the annular spacer 242 as a mask to form a pseudo-functional structure, then the pseudo-functional structure formed is a ring structure, and the ring structure is more stable than the discrete structure .
  • the process steps of removing the initial mask layer 240 located in the trimmed area 211 include: forming a pattern layer 250 covering the dummy area 220 (refer to FIG. 4 ) and the forming area 212 (refer to FIG. 4 ) 4) the initial mask layer 240, and the initial mask layer 240 in the trimmed area 211 (refer to FIG. 4) is exposed; using the pattern layer 250 as a mask, the initial mask layer in the trimmed area 211 (refer to FIG. 4) is removed by etching 240.
  • the length of the stem 230 in the dummy area 220 (refer to FIG. 4 ) is shorter than the length of the stem 230 in the central area 210 (refer to FIG. 4 ), and the two ends of the stem 230 in the dummy area 220 do not exceed the length of the stem 230 in the central area 210 at both ends of the stem 230, so when the pattern layer 250 needs to cover the stem 230 located in the dummy area 220 and the stem 230 located in the molding area 212, the shape of the orthographic projection of the pattern layer 250 on the substrate 200 is a rectangle .
  • the substrate 200 is etched using the mask spacer 241 as a mask to form a plurality of functional structures 261 , and the annular spacer 242 is used as a mask to etch the substrate 200 to form a plurality of functional structures. Pseudo-functional structures 262 on either side of 261.
  • the substrate 200 is etched by using the mask sidewall strips 241 as a mask, including: etching the initial bit line layer 201 (refer to FIG. 5 ) to form a functional structure 261 , and the functional structure 261 is a bit line structure;
  • the spacer 242 is a mask to etch the substrate 200 , including: etching the initial bit line layer 201 (refer to FIG. 5 ) to form a dummy functional structure 262 , which is a dummy bit line structure.
  • using the mask spacer as a mask to etch the substrate includes: etching an initial word line layer to form a functional structure, where the functional structure is a word line structure; and using the annular spacer as a mask to etch the substrate , comprising: etching the initial word line layer to form a dummy function structure, and the dummy function structure is a dummy word line structure.
  • the functional structure 261 and the dummy functional structure 262 are formed by etching the same substrate 200 , the functional structure 261 and the dummy functional structure 262 are made of the same material, which may be tungsten metal or copper metal.
  • the dummy functional structure 262 and the functional structure 261 formed by etching are located on the substrate 202 (see FIG. 5 ).
  • a pseudo-functional structure is formed on both sides of the functional structure, and the pseudo-functional structure is a ring structure.
  • the ring-shaped pseudo-functional structure can ensure that the edge pattern of the semiconductor structure formed by the optical proximity effect is irregular in the pseudo-function Structurally, the functional structure is not affected, and the ring-shaped pseudo-functional structure is more stable than the discrete pseudo-functional structure, is not easily deformed, and will not cause adverse effects on the semiconductor structure.
  • 12 to 17 are schematic structural diagrams corresponding to each step of a method for forming a semiconductor structure provided by the second embodiment of the present disclosure.
  • the method for forming a semiconductor structure provided in the second embodiment of the present disclosure is substantially the same as the method for forming the semiconductor structure provided in the first embodiment, and the main difference is that in the first embodiment, the length of the stem formed in the dummy region is shorter than The length of the stem in the central area.
  • the length of the stem located in the dummy area is the same as the length of the stem located in the central area, and the end faces are flush.
  • a plurality of spaced stems 330 are formed on the substrate 300 , and the stems 330 located in the central region 210 (see FIG. 4 ) span the forming region 212 (see FIG. 4 ) and the cutting region 211 (see FIG. 4 ) , each dummy region 220 (see FIG. 4 ) is formed with at least one stem 330 .
  • the length of the stem 330 located in the dummy area 220 (see FIG. 4 ) is the same as the length of the stem 330 located in the central area 210 (see FIG. 4 ) and the end faces are flush.
  • the pattern of the mask is simple, which simplifies the process steps.
  • an initial mask layer 340 surrounding and covering the sidewalls of the stem 330 is formed on the substrate 300 .
  • the length of the stem 330 located in the dummy area 220 (refer to FIG. 4 ) is the same as the length of the stem 330 located in the central area 210 (refer to FIG. 4 ). Therefore, in the second direction, the initial The length of the mask layer 340 is also the same.
  • a pattern layer 350 is formed.
  • the pattern layer 350 covers the dummy area 220 (refer to FIG. 4 ) and the initial mask layer 340 of the forming area 212 (refer to FIG. 4 ), and exposes the initial Mask layer 340:
  • the initial mask layer 340 in the cutting area 211 is removed by etching.
  • the length of the stem 330 located in the dummy area 220 (refer to FIG. 4 ) is the same as the length of the stem 330 located in the center area 210 (refer to FIG. 4 ) and both ends are flush, when the pattern layer 350 is required to cover the dummy area 220
  • the shape of the orthographic projection of the graphic layer 350 on the substrate 300 is an I-shape.
  • the initial mask layer 340 located in the cutting area 211 is removed to form a plurality of spaced mask sidewall strips 341 located in the forming area 212 (refer to FIG. 4 ), and remain in the dummy area
  • the initial mask layer 340 of 220 serves as the annular spacer 342 .
  • the length of the annular spacer 342 is greater than that of the mask spacer 341 .
  • the substrate 300 is etched using the mask spacer 341 as a mask to form a plurality of functional structures 361 , and the annular spacer 342 is used as a mask to etch the substrate 300 to form a plurality of functional structures. Pseudo-functional structures 362 on either side of 361.
  • the length of the dummy functional structure 362 is greater than that of the functional structure 361, and the longer the dummy functional structure 362 is, which indicates that the area occupied by the dummy functional structure 362 is larger. It is easier for the irregular area of the figure to fall into the area where the pseudo-function structure 362 is located.
  • the dummy functional structure is longer than the functional structure, and the area occupied by the dummy functional structure is enlarged, so that when the semiconductor structure is formed, the optical The irregular area of the edge pattern caused by the proximity effect is more likely to fall into the area where the pseudo-functional structure is located, which ensures that the structure of the formed functional structure conforms to the expected effect.
  • a third embodiment of the present disclosure provides a semiconductor structure formed based on the above-described semiconductor structure forming method.
  • the semiconductor structure provided in this embodiment includes: a substrate 200 .
  • the substrate 200 includes a central region 210 (see FIG. 4 ) and dummy regions 220 (see FIG. 4 ) on opposite sides of the central region 210 (see FIG. 4 ). ); a plurality of spaced functional structures 261, the functional structures 261 are located on the substrate 200 in the central area 210 (see FIG. 4); pseudo-functional structures 262, the pseudo-functional structures 262 are located on the substrate 200 in the dummy area 220 (see FIG. 4) above, and the pseudo-function structure 262 is a ring structure.
  • the pseudo-function structure 262 is a rectangular ring structure.
  • the pseudo-functional structure may also be other annular structures, such as a circular annular structure or an elliptical annular structure.
  • the plurality of functional structures 261 are arranged in parallel along the first direction, and along the first direction, the thickness of the functional structures 261 is greater than or equal to the thickness of the dummy functional structures 262 . Because the functional structure is an effective structure used by the semiconductor structure, and the pseudo-functional structure is only a protection measure, the material used and the space occupied by the pseudo-functional structure are relatively small. It can be understood that, in other embodiments, along the first direction, the thickness of the dummy functional structure may also be greater than the thickness of the functional structure.
  • the functional structure 261 extends along the second direction, and along the second direction, the length of the pseudo-functional structure 262 is less than or equal to the length of the functional structure 261 .
  • the functional structure 361 extends along the second direction, and along the second direction, the length of the pseudo-functional structure 362 is greater than the length of the functional structure 361 .
  • the length of the dummy functional structure 362 is greater than that of the functional structure 361, and the longer the dummy functional structure 362 is, which indicates that the area occupied by the dummy functional structure 362 is larger. It is easier for the irregular area of the figure to fall into the area where the pseudo-function structure 362 is located.
  • the pseudo-function structure 262 includes a first side, a second side, a third side, and a fourth side connected in sequence, and the first side is opposite to the third side, and the first side is opposite to the third side.
  • the side and the third side are parallel to the functional structure 261 . in other embodiments. It can also be that the second side and the fourth side of the pseudo-functional structure are parallel to the functional structure, and the first side and the third side are not parallel to the functional structure.
  • the functional structure 261 is a bit line structure or a word line structure
  • the dummy functional structure 262 is a dummy bit line structure or a dummy word line structure.
  • the present embodiment provides a semiconductor structure with annular pseudo-functional structures located on opposite sides of the functional structure, because the pseudo-functional structure is located at the edge of the functional structure, and the irregular region of the edge pattern caused by the optical proximity effect is located in the pseudo-functional structure, It will not affect the functional structure, and because the pseudo-functional structure is a ring structure, it is more stable than the discrete pseudo-functional structure, and is not easily deformed to adversely affect the semiconductor structure.
  • a dummy functional structure is formed on both sides of the functional structure, and the dummy functional structure is a ring structure, and the optical proximity effect causes irregularities in the edge pattern of the formed semiconductor structure.
  • the ring-shaped pseudo-functional structure is stable and firm, and is not easily deformed.

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Abstract

本公开实施例提供一种半导体结构的形成方法及半导体结构，包括：提供基底，基底包括中心区和位于中心区第一方向边缘的相对两外侧的虚置区，中心区包括成型区以及位于成型区第二方向边缘的相对两外侧的裁剪区；在基底上形成多个间隔设置的芯柱；在基底上形成环绕且覆盖芯柱侧壁的初始掩膜层；去除位于裁剪区的初始掩膜层，以形成位于成型区的若干间隔设置的掩膜侧墙条，且保留位于虚置区的初始掩膜层作为环状侧墙；去除位于中心区以及虚置区的芯柱；以掩膜侧墙条为掩膜刻蚀基底，形成多个功能结构，且以环状侧墙为掩膜刻蚀基底，形成位于多个功能结构两侧的伪功能结构。

Description

半导体结构的形成方法及半导体结构
本公开要求在2020年11月06日提交中国专利局、申请号为202011233498.8、发明名称为“半导体结构的形成方法及半导体结构”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及但不限于一种半导体结构的形成方法及半导体结构。
背景技术
随着各种电子产品朝小型化发展的趋势，存储器单元的设计也必须符合高集成度及高密度的要求。然而，由于光学邻近效应，容易在形成存储器单元的功能结构时，造成功能结构的边缘处图形不规则。
现有技术中在功能结构的一侧提供多个间隔设置的伪功能结构，解决由于光学邻近效应带来的功能结构边缘处图形不规则的问题，但由于多个间隔设置的伪功能结构互不连接，单个伪功能结构稳固性不够，容易发生形变，对半导体结构造成不良影响。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种半导体结构的形成方法及半导体结构，有利于解决伪功能结构不稳固的问题。
本公开的第一方面提供一种半导体结构的形成方法，包括：提供基底，所述基底包括中心区和位于所述中心区第一方向边缘的相对两外侧的虚置区，所述中心区包括成型区以及位于所述成型区第二方向边缘的相对两外侧的裁剪区；在所述基底上形成多个间隔设置的芯柱，位于所述中心区的所述芯柱横跨所述成型区以及所述裁剪区，每一所述虚置区形成有至少一个所述芯柱；在所述基底上形成环绕且覆盖所述芯柱侧壁的初始掩膜层；去除位于 所述裁剪区的所述初始掩膜层，以形成位于所述成型区的若干间隔设置的掩膜侧墙条，且保留位于所述虚置区的所述初始掩膜层作为环状侧墙；去除位于所述中心区以及所述虚置区的所述芯柱；以所述掩膜侧墙条为掩膜刻蚀基底，形成多个功能结构，且以所述环状侧墙为掩膜刻蚀基底，形成位于多个所述功能结构两侧的伪功能结构。
在本公开的一些实施例中，去除位于所述裁剪区的所述初始掩膜层的工艺步骤包括：形成图形层，所述图形层覆盖所述虚置区以及所述成型区的所述初始掩膜层，且露出所述裁剪区的所述初始掩膜层；以所述图形层为掩模，刻蚀去除所述裁剪区的所述初始掩膜层。
在本公开的一些实施例中，位于所述虚置区的所述芯柱的长度短于位于所述中心区的所述芯柱的长度；形成的所述图形层在所述基底上的正投影的形状为矩形。
在本公开的一些实施例中，位于所述虚置区的所述芯柱与位于所述中心区的所述芯柱的长度相同且端面齐平；形成的所述图形层在所述基底上的正投影的形状为工字型。
在本公开的一些实施例中，先去除所述芯柱，后去除位于所述裁剪区的所述初始掩膜层。
在本公开的一些实施例中，先去除位于所述裁剪区的所述初始掩膜层，后去除所述芯柱。
在本公开的一些实施例中，采用湿法刻蚀工艺，去除所述芯柱。
在本公开的一些实施例中，所述基底包括衬底以及位于所述衬底上的初始位线层；以所述掩膜侧墙条为掩膜刻蚀基底，包括：刻蚀所述初始位线层，形成所述功能结构，所述功能结构为位线结构；以所述环状侧墙为掩膜刻蚀基底，包括：刻蚀所述初始位线层，形成所述伪功能结构，所述伪功能结构为伪位线结构。
本公开的第二方面提供一种半导体结构，包括：基底，所述基底包括中心区和位于所述中心区相对两侧的虚置区；多个间隔设置的功能结构，所述功能结构位于所述中心区的基底上；伪功能结构，所述伪功能结构位于所述虚置区的所述基底上，且所述伪功能结构为环状结构。
在本公开的一些实施例中，所述伪功能结构为矩形环状结构。
在本公开的一些实施例中，多个所述功能结构沿第一方向平行排布；且在沿所述第一方向上，所述功能结构的厚度大于或等于所述伪功能结构的厚度。
在本公开的一些实施例中，所述功能结构沿第二方向延伸，且在沿所述第二方向上，所述伪功能结构的长度小于或等于所述功能结构的长度。
在本公开的一些实施例中，所述伪功能结构包括顺次连接的第一侧边、第二侧边、第三侧边和第四侧边，且所述第一侧边与所述第三侧边相对，且所述第一侧边、所述第三侧边与所述功能结构平行。
在本公开的一些实施例中，所述功能结构为位线结构或字线结构，所述伪功能结构为伪位线结构或伪字线结构。
与现有技术相比，本公开实施例提供的技术方案具有以下优点：
本公开实施例提供的半导体结构的形成方法，形成位于功能结构两侧的伪功能结构，且伪功能结构为环状结构，光学邻近效应导致形成的半导体结构的边缘图形不规则处位于伪功能结构上，不会对功能结构产生影响，而且环状的伪功能结构结构稳定牢固，不容易发生形变。
虚置区的芯柱长度短于中心区的芯柱长度，形成的图形层在基底上的正投影的形状为矩形，通过控制不同区域的芯柱的长短，使得在后续的刻蚀去除裁剪区的初始掩膜层的步骤中，作为掩膜的图形层形成更简单，刻蚀步骤更方便进行。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本申请的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1为一种半导体结构的在基底上形成芯柱的步骤对应的结构示意图；
图2为一种半导体结构的在基底上形成初始掩膜层的步骤对应的结构示意图；
图3为一种半导体结构的形成功能结构的步骤对应的结构示意图；
图4为本公开第一实施例提供的半导体结构的基底的俯视视角的结构示意图；
图5为本公开第一实施例提供的半导体结构的基底的主视视角的结构示意图；
图6为本公开第一实施例提供的半导体结构的在基底上形成芯柱的步骤对应的结构示意图；
图7为本公开第一实施例提供的半导体结构的在基底上形成初始掩膜层的步骤对应的结构示意图；
图8为本公开第一实施例提供的半导体结构的去除芯柱的步骤对应的结构示意图；
图9为本公开第一实施例提供的半导体结构的形成图形层的步骤对应的结构示意图；
图10为本公开第一实施例提供的半导体结构的形成掩膜侧墙条和环状侧墙的步骤对应的结构示意图；
图11为本公开第一实施例提供的半导体结构的形成功能结构和伪功能结构的步骤对应的结构示意图；
图12为本公开第二实施例提供的半导体结构的在基底上形成芯柱的步骤对应的结构示意图；
图13为本公开第二实施例提供的半导体结构的在基底上形成初始掩膜层的步骤对应的结构示意图；
图14为本公开第二实施例提供的半导体结构的去除芯柱的步骤对应的结构示意图；
图15为本公开第二实施例提供的半导体结构的形成图形层的步骤对应的结构示意图；
图16为本公开第二实施例提供的半导体结构的形成掩膜侧墙条和环状侧墙的步骤对应的结构示意图；
图17为本公开第二实施例提供的半导体结构的形成功能结构和伪功能结构的步骤对应的结构示意图。
具体实施方式
由背景技术可知，现有技术的伪功能结构不稳固。
图1～图3为一种半导体结构的形成方法中各步骤对应的结构示意图。
参考图1，在基底100上形成芯柱130。
参考图2，在基底100上形成环绕且覆盖芯柱130侧壁的初始掩膜层140。初始掩膜层140为环绕芯柱130的环状结构。
参考图3，去除芯柱130和部分初始掩膜层140，形成间隔设置的掩膜侧墙条，以掩膜侧墙条为掩膜形成间隔设置的功能结构161，功能结构161可以为位线。
半导体结构中形成功能结构161的边缘处的材料与功能结构161的材料不同，在形成功能结构161时，由于材料不同，光学邻近效应会导致形成的功能结构161的边缘处图形不规则，形成的功能结构边缘处结构不符合预期。
现有技术中有在功能结构161一侧形成与功能结构材料相同的、间隔设置的伪功能结构以消除光学邻近效应对功能结构的影响的方法，但是间隔设置的的伪功能结构不够稳固，容易发生形变，对整个半导体结构造成不良影响。
本公开第一方面技术方案提供一种半导体结构的形成方法，在形成功能结构的同时形成环形的伪功能结构，在消除光学邻近效应对功能结构造成的不良影响的同时，保证了伪功能结构的稳固性。
下面将结合附图对本发明的各实施例进行详细的阐述。然而，本领域的技术人员可以理解，在本发明各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
以下将结合附图对本公开实施例提供的半导体结构的形成方法进行详细说明。
图4～图11为本公开第一实施例提供的一种半导体结构的形成方法的各 步骤对应的结构示意图；图4、图6～图11为俯视结构示意图，图5为图4沿AA1方向切割的截面示意图。
结合参考图4及图5，提供基底200，基底200包括中心区210和位于中心区210第一方向边缘的相对两外侧的虚置区220，中心区210包括成型区212以及位于成型区212第二方向边缘的相对两外侧的裁剪区211。
中心区210为半导体结构的功能区域，后续工艺中在中心区210形成功能结构；虚置区220为半导体结构的保护区域，后续工艺中在虚置区220形成伪功能结构，起到保护功能结构的作用；而中心区210又分为成型区212和裁剪区211，在后续形成功能结构的工艺中，位于裁剪区211的结构要被去除，以形成更符合半导体结构要求的功能结构。
本实施例中，基底200包括衬底202和初始位线层201。
衬底202可以为硅衬底、锗衬底、锗化硅衬底或者绝缘体上的硅衬底等；初始位线层201包括位于衬底202上的一层或多层导电层，初始位线层201的材料包括：多晶硅、钨金属、铜金属、铝金属、金金属或者银金属等其中一种或多种。初始位线层201还可包括一层或多层导电层绝缘层，比如氮化硅、二氧化硅等其中一种或多种。
在其他实施例中，基底可以包括衬底和初始字线层；基底可以包括初始字线层或初始位线层中的任意一种。
参考图6，在基底200上形成多个间隔设置的芯柱230，位于中心区210(参见图4)的芯柱230横跨成型区212(参见图4)以及裁剪区211(参见图4)，每一虚置区220(参见图4)形成有至少一个芯柱230。
本实施例中，不同区域的芯柱230同时形成，且不同区域的芯柱230的材料相同，简化了工艺步骤。
芯柱230的材料与基底200的材料不同，可以为非晶硅或非晶碳。
形成芯柱230的方法可以为双层图形化工艺，先形成芯柱膜层，再刻蚀形成芯柱230。芯柱230可以作为后续形成初始掩膜层的核心层。
位于虚置区220(参见图4)的芯柱230的长度短于位于中心区210(参见图4)的芯柱230的长度。
因为位于虚置区220(参考图4)的芯柱230的长度不仅短于位于中心区210(参考图4)的芯柱230的长度，而且位于虚置区220的芯柱230的端部 没有超过位于中心区210的芯柱230的端部，所以环绕芯柱230形成初始掩膜层，然后去除部分初始掩膜层时，所用的作为掩膜的图形层的形状在基底200上的正投影为矩形，图形层的形状简单容易形成，简化了工艺步骤。
参考图7，在基底200上形成环绕且覆盖芯柱230侧壁的初始掩膜层240。
形成初始掩膜层240的方法可以为自对准图形化法，以芯柱230作为核心层，在核心层上形成初始掩膜，然后用无掩膜刻蚀工艺去除芯柱230顶部和四周的初始掩膜，只保留环绕芯柱230侧壁的初始掩膜作为初始掩膜层240。
初始掩膜层240的材料与芯柱230和基底200的材料都不同，可以为：氮化硅、氧化硅或氧化钛，不限于此。
本实施例中，环绕虚置区220(参考图4)的芯柱230侧壁的初始掩膜层240至少位于虚置区220内，且在第一方向上，位于虚置区220的初始掩膜层240的厚度等于位于中心区210的初始掩膜层240的厚度。
在其他实施例中，在第一方向上，位于虚置区的初始掩膜层的厚度大于位于中心区的初始掩膜层的厚度，虚置区的初始掩膜层的厚度越大，以初始掩膜层为掩膜形成的伪功能结构的厚度也越大，伪功能结构的厚度越大，伪功能结构的稳固性越好。
参考图8，本实施例中，先去除位于虚置区220(参考图4)和中心区210(参考图4)的芯柱230，后去除位于裁剪区211(参考图4)的初始掩膜层240。在其他实施例中，先去除位于裁剪区的初始掩膜层，后去除芯柱。
本实施例中，可以采用湿法刻蚀工艺，去除芯柱230。在其他实施例中，也可以采用干法刻蚀工艺去除芯柱。
参考图9和图10，去除位于裁剪区211(参考图4)的初始掩膜层240，以形成位于成型区212(参考图4)的若干间隔设置的掩膜侧墙条241，且保留位于虚置区220(参考图4)的初始掩膜层240作为环状侧墙242。
虚置区形成的是环状侧墙242，以环状侧墙242作为掩膜刻蚀基底200形成伪功能结构，则形成的伪功能结构为环状结构，环状结构相对于分立结构更稳固。
参考图9，去除位于裁剪区211(参考图4)的初始掩膜层240的工艺步 骤包括：形成图形层250，图形层250覆盖虚置区220(参考图4)以及成型区212(参考图4)的初始掩膜层240，且露出裁剪区211(参考图4)的初始掩膜层240；以图形层250为掩模，刻蚀去除裁剪区211(参考图4)的初始掩膜层240。
因为位于虚置区220(参考图4)的芯柱230长度短于位于中心区210(参考图4)的芯柱长度，且位于虚置区220的芯柱230的两端没有超过位于中心区210的芯柱230的两端，所以当需要图形层250覆盖位于虚置区220的芯柱230和位于成型区212的芯柱230时，图形层250在基底200上的正投影的形状为矩形。
参考图10和图11，以掩膜侧墙条241为掩膜刻蚀基底200，形成多个功能结构261，且以环状侧墙242为掩膜刻蚀基底200，形成位于多个功能结构261两侧的伪功能结构262。
本实施例中，以掩膜侧墙条241为掩膜刻蚀基底200，包括：刻蚀初始位线层201(参考图5)，形成功能结构261，功能结构261为位线结构；以环状侧墙242为掩膜刻蚀基底200，包括：刻蚀所述初始位线层201(参考图5)，形成伪功能结构262，伪功能结构262为伪位线结构。
在其他实施例中，以掩膜侧墙条为掩膜刻蚀基底，包括：刻蚀初始字线层，形成功能结构，功能结构为字线结构；以环状侧墙为掩膜刻蚀基底，包括：刻蚀所述初始字线层，形成伪功能结构，伪功能结构为伪字线结构。
因为功能结构261和伪功能结构262为刻蚀同一基底200形成，所以功能结构261和伪功能结构262材料相同，可以为钨金属或铜金属等。
刻蚀形成的伪功能结构262和功能结构261位于衬底202(参见图5)上。
本实施例中，形成了位于功能结构两侧的伪功能结构，且伪功能结构为环状结构，环状的伪功能结构可以保证光学邻近效应导致形成的半导体结构边缘图形不规则处在伪功能结构上，不对功能结构产生影响，而且环状的伪功能结构相对于分立的伪功能结构更稳固，不容易发生形变，不会对半导体结构造成不良影响。
图12～图17为本公开第二实施例提供的一种半导体结构的形成方法的各步骤对应的结构示意图。
本公开第二实施例提供的一种半导体结构的形成方法与第一实施例提供 的半导体结构的形成方法大致相同，主要区别点在于第一中，形成的位于虚置区的芯柱长度短于位于中心区的芯柱长度。而本公开第二实施例中，位于虚置区的芯柱的长度与位于中心区的芯柱的长度相同且端面齐平。以下将结合附图对本实施例进行详细说明。
参考图12，在基底300上形成多个间隔设置的芯柱330，位于中心区210(参见图4)的芯柱330横跨成型区212(参见图4)以及裁剪区211(参见图4)，每一虚置区220(参见图4)形成有至少一个芯柱330。位于虚置区220(参见图4)的芯柱330的长度与位于中心区210(参见图4)的芯柱330的长度相同且端面齐平。
因为不同区域的芯柱330长度相同且端面齐平，所以在形成芯柱330的工艺中，掩膜版的图形简单，简化了工艺步骤。
参考图13，在基底300上形成环绕且覆盖芯柱330侧壁的初始掩膜层340。本实施例中，位于虚置区220(参考图4)的芯柱330的长度与位于中心区210(参考图4)的芯柱330长度相同，所以在第二方向上，不同区域形成的初始掩膜层340的长度也相同。
参考图14，去除芯柱330。
参考图15，形成图形层350，图形层350覆盖虚置区220(参考图4)以及成型区212(参考图4)的初始掩膜层340，且露出裁剪区211(参考图4)的初始掩膜层340；以图形层350为掩模，刻蚀去除裁剪区211(参考图4)的初始掩膜层340。
因为位于虚置区220(参考图4)的芯柱330长度与位于中心区210(参考图4)的芯柱330长度相同且两端齐平，所以当需要图形层350覆盖位于虚置区220的芯柱330和位于成型区212的芯柱330时，图形层350在基底300上的正投影的形状为工字型。
参考图16，去除位于裁剪区211(参考图4)的初始掩膜层340，以形成位于成型区212(参考图4)的若干间隔设置的掩膜侧墙条341，且保留位于虚置区220(参考图4)的初始掩膜层340作为环状侧墙342。
在第二方向上，环状侧墙342的长度大于掩膜侧墙条341。
参考图16和图17，以掩膜侧墙条341为掩膜刻蚀基底300，形成多个功能结构361，且以环状侧墙342为掩膜刻蚀基底300，形成位于多个功能结构 361两侧的伪功能结构362。
在第二方向上，伪功能结构362的长度大于功能结构361，伪功能结构362的长度越长，这表明伪功能结构362所占据区域越大，在形成半导体结构时，光学邻近效应造成的边缘图形不规则区域越容易落到伪功能结构362所在区域。
本实施例提供的半导体结构的形成方法，与第一实施例相比，在第二方向上，伪功能结构比功能结构长，扩大了伪功能结构所占区域，使得在形成半导体结构时，光学邻近效应造成的边缘图形不规则区域更容易落到伪功能结构所在区域，保证了形成的功能结构的结构符合预期效果。
本公开第三实施例提供一种基于上述半导体结构形成方法形成的半导体结构。
参考图11，本实施例提供的半导体结构，包括：基底200，基底200包括中心区210(参见图4)和位于中心区210(参见图4)相对两侧的虚置区220(参见图4)；多个间隔设置的功能结构261，功能结构261位于中心区210(参见图4)的基底200上；伪功能结构262，伪功能结构262位于虚置区220(参见图4)的基底200上，且伪功能结构262为环状结构。
本实施例中，伪功能结构262为矩形环状结构。在其他实施例中，在不影响伪功能结构的稳定性的前提下，伪功能结构还可以为其他环状结构，比如：圆形环状结构或椭圆形环状结构。
多个功能结构261沿第一方向平行排布，且在沿第一方向上，功能结构261的厚度大于或等于伪功能结构262的厚度。因为功能结构为半导体结构用到的有效结构，伪功能结构仅为保护措施，所以伪功能结构所用材料和所占空间相对较少。可以理解的是，在其他实施例中，沿第一方向上，伪功能结构的厚度也可以大于功能结构的厚度。
本实施例中，功能结构261沿第二方向延伸，且在沿第二方向上，伪功能结构262的长度小于或等于功能结构261的长度。
在其他实施例中，参考图14，功能结构361沿第二方向延伸，且在沿第二方向上，伪功能结构362的长度大于功能结构361的长度。在第二方向上，伪功能结构362的长度大于功能结构361，伪功能结构362的长度越长，这表明伪功能结构362所占据区域越大，在形成半导体结构时，光学邻近效 应造成的边缘图形不规则区域越容易落到伪功能结构362所在区域。
本实施例中，伪功能结构262包括顺次连接的第一侧边、第二侧边、第三侧边和第四侧边，且第一侧边与第三侧边相对，且第一侧边、第三侧边与功能结构261平行。在其他实施例中。也可以为伪功能结构的第二侧边、第四侧边与功能结构平行，第一侧边、第三侧边与功能结构不平行。
功能结构261为位线结构或字线结构，伪功能结构262为伪位线结构或伪字线结构。
本实施例提供一种半导体结构，具有位于功能结构相对两侧的环状的伪功能结构，因为伪功能结构位于功能结构的边缘，光学邻近效应导致的边缘图形不规则区域位于伪功能结构中，不会对功能结构产生影响，而且由于伪功能结构是环状结构，相对于分立的伪功能结构稳固性更好，不容易变形对半导体结构产生不良影响。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在 下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的半导体结构的形成方法及半导体结构，形成位于功能结构两侧的伪功能结构，且伪功能结构为环状结构，光学邻近效应导致形成的半导体结构的边缘图形不规则处位于伪功能结构上，不会对功能结构产生影响，而且环状的伪功能结构结构稳定牢固，不容易发生形变。

Claims (15)

  1. 一种半导体结构的形成方法，所述半导体结构的形成方法包括：
    提供基底，所述基底包括中心区和位于所述中心区第一方向边缘的相对两外侧的虚置区，所述中心区包括成型区以及位于所述成型区第二方向边缘的相对两外侧的裁剪区；
    在所述基底上形成多个间隔设置的芯柱，位于所述中心区的所述芯柱横跨所述成型区以及所述裁剪区，每一所述虚置区形成有至少一个所述芯柱；
    在所述基底上形成环绕且覆盖所述芯柱侧壁的初始掩膜层；
    去除位于所述裁剪区的所述初始掩膜层，以形成位于所述成型区的若干间隔设置的掩膜侧墙条，且保留位于所述虚置区的所述初始掩膜层作为环状侧墙；
    去除位于所述中心区以及所述虚置区的所述芯柱；
    以所述掩膜侧墙条为掩膜刻蚀基底，形成多个功能结构，且以所述环状侧墙为掩膜刻蚀基底，形成位于多个所述功能结构两侧的伪功能结构。
  2. 根据权利要求1所述的半导体结构的形成方法，其中，去除位于所述裁剪区的所述初始掩膜层的工艺步骤包括：形成图形层，所述图形层覆盖所述虚置区以及所述成型区的所述初始掩膜层，且露出所述裁剪区的所述初始掩膜层；以所述图形层为掩模，刻蚀去除所述裁剪区的所述初始掩膜层。
  3. 根据权利要求2所述的半导体结构的形成方法，其中，位于所述虚置区的所述芯柱的长度短于位于所述中心区的所述芯柱的长度；形成的所述图形层在所述基底上的正投影的形状为矩形。
  4. 根据权利要求2所述的半导体结构的形成方法，其中，位于所述虚置区的所述芯柱与位于所述中心区的所述芯柱的长度相同且端面齐平；形成的所述图形层在所述基底上的正投影的形状为工字型。
  5. 根据权利要求1所述的半导体结构的形成方法，其中，先去除所述芯柱，后去除位于所述裁剪区的所述初始掩膜层。
  6. 根据权利要求1所述的半导体结构的形成方法，其中，先去除位于所述裁剪区的所述初始掩膜层，后去除所述芯柱。
  7. 根据权利要求5所述的半导体结构的形成方法，其中，采用湿法刻 蚀工艺，去除所述芯柱。
  8. 根据权利要求6所述的半导体结构的形成方法，其中，采用湿法刻蚀工艺，去除所述芯柱。
  9. 根据权利要求1所述的半导体结构的形成方法，其中，所述基底包括衬底以及位于所述衬底上的初始位线层；以所述掩膜侧墙条为掩膜刻蚀基底，包括：刻蚀所述初始位线层，形成所述功能结构，所述功能结构为位线结构；以所述环状侧墙为掩膜刻蚀基底，包括：刻蚀所述初始位线层，形成所述伪功能结构，所述伪功能结构为伪位线结构。
  10. 一种半导体结构，所述半导体结构包括：
    基底，所述基底包括中心区和位于所述中心区相对两侧的虚置区；
    多个间隔设置的功能结构，所述功能结构位于所述中心区的基底上；
    伪功能结构，所述伪功能结构位于所述虚置区的所述基底上，且所述伪功能结构为环状结构。
  11. 根据权利要求10所述的半导体结构，其中，所述伪功能结构为矩形环状结构。
  12. 根据权利要求10所述半导体结构，其中，多个所述功能结构沿第一方向平行排布；且在沿所述第一方向上，所述功能结构的厚度大于或等于所述伪功能结构的厚度。
  13. 根据权利要求10所述的半导体结构，其中，所述功能结构沿第二方向延伸，且在沿所述第二方向上，所述伪功能结构的长度小于或等于所述功能结构的长度。
  14. 根据权利要求10所述的半导体结构，其中，所述伪功能结构包括顺次连接的第一侧边、第二侧边、第三侧边和第四侧边，且所述第一侧边与所述第三侧边相对，且所述第一侧边、所述第三侧边与所述功能结构平行。
  15. 根据权利要求10所述的半导体结构，其中，所述功能结构为位线结构或字线结构，所述伪功能结构为伪位线结构或伪字线结构。
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