WO2023155632A1 - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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Publication number
WO2023155632A1
WO2023155632A1 PCT/CN2023/070667 CN2023070667W WO2023155632A1 WO 2023155632 A1 WO2023155632 A1 WO 2023155632A1 CN 2023070667 W CN2023070667 W CN 2023070667W WO 2023155632 A1 WO2023155632 A1 WO 2023155632A1
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sub
sacrificial
sacrifice layer
layer
holes
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PCT/CN2023/070667
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English (en)
French (fr)
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廖大庆
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长鑫存储技术有限公司
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Publication of WO2023155632A1 publication Critical patent/WO2023155632A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0805—Capacitors only

Definitions

  • the invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof.
  • the size of the capacitance is defined by the line width of the double imaging. If you want to expand the capacitance, you need to set the line width of the capacitance pattern in the double imaging process to be thinner, but the thinner the line width The more difficult it is to control the stability of the fine process, and the higher the cost needs to be invested.
  • the object of the present invention is to provide a semiconductor structure and its manufacturing method, which can increase the area of the capacitance hole to increase the capacitance without changing the line width of the capacitance pattern, and the process is simple and the cost is low.
  • a method for manufacturing a semiconductor structure includes: providing a substrate; forming a sacrificial layer on the substrate, the sacrificial layer including a first sub-sacrifice layer and a second sub-sacrifice layer arranged at intervals, the first sub-sacrifice layer A sub-sacrifice layer and the second sub-sacrifice layer are respectively in contact with the substrate, the etching rate of the first sub-sacrifice layer is lower than the etching rate of the second sub-sacrifice layer; a mask layer is formed on the On the sacrificial layer, the mask layer includes a plurality of first mask openings, and the plurality of first mask openings are located on the first sub-sacrifice layer; through the first mask openings, the first The sub-sacrifice layer is etched to form a plurality of first sacrificial holes, and part of the edges of the first sacrificial holes extend into the
  • the step of forming a plurality of the first sacrificial holes includes: etching the first sub-sacrifice layer through a dry etching process to form a plurality of holes on the first sub-sacrifice layer. a plurality of first initial sacrificial holes, part of the edges of the first initial sacrificial holes are in contact with the second sub-sacrifice layer; the first initial sacrificial holes are etched by a wet process to form the first sacrificial holes hole, so that part of the edge of the first sacrificial hole extends into the second sub-sacrifice layer.
  • the mask layer further includes a plurality of second mask openings, and the plurality of second mask openings are located on the second sub-sacrifice layer.
  • the manufacturing method further includes etching the second sub-sacrifice layer through the second mask opening to form a plurality of second sacrificial holes; wherein the second sacrificial holes Part of the edge is in contact with the first sub-sacrifice layer.
  • the step of forming a plurality of second sacrificial holes includes: etching the second sub-sacrifice layer through a dry etching process, so as to form a plurality of holes in the second sub-sacrifice layer.
  • the second initial sacrificial hole, the edge of the second initial sacrificial hole is located in the second sub-sacrifice layer; a plurality of the second initial sacrificial holes are etched by a wet etching process to form a plurality of first sacrificial holes and two sacrificial holes, so that part of the edge of the second sacrificial hole is in contact with the first sub-sacrifice layer.
  • another part of the edge of the second sacrificial hole extends in a direction away from the center of the second sacrificial hole in the second sub-sacrifice layer.
  • a plurality of the first sacrificial holes and a plurality of the second sacrificial holes are alternately arranged; wherein, the first direction is perpendicular to The direction of the first sub-sacrifice layer, the second direction is a direction parallel to the first sub-sacrifice layer.
  • the method further includes: etching the substrate through the plurality of second sacrificial holes to form a plurality of second capacitance holes.
  • the width of the first capacitor hole in the first direction is greater than the width of the second capacitor hole in the first direction;
  • the widths in the two directions are smaller than the width of the second capacitor hole in the second direction.
  • the step of forming the sacrificial layer includes: forming a first sacrificial layer on the substrate; etching the first sacrificial layer to form spaced a plurality of grooves, the grooves expose the substrate, and the remaining first sacrificial layer is defined as the first sub-sacrifice layer; the plurality of grooves are filled to form a plurality of the first sacrificial layers The second sub-sacrifice layer.
  • the material of the first sub-sacrifice layer is different from the material of the second sub-sacrifice layer.
  • the material of the first sub-sacrifice layer is the same as that of the second sub-sacrifice layer, and the ion doping type in the first sub-sacrifice layer is the same as that of the second sub-sacrifice layer.
  • the ion doping types are the same, and the ion doping concentration of the first sub-sacrifice layer is different from the ion doping concentration of the second sub-sacrifice layer.
  • the material of the first sub-sacrifice layer is the same as that of the second sub-sacrifice layer, and the ion doping type in the first sub-sacrifice layer is the same as that of the second sub-sacrifice layer.
  • ion doping There are different types of ion doping.
  • the invention also proposes a semiconductor structure.
  • a semiconductor structure includes: a substrate; a plurality of first capacitance holes located in the substrate; wherein, the width of the first capacitance holes in the first direction is larger than that of the first capacitance holes in the second direction. Width in the direction; a plurality of second capacitance holes located in the substrate; wherein, the width of the second capacitance holes in the first direction is smaller than the width of the second capacitance holes in the second direction Width, the width of the first capacitance hole in the first direction is greater than the width of the second capacitance hole in the first direction; the width of the first capacitance hole in the second direction is smaller than The width of the second capacitance hole in the second direction.
  • a plurality of the first capacitance holes are parallel to a plurality of the second capacitance holes; and the first capacitance holes Alternately arranged with the second capacitor holes.
  • the semiconductor structure and the manufacturing method thereof by forming the first sub-sacrifice layer and the second sub-sacrifice layer spaced apart on the substrate, the first sub-sacrifice layer and the second sub-sacrifice layer are respectively in contact with the substrate; and then Form a first mask opening on the first sub-sacrifice layer, and then etch the first sub-sacrifice layer according to the first mask opening, thereby forming a plurality of first sacrificial holes, due to the etching of the first sub-sacrifice layer
  • the etch rate is lower than the etch rate of the second sub-sacrifice layer, so part of the edge of the first sacrificial hole will extend into the second sub-sacrifice layer, thereby increasing the area of the first sacrificial hole, so through the first sacrificial hole to When the substrate is etched, the area of the first capacitor hole will be increased, that is, the capac
  • FIG. 1 is a flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present invention
  • Fig. 2, Fig. 4, Fig. 6, Fig. 8, Fig. 10, Fig. 12, Fig. 14, Fig. 16, and Fig. 18 are schematic cross-sectional structure diagrams of each step of a method for manufacturing a semiconductor structure according to an embodiment of the present invention
  • FIG. 3 is a top view corresponding to FIG. 2 of a semiconductor structure manufacturing method according to an embodiment of the present invention
  • FIG. 5 is a top view corresponding to FIG. 4 of a semiconductor structure manufacturing method according to an embodiment of the present invention.
  • FIG. 7 is a top view corresponding to FIG. 6 of a semiconductor structure manufacturing method according to an embodiment of the present invention.
  • FIG. 9 is a top view corresponding to FIG. 8 of a semiconductor structure manufacturing method according to an embodiment of the present invention.
  • FIG. 11 is a top view corresponding to FIG. 10 of a semiconductor structure manufacturing method according to an embodiment of the present invention.
  • FIG. 13 is a top view corresponding to FIG. 12 of a semiconductor structure manufacturing method according to an embodiment of the present invention.
  • FIG. 15 is a top view corresponding to FIG. 14 of a semiconductor structure manufacturing method according to an embodiment of the present invention.
  • FIG. 17 is a top view corresponding to FIG. 16 of a semiconductor structure manufacturing method according to an embodiment of the present invention.
  • FIG. 19 is a top view corresponding to FIG. 18 of a semiconductor structure manufacturing method according to an embodiment of the present invention.
  • first initial sacrificial hole 32: first sacrificial hole
  • 33 second initial sacrificial hole
  • 34 second sacrificial hole
  • 35 first capacitor hole
  • 36 second capacitor hole
  • hard mask layer 41: spin-on hard mask layer, 42: silicon oxynitride layer, 43: photoresist layer;
  • the method for manufacturing a semiconductor structure includes: providing a substrate 1; forming a sacrificial layer 2 on the substrate 1, and the sacrificial layer 2 includes first sub-sacrificial layers arranged at intervals 21 and a second sub-sacrifice layer 22, the first sub-sacrifice layer 21 and the second sub-sacrifice layer 22 are respectively in contact with the substrate 1, and the etching rate of the first sub-sacrifice layer 21 is lower than that of the first sub-sacrifice layer 21 Second, the etching rate of the sacrificial layer 22; a mask layer is formed on the sacrificial layer 2, and the mask layer includes a plurality of first mask openings, and the plurality of first mask openings are located in the first On the sub-sacrifice layer 21; the first sub-sacrifice layer 21 is etched through the first mask opening to form a plurality of first sacrificial holes 32,
  • FIGS. 2-17 are cross-sectional views and top views of each step of a method for manufacturing a semiconductor structure according to an embodiment of the present invention.
  • the method for manufacturing a semiconductor structure and the semiconductor structure according to an embodiment of the present invention will be described below in conjunction with FIGS. 2-17 .
  • the substrate 1 can be made of silicon or silicon germanium, and devices such as transistors can also be formed in the substrate 1. As shown in FIGS. 11 and the device structure 17 below the stacked structure 11, the capacitor hole penetrates the stacked structure 11, the capacitor structure is formed in the capacitor hole, and the device structure 17 can be electrically contacted with the subsequently formed capacitor structure.
  • the laminated structure 11 sequentially includes a first oxide layer 12, a first nitride layer 13, a second oxide layer 14, a second nitride layer 15 and a third nitride layer from bottom to top.
  • the compound layer 16 further, the first oxide layer 12 and the second oxide layer 14 can be silicon oxide layers, the first nitride layer 13 and the second nitride layer 15 can be silicon nitride layers, the third nitride layer
  • the compound layer 16 may be a silicon oxynitride layer 42 .
  • first oxide layer 12 and the second oxide layer 14 are formed as a sacrificial layer
  • first nitride layer 13 and the second nitride layer 15 are formed as a support layer
  • first nitride layer is removed.
  • the first oxide layer 12, the second oxide layer 14 and the third nitride layer 16, while the first nitride layer 13 and the second nitride layer 15 remain, are deposited in the capacitor hole to form a capacitor structure.
  • the sacrificial layer 2 is formed on the substrate 1.
  • the sacrificial layer 2 may include a first sub-sacrifice layer 21 and a second sub-sacrifice layer 22 arranged at intervals.
  • the sacrificial layers 22 are respectively in contact with the substrate 1, that is to say, the first sub-sacrifice layer 21 and the second sub-sacrifice layer 22 are all formed on the substrate 1, and the first sub-sacrifice layer 21 and the second sub-sacrifice layer 22 are formed on the plane of the substrate 1.
  • the sacrificial layers 22 are arranged alternately, wherein the first sub-sacrifice layer 21 and the second sub-sacrifice layer 22 can form a line shape, for example, the first sub-sacrifice layer 21 can include a plurality of first sub-sacrifice strips arranged at intervals, and the second sub-sacrifice layer
  • the layer 22 may include a plurality of second sub-sacrificial strips arranged at intervals, and the plurality of second sub-sacrificial strips are located between the plurality of first sub-sacrificial strips so as to be distributed alternately with the first sub-sacrificial strips in the plane direction of the substrate 1. set up.
  • first sacrificial strip and the second sacrificial strip can be formed into a straight line or an S shape, or can also be formed into other shapes, the present invention is not limited to this, as long as the first sacrificial strip and the second sacrificial strip are arranged alternately and spaced apart from each other .
  • the substrate 1 may be in direct or indirect contact with the first sub-sacrifice layer 21 and the second sub-sacrifice layer 22, for example, the first sub-sacrifice layer 21 and the second sub-sacrifice layer 22 may be alternately formed on the substrate 1 to be in contact with the substrate 1, or other film layers may be formed between the substrate 1 and the sacrificial layer 2, for example, a sacrificial buffer layer 5 may also be formed between the substrate 1 and the sacrificial layer 2, and the first sub-sacrifice layer 21 and the second sub-sacrifice layer 22 are formed on the surface of the sacrificial buffer layer 5, and the first sub-sacrifice layer 21 and the second sub-sacrifice layer 22 are alternately formed on the surface of the sacrificial buffer layer 5 to indirectly contact the substrate 1 through the sacrificial buffer layer 5 , the capacitance pattern on the subsequent sacrificial layer 2 can be transferred to the sacrificial
  • the material of the sacrificial buffer layer 5 can be polysilicon, and the thickness of the sacrificial buffer layer 5 can be close to the thickness of the stacked structure 11.
  • the thickness of the sacrificial buffer layer 5 can be the same as the thickness of the stacked structure 11, so that the capacitor is formed during etching.
  • the sacrificial buffer layer 5 can be consumed at the same time when the hole is formed, and the good transfer of the etching pattern of the capacitor hole can also be ensured by setting the sacrificial buffer layer 5, so as to obtain a capacitor hole with a good shape.
  • the steps of forming the sacrificial layer 2 include:
  • first sacrificial layer 23 As shown in Fig. 2 and Fig. 3, form the first sacrificial layer 23 on the substrate 1, wherein the first sacrificial layer 23 covers the surface of the substrate 1, in the example shown in Fig. 2-Fig. 11, also form on the substrate 1 There is a sacrificial buffer layer 5 , and the first sacrificial layer 23 covers the surface of the sacrificial buffer layer 5 .
  • the first sacrificial layer 23 is etched to form a plurality of grooves 24 arranged at intervals on the first sacrificial layer 23, the grooves 24 expose the substrate 1, and the remaining The first sacrificial layer 23 is defined as the first sub-sacrifice layer 21. Specifically, as shown in FIG.
  • a hard mask layer 4 is formed on the first sacrificial layer 23, and the hard mask layer 4 may be a hard mask
  • the combined layer for example, the hard mask layer 4 may include a spin-coated hard mask layer 41 and a silicon oxynitride layer 42 arranged in sequence from bottom to top, and a photoresist layer 43 is formed on the hard mask layer 4, and then exposure treatment is performed to Etching the hard mask layer 4, and forming a hard mask pattern to define the pattern for forming the first sub-sacrifice layer 21, using the hard mask pattern as a mask to etch the first sacrificial layer 23 to form a plurality of exposed substrates 1 grooves 24, and form a linear first sub-sacrifice layer 21.
  • a plurality of grooves 24 are filled to form a plurality of second sub-sacrifice layers 22.
  • a second sacrificial layer 2 can be formed on the surface of the grooves 24 and the first sub-sacrifice layer 21.
  • the second sacrificial layer 2 located on the surface of the first sub-sacrifice layer 21 may be removed using a process including but not limited to chemical mechanical polishing, and the second sacrificial layer 2 located in the trench 24 may be retained to form the second sub-sacrifice layer 22 .
  • a mask layer 6 is formed on the sacrificial layer 2, the mask layer 6 includes a plurality of first mask openings 61, and the plurality of first mask openings 61 are located on the first sub-sacrifice layer 21 , the first sub-sacrifice layer 21 is etched through the first mask opening 61 to form a plurality of first sacrificial holes 32, and part of the edges of the first sacrificial holes 32 extend into the second sub-sacrifice layer 22, that is, along the As shown in FIG. 12 in the up and down direction, a plurality of first mask openings 61 are correspondingly formed on the first sub-sacrifice layer 21.
  • the pattern of the first mask openings 61 corresponds to transfer to the first sub-sacrifice layer 21, specifically, when etching with the first mask opening 61 as a mask, the first sub-sacrifice layer 21 can be etched, and when the etching reaches the first sub-sacrifice layer 21, the first sacrificial hole 32 has not been etched to the required size at this time, and the etching still needs to be continued, so that the etching of the first sacrificial hole 32 will continue to be partly performed on the first sub-sacrifice layer 21, and partly to the first sub-sacrifice layer 21.
  • Etching the second sub-sacrifice layer 22 outside, that is, the first sacrificial hole 32 can extend into the second sub-sacrifice layer 22, because the etching rate of the first sub-sacrifice layer 21 is lower than the etching rate of the second sub-sacrifice layer 22,
  • the etching extension speed of the first sacrificial hole 32 in the second sub-sacrifice layer 22 is greater than the etching extension speed in the first sub-sacrifice layer 21, compared to only continuing to etch in the first sub-sacrifice layer 21 to form the first sacrificial hole 32 , the first sacrificial hole 32 continues to be etched in the second sub-sacrifice layer 32 with a faster etching rate and a larger expansion area, so under the same etching conditions, the first sacrificial hole 32 continues to be etched in the first sub-sacrifice layer 21 to a certain size, the expansion size of the first sa
  • the substrate 1 is etched through a plurality of first sacrificial holes 32 to form a plurality of first capacitor holes 35 .
  • the hole 32 is etched to form the first capacitor hole 35
  • the area of the first capacitor hole 35 is also increased, and the area of the subsequently formed capacitor structure is also increased.
  • the capacitance of the capacitor structure is proportional to the area of the capacitor structure, and the area of the capacitor structure Therefore, the size of the capacitance is also increased, and the line width of the double imaging does not need to be reduced, which reduces the research and development cost.
  • the step of forming a plurality of first sacrificial holes 32 includes: as shown in FIG. 12-FIG. 13, etching the first sub-sacrificial layer 21 by dry etching etch to form a plurality of first initial sacrificial holes 31 on the first sub-sacrifice layer 21, and part of the edges of the first initial sacrificial holes 31 are in contact with the second sub-sacrifice layer 22; as shown in FIGS.
  • the first initial sacrificial hole 31 is etched by a wet process to form the first sacrificial hole 32, so that part of the edge of the first sacrificial hole 32 extends into the second sub-sacrificial layer 22
  • dry etching can be used to form the first initial sacrificial hole 31 in the first sub-sacrifice layer 21 first, and the vertical etching rate of dry etching is fast so that the etching of the first initial sacrificial hole 31 can be accelerated , and the use of dry etching can better ensure that the etching morphology is good.
  • wet etching can be performed on the first sub-sacrifice layer 21 and the second sub-sacrifice layer 22 simultaneously to form the first sacrificial hole 32, that is Continue to etch the second sub-sacrifice layer 22 along the partial edge of the first initial sacrificial hole 31 by wet process, so that the partial edge of the first sacrificial hole 32 extends into the second sub-sacrifice layer 22, and along the first initial sacrificial hole 31 31 continues to etch the first sub-sacrifice layer 21.
  • the wet etching will The expansion area of the first sub-sacrifice layer 21 is larger than the expansion area of the first sub-sacrifice layer 21 by wet etching. Compared with only forming the first sacrificial hole 32 in the first sub-sacrifice layer 21, the area of the first sacrificial hole 32 can be increased to The area of the subsequently formed first capacitor hole 35 is increased.
  • the mask layer 6 further includes a plurality of second mask openings 62, and the plurality of second mask openings 62 are located on the second sub-sacrifice layer 22, that is, the mask The layer 6 is formed on the sacrificial layer 2, and the second mask opening 62 is correspondingly located on the second sub-sacrifice layer 22 in the up-down direction, and the second sub-sacrifice layer 22 can be etched downward through the second mask opening 62.
  • the mask layer 6 with the second mask opening 62 may be formed by a double imaging process.
  • the second sub-sacrifice layer 22 is etched through the second mask opening 62 to form a plurality of second sacrificial holes 34, and the mask layer 6 is removed, Part of the edge of the second sacrificial hole 34 is in contact with the first sub-sacrifice layer 21, the other part of the edge of the second sacrificial hole 34 is located in the second sub-sacrifice layer 22, and the second sacrificial hole 34 is formed through the second mask opening 62 and
  • the second capacitance hole 36 can be subsequently formed, compared with only the first capacitance hole 35, thereby increasing the total area of the capacitance hole, and the second sacrificial hole 34 is formed in the second sub-sacrifice layer 22, and the second sub-sacrifice layer 22 Both sides are the first sub-sacrifice layer 21, and the etch rate of the first sub-sacrifice layer 21 is small, so that the etching rate of the second s
  • the substrate 1 is etched through a plurality of second sacrificial holes 34 to form a plurality of second capacitance holes 36, so that the area of the second capacitance holes 36 can be increased to increase the subsequent The size of the capacitive structure formed.
  • the step of forming a plurality of second sacrificial holes 34 includes: as shown in FIGS. 12-15, etching the second sub-sacrifice layer 22 through a dry etching process to A plurality of second initial sacrificial holes 33 are formed in the sub-sacrifice layer 22, and the edges of the second initial sacrificial holes 33 are located in the second sub-sacrifice layer 22, that is, the second initial sacrificial holes 33 do not exceed the second sub-sacrifice layer 22, and the first The edge of the second initial sacrificial hole 33 does not extend to the edge of the second sub-sacrifice layer 22; in this step, dry etching can be used to increase the vertical etching efficiency, so as to speed up the formation of the second initial sacrificial hole 33 on the second sub-sacrifice layer 22.
  • the etching speed is high, and the dry etching can better ensure the etching morphology is good; as shown in Fig. 16-Fig. etch, to form a plurality of second sacrificial holes 34, so that part of the edges of the second sacrificial holes 34 are in contact with the first sub-sacrifice layer 21, specifically, when performing wet etching, when etching to the second sub-sacrifice layer 22 and the contact edge of the second sub-sacrifice layer 22, the first sub-sacrifice layer 21 has a blocking effect to block the second sacrificial hole 34 from continuing to extend to the first sub-sacrifice layer 21, so that the edge of the second sacrificial hole 34 is in contact with the first sub-sacrifice layer 21.
  • the sub-sacrifice layer 21 is in contact. As shown in FIG. 17 , another part of the edge of the second sacrificial hole 34 extends away from the center of the second sacrificial hole 34 in the second sub-sacrifice layer 22 , so that part of the edge of the second sacrificial hole 34 faces the second sub-sacrifice layer 22
  • the direction of the first sub-sacrifice layer 21 on both sides extends to the first sub-sacrifice layer 21, and the etch rate of the first sub-sacrifice layer 21 limits the extended etching of the second sacrificial hole 34, so that the second sacrificial hole 34 faces the first sub-sacrifice layer 21.
  • the diameter of a portion of the edge extending in the direction of a sub-sacrifice layer 21 is smaller than the diameter of the second sacrificial hole 34 in the direction away from the center of the second sub-sacrifice layer 22, so that the area of the second sacrificial hole 34 can be further increased to increase the subsequent The area of the formed second capacitive hole 36 and the size of the capacitive structure.
  • the expansion directions of the first sacrificial hole 32 and the second sacrificial hole 34 are different, so that the subsequently formed first capacitor hole 35 and the second capacitor hole 36 can expand in different directions, so as to effectively expand the capacity of the subsequently formed capacitor structure. capacitive area without reducing the line width of the double imaging.
  • a mask layer 6 can be formed on the sacrificial layer 2 by using a double imaging process, and the mask layer 6 can include a first mask opening 61 and a second mask opening 62, that is, the first mask
  • the opening 61 and the second mask opening 62 can be formed simultaneously by a dual imaging process, as shown in FIG. 12-FIG. and the second sacrificial hole 34, the first sacrificial hole 32 and the second sacrificial hole 34 can be directly formed by one-step etching, or can be formed by dry etching first and then combined with wet etching, so that the final formation can be improved.
  • the morphology of the first sacrificial hole 32 and the second sacrificial hole 34 can be formed on the sacrificial layer 2 by using a double imaging process, and the mask layer 6 can include a first mask opening 61 and a second mask opening 62, that is, the first mask
  • the opening 61 and the second mask opening 62 can be formed simultaneously by a dual
  • the width of the first sub-sacrifice layer 21 (for example, the width along the first direction) can be smaller than the width of the second sub-sacrifice layer 22 (for example, the width along the first direction), so that through the first mask opening 61 and the second When the mask opening 62 etches the sacrificial layer 2, since the etch rate of the first sub-sacrifice layer 21 is lower than the etch rate of the second sub-sacrifice layer 22, the first initial sacrificial hole 31 and the second initial sacrificial hole are formed.
  • the first initial sacrificial hole 31 can extend toward the second sub-sacrifice layer 22 to form the first sacrificial hole 32, and the second initial sacrificial hole 33 can be in the second sub-sacrifice layer 22
  • the etching rate of the second sub-sacrifice layer 22 is high, which can further increase the area of the first sacrificial hole 32 and the second sacrificial hole 34 formed by wet etching, In order to improve the capacitance of the finally formed capacitor structure.
  • the edge of the first initial sacrificial hole 31 is located in the first sub-sacrifice layer 21 , and part of the edge of the second initial sacrificial hole 33 may also be in contact with the first sub-sacrifice layer 21 . In some embodiments, part of the edge of the first initial sacrificial hole 31 is in contact with the second sub-sacrifice layer 21 , and a part of the edge of the second initial sacrificial hole 33 is in contact with the first sub-sacrifice layer 21 .
  • the etching rate of the second sub-sacrifice layer 22 is large, the area of the first sacrificial layer hole 32 and the second sacrificial hole 34 can be increased to improve The capacitance of the resulting capacitive structure.
  • a plurality of first sacrificial holes 32 and a plurality of second sacrificial holes 34 are alternately arranged; wherein, the first direction is perpendicular to the first sub-sacrifice layer 21
  • the second direction is a direction parallel to the first sub-sacrifice layer 21, specifically, a plurality of first sacrificial holes 32 and a plurality of second sacrificial holes 34 are distributed in an array, and a plurality of first sacrificial holes 32 and a plurality of The second sacrificial holes 34 can be formed in multiple rows and columns, and the rows of first sacrificial holes 32 and the rows of second sacrificial holes 34 are alternately distributed in one direction in the first direction or the second direction, and adjacent Two rows of multiple first sacrificial holes 32 and multiple second sacrificial holes 34 are staggered in another direction, so that more first sacrificial holes 32 and second s
  • first sacrificial holes 32 and the second sacrificial holes 34 are not staggered, for example, the first sacrificial holes 32 and the second sacrificial holes 34 are distributed alternately along the same direction, the number of the first sacrificial holes 32 and the second sacrificial holes 34 will be reduced.
  • first sacrificial hole 32 and the second sacrificial hole 32 are compact, which will make the distance between the first sacrificial hole 32 and the second sacrificial hole 34 closer or easy to contact.
  • the subsequently formed first capacitor hole 35 and the second capacitor hole 36 may be in contact with each other or connected together, thereby reducing the area of the capacitor hole and reducing the capacitance.
  • the width of the first capacitor hole 35 in the first direction is greater than the width of the second capacitor hole 36 in the first direction, and the width of the first capacitor hole 35 in the second direction is smaller than that of the second capacitor hole 36 Width on the second direction, and the first capacitance hole 35 and the second capacitance hole 36 are arranged in a staggered manner parallel to the first direction or the second direction, thereby the first capacitance hole 35 and the second capacitance hole 36 can be increased area to increase the size of the final capacitive structure.
  • the first capacitor hole 35 and the second capacitor hole 36 are both formed in an oval shape, wherein the major axis of the first capacitor hole 35 and the minor axis of the second capacitor hole 36 are all along the first direction.
  • the short axis of the first capacitance hole 35 and the long axis of the second capacitance hole 36 are all arranged along the second direction, so that the long axis of the first capacitance hole 35 is staggered with the long axis of the second capacitance hole 36, thereby in the same
  • the number of formed first capacitor holes 35 and second capacitor holes 36 can be increased to further increase the capacitance of the finally formed capacitor structure.
  • the material of the first sub-sacrifice layer 21 and the material of the second sub-sacrifice layer 22 are different, so that the etching rate of the first sub-sacrifice layer 21 is lower than that of the second sub-sacrifice layer 22
  • the material of the first sub-sacrifice layer 21 may be silicon oxide
  • the material of the second sub-sacrifice layer 22 may be silicon nitride.
  • the material of the first sub-sacrifice layer 21 is the same as that of the second sub-sacrifice layer 22, and the ion doping type in the first sub-sacrifice layer 21 is the same as the ion doping type of the second sub-sacrifice layer 22.
  • both the first sub-sacrifice layer 21 and the second sub-sacrifice layer 22 can be silicon oxide layers, and the doping concentrations of boron and phosphorus elements affect the etching efficiency of the film layer, specifically, after boron doping , will cause a large induced stress in the film layer, causing silicon oxide to resist external forces greater than that caused by phosphorus-doped silicon oxide, resulting in an increase in the boron content, and the etching rate of the film layer will decrease.
  • the etching rate will increase, so when the first sub-sacrifice layer 21 and the second sub-sacrifice layer 22 are doped with the same type of elements or when both are doped with two types of elements at the same time, by controlling the ion doping of the doping elements
  • the impurity concentration can control the etching rate of the first sub-sacrifice layer 21 and the second sub-sacrifice layer 22, for example, when the first sub-sacrifice layer 21 and the second sub-sacrifice layer 22 are both doped with boron, the first sub-sacrifice layer can be controlled
  • the ion doping concentration of boron element at 21 is greater than the ion doping concentration of boron element in the second sub-sacrifice layer 22 , so that the etching rate of the first sub-sacrifice layer 21 is lower than the etching rate of the second sub-sacrifice layer 22 .
  • the ion doping concentration of phosphorus in the first sub-sacrifice layer 21 can be controlled to be lower than that of the phosphorus in the second sub-sacrifice layer 22. ion doping concentration, so that the etching rate of the first sub-sacrifice layer 21 is lower than the etching rate of the second sub-sacrifice layer 22 .
  • the material of the first sub-sacrifice layer 21 is the same as that of the second sub-sacrifice layer 22, and the ion doping type in the first sub-sacrifice layer 21 is the same as the ion doping type of the second sub-sacrifice layer 22.
  • Different doping types specifically, different ion doping types affect the etching rate of the film layer, and the etching rate of the first sub-sacrifice layer 21 and the second sub-sacrifice layer 22 can be controlled by doping different elements, for example, it can be added to the first sub-sacrifice layer 22.
  • One sub-sacrifice layer 21 is doped with boron
  • the second sub-sacrifice layer 22 can be doped with phosphorus
  • the first sub-sacrifice layer 21 can be doped with boron
  • the second sub-sacrifice layer 22 can be doped with boron and phosphorus element, or, the first sub-sacrifice layer 21 is not ion-doped, and the second sub-sacrifice layer 22 is at least doped with phosphorus element
  • boron element will reduce the etching rate of the film layer
  • doping phosphorus element will improve the film layer etching rate, so that the etching rate of the first sub-sacrifice layer 21 can be lower than the etching rate of the second sub-sacrifice layer 22 .
  • the material of the first sub-sacrifice layer 21 is the same as that of the second sub-sacrifice layer 22, but the deposition processes of the first sub-sacrifice layer 21 and the second sub-sacrifice layer 22 are different, for example, Both the first sub-sacrifice layer 21 and the second sub-sacrifice layer 22 can be silicon oxide layers, wherein the second sub-sacrifice layer 22 can be formed by annealing compared with the first sub-sacrifice layer 21 during the deposition process, or the first sub-sacrifice layer
  • the layer 21 may be an HDP oxide layer
  • the second sub-sacrifice layer 22 may be a TEOS oxide layer.
  • the etch rate of the first sub-sacrifice layer 21 is greater than the etch rate of the second sub-sacrifice layer 22 .
  • the following table shows the etching rate when the same material is doped with different elements and different processes are used under the same conditions of hydrofluoric acid etching.
  • the etching rate of TEOS is significantly different from that of BPTEOS.
  • the etching rate of TEOS oxide layer is higher than that of the oxide layer formed by BPTEOS with B (boron) content of 3.6% and P (phosphorus element) content of 9%.
  • the etching rate is greater than the etching rate of the oxide layer formed by BPTEOS with a B (boron) content of 2.03% and a P (phosphorus) content of 7.95%.
  • the B (boron) content is 3.6%
  • the P (phosphorus) content is 3.6%.
  • etching rate of the oxide layer that 9% BPTEOS forms is greater than B (boron element) content is 2.03%, and the etching rate of the oxide layer that P (phosphorus element) content is 7.95% BPTEOS forms;
  • B boron element
  • P phosphorus element
  • the doping concentration is relatively large.
  • the etching rate of the silicon oxide produced by the TEOS of the ozone technology is greater than the etching rate of the silicon oxide produced by the TEOS of the ozone technology of the annealing process, wherein the first sub-sacrifice layer 21 and the second sub-sacrifice layer 22 can be in the above table Any two, as long as the etching rate of the first sub-sacrifice layer 21 is lower than the etching rate of the second sub-sacrifice layer 22 .
  • the invention also proposes a semiconductor structure.
  • a semiconductor structure may include a substrate 1 and a plurality of first capacitor holes 35, and a plurality of the first capacitor holes 35 are located in the substrate 1; wherein, the first capacitor holes 35 are The width in one direction is greater than the width in the second direction of the first capacitor hole 35 , for example, as shown in FIG. 17 , the first capacitor hole 35 may be formed as an elliptical hole.
  • the expansion of the first capacitive hole 35 in the first direction is larger than that in the second direction, and the first capacitive hole 35 is subsequently used to form a capacitive structure, so that the area of the capacitive structure can be increased in the first direction to improve capacitance.
  • the semiconductor structure further includes a plurality of second capacitance holes 36, and the plurality of second capacitance holes 36 are located in the substrate 1; wherein, the width of the second capacitance holes 36 in the first direction is smaller than that of the second capacitance hole.
  • the width of the capacitance hole 36 in the second direction that is, the expansion of the second capacitance hole 36 in the first direction is greater than the expansion in the second direction, and the second capacitance hole 36 is subsequently used to form a capacitance structure, thereby enabling the expansion in the second direction Increase the area of the capacitor structure to increase the capacitance.
  • the second capacitive hole 36 may be formed in an oval shape.
  • the width of the first capacitive hole 35 in the first direction is greater than the width of the second capacitive hole 36 in the first direction; the width of the first capacitive hole 35 in the second direction is smaller than the second
  • the width of the capacitor hole 36 in the second direction, in the first direction and the second direction, the expansion direction of the large diameter of the first capacitor hole 35 and the second capacitor hole 36 is different, thereby facilitating the first capacitor
  • the formation of the holes 35 and the second capacitor holes 36 and the staggered arrangement in the first direction and the second direction can also facilitate the formation of more first capacitor holes 35 and second capacitor holes 36 on the same plane.
  • a plurality of first capacitance holes 35 are parallel to a plurality of second capacitance holes 36; and the first capacitance holes 35 and the second capacitance holes 36 Arranged alternately, specifically, a plurality of first capacitance holes 35 and a plurality of second capacitance holes 36 are distributed in an array, and a plurality of first capacitance holes 35 and a plurality of second capacitance holes 36 can be formed in multiple rows and columns, and Multiple rows of first capacitor holes 35 and multiple rows of second capacitor holes 36 are alternately distributed in one direction in the first direction and the second direction, and multiple first capacitor holes 35 and multiple second capacitor holes in two adjacent rows
  • the capacitor holes 36 are arranged alternately in another direction, so that more first capacitor holes 35 and second capacitor holes 36 can be formed on the same area, so as to further increase the capacitance of the capacitor structure.

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Abstract

该发明公开了一种半导体结构及其制造方法，所述制造方法包括：提供一基底；形成牺牲层于基底上，牺牲层包括间隔设置的第一子牺牲层和第二子牺牲层，第一子牺牲层和第二子牺牲层分别与基底接触，第一子牺牲层的刻蚀速率小于第二子牺牲层的刻蚀速率；形成掩膜层于牺牲层上，掩膜层包括多个第一掩膜开口，多个第一掩膜开口位于第一子牺牲层上；通过第一掩膜开口对第一子牺牲层进行刻蚀，以形成多个第一牺牲孔，第一牺牲孔的部分边缘延伸至第二子牺牲层内；通过多个第一牺牲孔对基底进行刻蚀，以形成多个第一电容孔。根据本发明实施例的制造方法能够增加电容孔的面积以增大电容且不需要改变电容图案线宽，工艺简单且成本低。

Description

半导体结构及其制造方法
相关申请引用说明
本申请要求于2022年02月21日递交的中国专利申请号202210158877.8、申请名为“半导体结构及其制造方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本发明涉及半导体技术领域，具体涉及一种半导体结构及其制造方法。
背景技术
对于现有技术的半导体结构在制备电容时，电容的大小由双重成像的线宽定义出，若想扩大电容则需要将双重成像工艺中的电容图案的线宽设置的更细，但线宽越细制程稳定度越难控制，并且需要投入更高的成本。
发明内容
本发明的目的在于提供一种半导体结构及其制造方法，能够增加电容孔的面积以增大电容且不需要改变电容图案线宽，工艺简单且成本低。
根据本发明实施例的半导体结构的制造方法，包括：提供一基底；形成牺牲层于所述基底上，所述牺牲层包括间隔设置的第一子牺牲层和第二子牺牲层，所述第一子牺牲层和所述第二子牺牲层分别与所述基底接触，所述第一子牺牲层的刻蚀速率小于所述第二子牺牲层的刻蚀速率；形成掩膜层于所述牺牲层上，所述掩膜层包括多个第一掩膜开口，多个所述第一掩膜开口位于所述第一子牺牲层上；通过所述第一掩膜开口对所述第一子牺牲层进行刻蚀，以形成多个第一牺牲孔，所述第一牺牲孔的部分边缘延伸至所述第二子牺牲层内；通过多个所述第一牺牲孔对所述基底进行刻蚀，以形成多个第一电容孔。
根据本发明的一些实施例，形成多个所述第一牺牲孔的步骤包括：通过干法刻蚀工艺对所述第一子牺牲层进行刻蚀，以在所述第一子牺牲层上形成多个第一初始牺牲孔，所述第一初始牺牲孔的部分边缘与所述第二子牺牲层接触；通过湿法工艺对所述第一初始牺牲孔进行刻蚀以形成所述第一牺牲孔，使得所述第一牺牲孔的部分边缘延伸至所述第二子牺牲层内。
根据本发明的一些实施例，所述掩膜层还包括多个第二掩膜开口，多个所述第二掩膜开口位于所述第二子牺牲层上。
根据本发明的一些实施例，所述制造方法还包括通过所述第二掩膜开口对所述第二子牺牲层进行刻蚀，以形成多个第二牺牲孔；其中所述第二牺牲孔的部分边缘与所述第一子牺牲层接触。
根据本发明的一些实施例，形成多个第二牺牲孔的步骤包括：通过干法刻蚀工艺对所述第二子牺牲层进行刻蚀，以在所述第二子牺牲层内形成多个第二初始牺牲孔，所述第二初始牺牲孔的边缘位于所述第二子牺牲层内；通过湿法刻蚀工艺对多个所述第二初始牺牲孔进行刻蚀，以形成多个第二牺牲孔，使得所述第二牺牲孔的部分边缘与所述第一子牺牲层接触。
根据本发明的一些实施例，所述第二牺牲孔的另一部分边缘在所述第二子牺牲层内向 远离所述第二牺牲孔中心的方向延伸。
根据本发明的一些实施例，在平行于第一方向或第二方向上，多个所述第一牺牲孔和多个所述第二牺牲孔交错排列；其中，所述第一方向为垂直于所述第一子牺牲层的方向，所述第二方向为平行于所述第一子牺牲层的方向。
根据本发明的一些实施例，在形成多个所述第二牺牲孔之后，还包括：通过多个所述第二牺牲孔对所述基底进行刻蚀，以形成多个第二电容孔。
根据本发明的一些实施例，所述第一电容孔在所述第一方向上的宽度大于所述第二电容孔在所述第一方向上的宽度；所述第一电容孔在所述第二方向上的宽度小于所述第二电容孔在所述第二方向上的宽度。
根据本发明的一些实施例，形成所述牺牲层的步骤包括；形成第一牺牲层于所述基底上；刻蚀所述第一牺牲层，以在所述第一牺牲层上形成间隔设置的多个沟槽，所述沟槽暴露出所述基底，将剩余的所述第一牺牲层定义为所述第一子牺牲层；填满多个所述沟槽，以形成多个所述第二子牺牲层。
根据本发明的一些实施例，所述第一子牺牲层的材料和所述第二子牺牲层的材料不同。
根据本发明的一些实施例，所述第一子牺牲层的材料与所述第二子牺牲层的材料相同，所述第一子牺牲层内的离子掺杂类型与所述第二子牺牲层的离子掺杂类型相同，且所述第一子牺牲层的离子掺杂浓度与所述第二子牺牲层的离子掺杂浓度不同。
根据本发明的一些实施例，所述第一子牺牲层的材料与所述第二子牺牲层的材料相同，所述第一子牺牲层内的离子掺杂类型与所述第二子牺牲层的离子掺杂类型不同。
本发明还提出了一种半导体结构。
根据本发明实施例的半导体结构包括：基底；多个第一电容孔，位于所述基底内；其中，所述第一电容孔在第一方向上的宽度大于所述第一电容孔在第二方向上的宽度；多个第二电容孔，位于所述基底内；其中，所述第二电容孔在所述第一方向上的宽度小于所述第二电容孔在所述第二方向上的宽度，所述第一电容孔在所述第一方向上的宽度大于所述第二电容孔在所述第一方向上的宽度；所述第一电容孔在所述第二方向上的宽度小于所述第二电容孔在所述第二方向上的宽度。
根据本发明的一些实施例，在平行于所述第一方向或所述第二方向上，多个所述第一电容孔平行于多个所述第二电容孔；且所述第一电容孔和所述第二电容孔交替排列。
根据本发明实施例的半导体结构及其制造方法，通过在基底上形成间隔设置的第一子牺牲层和第二子牺牲层，第一子牺牲层和第二子牺牲层分别与基底接触；然后在第一子牺牲层上形成第一掩膜开孔，然后根据第一掩膜开孔对第一子牺牲层进行刻蚀，从而形成多个第一牺牲孔，由于第一子牺牲层的刻蚀速率小于第二子牺牲层的刻蚀速率，因此第一牺牲孔的部分边缘会延伸至第二子牺牲层内，由此增大了第一牺牲孔的面积，因此通过第一牺牲孔对基底进行刻蚀时，会增大第一电容孔的面积，也就是可以提高后续电容结构的电容。同时该制造方法不需要改变电容图案的线宽，就可以提高电容结构的电容，工艺简单且成本低。
附图说明
图1为根据本发明实施例的半导体结构的制造方法的流程图；
图2、图4、图6、图8、图10、图12、图14、图16、图18为根据本发明实施例的半导体结构的制造方法的各步骤的剖面结构示意图；
图3为根据本发明实施例的半导体结构制造方法的图2对应的俯视图；
图5为根据本发明实施例的半导体结构制造方法的图4对应的俯视图；
图7为根据本发明实施例的半导体结构制造方法的图6对应的俯视图；
图9为根据本发明实施例的半导体结构制造方法的图8对应的俯视图；
图11为根据本发明实施例的半导体结构制造方法的图10对应的俯视图；
图13为根据本发明实施例的半导体结构制造方法的图12对应的俯视图；
图15为根据本发明实施例的半导体结构制造方法的图14对应的俯视图；
图17为根据本发明实施例的半导体结构制造方法的图16对应的俯视图；
图19为根据本发明实施例的半导体结构制造方法的图18对应的俯视图；
附图标记：
1：基底，11：叠层结构，12：第一氧化物层，13：第一氮化物层，14：第二氧化物层，15：第二氮化物层，16：第三氮化物层，17：器件结构；
2：牺牲层，21：第一子牺牲层，22：第二子牺牲层，23：第一牺牲层，24：沟槽；
31：第一初始牺牲孔，32：第一牺牲孔，33：第二初始牺牲孔，34：第二牺牲孔，35：第一电容孔，36：第二电容孔；
4：硬掩模层，41：旋涂硬掩模层，42：氮氧化硅层，43：光刻胶层；
5：牺牲缓冲层；
6：掩膜层，61：第一掩膜开口，6：第二掩膜开口。
具体实施方式
以下结合附图和具体实施方式对本发明提出的一种半导体结构及其制造方法作进一步详细说明。
如图1所示，根据本发明实施例的半导体结构的制造方法，包括：提供一基底1；形成牺牲层2于所述基底1上，所述牺牲层2包括间隔设置的第一子牺牲层21和第二子牺牲层22，所述第一子牺牲层21和所述第二子牺牲层22分别与所述基底1接触，所述第一子牺牲层21的刻蚀速率小于所述第二子牺牲层22的刻蚀速率；形成掩膜层于所述牺牲层2上，所述掩膜层包括多个第一掩膜开口，多个所述第一掩膜开口位于所述第一子牺牲层21上；通过所述第一掩膜开口对所述第一子牺牲层21进行刻蚀，以形成多个第一牺牲孔32，所述第一牺牲孔32的部分边缘延伸至所述第二子牺牲层22内；通过多个所述第一牺牲孔32对所述基底1进行刻蚀，以形成多个第一电容孔35。
图2-图17为根据本发明实施例的半导体结构的制造方法的各步骤的剖视图和俯视图，下面结合附图2-图17描述根据本发明实施例的半导体结构的制造方法和半导体结构。
所述基底1可以为硅或硅锗材料，基底1中还可以形成晶体管等器件，如图1-图17所 示，基底1可以包括氧化物层和和氮化物层层叠交替设置的叠层结构11和叠层结构11下方的器件结构17，电容孔贯穿叠层结构11，电容结构形成在电容孔内，器件结构17可与后续形成的电容结构电性接触。
如图2所示，叠层结构11在从下至上的方向上依次包括第一氧化物层12、第一氮化物层13、第二氧化物层14、第二氮化物层15和第三氮化物层16，进一步地，第一氧化物层12和第二氧化物层14均可以为氧化硅层，第一氮化物层13和第二氮化物层15可以为氮化硅层，第三氮化物层16可以为氮氧化硅层42。其中第一氧化物层12和第二氧化物层14形成为牺牲层，第一氮化物层13和第二氮化物层15形成为支撑层，在叠层结构11中形成电容孔后，去除第一氧化物层12和第二氧化物层14和第三氮化物层16，保留第一氮化物层13和第二氮化物层15，于电容孔内沉积形成电容结构。
如图2-图11所示，形成牺牲层2于基底1上，牺牲层2可以包括间隔设置的第一子牺牲层21和第二子牺牲层22，第一子牺牲层21和第二子牺牲层22分别与基底1接触，也就是说，第一子牺牲层21和第二子牺牲层22均形成在基底1上，而且在基底1的平面上第一子牺牲层21和第二子牺牲层22交替设置，其中第一子牺牲层21和第二子牺牲层22可以形成线型，例如，第一子牺牲层21可以包括多个间隔设置的第一子牺牲条，第二子牺牲层22可以包括多个间隔设置的第二子牺牲条，多个第二子牺牲条位于多个第一子牺牲条之间，以在基底1的平面方向上与第一子牺牲条彼此交替分布设置。其中第一牺牲条和第二牺牲条可以形成为直线型或S形，或者也可以形成为其它形状，对此本发明不作限定，只要第一牺牲条和第二牺牲条彼此交替间隔设置即可。
需要说明的是，基底1与第一子牺牲层21和第二子牺牲层22可以直接接触也可以间接接触，例如，第一子牺牲层21和第二子牺牲层22可以间隔交替形成在基底1的表面上以均与基底1接触，或者基底1和牺牲层2之间可形成有其它膜层，例如基底1和牺牲层2之间还可形成有牺牲缓冲层5，第一子牺牲层21和第二子牺牲层22形成在牺牲缓冲层5表面上，第一子牺牲层21和第二子牺牲层22间隔交替形成在牺牲缓冲层5表面以与基底1通过牺牲缓冲层5间接接触，后续牺牲层2上的电容图案可转移到牺牲缓冲层5化后再转移至基底1上。
牺牲缓冲层5的材料可以为多晶硅，牺牲缓冲层5的厚度可与叠层结构11的厚度相近，例如，牺牲缓冲层5的厚度可与叠层结构11的厚度相同，这样在刻蚀形成电容孔时可同时消耗牺牲缓冲层5，通过设置牺牲缓冲层5也能够保证电容孔刻蚀图案的良好转移，以得到形貌良好的电容孔。
结合图2-图11所示，形成牺牲层2的步骤包括：
如图2和图3所示，形成第一牺牲层23于基底1上，其中第一牺牲层23覆盖基底1的表面，在如图2-图11所示的示例中，基底1上还形成有牺牲缓冲层5，第一牺牲层23覆盖牺牲缓冲层5的表面。
如图4-图9所示，刻蚀所述第一牺牲层23，以在所述第一牺牲层23上形成间隔设置的多个沟槽24，沟槽24暴露出基底1，将剩余的第一牺牲层23定义为第一子牺牲层21，具 体地，如图4所示，在第一牺牲层23上形成有硬掩膜层4，所述硬掩膜层4可以为硬掩膜组合层，例如硬掩膜层4可以包括从下至上依次设置的旋涂硬掩模层41和氮氧化硅层42，在硬掩模层4上形成光刻胶层43，然后进行曝光处理以刻蚀硬掩模层4，并形成硬掩膜图案以定义出形成第一子牺牲层21的图案，以硬掩模图案为掩膜刻蚀第一牺牲层23，以形成多个暴露基底1的沟槽24，并形成线型的第一子牺牲层21。
如图10和图11所示，填满多个沟槽24，以形成多个第二子牺牲层22，具体地，可在沟槽24和第一子牺牲层21表面形成第二牺牲层2，可采用包括但不限于化学机械研磨工艺去除位于第一子牺牲层21表面的第二牺牲层2，保留位于沟槽24内的第二牺牲层2以形成第二子牺牲层22。
结合图12-图13所示，形成掩膜层6于牺牲层2上，掩膜层6包括多个第一掩膜开口61，多个第一掩膜开口61位于第一子牺牲层21上，通过第一掩膜开口61对第一子牺牲层21进行刻蚀，以形成多个第一牺牲孔32，第一牺牲孔32的部分边缘延伸至第二子牺牲层22内，即在沿如附图12所示的上下方向上，多个第一掩膜开口61对应形成在第一子牺牲层21上，在对牺牲层2进行刻蚀时，第一掩膜开口61的图案对应向下转移至第一子牺牲层21上，具体地，在以第一掩膜开口61为掩膜进行刻蚀时，可对第一子牺牲层21刻蚀，当刻蚀至第一子牺牲层21的边缘时，此时第一牺牲孔32并未刻蚀至需要的尺寸大小，仍需要继续刻蚀，使得第一牺牲孔32的刻蚀部分继续在第一子牺牲层21进行，部分向外刻蚀第二子牺牲层22，即第一牺牲孔32能够延伸至第二子牺牲层22内，由于第一子牺牲层21的刻蚀速率小于第二子牺牲层22的刻蚀速率，第一牺牲孔32在第二子牺牲层22的刻蚀延伸速度大于在第一子牺牲层21的刻蚀延伸速度，相比仅在第一子牺牲层21继续刻蚀形成第一牺牲孔32，第一牺牲孔32继续在第二子牺牲层32的刻蚀速率更快，扩展面积更大，这样相同刻蚀条件下，第一牺牲孔32继续在第一子牺牲层21刻蚀至一定尺寸时，第一牺牲孔32继续在第二子牺牲层22的扩展尺寸大于在第一子牺牲层31的扩展尺寸，从而能够增大第一牺牲孔32的面积，而且第一牺牲孔32在朝向第二子牺牲层22的方向扩展尺寸大于在第一子牺牲层21的扩展尺寸，也能够改变第一牺牲孔32的形貌，在此步骤中可采用双重成像定义第一掩膜开口61的图案并对牺牲层2进行刻蚀以形成多个第一牺牲孔32。
如图16-图19所示，通过多个第一牺牲孔32对基底1进行刻蚀，以形成多个第一电容孔35，由于第一牺牲孔32的面积增大，后续通过第一牺牲孔32刻蚀形成第一电容孔35时，从而也增加了第一电容孔35的面积，也增加后续形成的电容结构的面积，电容结构的电容大小与电容结构的面积成正比，电容结构面积增大从而也增大了电容大小，而且不需要缩小双重成像的线宽，降低了研发成本。
具体地，结合图12-图15所示，形成多个第一牺牲孔32的步骤包括：如图12-图13所示，通过干法刻蚀工艺对所述第一子牺牲层21进行刻蚀，以在所述第一子牺牲层21上形成多个第一初始牺牲孔31，第一初始牺牲孔31的部分边缘与所述第二子牺牲层22接触；如图14-图15所示，通过湿法工艺对所述第一初始牺牲孔31进行刻蚀以形成所述第一牺牲孔32，使得所述第一牺牲孔32的部分边缘延伸至所述第二子牺牲层22内，也就是说，可 先采用干法刻蚀在第一子牺牲层21以形成第一初始牺牲孔31，干法刻蚀的纵向刻蚀速率快从而能够加快第一初始牺牲孔31的刻蚀，而且采用干法刻蚀也能够更好地保证刻蚀形貌良好，当第一初始牺牲孔31刻蚀至第一子牺牲层21与第二子牺牲层22接触时，干法刻蚀停止，然后采用湿法刻蚀对第一初始牺牲孔31继续刻蚀，此时湿法刻蚀可同时在第一子牺牲层21和第二子牺牲层22进行以形成第一牺牲孔32，即采用湿法工艺沿第一初始牺牲孔31的部分边缘继续刻蚀第二子牺牲层22，使得第一牺牲孔32的部分边缘延伸至第二子牺牲层22内，并沿第一初始牺牲孔31的另一部分边缘继续刻蚀第一子牺牲层21，由于第一子牺牲层21的刻蚀速率小于第二子牺牲层22的刻蚀速率，使得湿法刻蚀在第二子牺牲层22的扩展面积大于湿法刻蚀在第一子牺牲层21的扩展面积，相比仅在第一子牺牲层21内形成第一牺牲孔32，从而能够增大第一牺牲孔32的面积，以增大后续形成的第一电容孔35的面积。
在本发明的一些实施例中，如图13所示，掩膜层6还包括多个第二掩膜开口62，多个第二掩膜开口62位于第二子牺牲层22上，即掩膜层6形成在牺牲层2上，第二掩膜开口62在上下方向上对应位于第二子牺牲层22上，通过第二掩膜开口62可向下对第二子牺牲层22刻蚀，在此步骤中，可采用双重成像工艺形成具有第二掩膜开口62的掩膜层6。
结合图13、图15、图17和图19所示，通过第二掩膜开口62对第二子牺牲层22进行刻蚀，以形成多个第二牺牲孔34，并去除掩膜层6，其中第二牺牲孔34的部分边缘与第一子牺牲层21接触，第二牺牲孔34的其它部分边缘位于第二子牺牲层22内，通过第二掩膜开口62形成第二牺牲孔34并可后续形成第二电容孔36，相比仅形成第一电容孔35，从而增加了电容孔总面积，而且第二牺牲孔34形成在第二子牺牲层22内，第二子牺牲层22的两侧为第一子牺牲层21，第一子牺牲层21的刻蚀速率小，使得第二牺牲孔34部分边缘刻蚀邻近至第一子牺牲层21的边缘时刻蚀速率降低，而第二牺牲孔34在第二子牺牲层22的其它边缘刻蚀扩展速率快，这样使得第二牺牲孔34与第一牺牲孔32朝向不同方向扩大，使得后续形成的电容孔朝向不同方向扩大，能够有效提高后续形成的电容结构的电容。如图18-图19所示，通过多个第二牺牲孔34对基底1进行刻蚀，以形成多个第二电容孔36，从而能够增大第二电容孔36的面积，以增大后续形成的电容结构的大小。
如图12-图17所示，形成多个第二牺牲孔34的步骤包括：如图12-图15示，通过干法刻蚀工艺对第二子牺牲层22进行刻蚀，以在第二子牺牲层22内形成多个第二初始牺牲孔33，第二初始牺牲孔33的边缘位于第二子牺牲层22内，即第二初始牺牲孔33不超出第二子牺牲层22，且第二初始牺牲孔33的边缘未延伸至第二子牺牲层22的边缘；在此步骤中采用干法刻蚀能够增加纵向刻蚀效率，以加快第二初始牺牲孔33在第二子牺牲层22的刻蚀速度，而且采用干法刻蚀也能够更好地保证刻蚀形貌良好；如图16-图17所示，然后通过湿法刻蚀工艺对多个第二初始牺牲孔33进行刻蚀，以形成多个第二牺牲孔34，使得第二牺牲孔34的部分边缘与第一子牺牲层21接触，具体地，在进行湿法刻蚀时，在刻蚀至第二子牺牲层22和第二子牺牲层22的接触边缘时，第一子牺牲层21具有阻挡作用以阻挡第二牺牲孔34继续向第一子牺牲层21延伸，使得第二牺牲孔34的边缘与第一子牺牲层21 接触。如图17所示，第二牺牲孔34的另一部分边缘在第二子牺牲层22内向远离第二牺牲孔34中心的方向延伸，这样第二牺牲孔34的部分边缘朝向第二子牺牲层22两侧第一子牺牲层21方向延伸至第一子牺牲层21，第一子牺牲层21的刻蚀速率小限制了第二牺牲孔34的延伸刻蚀，从而使得第二牺牲孔34朝向第一子牺牲层21方向延伸的部分边缘的直径小于第二牺牲孔34在第二子牺牲层22朝向远离中心方向的直径，从而能够进一步地增大第二牺牲孔34的面积，以增大后续形成的第二电容孔36的面积和电容结构的大小。而且使得第一牺牲孔32和第二牺牲孔34的扩大方向不同，使得后续形成的第一电容孔35和第二电容孔36能够在不同方向上扩大，以有效扩大了后续形成的电容结构的电容面积，而且不需要缩小双重成像的线宽。
在一些具体示例中，可采用双重成像工艺在牺牲层2上形成掩膜层6，掩膜层6可包括第一掩膜开口61和第二掩膜开口62，也就是说，第一掩膜开口61和第二掩膜开口62可采用双重成像工艺同时形成，结合图12-图17所示，然后以掩膜层6为掩膜对牺牲层2进行刻蚀以同时形成第一牺牲孔32和第二牺牲孔34，第一牺牲孔32和第二牺牲孔34可采用一步刻蚀直接形成，或者可先采用干法刻蚀再结合湿法刻蚀的工艺形成，从而能够提高最终形成的第一牺牲孔32和第二牺牲孔34的形貌。
其中第一子牺牲层21的宽度(例如沿第一方向的宽度)可小于第二子牺牲层22的宽度(例如沿第一方向的宽度)，这样在通过第一掩膜开口61和第二掩膜开口62对牺牲层2进行刻蚀时，由于第一子牺牲层21的刻蚀速率小于第二子牺牲层22的刻蚀速率，在形成第一初始牺牲孔31和第二初始牺牲孔33时，从而使得第一初始牺牲孔31的部分边缘能够与第二子牺牲层22接触且第二初始牺牲孔33的边缘位于第二子牺牲层22内，在采用湿法工艺对第一初始牺牲孔31和第二初始牺牲孔33时，第一初始牺牲孔31可朝向第二子牺牲层22延伸以形成第一牺牲孔32，第二初始牺牲孔33能够在第二子牺牲层22内继续刻蚀延伸以形成第二牺牲孔34，而且第二子牺牲层22的刻蚀速率大，也能够进一步地增加湿法刻蚀形成的第一牺牲孔32和第二牺牲孔34的面积，以提高最终形成的电容结构的电容。
在一些实施例中，第一初始牺牲孔31的边缘位于第一子牺牲层21内，第二初始牺牲孔33的部分边缘还可以与第一子牺牲层21接触。在一些实施例中，第一初始牺牲孔31的部分边缘与第二子牺牲层21接触，且第二初始牺牲孔33的部分边缘与第一子牺牲层21接触。因此在形成第一牺牲孔32和第二牺牲孔34时，由于第二子牺牲层22的刻蚀速率大，由此可以提高第一牺牲层孔32和第二牺牲孔34的面积，以提高最终形成的电容结构的电容。
如图17所示，在平行于第一方向或第二方向上，多个第一牺牲孔32和多个第二牺牲孔34交错排列；其中，第一方向为垂直于第一子牺牲层21的方向，第二方向为平行于第一子牺牲层21的方向，具体地，多个第一牺牲孔32和多个第二牺牲孔34呈阵列分布，多个第一牺牲孔32和多个第二牺牲孔34均可形成为多排多列，且多排第一牺牲孔32和多排第二牺牲孔34在第一方向或第二方向上中的一个方向上交替分布，且相邻两排的多个第一牺牲孔32和多个第二牺牲孔34在另一个方向上交错开设置，从而在相同的面积上，能够 形成更多的第一牺牲孔32和第二牺牲孔34，而第一牺牲孔32和第二牺牲孔34若不交错排列，例如第一牺牲孔32和第二牺牲孔34均沿同一方向交替分布，会减少第一牺牲孔32和第二牺牲孔34的数量，而为了形成相同的电容孔面积，则需要使得第一牺牲孔32和第二牺牲孔32分布更加紧密，则会使得第一牺牲孔32和第二牺牲孔34距离较近或容易接触，这样后续形成的第一电容孔35和第二电容孔36可能会接触一起或连通，从而会导致电容孔面积降低，电容下降。
如图19所示，第一电容孔35在第一方向上的宽度大于第二电容孔36在第一方向上的宽度，第一电容孔35在第二方向上的宽度小于第二电容孔36在第二方向上的宽度，且第一电容孔35和第二电容孔36在平行于第一方向或第二方向上交错排列，从而能够增大第一电容孔35和第二电容孔36的面积，以增大最终形成的电容结构的大小。在如图19所示的示例中，第一电容孔35和第二电容孔36均形成为椭圆形，其中第一电容孔35的长轴与第二电容孔36的短轴均沿第一方向设置，第一电容孔35的短轴和第二电容孔36的长轴均沿第二方向设置，使得第一电容孔35的长轴与第二电容孔36的长轴错开，从而在相同的面积上能够增加形成的第一电容孔35和第二电容孔36的数量，以进一步地提高最终形成的电容结构的电容。
在本发明的一些实施例中，第一子牺牲层21的材料和第二子牺牲层22的材料不同，从而使得第一子牺牲层21的刻蚀速率小于第二子牺牲层22的刻蚀速率，例如第一子牺牲层21的材料可以为氧化硅，第二子牺牲层22的材料可以为氮化硅。
在本发明的另一些实施例中，第一子牺牲层21的材料与第二子牺牲层22的材料相同，第一子牺牲层21内的离子掺杂类型与第二子牺牲层22的离子掺杂类型相同，且第一子牺牲层21的离子掺杂浓度与第二子牺牲层22的离子掺杂浓度不同，从而使得第一子牺牲层21的刻蚀速率小于第二子牺牲层22的刻蚀速率，例如第一子牺牲层21和第二子牺牲层22均可以为氧化硅层，硼，磷元素的掺杂浓度影响膜层的刻蚀效率，具体地，掺杂硼元素后，会使得膜层产生较大的诱导应力，引起例如氧化硅抵抗外部作用力大于掺杂磷元素的氧化硅引起的外部作用力，导致增加硼的含量，则膜层的刻蚀速率会下降，增加磷的含量，刻蚀速率会上升，这样第一子牺牲层21和第二子牺牲层22掺杂同一类型元素时或同时均掺杂两种类型元素时，通过控制掺杂元素的离子掺杂浓度可控制第一子牺牲层21和第二子牺牲层22的刻蚀速率，例如第一子牺牲层21和第二子牺牲层22均掺杂硼元素时，可控制第一子牺牲层21的硼元素的离子掺杂浓度大于第二子牺牲层22的硼元素的离子掺杂浓度，以使得第一子牺牲层21的刻蚀速率小于第二子牺牲层22的刻蚀速率。或者，当第一子牺牲层21和第二子牺牲层22均掺杂磷元素时，可控制第一子牺牲层21的磷元素的离子掺杂浓度小于第二子牺牲层22的磷元素的离子掺杂浓度，以使得第一子牺牲层21的刻蚀速率小于第二子牺牲层22的刻蚀速率。
在本发明的另一些实施例中，第一子牺牲层21的材料与第二子牺牲层22的材料相同，第一子牺牲层21内的离子掺杂类型与第二子牺牲层22的离子掺杂类型不同，具体地，不同离子掺杂类型影响膜层的刻蚀速率，通过掺杂不同元素可控制第一子牺牲层21和第二子 牺牲层22的刻蚀速率，例如可向第一子牺牲层21掺杂硼元素，可向第二子牺牲层22掺杂磷元素，或者，可向第一子牺牲层21掺杂硼元素，可向第二子牺牲层22掺杂硼元素和磷元素，再或者，第一子牺牲层21不进行离子掺杂，而第二子牺牲层22至少掺杂磷元素，硼元素会降低膜层的刻蚀速率而掺杂磷元素会提高膜层的刻蚀速率，从而能够使得第一子牺牲层21的刻蚀速率小于第二子牺牲层22的刻蚀速率。
在本发明的又一些实施例中，第一子牺牲层21的材料与第二子牺牲层22的材料相同，但第一子牺牲层21和第二子牺牲层22沉积的工艺不同，例如，第一子牺牲层21和第二子牺牲层22均可以为氧化硅层，其中第二子牺牲层22在沉积过程中相比第一子牺牲层21可采用退火工艺形成，或者第一子牺牲层21可以为HDP氧化层，第二子牺牲层22可以为TEOS氧化层。在一些实施例中，由于HDP氧化层的致密度低于TEOS氧化层的致密度，因此第一子牺牲层21的刻蚀速率大于第二子牺牲层22的刻蚀速率。
下表为采用氢氟酸刻蚀同等条件下，相同材料掺杂不同元素以及采用不同工艺时的刻蚀速率情况表。
Figure PCTCN2023070667-appb-000001
根据上述表格可知，TEOS相较BPTEOS刻蚀速率明显不同，例如TEOS氧化层的刻蚀速率大于B(硼元素)含量为3.6％，P(磷元素)含量为9％的BPTEOS形成的氧化层的刻蚀速率，且大于B(硼元素)含量为2.03％，P(磷元素)含量为7.95％的BPTEOS形成的氧化层的刻蚀速率，B(硼元素)含量为3.6％，P(磷元素)含量为9％的BPTEOS形成的氧化层的刻蚀速率大于B(硼元素)含量为2.03％，P(磷元素)含量为7.95％的BPTEOS形成的氧化层的刻蚀速率；对于BPTEOS(B＝3.6％，P＝9％)和BPTEOS(B＝2.03％，P＝7.95％)，BPTEOS(B＝3.6％，P＝9％)形成的氧化层的刻蚀速率大于BPTEOS(B＝2.03％，P＝7.95％)形成的氧化层的刻蚀速率，其中BPTEOS(B＝3.6％，P＝9％)和BPTEOS(B＝2.03％，P＝7.95％)相比，硼元素和磷元素的掺杂浓度均较大，在沉积BPTEOS时，当硼元素浓度增大时，会提高磷元素的扩散效率，因此会有更多的磷元素掺杂进去，从而会提高BBPTEOS的刻蚀速率，即硼浓度越大则磷扩散速率越大，因此BPTEOS(B＝3.6％，P＝9％)和BPTEOS(B＝2.03％，P＝7.95％)相比拥有较快的蚀刻速率；采用退火工艺的臭氧技术的TEOS生成的氧化硅的刻蚀速率大于采用退火工艺的臭氧技术的TEOS生成的氧化硅的刻蚀速率，其中第一子牺牲层21和第二子牺牲层22可以为上述表格中的任意两种，只要第一子牺牲层21的刻蚀速率小于第二子牺牲层22的刻蚀速率即可。
本发明还提出了一种半导体结构。
如图19所示，根据本发明实施例的半导体结构可以包括基底1和多个第一电容孔35，多个所述第一电容孔35位于基底1内；其中，第一电容孔35在第一方向上的宽度大于第一电容孔35在第二方向上的宽度，例如，如图17所示，第一电容孔35可形成为椭圆形孔。由此第一电容孔35在第一方向的扩展大于在第二方向的扩展，第一电容孔35后续用于形成电容结构，从而使得能够在第一方向上增大电容结构的面积，以提高电容量。
在本发明的一些实施例中，半导体结构还包括多个第二电容孔36，多个第二电容孔36位于基底1内；其中，第二电容孔36在第一方向上的宽度小于第二电容孔36在第二方向上的宽度，即第二电容孔36在第一方向的扩展大于在第二方向的扩展，第二电容孔36后续用于形成电容结构，从而使得能够在第二方向上增大电容结构的面积，以提高电容量。在如图17所示的示例中，第二电容孔36可形成为椭圆形。
在本发明的一些实施例中，第一电容孔35在第一方向上的宽度大于第二电容孔36在第一方向上的宽度；第一电容孔35在第二方向上的宽度小于第二电容孔36在第二方向上的宽度，这样在第一方向和第二方向上，第一电容孔35和第二电容孔36的宽度大的直径所在的扩展方向不同，从而有利于第一电容孔35和第二电容孔36的形成和在第一方向和第二方向的交错排布，在同一平面上也能够有利于形成更多的第一电容孔35和第二电容孔36。
在本发明的一些实施例中，在平行于第一方向或第二方向上，多个第一电容孔35平行于多个第二电容孔36；且第一电容孔35和第二电容孔36交替排列，具体地，多个第一电容孔35和多个第二电容孔36呈阵列分布，多个第一电容孔35和多个第二电容孔36均可形成为多排多列，且多排第一电容孔35和多排第二电容孔36在第一方向和第二方向上中的一个方向上交替分布，且相邻两排的多个第一电容孔35和多个第二电容孔36在另一个方向上交错开设置，从而在相同的面积上，能够形成更多的第一电容孔35和第二电容孔36，以进一步地提高电容结构的电容大小。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (15)

  1. 一种半导体结构的制造方法，包括：
    提供一基底；
    形成牺牲层于所述基底上，所述牺牲层包括间隔设置的第一子牺牲层和第二子牺牲层，所述第一子牺牲层和所述第二子牺牲层分别与所述基底接触，所述第一子牺牲层的刻蚀速率小于所述第二子牺牲层的刻蚀速率；
    形成掩膜层于所述牺牲层上，所述掩膜层包括多个第一掩膜开口，多个所述第一掩膜开口位于所述第一子牺牲层上；
    通过所述第一掩膜开口对所述第一子牺牲层进行刻蚀，以形成多个第一牺牲孔，所述第一牺牲孔的部分边缘延伸至所述第二子牺牲层内；
    通过多个所述第一牺牲孔对所述基底进行刻蚀，以形成多个第一电容孔。
  2. 根据权利要求1所述的半导体结构的制造方法，其中，包括：形成多个所述第一牺牲孔的步骤包括：
    通过干法刻蚀工艺对所述第一子牺牲层进行刻蚀，以在所述第一子牺牲层上形成多个第一初始牺牲孔，所述第一初始牺牲孔的部分边缘与所述第二子牺牲层接触；
    通过湿法工艺对所述第一初始牺牲孔进行刻蚀以形成所述第一牺牲孔，使得所述第一牺牲孔的部分边缘延伸至所述第二子牺牲层内。
  3. 根据权利要求1所述的半导体结构的制造方法，其中，所述掩膜层还包括多个第二掩膜开口，多个所述第二掩膜开口位于所述第二子牺牲层上。
  4. 根据权利要求3所述的半导体结构的制造方法，其中，还包括通过所述第二掩膜开口对所述第二子牺牲层进行刻蚀，以形成多个第二牺牲孔；其中所述第二牺牲孔的部分边缘与所述第一子牺牲层接触。
  5. 根据权利要求4所述的半导体结构的制造方法，其中，形成多个第二牺牲孔的步骤包括：
    通过干法刻蚀工艺对所述第二子牺牲层进行刻蚀，以在所述第二子牺牲层内形成多个第二初始牺牲孔，所述第二初始牺牲孔的边缘位于所述第二子牺牲层内；
    通过湿法刻蚀工艺对多个所述第二初始牺牲孔进行刻蚀，以形成多个第二牺牲孔，使得所述第二牺牲孔的部分边缘与所述第一子牺牲层接触。
  6. 根据权利要求5所述的半导体结构的制造方法，其中，所述第二牺牲孔的另一部分边缘在所述第二子牺牲层内向远离所述第二牺牲孔中心的方向延伸。
  7. 根据权利要求4所述的半导体结构的制造方法，其中，在平行于第一方向或第二方向上，多个所述第一牺牲孔和多个所述第二牺牲孔交错排列；其中，所述第一方向为垂直于所述第一子牺牲层的方向，所述第二方向为平行于所述第一子牺牲层的方向。
  8. 根据权利要求7所述的半导体结构的制造方法，其中，在形成多个所述第二牺牲孔之后，还包括：
    通过多个所述第二牺牲孔对所述基底进行刻蚀，以形成多个第二电容孔。
  9. 根据权利要求8所述的半导体结构的制造方法，其中，所述第一电容孔在所述第一方向上的宽度大于所述第二电容孔在所述第一方向上的宽度；所述第一电容孔在所述第二方 向上的宽度小于所述第二电容孔在所述第二方向上的宽度。
  10. 根据权利要求1所述的半导体结构的制造方法，其中，形成所述牺牲层的步骤包括；
    形成第一牺牲层于所述基底上；
    刻蚀所述第一牺牲层，以在所述第一牺牲层上形成间隔设置的多个沟槽，所述沟槽暴露出所述基底，将剩余的所述第一牺牲层定义为所述第一子牺牲层；
    填满多个所述沟槽，以形成多个所述第二子牺牲层。
  11. 根据权利要求10所述的半导体结构的制造方法，其中，所述第一子牺牲层的材料和所述第二子牺牲层的材料不同。
  12. 根据权利要求10所述的半导体结构的制造方法，其中，所述第一子牺牲层的材料与所述第二子牺牲层的材料相同，所述第一子牺牲层内的离子掺杂类型与所述第二子牺牲层的离子掺杂类型相同，且所述第一子牺牲层的离子掺杂浓度与所述第二子牺牲层的离子掺杂浓度不同。
  13. 根据权利要求10所述的半导体结构的制造方法，其中，所述第一子牺牲层的材料与所述第二子牺牲层的材料相同，所述第一子牺牲层内的离子掺杂类型与所述第二子牺牲层的离子掺杂类型不同。
  14. 一种半导体结构，包括：
    基底；
    多个第一电容孔，位于所述基底内；
    其中，所述第一电容孔在第一方向上的宽度大于所述第一电容孔在第二方向上的宽度；
    多个第二电容孔，位于所述基底内；
    其中，所述第二电容孔在所述第一方向上的宽度小于所述第二电容孔在所述第二方向上的宽度，所述第一电容孔在所述第一方向上的宽度大于所述第二电容孔在所述第一方向上的宽度；所述第一电容孔在所述第二方向上的宽度小于所述第二电容孔在所述第二方向上的宽度。
  15. 根据权利要求14所述的半导体结构，其中，在平行于所述第一方向或所述第二方向上，多个所述第一电容孔平行于多个所述第二电容孔；且所述第一电容孔和所述第二电容孔交替排列。
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Citations (3)

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JP2004334064A (ja) * 2003-05-12 2004-11-25 Sharp Corp 液晶表示装置及びその製造方法
CN110875285A (zh) * 2018-08-30 2020-03-10 台湾积体电路制造股份有限公司 半导体结构及其形成方法
CN112713087A (zh) * 2019-10-24 2021-04-27 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004334064A (ja) * 2003-05-12 2004-11-25 Sharp Corp 液晶表示装置及びその製造方法
CN110875285A (zh) * 2018-08-30 2020-03-10 台湾积体电路制造股份有限公司 半导体结构及其形成方法
CN112713087A (zh) * 2019-10-24 2021-04-27 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法

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