WO2022095462A1 - 半导体结构及半导体结构的制造方法 - Google Patents

半导体结构及半导体结构的制造方法 Download PDF

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Publication number
WO2022095462A1
WO2022095462A1 PCT/CN2021/101614 CN2021101614W WO2022095462A1 WO 2022095462 A1 WO2022095462 A1 WO 2022095462A1 CN 2021101614 W CN2021101614 W CN 2021101614W WO 2022095462 A1 WO2022095462 A1 WO 2022095462A1
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Prior art keywords
capacitors
capacitor
layer
semiconductor structure
support layer
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PCT/CN2021/101614
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English (en)
French (fr)
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吴锋
朴相烈
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长鑫存储技术有限公司
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Priority to US17/439,894 priority Critical patent/US11622488B2/en
Priority to EP21888165.4A priority patent/EP4199088A4/en
Publication of WO2022095462A1 publication Critical patent/WO2022095462A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for manufacturing the semiconductor structure.
  • DRAM Dynamic random access memory
  • the capacitor array structure includes an array area and a peripheral circuit area connected to the array area, wherein a plurality of capacitors arranged in a rectangular array are arranged in the array area, and a capacitor connected to each capacitor is arranged in the peripheral circuit area.
  • Drive circuit In the dynamic random access memory, the capacitor array structure includes an array area and a peripheral circuit area connected to the array area, wherein a plurality of capacitors arranged in a rectangular array are arranged in the array area, and a capacitor connected to each capacitor is arranged in the peripheral circuit area.
  • Drive circuit is driven circuit.
  • a first aspect of the embodiments of the present application provides a semiconductor structure, which includes: a substrate, the substrate includes an array area and a peripheral circuit area surrounding the array area; the array area is provided with a plurality of capacitors arranged in an array , among the plurality of capacitors located at the edge of the array area, an imaginary angle formed by the center connection lines of any consecutively adjacent three capacitors is greater than 90°.
  • a second aspect of the embodiments of the present application provides a method for manufacturing a semiconductor structure, which includes the following steps:
  • a plurality of capacitors are formed in the support layer corresponding to the array area, a plurality of capacitor arrays are arranged on the array area, and among the capacitors located at the edge of the array area, any continuous adjacent ones An imaginary angle formed by the central connecting lines of the three capacitors is greater than 90°.
  • a virtual angle formed by the center connection lines of any continuous adjacent three capacitors is greater than 90°, to avoid Among the capacitors located at the edge of the array area, the center lines of any adjacent three capacitors form a right angle, that is, to prevent the capacitors located at the edge of the array area from forming a rectangular pattern, which can reduce the number of capacitors located at the edge of the array area. Therefore, the damage probability of the capacitors located on the edge of the array region is reduced, and the storage performance of the semiconductor structure is improved.
  • FIG. 1 is a schematic diagram 1 of a semiconductor structure provided in the related art
  • FIG. 2 is a schematic diagram 2 of a semiconductor structure provided in the related art
  • FIG. 3 is a schematic diagram 1 of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 4 is a second schematic diagram of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram 3 of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram 4 of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 7 is a perspective view of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 8 is a plan view 1 of a support layer provided by an embodiment of the present application.
  • FIG. 9 is a top view 2 of a support layer provided by an embodiment of the present application.
  • FIG. 10 is a process flow diagram of a method for manufacturing a semiconductor structure provided by an embodiment of the present application.
  • FIG. 11 is a first structural schematic diagram of forming a first photoresist layer and a second photoresist layer in the manufacturing method of the semiconductor structure provided by the embodiment of the present application;
  • FIG. 12 is a structural schematic diagram 2 of forming a first photoresist layer and a second photoresist layer in the manufacturing method of the semiconductor structure provided by the embodiment of the application;
  • FIG. 13 is a schematic structural diagram of forming a first photoresist layer and a second photoresist layer in a method for manufacturing a semiconductor structure in the related art
  • FIG. 14 is a schematic structural diagram of forming a capacitor hole in a method for manufacturing a semiconductor structure provided by an embodiment of the present application.
  • FIG. 15 is a schematic structural diagram of forming a capacitor hole in a manufacturing method of a semiconductor structure in the related art
  • 16 is a schematic structural diagram of forming a first electrode layer in a method for manufacturing a semiconductor structure provided by an embodiment of the present application;
  • FIG. 17 is a schematic structural diagram of forming a first electrode layer in a method for manufacturing a semiconductor structure in the related art
  • FIG. 18 is a schematic structural diagram of forming a third photoresist layer in a method for manufacturing a semiconductor structure in the related art
  • FIG. 19 is a schematic structural diagram of forming a third photoresist layer in the method for manufacturing a semiconductor structure provided by an embodiment of the present application.
  • the capacitor array structure includes an array area 10 and a peripheral circuit area 20 connected to the array area 10 , and a plurality of capacitors 11 are arranged in the array area 10 , and the plurality of capacitors 11 are arranged in a rectangular array , that is to say, the plurality of capacitors 11 can be divided into several rows of capacitor groups, and several rows of capacitor groups are arranged at intervals along the column direction, wherein the capacitors in the adjacent two rows of capacitor groups can be arranged in a staggered position to form an arrangement as shown in FIG. 1 , The capacitors in two adjacent rows of capacitor banks can also be aligned to form an arrangement as shown in FIG. 2 .
  • the capacitors 11 near the edge of the array area 10 are subject to greater stress, and in the subsequent etching, development or exposure processes, the capacitors 11 close to the array area 10 are subject to greater stress.
  • the capacitors 11 at the edge of the region 10 are easily damaged, for example, the capacitors 11 are easily collapsed, and the above phenomenon is called the loading effect.
  • the capacitors 11 located at the corners of the rectangular array area that is, the capacitors 11 in the area A shown in FIG. 1 and the capacitors 11 in the area B shown in FIG. It will also be stressed by the two adjacent right-angled sides of the rectangular array area, resulting in stress concentration at the corners of the array area 10, which in turn causes the capacitors 11 at the corners of the array area 10 to be damaged due to the load effect. storage performance.
  • the embodiments of the present application provide a semiconductor structure and a method for manufacturing the semiconductor structure, so that among several capacitors located at the edge of the array area, a virtual circuit formed by the center lines of any continuous adjacent three capacitors is formed. If the angle is greater than 90°, at least one of the angles formed by the center connection lines of adjacent three capacitors among the capacitors located on the edge of the array area is avoided to be a right angle, that is, to avoid the formation of several capacitors located on the edge of the array area.
  • the rectangular pattern can reduce the stress on the capacitors located on the edge of the array area, thereby reducing the damage probability of the capacitors located on the edge of the array area, and improving the storage performance of the semiconductor structure.
  • an embodiment of the present application provides a semiconductor structure, the semiconductor structure includes a substrate, and the substrate is used as a supporting member of the semiconductor structure to support other components disposed thereon, wherein the substrate can be composed of It is made of semiconductor material, and the semiconductor material can be one or more of silicon, germanium, silicon-germanium compound and silicon-carbon compound.
  • the semiconductor structures mentioned in the embodiments of the present application may be memories, transistors, or other semiconductor devices.
  • the following embodiments are described by taking memories as an example.
  • the substrate includes an array area 10 and a peripheral circuit area 20 surrounding the array area 10 , wherein the peripheral circuit area 20 is provided with a driving circuit for electrically connecting with the capacitor 11 in the array area 10 to provide a driving signal for the capacitor 11 .
  • surrounding can be understood as half surrounding, that is to say, the peripheral circuit areas 20 may be disposed on opposite sides of the array area 10, or the peripheral circuit areas 20 may surround the array area 10 and two adjacent to each other.
  • the side, or the surrounding can be understood as full surrounding, that is, the peripheral circuit area 20 is arranged around the array area 10 .
  • the array area 10 is provided with a plurality of capacitors 11, and the plurality of capacitors 11 are arranged in an array on the array area 10, that is, the plurality of capacitors 11 are distributed on the array area 10 according to a certain rule, for example, the plurality of capacitors 11 can be in a circular array Among the capacitors 11 arranged on the array area 10 and located on the edge 12 of the array area, an imaginary angle ⁇ formed by the center lines of the three adjacent capacitors is greater than 90°, that is, any continuous One of the center points of the adjacent three capacitors 11 is used as a vertex, and the connection between the other two center points and the vertex is used as two sides to form a virtual angle ⁇ , and then the other two center points are used as vertices in turn to form the other two. and one of the three virtual angles ⁇ is greater than 90 degrees, that is, the virtual angle ⁇ may be an obtuse angle or a flat angle.
  • At least one of the angles formed by the center lines of adjacent three capacitors among the capacitors 11 located at the edge 12 of the array area is a right angle, that is, the first row of capacitor banks
  • the first capacitor, the second capacitor, and the first capacitor in the third row capacitor bank form a right triangle, or, as shown in FIG.
  • At least one of the angles formed by the center lines of the capacitors is a right angle, that is, the first capacitor in the first row capacitor bank, the second capacitor in the second row capacitor bank and the first capacitor in the second row capacitor bank form a right triangle,
  • the pattern formed by the capacitors 11 located at the edge 12 of the array area is a rectangle, which increases the damage probability of the capacitors 11 located at the corners of the rectangle, that is, increases the capacitors located in the area A in FIG. 2, the damage probability of the capacitor in the B region, which in turn reduces the storage performance of the semiconductor structure.
  • an imaginary angle ⁇ formed by the center lines of any continuous adjacent three capacitors 11 is greater than 90°, so as to ensure that the capacitors 11 located in the array area are
  • the patterns formed by the capacitors 11 on the edge 12 are not rectangular, so that the stress on the capacitors 11 on the edge 12 of the array area can be reduced, which can be reduced in subsequent etching, development or exposure processes.
  • the loading effect of the edge 12 of the array region further reduces the damage probability of the capacitors 11 located on the edge 12 of the array region, and improves the storage performance of the semiconductor structure.
  • the edge 12 of the array area can be understood as the boundary line between the array area 10 and the peripheral circuit area 20 .
  • the plurality of capacitors 11 arranged in an array includes capacitor banks arranged in rows and columns, and the capacitors 11 on the edge 12 of the array area include capacitor banks in rows and columns of capacitor banks. capacitors at the terminals.
  • capacitors 11 at the endpoints of several rows of capacitor banks in this embodiment refer to the first capacitor 11 and the last capacitor 11 of each row of capacitor banks, and at the same time, the capacitors at the endpoints of several columns of capacitor banks 11 refers to the first capacitor 11 and the last capacitor 11 of each column of capacitor banks.
  • a plurality of capacitors 11 constitute a row of capacitor banks, so that a plurality of capacitors constitute a plurality of row capacitor banks, and the plurality of row capacitor banks are arranged at intervals along a column direction, wherein the row direction and the column direction are perpendicular to each other.
  • the plurality of capacitors may be divided into series of capacitor groups, and the series of capacitor groups are arranged at intervals along the row direction.
  • the first capacitor 11 and the last capacitor 11 in each row of capacitor banks, and the center lines of the first capacitor 11 and the last capacitor 11 in each column of capacitor banks form a polygon.
  • any consecutive adjacent A virtual angle ⁇ formed by the center lines of the three capacitors 11 is greater than 90°, so as to ensure that the pattern formed by the capacitors 11 located at the edge 12 of the array area is not a rectangle, which can reduce the number of edges 12 located on the array area.
  • the stress on the capacitors 11 can reduce the load effect of the edge 12 of the array area in the subsequent etching, development or exposure process, thereby reducing the damage probability of the capacitors 11 located at the edge 12 of the array area.
  • the memory performance of the semiconductor structure is improved.
  • the center lines of capacitors 11 located at the endpoints of several rows of capacitor banks and several columns of capacitor banks form a rectangle with chamfered corners, that is, all capacitors 11 in the first row of capacitor banks, the last row All the capacitors 11 in the capacitor bank and the center lines of the capacitors 11 at the end points in the rows of capacitor banks between the first row of capacitor banks and the last row of capacitor banks form a rectangle with chamfered corners.
  • the arrangement of the plurality of capacitors 11 on the array area 10 can be described by the following two embodiments. It should be noted that the following two embodiments are only exemplary to provide two feasible implementations rather than limiting the arrangement of multiple capacitors in the array area.
  • the capacitors 11 in one row of capacitor banks and the capacitors 11 in the other row of capacitor banks can be arranged in a staggered position.
  • the first row of capacitor banks The first and second capacitors in the capacitor bank in the second row and the first capacitor in the capacitor bank in the second row form a virtual obtuse triangle 13, the first capacitor in the capacitor bank in the eighth row and the capacitor in the capacitor bank in the ninth row.
  • Two capacitors form a virtual obtuse triangle 13.
  • the center line of the first capacitor in the three rows of capacitor banks forms a virtual obtuse triangle 13, which can Avoid the capacitors located on the edge 12 of the array area from forming a right angle, so as to reduce the stress on the capacitors 11 located on the edge 12 of the array area.
  • the array can be reduced The loading effect of the edge 12 of the region, thereby reducing the damage probability of several capacitors 11 located on the edge 12 of the array region, improves the storage performance of the semiconductor structure.
  • the first and second capacitors in the capacitor bank in the first row and the first capacitor in the capacitor bank in the second row form a virtual obtuse triangle 13, and the first capacitor in the capacitor bank in the eighth row It forms a virtual obtuse triangle 13 with the first and second capacitors in the ninth row of capacitor banks; in the second row to the eighth row of capacitor banks, in any adjacent three row capacitor banks, the first in the three row capacitor banks
  • the center lines of the capacitors can also form a flat angle, so that the center lines of the capacitors 11 located on the edge 12 of the array area, that is, the center lines of the capacitors 11 located at the end points of several rows of capacitor banks and several columns of capacitor banks, form a hexagonal
  • the inner corners of the hexagon are obtuse angles, which can prevent the capacitors located at the edge of the array area from forming right angles, thus reducing the stress on the capacitors 11 located at the edge 12 of the array area.
  • the loading effect of the edge 12 In the process of developing or exposing, the loading effect of the
  • the number of capacitors 11 in each row of capacitor banks is distributed in a trend of increasing first and then decreasing. Distributed on both sides of the symmetry axis, wherein, from the first row capacitor bank to the fourth row capacitor bank, the number of capacitors 11 in each row capacitor bank increases sequentially, from the sixth row capacitor bank to the ninth row capacitor bank, each The number of capacitors in the row capacitor bank decreases sequentially.
  • the capacitors 11 in one row of capacitor banks and the capacitors 11 in the other row of capacitor banks can be arranged in alignment.
  • the plurality of capacitors include nine rows of capacitor banks, the number of capacitors in the first row of capacitor banks is equal to the number of capacitors in the last row of capacitor banks, and the capacitor banks in the first row and the last row of capacitor banks are located in the same row.
  • the number of capacitors is the same, and the number of capacitors in the first row capacitor bank is smaller than that of the remaining capacitor banks, so that the plurality of capacitors located at the edge 12 of the array area, that is, at the endpoints of several row capacitor banks and several column capacitor banks
  • the center connection line of the capacitor 11 forms an octagon, and the interior angles of the octagon are all obtuse angles.
  • the number of capacitors 11 in the capacitor bank in the first row is equal to the number of capacitors 11 in the capacitor bank in the last row, and the number of capacitors 11 in the capacitor bank in the second row is the same as the number of capacitors in the capacitor bank in the eighth row.
  • the number of capacitors 11 in the group is equal, the number of capacitors 11 in the second row capacitor bank is the same as the number of capacitors 11 in the eighth row capacitor bank, and the number of capacitors 11 in the first row capacitor bank is smaller than that in the second row
  • the number of capacitors 11 in the capacitor bank is such that the plurality of capacitors 11 located at the edge 12 of the array area, that is, the center lines of the capacitors 11 at the endpoints of several row capacitor banks and several column capacitor banks form an octagon, and eight The interior angles of a polygon are obtuse angles.
  • the patterns formed by the capacitors 11 located on the edge 12 of the array area are not rectangular, which can reduce the stress on the capacitors 11 located on the edge 12 of the array area.
  • the loading effect of the edge 12 of the array area can be reduced, thereby reducing the damage probability of several capacitors 11 located on the edge 12 of the array area, and improving the storage performance of the semiconductor structure.
  • a line connecting the centers of the capacitors located on two adjacent straight sides and the center of the capacitor located on the chamfered corners between the two straight sides forms a virtual obtuse triangle.
  • the loading effect is preferentially formed at the corners of the rectangle, therefore, the center of the capacitor 11 located on the two adjacent straight sides and the chamfer located between the two straight sides
  • the connection between the centers of the capacitors 11 on the upper part forms a virtual obtuse triangle 13, so that the two adjacent right-angled sides of the rectangle form chamfers, which reduces the load effect at the corners of the rectangle, and further reduces the number of elements located on the edge 12 of the array area.
  • the damage probability of the capacitor 11 improves the storage performance of the semiconductor structure.
  • capacitors 11 located at the endpoints of adjacent rows are simultaneously located on different columns, and capacitors 11 located at the endpoints of adjacent columns are simultaneously located on different rows.
  • the capacitors 11 at the endpoints of one row of capacitor banks and the capacitors 11 at the endpoints of the other row of capacitor banks are located in different columns; in two adjacent columns of capacitor banks, one of the capacitors is in a different column.
  • the capacitors 11 at the endpoints of a bank are located in different rows than the capacitors 11 at the endpoints of another column of capacitor banks.
  • the plurality of capacitors 11 include nine rows of capacitor banks.
  • the first capacitor and the second row of capacitor banks in the first row capacitor bank The first capacitor in the first column is located in the third column and the second column, the first capacitor in the first column capacitor group and the first capacitor in the second column capacitor group are located in the third row and the second row respectively, and the other two adjacent
  • the capacitors at the endpoints of the capacitor banks in one row or two columns are also located in different columns or different rows, which will not be described in detail here in this embodiment.
  • the first capacitor in the capacitor bank in the first row and the first capacitor in the capacitor bank in the second row are respectively located in the fifth column and the fourth column, and the first capacitor in the capacitor bank in the first column is located in the fifth column and the fourth column respectively.
  • the first capacitor in the capacitor bank of the second column are respectively located in the fifth row and the fourth row, and the capacitors at the endpoints of the other two adjacent rows or two columns of capacitor banks are also located in different columns or different rows, and this embodiment is here I won't go into details.
  • the vertical distance between adjacent rows is not equal to the vertical distance between adjacent columns.
  • the vertical distance b between adjacent rows is greater than that of adjacent columns.
  • the vertical distance b between adjacent rows is smaller than the vertical distance a between adjacent columns. In this way, according to the actual area of the array area 10, to adjust the arrangement of the plurality of capacitors 11 .
  • the semiconductor structure further includes a support layer 40 disposed on the substrate 30 , a plurality of capacitor holes are formed on the support layer 40 , and each capacitor hole is provided with a capacitor 11 .
  • the support layer 40 can be formed on the substrate 30 by means of deposition, a plurality of capacitor holes are formed on the support layer 40, and the plurality of capacitor holes can be extended along the vertical direction, so that the bottom of the capacitor holes is located on the substrate 30, when each capacitor When the capacitor 11 is formed in the hole, the capacitor 11 can be electrically connected to the peripheral circuit area 20 to realize the control of the capacitor 11 by the peripheral circuit area 20 .
  • the support layer 40 can separate the plurality of capacitors 11 to facilitate the individual control of the plurality of capacitors 11; on the other hand, the support layer 40 can also support the capacitors 11 to improve the semiconductor structure. strength.
  • each capacitor 11 has a bottom end facing the base and a top end away from the base, and the support layer 40 includes a top support layer 41 , a middle support layer 42 and a bottom support layer (not shown in the figure), wherein the top support layer 40
  • the support layer 41 is located between the plurality of capacitors, and the top surface of the top support layer 41 is flush with the top of the capacitor 11 , and the bottom surface of the top support layer 41 is spaced from the substrate 30 ;
  • the middle support layer 42 is located between the top support layer 41 and the substrate 30 . between; the bottom support layer is provided in the base 30 .
  • This embodiment adopts a three-point support method, which can ensure the structural strength of the semiconductor.
  • a cross-section parallel to the substrate 30 is taken as the cross-section, and the outer contour of the cross-section of the support layer 40 is circular or annular.
  • the stress on the support layer 40 is reduced, so that in the subsequent etching, development or exposure process, the load effect of the edge 12 of the array region can be reduced, the damage to the support layer 40 can be reduced, and the damage to the support layer 40 can be reduced accordingly.
  • the probability of damage to several capacitors 11 on the edge 12 of the array area improves the memory performance of the semiconductor structure.
  • the ring includes a plurality of connecting segments 43 connected end to end in sequence, and an arc-shaped transition is adopted between at least some of the adjacent connecting segments 43; and the tangential direction of the arc between the two connecting segments is the same as the
  • the included angle ⁇ between the connecting segments of the arc connection is an obtuse angle.
  • the ring may include four connecting segments 43 connected end to end in sequence, and arc transitions are adopted between two adjacent connecting segments 43, that is, the ring is a rectangular structure with rounded corners, so that in the During the fabrication process of the semiconductor structure, damage to the corners of the support layer 40 can be reduced, thereby protecting the capacitor.
  • the ring may further include a plurality of straight line segments 44 connected end to end in sequence, and the included angle between at least some of the two adjacent straight line segments 44 is an obtuse angle. As shown in FIG. 9 , the ring may also include eight straight line segments 44 connected end to end, so that the ring has an octagonal structure, which facilitates the manufacture of the support layer 40 , reduces the difficulty of manufacturing the support layer 40 , and saves production costs.
  • a second aspect of the embodiments of the present application further provides a method for manufacturing a semiconductor structure, including the following steps:
  • S100 Provide a substrate, the substrate includes an array area and a peripheral circuit area surrounding the array area.
  • the substrate is used as a supporting member of the semiconductor structure to support other components disposed thereon, wherein the substrate can be made of semiconductor material, for example, the semiconductor material can be silicon, germanium, silicon-germanium compound and silicon-carbon compound one or more of.
  • a layer of insulating material may be deposited on the substrate by means of chemical deposition, physical deposition or evaporation, and the layer of insulating material constitutes a support layer.
  • the first support layer, the first sacrificial layer, the second support layer, the second sacrificial layer and the third support layer may be sequentially deposited on the substrate by chemical deposition, physical deposition or evaporation, and the capacitor hole runs through at least the first support layer.
  • the material of the sacrificial layer is silicon oxide.
  • S300 forming a plurality of capacitors in the supporting layer corresponding to the array area, the arrays of the plurality of capacitors are arranged on the array area, and among the capacitors located on the edge of the array area, the centers of any consecutive adjacent three capacitors are connected to each other.
  • An imaginary angle formed by the line is greater than 90°, and its structure is shown in FIG. 3 to FIG. 6 .
  • a first photoresist layer is formed on the supporting layer 40 corresponding to the array area 10 by a coating-curing method, an inkjet printing method or a deposition method, and the first photoresist layer covers the supporting layer 40 corresponding to the array area 10 the upper surface.
  • the first photoresist layer is patterned by masking, exposing, developing, etching and other patterning methods.
  • the first photoresist layer includes a first mask pattern 50, and the first mask pattern 50 includes alternating A plurality of first shielding areas 51 and a plurality of first opening areas 52 are provided.
  • the second photoresist layer is patterned by masking, exposing, developing, etching and other patterning methods, the second photoresist layer includes a second mask pattern, and the second mask pattern includes a second shielding area 60 and the second opening area, the second shielding area 60 is used to cover part of the first shielding area 51 and part of the first opening area 52, and an arc-shaped transition is adopted between the two adjacent edges of the second shielding area 60 Or use a straight line segment transition;
  • a cleaning process such as ultrasonic cleaning or plasma cleaning, can be used to remove the support layer 40 to be removed, so as to retain the support layer 40 corresponding to the first shielding area 51 and the second shielding area 60, In order to form a plurality of capacitor holes 111 on the support layer 40 .
  • a plurality of capacitor holes 111 are arrayed in the array area 10 , among the plurality of capacitor holes 111 located at the edge 12 of the array area, one is formed by the center line of any continuous adjacent three capacitor holes.
  • the virtual angle is greater than 90°
  • the shape of the second shielding region 60 is L-shaped, and its structure is shown in FIG. 13 , so that the arrangement of the plurality of capacitor holes formed later is as shown in FIG. 15 , the plurality of capacitor holes 111 are Matrix arrangement.
  • the second photoresist layer is improved, so that an arc-shaped transition or a straight-line transition is adopted between two adjacent edges of the second shielding region 60, so that the edge 12 located in the array region can be Among the capacitor holes 111 above, an imaginary angle formed by the center connection line of any continuous adjacent three capacitor holes is greater than 90°, to avoid the adjacent three capacitor holes 111 located on the edge 12 of the array area.
  • the center lines of the capacitor holes form a right angle, that is, to avoid forming a rectangular pattern for the capacitor holes 111 located on the edge 12 of the array area, which can reduce the stress on the capacitor holes 111 located on the edge 12 of the array area. , thereby reducing the damage probability of several capacitors 11 located on the edge 12 of the array area, and improving the storage performance of the semiconductor structure.
  • S340 Remove the first photoresist layer and the second photoresist layer.
  • a cleaning process such as an ultrasonic cleaning method or a plasma cleaning method, may be used to remove the first photoresist layer and the second photoresist layer. remove.
  • the first electrode layer 112 is also formed in the capacitor hole 111 by means of deposition to form the structure as shown in FIG. 17 .
  • an imaginary angle formed by the center lines of the three adjacent capacitor holes 111 is greater than 90°.
  • a third photoresist layer is formed on the third supporting layer by a coating-curing method, an inkjet printing method or a deposition method, the third photoresist layer covers the upper surface of the third supporting layer, and the third photoresist layer is The projection of the photoresist layer on the substrate 30 coincides with the array region 10, and the third photoresist layer is a rectangle with rounded or chamfered corners.
  • the structure of the third photoresist layer is shown in FIG. That is to say, the third photoresist layer is a rectangle. Therefore, compared with the related art, the third photoresist layer provided in this embodiment can make the subsequently prepared supporting layer be a rectangle with rounded or chamfered corners. In this way, damage to the corners of the support layer can be reduced, and further damage to the capacitors located at the corners of the support layer can be reduced, thereby ensuring the storage performance of the semiconductor structure.
  • the third photoresist layer is patterned to form a third mask pattern 70 .
  • the third mask pattern 70 includes a plurality of third blocking regions 71 and a plurality of third opening regions 72 , wherein the third opening regions 72 are on the supporting layer 40
  • the projection of at least partially overlaps the area between the capacitive holes 111 .
  • the corresponding support layer 40 on the peripheral circuit area 20 is removed to retain the corresponding support layer 40 on the array area.
  • the third support layer corresponding to the third opening area 72 and a part of the first electrode layer 112 are removed to expose the second sacrificial layer corresponding to the third opening area 72, wherein the unremoved third support layer constitutes a top support layer 41.
  • the second sacrificial layer, part of the second supporting layer and the first sacrificial layer are removed, wherein the unremoved second supporting layer constitutes the middle supporting layer 42, and the unremoved first supporting layer constitutes the bottom supporting layer.
  • a plurality of fourth opening areas may be formed at intervals on the second support layer, and fourth shielding areas are formed between adjacent fourth openings, wherein the fourth opening areas are The regions between the projections on the second support layer and the capacitive holes at least partially overlap.
  • the second support layer and part of the first electrode layer corresponding to the fourth opening area are removed to expose the first sacrificial layer corresponding to the fourth opening.
  • the first sacrificial layer is removed, and the unremoved second support layer constitutes the intermediate support layer 42 .
  • a plurality of capacitors are formed in the array area, and one of the plurality of capacitors located on the edge of the array area is formed by connecting the center lines of any continuous adjacent three capacitors.
  • the virtual angle is greater than 90°, so that at least one of the angles formed by the center connecting lines of adjacent three capacitors among the capacitors located on the edge of the array area is a right angle, that is, to avoid the formation of several capacitors located on the edge of the array area.
  • the rectangular pattern can reduce the stress on the capacitors located on the edge of the array area, thereby reducing the damage probability of the capacitors located on the edge of the array area, and improving the storage performance of the semiconductor structure.

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Abstract

本申请提供一种半导体结构及半导体结构的制造方法，涉及显示技术领域，该半导体结构包括基底，所述基底包括阵列区以及围绕所述阵列区的周边电路区，所述阵列区内设有阵列排布的多个电容器，本申请通过使位于所述阵列区的边缘的数个所述电容器中，任意连续相邻的三个所述电容器的中心连线构成的一个虚拟角大于90°，避免位于阵列区的边缘上的数个电容器中任意相邻的三个电容器的中心连线形成直角，即，避免位于阵列区的边缘上的数个电容器形成矩形图案，这样可以降低位于阵列区的边缘上的数个电容器所受的应力，进而降低了位于阵列区的边缘上的数个电容器的损坏几率，提高了半导体结构的存储性能。

Description

半导体结构及半导体结构的制造方法
本申请要求于2020年11月05日提交中国专利局、申请号为202011223554.X、申请名称为“半导体结构及半导体结构的制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体结构及半导体结构的制造方法。
背景技术
动态随机存储器(dynamic random access memory，简称DRAM)是一种高速地、随机地写入和读取数据的半导体存储器，被广泛地应用到数据存储设备或装置中。
在动态随机存储器中，电容器阵列结构包括阵列区以及与阵列区连接的周边电路区，其中，阵列区内设置有呈矩形阵列排布的多个电容器，周边电路区内设有与各个电容器连接的驱动电路。
但是，在制作采用上述的矩形阵列排布的多个电容器时，位于矩形阵列的拐角处的电容器易出现损坏，影响电容器的存储性能。
发明内容
本申请实施例的第一方面提供一种半导体结构，其包括：基底，所述基底包括阵列区以及围绕所述阵列区的周边电路区；所述阵列区内设有阵列排布的多个电容器，位于所述阵列区的边缘的数个所述电容器中，任意连续相邻的三个所述电容器的中心连线构成的一个虚拟角大于90°。
本申请实施例的第二方面提供一种半导体结构的制造方法，其包括如下的步骤：
提供基底，所述基底包括阵列区以及围绕所述阵列区的周边电路区；
在所述基底上形成支撑层；
在与所述阵列区对应的所述支撑层内形成多个电容器，多个电容器阵列排布在所述阵列区上，位于所述阵列区的边缘的数个所述电容器中，任意连续相邻的三个所述电容器的中心连线构成的一个虚拟角大于90°。
本申请实施例所提供的半导体结构及半导体结构的制造方法中，位于阵列区的边缘的数个电容器中，任意连续相邻的三个电容器的中心连线构成的一个虚拟角大于90°，避免位于阵列区的边缘的数个电容器中任意相邻的三个电容器的中心连线形成直角，即，避免位于阵列区的边缘上的数个电容器形成矩形图案，这样可以降低位于阵列区的边缘上的数个电容器所受的应力，进而降低了位于阵列区的边缘上的数个电容器的损坏几率，提高了半导体结构的存储性能。
除了上面所描述的本申请实施例解决的技术问题、构成技术方案的技术特征以及由这些技术方案的技术特征所带来的有益效果外，本申请实施例提供的半导体结构及半导体结构的制造方法所能解决的其他技术问题、技术方案中包含的其他技术特征以及这些技术特征带来的有益效果，将在具体实施方式中作出进一步详细的说明。
附图说明
图1为相关技术中提供的半导体结构的示意图一；
图2为相关技术中提供的半导体结构的示意图二；
图3为本申请实施例提供的半导体结构的示意图一；
图4为本申请实施例提供的半导体结构的示意图二；
图5为本申请实施例提供的半导体结构的示意图三；
图6为本申请实施例提供的半导体结构的示意图四；
图7为本申请实施例提供的半导体结构的立体图；
图8为本申请实施例提供的支撑层的俯视图一；
图9为本申请实施例提供的支撑层的俯视图二；
图10为本申请实施例提供的半导体结构的制造方法的工艺流程图；
图11为本申请实施例提供的半导体结构的制造方法中形成第一光刻胶层和第二光刻胶层的结构示意图一；
图12为本申请实施例提供的半导体结构的制造方法中形成第一光刻 胶层和第二光刻胶层的结构示意图二；
图13为相关技术中半导体结构的制造方法中形成第一光刻胶层和第二光刻胶层的结构示意图；
图14为本申请实施例提供的半导体结构的制造方法中形成电容孔的结构示意图；
图15为相关技术中半导体结构的制造方法中形成电容孔的结构示意图；
图16为本申请实施例提供的半导体结构的制造方法中形成第一电极层的结构示意图；
图17为相关技术中半导体结构的制造方法中形成第一电极层的结构示意图；
图18为相关技术中半导体结构的制造方法中形成第三光刻胶层的结构示意图；
图19为本申请实施例提供的半导体结构的制造方法中形成第三光刻胶层的结构示意图。
附图标记：
10：阵列区；11：电容器；111：电容孔；112：第一电极层；12：阵列区的边缘；13：虚拟钝角三角形；20：周边电路区；30：基底；40：支撑层；41：顶部支撑层；42：中间支撑层；43：连接段；44：直线段；50：第一掩膜图案；51：第一遮挡区；52：第一开口区；60：第二遮挡区；70：第三掩膜图案；71：第三遮挡区；72：第三开口区；α：虚拟角。
具体实施方式
本申请的发明人在实际工作中发现，电容器阵列结构包括阵列区10以及与阵列区10连接的周边电路区20，阵列区10内设有多个电容器11，多个电容器11呈矩形阵列排布，也就是说，多个电容器11可以分为数行电容器组，数行电容器组沿列方向间隔设置，其中，相邻两行电容器组中电容器可以错位设置，形成如图1所示的排列方式，相邻两行电容器组中电容器也可以对齐设置，形成如图2所示的排列方式。
鉴于周边电路区20内元件的密度与阵列区10内的元件密度差异较大， 靠近阵列区10边缘的电容器11受到应力较大，进而在后续的刻蚀、显影或者曝光的工艺中，靠近阵列区10边缘的电容器11容易发生损坏，例如，电容器11容易发生坍塌，上述的现象称之为负载效应。
尤其是，位于矩形阵列区的拐角处的电容器11，即图1中所示的A区域内的电容器11和图2中所示的B区域内的电容器11，既会受到周边电路区的应力，也会受到矩形阵列区的两个相邻的直角边的应力，造成阵列区10的拐角处的应力集中，进而造成阵列区10的拐角处的电容器11因负载效应而发生损坏，影响电容器11的存储性能。
针对上述的技术问题，本申请实施例提供一种半导体结构及半导体结构的制造方法，使得位于阵列区的边缘的数个电容器中，任意连续相邻的三个电容器的中心连线构成的一个虚拟角大于90°，避免位于阵列区的边缘上的数个电容器中相邻的三个电容器的中心连线构成的角中至少一个为直角，即，避免位于阵列区的边缘上的数个电容器形成矩形图案，这样可以降低位于阵列区的边缘上的数个电容器所受的应力，进而降低了位于阵列区的边缘上的数个电容器的损坏几率，提高了半导体结构的存储性能。
为了使本申请实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本申请保护的范围。
如图3和图4所示，本申请实施例提供了一种半导体结构，该半导体结构包括基底，基底作为半导体结构的支撑部件，用于支撑设在其上的其他部件，其中，基底可以由半导体材料制成，半导体材料可以为硅、锗、硅锗化合物以及硅碳化合物中的一种或者多种。
本申请实施例中所提到半导体结构可以为存储器、晶体管或者其他半导体器件，为了便于下文的描述，以下的实施例均以存储器为例进行阐述。
基底包括阵列区10以及围绕阵列区10的周边电路区20，其中，周边电路区20内设置有驱动电路，驱动电路用于与阵列区10内电容器11电连接，以为电容器11提供驱动信号。
需要说明是，本实施例中围绕可以理解为半围绕，也就是说，周边电 路区20可以相对设置在阵列区10的两侧，也可以是周边电路区20围绕阵列区10两个相邻接的侧边，或者是，围绕可以为理解全围绕，即周边电路区20环绕阵列区10设置。
阵列区10内设有多个电容器11，多个电容器11阵列排布在阵列区10上，即，多个电容器11按一定规律分布在阵列区10上，例如，多个电容器11可以呈环形阵列排布在阵列区10上，位于阵列区的边缘12上的数个电容器11中，任意连续相邻的三个电容器的中心连线构成的一个虚拟角α大于90°，也就是说，任意连续相邻的三个电容器11的中心点中一个作为顶点，另外两个中心点与顶点的连线作为两个边，形成一个虚拟角α，再利用另外两个中心点依次作为顶点，形成另外两个虚拟角α，且三个虚拟角α中一个大于90度，也就是说，虚拟角α可以为钝角或者平角。
相关技术中，如图1所示，位于阵列区的边缘12的数个电容器11中相邻的三个电容器的中心连线构成的角中至少一个为直角，也就是说，第一行电容器组中第一个电容器、第二个电容器以及第三行电容器组中的第一个电容器组成直角三角形，或者，如图2所示，位于阵列区的边缘12的数个电容器11中相邻的三个电容器的中心连线构成的角中至少一个为直角，也就是说，第一行电容器组中第一个电容器、第二个电容器以及第二行电容器组中的第一个电容器组成直角三角形，这样会使得位于阵列区的边缘12的数个电容器11形成的图案为矩形，增大了位于矩形转角处的电容器11损坏几率，即增加了位于图1中的A区域内的电容器，以及位于图2中B区域内的电容器的损坏几率，进而降低了半导体结构的存储性能。
因此，本实施例通过使位于阵列区的边缘12上的数个电容器11中，任意连续相邻的三个电容器11的中心连线构成的一个虚拟角α大于90°，以保证位于阵列区的边缘12上的数个电容器11形成的图案并非为矩形，这样可以降低位于阵列区的边缘12上的数个电容器11所受的应力，在后续的刻蚀、显影或者曝光的工艺中，可以降低阵列区的边缘12的负载效应，进而降低了位于阵列区的边缘12上的数个电容器11的损坏几率，提高了半导体结构的存储性能。
需要说明的是，在本实施例中，阵列区的边缘12可以理解为，阵列区10与周边电路区20的交界线。
在一些实施例中，阵列排布的多个电容器11包括排列成若干行和若干列的电容器组，位于阵列区的边缘12上的数个电容器11包括位于若干行电容器组和若干列电容器组的端点处的电容器。
需要说明的是，本实施例中若干行电容器组的端点处的电容器11指代的是每行电容器组的第一个电容器11和最后一个电容器11，同时，若干列电容器组的端点处的电容器11指代的是每列电容器组的第一个电容器11和最后一个电容器11。
在本实施例中，数个电容器11构成一行电容器组，使得多个电容器构成若干行电容器组，多行电容器组沿着列方向间隔排布，其中，行方向和列方向相互垂直。或者是，多个电容器可以分为数列电容器组，数列电容器组沿着行方向间隔设置。
每行电容器组中第一个电容器11和最后一个电容器11，以及每列电容器组中第一个电容器11和最后一个电容器11的中心连线组成一个多边形，在这个多边形中，任意连续相邻的三个电容器11的中心连线构成的一个虚拟角α大于90°，以保证位于阵列区的边缘12的数个电容器11形成的图案并非为矩形，这样可以降低位于阵列区上的边缘12的数个电容器11所受的应力，在后续的刻蚀、显影或者曝光的工艺中，可以降低阵列区的边缘12的负载效应，进而降低了位于阵列区的边缘12的数个电容器11的损坏几率，提高了半导体结构的存储性能。
在一些实施例中，位于若干行电容器组和若干列电容器组的端点处的电容器11的中心连线形成具有倒角的矩形，也就是说，第一行电容器组中所有的电容器11、最后一行电容器组中所有的电容器11以及位于第一行电容器组与最后一行电容器组之间的数行电容器组中端点处电容器11的中心连线形成具有倒角的矩形。
其中，阵列区10上的多个电容器11的排布方式，可以通过以下两种实施方式进行描述，需要说明的是，下面的两种实施例方式仅是示例性地给出两种可行的实施方式，而不是对阵列区内多个电容器的排布方式进行限定。
在一种实施方式中，在任意相邻的两行电容器组中，其中一行电容器组中电容器11与另一行电容器组中电容器11可以错位设置，比如，如图3所示，第一行电容器组中第一个电容器和第二个电容器以及第二行电容 器组中第一个电容器形成虚拟钝角三角形13，第八行电容器组中第一个电容器与第九行电容器组中第一个电容器和第二电容器组成虚拟钝角三角形13，从第二行到第八行电容器组，任意相邻的三行电容器组中，三行电容器组中第一个电容器的中心连线构成虚拟钝角三角形13，这样可以避免位于阵列区的边缘12上的数个电容器形成直角，这样降低位于阵列区的边缘12上的数个电容器11所受的应力，在后续的刻蚀、显影或者曝光的工艺中，可以降低阵列区的边缘12的负载效应，进而降低了位于阵列区的边缘12上的数个电容器11的损坏几率，提高了半导体结构的存储性能。
又比如，如图4所示，第一行电容器组中第一个和第二个电容器以及第二行电容器组中第一个电容器形成虚拟钝角三角形13，第八行电容器组中第一个电容器与第九行电容器组中第一个和第二电容器组成虚拟钝角三角形13；在第二行电容器组至第八行电容器组，任意相邻的三行电容器组中，三行电容器组中第一个电容器的中心连线也可以形成平角，这样，位于阵列区的边缘12上的多个电容器11，即位于若干行电容器组和若干列电容器组的端点处的电容器11的中心连线形成六边形，且六边形的内角均为钝角，这样可以避免位于阵列区的边缘的数个电容器形成直角，这样降低位于阵列区的边缘12的数个电容器11所受的应力，在后续的刻蚀、显影或者曝光的工艺中，可以降低阵列区的边缘12的负载效应，进而降低了位于阵列区的边缘12的数个电容器11的损坏几率，提高了半导体结构的存储性能。
在图4所示的结构中，每行电容器组中电容器11的个数呈先增加后减小的趋势分布，也就是说，以第五行电容器组的中心线为对称轴，其余行电容器组对称分布在对称轴的两侧，其中，从第一行电容器组到第四行电容器组，每行电容器组中电容器11的个数依次增加，从第六行电容器组到第九行电容器组，每行电容器组中电容器的个数依次减少。
在另一种实施例方式中，在任意相邻的两行电容器组中，其中一行电容器组中电容器11与另一行电容器组中电容器11可以对齐设置，比如，如图5所示，本申请实施例提供的半导体结构中，多个电容器包括九行电容器组，第一行电容器组中电容器的个数与最后一行电容器组中的电容器的个数相等，位于第一行电容器组与最后一行电容器组中电容器的个数相同，且第一行电容器组中的电容器的个数小于其余电容器组，使得位于阵 列区的边缘12的多个电容器，即位于若干行电容器组和若干列电容器组的端点处的电容器11的中心连线形成八边形，且八边形的内角均为钝角。
又比如，如图6所示，第一行电容器组中电容器11的个数与最后一行电容器组中的电容器11的个数相等，第二行电容器组中电容器11的个数与第八行电容器组中电容器11的个数相等，位于第二行电容器组电容器11的个数与第八行电容器组中电容器11的个数相同，且第一行电容器组中电容器11的个数小于第二行电容器组中电容器11的个数，使得位于阵列区的边缘12的多个电容器11，即位于若干行电容器组和若干列电容器组的端点处的电容器11的中心连线形成八边形，且八边形的内角均为钝角。
本实施例通过上述的设计，能够保证位于阵列区的边缘12上的数个电容器11形成的图案并非矩形，这样可以降低位于阵列区的边缘12上的数个电容器11所受的应力，在后续的刻蚀、显影或者曝光的工艺中，可以降低阵列区的边缘12的负载效应，进而降低了位于阵列区的边缘12上的数个电容器11的损坏几率，提高了半导体结构的存储性能。
在一些实施例中，在具有倒角的矩形中，位于相邻的两个直边上电容器的中心与位于两个直边之间的倒角上的电容器的中心的连线构成虚拟钝角三角形。
在半导体结构的刻蚀、显影或者曝光的工艺中，负载效应优先形成在矩形的转角处，因此，位于相邻的两个直边上电容器11的中心与位于两个直边之间的倒角上的电容器11的中心的连线构成虚拟钝角三角形13，使得矩形的两个相邻的直角边形成倒角，降低矩形的转角处的负载效应，进而降低位于阵列区的边缘12上的数个电容器11的损坏几率，提高了半导体结构的存储性能。
在一些实施例中，位于相邻行的端点处的电容器11同时位于不同列上，位于相邻列的端点处的电容器11同时位于不同行上。
也就是说，在相邻两行电容器组中，其中一行电容器组的端点处的电容器11与另一行电容器组的端点处的电容器11位于不同列；在相邻两列电容器组中，其中一列电容器组的端点处的电容器11与另一列电容器组的端点处的电容器11位于不同行。
具体地，如图3所示，本实施例提供的半导体结构中，多个电容器11包括九行电容器组，在本实施例中，第一行电容器组中第一个电容器和第 二行电容器组中第一个电容器分别位于第三列和第二列，第一列电容器组中第一个电容器和第二列电容器组中第一个电容器分别位于第三行和第二行，其他相邻两行或者两列电容器组中的端点处的电容器，也位于不同列或者不同行，本实施例在此就不一一赘述了。
又比如，如图4所示，第一行电容器组中第一个电容器和第二行电容器组中第一个电容器分别位于第五列和第四列，第一列电容器组中第一个电容器和第二列电容器组中第一个电容器分别位于第五行和第四行，其他相邻两行或者两列电容器组中的端点处的电容器，也位于不同列或者不同行，本实施例在此就不一一赘述了。
在一些实施例中，相邻行之间的垂直距离与相邻列之间的垂直距离不等，比如，如图3和图4所示，相邻行之间的垂直距离b大于相邻列之间的垂直距离a，又比如，如图5和图6所示，相邻行之间的垂直距离b小于相邻列之间的垂直距离a，这样，可以根据阵列区10的实际面积，来调整多个电容器11的排布方式。
在一些实施例中，如图7所示，半导体结构还包括设置在基底30上的支撑层40，支撑层40上形成多个电容孔，每个电容孔内设有一个电容器11。
支撑层40可以采用沉积的方式在基底30上形成，支撑层40上形成多个电容孔，多个电容孔可以沿着垂直方向延伸，以使电容孔的底部位于基底30上，当每个电容孔内形成电容器11时，电容器11可以与周边电路区20电连接，以实现周边电路区20对电容器11的控制。
在本实施例中，支撑层40一方面可以将多个电容器11分隔开，便于对多个电容器11的单独控制；另一方面，支撑层40还可以对电容器11进行支撑，提高半导体结构的强度。
如图7所示，每个电容器11具有朝向基底的底端和远离基底的顶端，支撑层40包括顶部支撑层41、中间支撑层42以及底部支撑层(图中未示出)，其中，顶部支撑层41位于多个电容器之间，且顶部支撑层41的顶面与电容器11的顶端平齐，顶部支撑层41的底面与基底30间隔设置；中间支撑层42位于顶部支撑层41与基底30之间；底部支撑层设置在基底30内。本实施例采用三点支撑的方式，能够保证半导体的结构强度。
在一些实施例中，以平行于基底30的截面为横截面，支撑层40的横 截面外轮廓为圆形或者环形，相对于相关技术中支撑层40的横截面外轮廓为矩形而言，会减少支撑层40上所受的应力，这样在后续的刻蚀、显影或者曝光的工艺中，可以降低阵列区的边缘12的负载效应，降低对支撑层40的损坏，相应地也会降低了位于阵列区的边缘12上的数个电容器11的损坏几率，提高了半导体结构的存储性能。
在一些实施例中，环形包括多个依次首尾连接的连接段43，至少部分相邻的两个连接段43之间采用弧形过渡；且两个连接段之间的弧形的切线方向，与该弧形连接的连接段之间的夹角β为钝角。
如图8所示，环形可以包括四个依次首尾连接的连接段43，相邻的两个连接段43之间均采用弧形过渡，也就是说，环形为具有圆角的矩形结构，这样在半导体结构的制作工艺中，可以降低对支撑层40的拐角处的损坏，进而可以保护电容器。
在一些实施例中，环形还可以包括多个依次首尾连接的直线段44，至少部分相邻的两个直线段44之间夹角为钝角。如图9所示，环形还可以包括八段依次首尾连接的直线段44，使得环形为八边形结构，这样可以方便支撑层40的制作，降低支撑层40的制备难度，节约生产成本。
如图10所示，本申请实施例的第二方面还提供了一种半导体结构的制造方法，包括如下的步骤：
S100：提供基底，基底包括阵列区以及围绕阵列区的周边电路区。
其中，基底作为半导体结构的支撑部件，用于支撑设在其上的其他部件，其中，基底可以为由半导体材料制成，比如，半导体材料可以为硅、锗、硅锗化合物以及硅碳化合物中的一种或者多种。
S200：在基底上形成支撑层。
在此步骤中，可以通过化学沉积、物理沉积或者是蒸镀的方式在基底上沉积一层绝缘材料，该层绝缘材料构成支撑层。
比如，可以通过化学沉积、物理沉积或者是蒸镀的方式在基底上依次沉积第一支撑层、第一牺牲层、第二支撑层、第二牺牲层以及第三支撑层，电容孔至少贯穿第一牺牲层、第二支撑层、第二牺牲层以及第三支撑层；其中，第一支撑层、第二支撑层以及第三支撑层的材质均为氮化硅，第一牺牲层和第二牺牲层的材质为氧化硅。
S300：在与阵列区对应的支撑层内形成多个电容器，多个电容器阵列 排布在阵列区上，位于阵列区的边缘上的数个电容器中，任意连续相邻的三个电容器的中心连线构成的一个虚拟角大于90°，其结构为图3至图6所示。
在此步骤中，可以采用如下的方式完成：
S310：在与阵列区对应的支撑层上形成第一光刻胶层，第一光刻胶层包括第一掩膜图案，第一掩膜图案包括交替设置的多个第一遮挡区和多个第一开口区，其结构如图11和图12所示。
采用涂布-固化法、喷墨打印法或沉积法在与阵列区10对应的支撑层40上形成第一光刻胶层，第一光刻胶层覆盖在与阵列区10对应的支撑层40的上表面。
通过掩膜、曝光、显影、刻蚀等图形化处理方式，对第一光刻胶层进行图形化处理，第一光刻胶层包括第一掩膜图案50，第一掩膜图案50包括交替设置的多个第一遮挡区51和多个第一开口区52。
S320：在与周边电路区20对应的支撑层40上形成第二光刻胶层，即，采用涂布-固化法、喷墨打印法或沉积法在与周边电路区对应的基底上形成第二光刻胶层，第二光刻胶层覆盖在与周边电路区20对应的支撑层40的上表面。
通过掩膜、曝光、显影、刻蚀等图形化处理方式，对第二光刻胶层进行图形化处理，第二光刻胶层包括第二掩膜图案，第二掩膜图案包括第二遮挡区60和第二开口区，第二遮挡区60用于覆盖部分第一遮挡区51和部分第一开口区52，且第二遮挡区60的两个相邻接的边缘之间采用弧形过渡或者是采用直线段过渡；
S330：去除与第一开口区对应的支撑层，在与阵列区对应的支撑层内形成多个电容孔，其结构如图14所示。
在此步骤中，可以利用清洗工艺，比如超声清洗法或者等离子清洗法，将所要去除的支撑层40进行清除，以保留与第一遮挡区51和第二遮挡区60对应设置的支撑层40，以在支撑层40上形成多个电容孔111。
在本实施例中，多个电容孔111阵列排布在阵列区10内，位于阵列区的边缘12的数个电容孔111中，任意连续相邻的三个电容孔的中心连线构成的一个虚拟角大于90°
而相关技术中，第二遮挡区60的形状为L型，其结构如图13所示， 使得在后续形成的多个电容孔的排布方式，如图15所示，多个电容孔111呈矩阵排布。
本实施例通过对第二光刻胶层进行改进，使得第二遮挡区60的两个相邻接的边缘之间采用弧形过渡或者是采用直线段过渡，这样可以使位于阵列区的边缘12上的数个电容孔111中，任意连续相邻的三个电容孔的中心连线构成的一个虚拟角大于90°，避免位于阵列区的边缘12上的数个电容孔111中相邻的三个电容孔的中心连线形成直角，即，避免位于阵列区的边缘12上的数个电容孔111形成矩形图案，这样可以降低位于阵列区的边缘12上的数个电容孔111所受的应力，进而降低了位于阵列区的边缘12上的数个电容器11的损坏几率，提高了半导体结构的存储性能。
S340：去除第一光刻胶层和第二光刻胶层，在此步骤中，可以利用清洗工艺，比如超声清洗法或者等离子清洗法，将第一光刻胶层和第二光刻胶层去除。
S350：在电容孔内形成第一电极层，形成图16的结构，通过沉积的方式在电容孔111内形成一层覆盖在电容孔111内表面的第一电极层112。
相关技术中，也是通过沉积的方式在电容孔111内形成第一电极层112，形成如图17的结构，本实施例与相关技术相比，本实施例中位于阵列区的边缘12上的数个电容孔111中，任意连续相邻的三个电容孔111的中心连线构成的一个虚拟角大于90°。
S360：在第三支撑层上形成第三光刻胶层，其结构如图19所示。
采用涂布-固化法、喷墨打印法或沉积法在第三支撑层上形成第三光刻胶层，第三光刻胶层覆盖在与第三支撑层的上表面，且第三光刻胶层在基底30上投影与阵列区10重合，且第三光刻胶层为具有圆角或者倒角的矩形，而相关技术中，第三光刻胶层的结构如图18所示，也就是说，第三光刻胶层为矩形，因此，与相关技术相比，本实施例中所提供的第三光刻胶层能够使后续制备的支撑层为具有圆角或者倒角的矩形，这样可以降低对支撑层拐角处的损坏，进而降低位于支撑层拐角处的电容器的损坏，保证了半导体结构的存储性能。
图形化第三光刻胶层形成第三掩膜图案70，第三掩膜图案70包括多个第三遮挡区71和多个第三开口区72，其中第三开口区72在支撑层40上的投影与电容孔111之间的区域至少部分交叠。
去除周边电路区20上对应的支撑层40，以保留阵列区上对应的支撑层40。
去除与第三开口区72对应的第三支撑层和部分第一电极层112，以暴露与第三开口区72对应的第二牺牲层，其中，未被去除的第三支撑层构成顶部支撑层41。
去除第二牺牲层、部分第二支撑层和第一牺牲层，其中，未被去除的第二支撑层构成中间支撑层42，未被去除的第一支撑层构成底部支撑层。
在此步骤中，可以在第二支撑层上形成多个间隔设置的第四开口区(图中未示出)，相邻的第四开口之间形成第四遮挡区，其中第四开口区在第二支撑层上的投影与电容孔之间的区域至少部分交叠。
去除与第四开口区对应的第二支撑层和部分第一电极层，以暴露与第四开口对应的第一牺牲层。
去除第一牺牲层，未被去除的第二支撑层构成中间支撑层42。
S370：在电容孔内形成覆盖第一电极层的介电层和第二电极层，第一电极层、介电层以及第二电极层形成电容器。
本申请实施例所提供的半导体结构的制造方法，在阵列区内形成多个电容器，通过位于阵列区的边缘上的数个电容器中，任意连续相邻的三个电容器的中心连线构成的一个虚拟角大于90°，避免位于阵列区的边缘上的数个电容器中相邻的三个电容器的中心连线构成的角中至少一个为直角，即，避免位于阵列区的边缘的数个电容器形成矩形图案，这样可以降低位于阵列区的边缘上的数个电容器所受的应力，进而降低了位于阵列区的边缘上的数个电容器的损坏几率，提高了半导体结构的存储性能。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方 式结合。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (15)

  1. 一种半导体结构，包括基底，所述基底包括阵列区以及围绕所述阵列区的周边电路区；
    所述阵列区内设有阵列排布的多个电容器，位于所述阵列区的边缘的数个所述电容器中，任意连续相邻的三个所述电容器的中心连线构成的一个虚拟角大于90°。
  2. 根据权利要求1所述的半导体结构，其中，所述阵列排布的多个电容器包括排列成若干行和若干列的所述电容器组，位于所述阵列区的边缘的数个电容器包括位于所述若干行电容器组和所述若干列电容器组的端点处的所述电容器。
  3. 根据权利要求2所述的半导体结构，其中，位于所述若干行电容器组和所述若干列电容器组的端点处的所述电容器的中心连线形成具有倒角的矩形。
  4. 根据权利要求3所述的半导体结构，其中，在具有倒角的矩形中，位于相邻的两个直边上所述电容器的中心与位于所述两个直边之间的所述倒角上的所述电容器的中心的连线构成虚拟钝角三角形。
  5. 根据权利要求2所述的半导体结构，其中，位于相邻行的端点处的所述电容器同时位于不同列上，位于相邻列的端点处的所述电容器同时位于不同行上。
  6. 根据权利要求2所述的半导体结构，其中，相邻行之间的垂直距离与相邻列之间的垂直距离不等。
  7. 根据权利要求1所述的半导体结构，其中，所述半导体结构还包括设置在所述基底上的支撑层，所述支撑层上形成多个电容孔，每个所述电容孔内设有一个所述电容器。
  8. 根据权利要求7所述的半导体结构，其中，以平行于所述基底的截面为横截面，所述支撑层的横截面外轮廓为圆形或者环形。
  9. 根据权利要求8所述的半导体结构，其中，所述环形包括多个依次首尾连接的连接段，至少部分相邻的两个所述连接段之间采用弧形过渡；或者，所述环形包括多个依次首尾连接的直线段，至少部分相邻的两个所述直线段之间夹角为钝角。
  10. 根据权利要求9所述的半导体结构，其中，两个所述连接段之间的弧形的切线方向，与该弧形连接的所述连接段之间的夹角为钝角。
  11. 一种半导体结构的制造方法，其中，包括如下的步骤：
    提供基底，所述基底包括阵列区以及围绕所述阵列区的周边电路区；
    在所述基底上形成支撑层；
    在与所述阵列区对应的所述支撑层内形成多个电容器，多个电容器阵列排布在所述阵列区上，位于所述阵列区的边缘上的数个所述电容器中，任意连续相邻的三个所述电容器的中心连线构成的一个虚拟角大于90°。
  12. 根据权利要求11所述的半导体结构的制造方法，其中，在与所述阵列区对应的所述支撑层内形成多个电容器的步骤中包括：
    在与所述阵列区对应的所述支撑层上形成第一光刻胶层，所述第一光刻胶层包括第一掩膜图案，所述第一掩膜图案包括交替设置的多个第一遮挡区和多个第一开口区；
    在与所述周边电路区对应的所述支撑层上形成第二光刻胶层，所述第二光刻胶层包括第二掩膜图案，所述第二掩膜图案包括第二遮挡区和第二开口区，所述第二遮挡区用于覆盖部分所述第一遮挡区和部分所述第一开口区，且所述第二遮挡区的两个相邻接的边缘之间采用弧形过渡；
    去除与所述第一开口区对应的所述支撑层，在与所述阵列区对应的所述支撑层内形成多个电容孔；
    在所述电容孔内形成第一电极层。
  13. 根据权利要求12所述的半导体结构的制造方法，其中，在所述基底上形成支撑层的步骤中包括：在所述基底上依次层叠第一支撑层、第一牺牲层、第二支撑层、第二牺牲层以及第三支撑层，所述电容孔至少贯穿所述第一牺牲层、所述第二支撑层、所述第二牺牲层以及所述第三支撑层；
    在去除所述第一开口区对应的所述支撑层的步骤之后，在所述电容孔内形成第一电极层的步骤之前，所述制造方法还包括：去除所述第一光刻胶层和所述第二光刻胶层。
  14. 根据权利要求13所述的半导体结构的制造方法，其中，在所述电容孔内形成第一电极层的步骤之后，所述制造方法还包括：
    在所述第三支撑层上形成第三光刻胶层；
    图形化所述第三光刻胶层形成第三掩膜图案，所述第三掩膜图案包括 多个第三遮挡区和多个第三开口区，其中所述第三开口区在所述支撑层上的投影与所述电容孔之间的区域至少部分交叠；
    去除与所述周边电路区上对应的所述支撑层，以保留所述阵列区上对应的所述支撑层；
    去除与所述第三开口区对应的所述第三支撑层和部分所述第一电极层，以暴露与所述第三开口对应的所述第二牺牲层，其中，未被去除的所述第三支撑层构成顶部支撑层；
    去除所述第二牺牲层、部分所述第二支撑层和所述第一牺牲层，其中，未被去除的所述第二支撑层构成中间支撑层，未被去除的第一支撑层构成底部支撑层。
  15. 根据权利要求14所述的半导体结构的制造方法，其中，在去除与所述周边电路区对应的支撑层的步骤之后，所述制造方法还包括：
    在所述电容孔内形成覆盖所述第一电极层的介电层和第二电极层，所述第一电极层、所述介电层以及所述第二电极层形成所述电容器。
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