WO2022092035A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2022092035A1
WO2022092035A1 PCT/JP2021/039336 JP2021039336W WO2022092035A1 WO 2022092035 A1 WO2022092035 A1 WO 2022092035A1 JP 2021039336 W JP2021039336 W JP 2021039336W WO 2022092035 A1 WO2022092035 A1 WO 2022092035A1
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WIPO (PCT)
Prior art keywords
region
drain
insulating film
source
semiconductor device
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Ceased
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PCT/JP2021/039336
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English (en)
French (fr)
Japanese (ja)
Inventor
靖史 濱澤
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to US18/031,015 priority Critical patent/US20230378345A1/en
Priority to JP2022559130A priority patent/JP7815134B2/ja
Publication of WO2022092035A1 publication Critical patent/WO2022092035A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/112—Field plates comprising multiple field plate segments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/031—Manufacture or treatment of isolation regions comprising PN junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/30—Isolation regions comprising PN junctions

Definitions

  • Patent Document 1 describes a p-board, a p-well, an n-type low-concentration diffusion layer, a source, and a drain.
  • a semiconductor device including a gate insulating film and a gate electrode is disclosed.
  • the p-well is formed on the p-board.
  • the n-type low-concentration diffusion layer is formed in the p-well.
  • the source is formed in the p-well at intervals from the n-type low concentration diffusion layer.
  • the drain is formed in the n-type low concentration diffusion layer at a distance from the source.
  • the gate insulating film covers the channel region between the source and drain.
  • the gate electrode is formed on the gate insulating film.
  • One embodiment of the present invention provides a semiconductor device capable of improving electrical characteristics.
  • a chip having a main surface, a drain region formed on the surface layer portion of the main surface, and a source region formed on the surface layer portion of the main surface at a distance from the drain region.
  • a channel inversion region formed on the source region side between the drain region and the source region on the surface layer portion of the main surface, and a region between the drain region and the channel inversion region on the surface layer portion of the main surface.
  • a gate insulating film having a drift region formed on the main surface, a first portion covering the channel inversion region on the main surface, and a second portion covering the drift region on the main surface, and the above.
  • a gate electrode having a first electrode portion that covers the first portion and a second electrode portion that is pulled out from the first electrode portion onto the second portion so as to partially expose the second portion.
  • FIG. 1 is a schematic view showing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 2 is an enlarged view showing the region II shown in FIG. 1 together with the gate electrode according to the first embodiment.
  • FIG. 3 is a cross-sectional view taken along the line III-III shown in FIG.
  • FIG. 4 is a cross-sectional view taken along the line IV-IV shown in FIG.
  • FIG. 5 is a cross-sectional view taken along the line VV shown in FIG.
  • FIG. 6 is a cross-sectional view taken along the line VI-VI shown in FIG.
  • FIG. 7A is an enlarged view showing the region II shown in FIG. 1 together with the gate electrode according to the second embodiment.
  • FIG. 7B is an enlarged view showing the region II shown in FIG.
  • FIG. 7C is an enlarged view showing the region II shown in FIG. 1 together with the gate electrode according to the fourth embodiment.
  • FIG. 7D is an enlarged view showing the region II shown in FIG. 1 together with the gate electrode according to the fifth embodiment.
  • FIG. 7E is an enlarged view showing the region II shown in FIG. 1 together with the gate electrode according to the sixth embodiment.
  • FIG. 8 is a schematic diagram showing a semiconductor device according to the second embodiment of the present invention.
  • FIG. 9 is an enlarged view showing the region IX shown in FIG. 8 together with the gate electrode according to the first embodiment.
  • FIG. 10 is a cross-sectional view taken along the line XX shown in FIG.
  • FIG. 11 is a cross-sectional view taken along the line XI-XI shown in FIG.
  • FIG. 1 is a schematic diagram showing a semiconductor device 1 according to the first embodiment of the present invention.
  • the semiconductor device 1 includes a rectangular parallelepiped semiconductor chip 2 (chip).
  • the semiconductor chip 2 is made of a silicon chip in this form (this embodiment).
  • the semiconductor chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. are doing.
  • the first main surface 3 and the second main surface 4 are formed in a rectangular shape in a plan view seen from their normal direction Z.
  • the normal direction Z is also the thickness direction of the semiconductor chip 2.
  • the first side surface 5A and the second side surface 5B extend in the first direction X along the first main surface 3 and face the second direction Y intersecting (specifically, orthogonal to) the first direction X.
  • the third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.
  • the semiconductor device 1 includes a p-type (first conductive type) first semiconductor region 6 formed on the surface layer portion of the second main surface 4 of the semiconductor chip 2.
  • the first semiconductor region 6 is formed over the entire surface layer portion of the second main surface 4, and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. That is, the first semiconductor region 6 has a part of the second main surface 4 and the first to fourth side surfaces 5A to 5D.
  • the first semiconductor region 6 may have a substantially constant p-type impurity concentration in the thickness direction.
  • the concentration of p-type impurities in the first semiconductor region 6 may be 1 ⁇ 10 14 cm -3 or more and 5 ⁇ 10 15 cm -3 or less.
  • the thickness of the first semiconductor region 6 may be 50 ⁇ m or more and 800 ⁇ m or less.
  • the thickness of the first semiconductor region 6 is adjusted by grinding the second main surface 4. In this form, the first semiconductor region 6 is formed of a p-type semiconductor substrate.
  • the semiconductor device 1 includes a p-type second semiconductor region 7 (semiconductor region) formed on the surface layer portion of the first main surface 3 of the semiconductor chip 2.
  • the second semiconductor region 7 is formed over the entire surface layer portion of the first main surface 3, and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. That is, the second semiconductor region 7 has a part of the first main surface 3 and the first to fourth side surfaces 5A to 5D.
  • the concentration of p-type impurities in the second semiconductor region 7 may be 1 ⁇ 10 14 cm -3 or more and 5 ⁇ 10 15 cm -3 or less.
  • the thickness of the second semiconductor region 7 may be 5 ⁇ m or more and 20 ⁇ m or less.
  • the second semiconductor region 7 is formed by a p-type epitaxial layer in this form.
  • the semiconductor device 1 includes a plurality of device regions 8 provided in the second semiconductor region 7.
  • the plurality of device areas 8 are areas in which various functional devices are formed.
  • the plurality of device regions 8 are partitioned into the inner portions of the first main surface 3 at intervals from the first to fourth side surfaces 5A to 5D in a plan view.
  • the number, arrangement and shape of the device regions 8 are arbitrary and are not limited to a specific number, arrangement and shape.
  • the plurality of functional devices may include at least one of a semiconductor switching device, a semiconductor rectifying device and a passive device, respectively.
  • Semiconductor switching devices include JFETs (Junction Field Effect Transistors), transistors (Metal Insulator Semiconductor Field Effect Transistors), BJTs (Bipolar Junction Transistors), and IGBTs (Insulated Gate Bipolar Junction Transistors). It may contain at least one of (bipolar transistors).
  • the semiconductor rectifying device may include at least one of a pn junction diode, a pin junction diode, a Zener diode, a Schottky barrier diode and a fast recovery diode.
  • the passive device may include at least one of a resistor, a capacitor, an inductor and a fuse.
  • the plurality of device regions 8 include at least one MISFET region 9 in this form.
  • the MISFET region 9 is a region including a planar gate structure type MISFET 10.
  • MISFET 10 a specific structure on the MISFET region 9 (MISFET 10) side will be described.
  • FIG. 2 is an enlarged view showing the region II shown in FIG. 1 together with the gate electrode 40 according to the first embodiment.
  • FIG. 3 is a cross-sectional view taken along the line III-III shown in FIG.
  • FIG. 4 is a cross-sectional view taken along the line IV-IV shown in FIG.
  • FIG. 5 is a cross-sectional view taken along the line VV shown in FIG.
  • FIG. 6 is a cross-sectional view taken along the line VI-VI shown in FIG.
  • the semiconductor device 1 includes a region separation structure 11 (a region separation structure) that electrically separates the MOSFET region 9 from other regions in the second semiconductor region 7.
  • the region separation structure 11 is formed in an annular shape surrounding a part of the first main surface 3 in a plan view, and partitions the MISFET region 9 having a predetermined shape.
  • the region separation structure 11 is formed in a square ring shape (rectangular ring shape extending in the first direction X in this form) in a plan view, and is rectangular shape (rectangular shape extending in the first direction X in this form) by the inner peripheral edge.
  • the MISFET region 9 of the above is partitioned.
  • the planar shape of the region separation structure 11 (the planar shape of the MISFET region 9) is arbitrary.
  • the region separation structure 11 includes a p-type first separation structure 12.
  • a ground potential may be applied to the first separation structure 12.
  • the first separation structure 12 is formed in an annular shape surrounding a part of the first main surface 3 in a plan view.
  • the first separation structure 12 extends from the first main surface 3 toward the first semiconductor region 6 in a wall shape so as to cross the second semiconductor region 7, and is electrically connected to the first semiconductor region 6.
  • the first separation structure 12 includes a p-type first buried region 13 and a p-type first separation region 14.
  • the first buried region 13 is formed at a boundary portion between the first semiconductor region 6 and the second semiconductor region 7.
  • the first buried region 13 is formed at a distance from the first main surface 3 and the second main surface 4 in the normal direction Z, and is electrically connected to the first semiconductor region 6 and the second semiconductor region 7. ..
  • the first buried region 13 has a p-type impurity concentration that exceeds the p-type impurity concentration of the first semiconductor region 6.
  • the concentration of p-type impurities in the first buried region 13 may be 5 ⁇ 10 16 cm -3 or more and 5 ⁇ 10 18 cm -3 or less.
  • the first separation region 14 is formed in a region between the first main surface 3 and the first buried region 13 in the second semiconductor region 7, and is electrically connected to the first buried region 13. In this embodiment, one first separation region 14 is formed, but the number of layers of the first separation region 14 is arbitrary as long as it is electrically connected to the first buried region 13.
  • a plurality of first separation regions 14 may be stacked from the first buried region 13 side to the first main surface 3 side.
  • the concentration of p-type impurities in the first separation region 14 may be 1 ⁇ 10 17 cm -3 or more and 1 ⁇ 10 19 cm -3 or less.
  • the first separation region 14 may have a p-type impurity concentration equal to or lower than the p-type impurity concentration of the first buried region 13.
  • the region separation structure 11 includes an n-type (second conductive type) second separation structure 15.
  • a power supply potential may be applied to the second separation structure 15.
  • the second separation structure 15 is formed at a distance inward from the inner peripheral edge of the first separation structure 12 in a plan view, and partitions the MOSFET region 9 in the region surrounded by the first separation structure 12.
  • the second separation structure 15 is formed in a tubular shape that surrounds a part of the second semiconductor region 7 from the bottom side of the second semiconductor region 7 toward the first main surface 3 side.
  • a part of the second semiconductor region 7 is electrically fixed in a floating state, and at the same time, a part of the second semiconductor region 7 is partitioned as a MISFET region 9.
  • the second separation structure 15 includes an n-type second buried region 16 and an n-type second separation region 17.
  • the second buried region 16 is formed at the boundary between the first semiconductor region 6 and the second semiconductor region 7 in the region surrounded by the first separation structure 12.
  • the concentration of n-type impurities in the second buried region 16 may be 5 ⁇ 10 17 cm -3 or more and 1 ⁇ 10 19 cm -3 or less.
  • the second buried region 16 is formed at a distance inward from the inner peripheral edge of the first separated structure 12, and a part of the first semiconductor region 6 is exposed from the inner peripheral edge of the first separated structure 12.
  • the second buried region 16 is formed at a distance from the first main surface 3 and the second main surface 4 in the normal direction Z, and is electrically connected to the first semiconductor region 6 and the second semiconductor region 7. ..
  • the second buried region 16 is formed in a rectangular shape (specifically, a rectangular shape extending in the first direction X) along the inner peripheral edge of the first separation structure 12 in a plan view.
  • the second separation region 17 is formed in a region between the peripheral portions of the first main surface 3 and the second buried region 16 in the second semiconductor region 7, and is electrically connected to the second buried region 16. In this embodiment, one second separation region 17 is formed, but the number of layers of the second separation region 17 is arbitrary as long as it is electrically connected to the second buried region 16. A plurality of second separation regions 17 may be laminated from the peripheral edge side of the second buried region 16 to the first main surface 3 side.
  • the concentration of n-type impurities in the second separation region 17 may be 1 ⁇ 10 17 cm -3 or more and 1 ⁇ 10 19 cm -3 or less.
  • the semiconductor device 1 includes a MISFET 10 formed in the MISFET region 9.
  • the MISFET 10 includes at least one MISFET cell 20 formed in the MISFET region 9.
  • the MISFET 10 includes a plurality of MISFET cells 20, the plurality of MISFET cells 20 may be formed in the MISFET region 9 at intervals in the first direction X.
  • the MISFET 10 is composed of a single MISFET cell 20 in this form.
  • the specific structure of the MISFET cell 20 will be described.
  • the MISFET cell 20 includes an n-type drainwell region 21 formed on the surface layer of the second semiconductor region 7 in the MISFET region 9.
  • the drain well region 21 is formed on one end side (third side surface 5C side) of the MISFET region 9.
  • the drainwell region 21 has an n-type impurity concentration that exceeds the p-type impurity concentration of the second semiconductor region 7.
  • the concentration of n-type impurities in the drain well region 21 may be 1 ⁇ 10 16 cm -3 or more and 2 ⁇ 10 18 cm -3 or less.
  • the drainwell region 21 is formed at a distance from the second separation structure 15 (second separation region 17) inward of the MISFET region 9 in a plan view, and is one of the second semiconductor regions 7 at the peripheral edge of the MISFET region 9. The part is exposed.
  • the drain well region 21 is formed in a rectangular shape along the inner peripheral edge (periphery of the second buried region 16) of the second separated structure 15 (second separated region 17) in a plan view.
  • the drain well region 21 is formed at a distance from the second buried region 16 to the first main surface 3 side in the normal direction Z, and faces the second buried region 16 with a part of the second semiconductor region 7 interposed therebetween. ing. That is, the drainwell region 21 has a side portion and a bottom portion electrically connected to the second semiconductor region 7.
  • the MOSFET cell 20 includes a p-type source well region 22 formed in the surface layer portion of the second semiconductor region 7 at a distance from the drain well region 21 in the MOSFET region 9.
  • the source well region 22 is formed on the other end side (fourth side surface 5D side) of the MISFET region 9 at intervals from the drain well region 21 in the first direction X.
  • the source well region 22 has an n-type impurity concentration that exceeds the p-type impurity concentration of the second semiconductor region 7.
  • the concentration of p-type impurities in the source well region 22 may be 5 ⁇ 10 16 cm -3 or more and 2 ⁇ 10 18 cm -3 or less.
  • the source well region 22 is formed at a distance from the second separation structure 15 (second separation region 17) inward of the MISFET region 9 in a plan view, and is one of the second semiconductor regions 7 at the peripheral edge of the MISFET region 9. The part is exposed.
  • the source well region 22 is formed in a rectangular shape along the inner peripheral edge (periphery of the second buried region 16) of the second separated structure 15 (second separated region 17) in a plan view.
  • the source well region 22 is formed at a distance from the second buried region 16 to the first main surface 3 side in the normal direction Z, and faces the second buried region 16 with a part of the second semiconductor region 7 interposed therebetween. ing. That is, the source well region 22 has a side portion and a bottom portion electrically connected to the second semiconductor region 7.
  • the MISFET cell 20 includes an n-type drain region 23 formed on the surface layer of the drain well region 21 in the MISFET region 9.
  • the drain region 23 has an n-type impurity concentration that exceeds the n-type impurity concentration of the drain well region 21.
  • the concentration of n-type impurities in the drain region 23 may be 1 ⁇ 10 19 cm -3 or more and 2 ⁇ 10 21 cm -3 or less.
  • the drain region 23 is formed in a plan view from the peripheral edge of the drain well region 21 at intervals inward, and is formed in a band shape extending in one direction (second direction Y).
  • the planar shape of the drain region 23 is arbitrary, and may be formed in a square shape, a hexagonal shape, or a circular shape.
  • the drain region 23 is formed at a distance from the bottom of the drain well region 21 to the first main surface 3 side in the normal direction Z, and faces the second semiconductor region 7 with a part of the drain well region 21 interposed therebetween. There is.
  • the MISFET cell 20 includes an n-type source region 24 formed on the surface layer of the source well region 22 in the MISFET region 9.
  • the source region 24 is formed on one end side (third side surface 5C side) of the source well region 22.
  • the source region 24 has an n-type impurity concentration that exceeds the n-type impurity concentration of the drain well region 21.
  • the concentration of n-type impurities in the source region 24 may be 1 ⁇ 10 19 cm -3 or more and 2 ⁇ 10 21 cm -3 or less.
  • the concentration of n-type impurities in the source region 24 is preferably substantially equal to the concentration of n-type impurities in the drain region 23.
  • the source region 24 is formed in a plan view from the peripheral edge of the source well region 22 at intervals inward, and is formed in a band shape extending in one direction (second direction Y).
  • the planar shape of the source region 24 is arbitrary, and may be formed in a square shape, a hexagonal shape, or a circular shape.
  • the source region 24 is formed at a distance from the bottom of the source well region 22 toward the first main surface 3 side in the normal direction Z, and faces the second semiconductor region 7 with a part of the source well region 22 interposed therebetween. There is.
  • the MISFET cell 20 includes a p-type contact region 25 formed on the surface layer of the source well region 22 in the MISFET region 9.
  • the contact region 25 is formed on the other end side (fourth side surface 5D side) of the source well region 22.
  • the contact region 25 has a p-type impurity concentration that exceeds the p-type impurity concentration of the source well region 22.
  • the concentration of p-type impurities in the contact region 25 may be 5 ⁇ 10 18 cm -3 or more and 1 ⁇ 10 20 cm -3 or less.
  • the contact region 25 is formed on the surface layer portion of the source well region 22 so as to be connected to the source region 24.
  • the contact region 25 is formed in a plan view from the peripheral edge of the source well region 22 at intervals inward, and is formed in a band shape extending in one direction (in this form, the second direction Y).
  • the planar shape of the contact region 25 is arbitrary, and may be formed in a square shape, a hexagonal shape, or a circular shape.
  • the contact region 25 is formed at a distance from the bottom of the source well region 22 toward the first main surface 3 side in the normal direction Z, and faces the second semiconductor region 7 with a part of the source well region 22 interposed therebetween. There is.
  • the MISFET cell 20 includes a channel inversion region 26 (channel region) formed in a region between the drain region 23 and the source region 24 in the surface layer portion of the first main surface 3.
  • the channel inversion region 26 is indicated by a thick dashed line.
  • the channel inversion region 26 is a region in which the conduction and interruption of the current path formed between the drain region 23 and the source region 24 are controlled.
  • the current flowing between the drain region 23 and the source region 24 is the drain source current.
  • the channel inversion region 26 is formed on the source region 24 side in the region between the drain region 23 and the source region 24. Specifically, the channel inversion region 26 is formed in the region between the drain well region 21 and the source region 24 in the surface layer portion of the first main surface 3. More specifically, the channel inversion region 26 is formed on the surface layer portion of the second semiconductor region 7 and the surface layer portion of the source well region 22 in the region between the drain well region 21 and the source region 24. In this form, the channel inversion region 26 is formed in a band shape extending in the second direction Y over the entire area of the facing region between the drain well region 21 and the source region 24 in a plan view.
  • the MISFET cell 20 includes a drain drift region 27 (drift region) formed in a region between the drain region 23 and the channel inversion region 26 in the surface layer portion of the first main surface 3.
  • the drain drift region 27 is indicated by a thin broken line.
  • the drain drift region 27 is a region that serves as a current path between the drain region 23 and the source region 24 (channel inversion region 26).
  • the current flowing between the drain region 23 and the source region 24 (channel inversion region 26) is the drain source current.
  • the drain drift region 27 is formed in the drain well region 21. Specifically, the drain drift region 27 is formed in the drain well region 21 between the drain region 23 and the channel inversion region 26. In this embodiment, the drain drift region 27 is formed in a band shape extending in the second direction Y over the entire area of the facing region between the drain region 23 and the channel inversion region 26 in a plan view. With respect to the first direction X, the length of the drain drift region 27 may be greater than or equal to the length of the channel inversion region 26 or less than the length of the channel inversion region 26. In the following description, the wording of the drain drift region 27 includes the drain well region 21.
  • the MISFET cell 20 includes a gate insulating film 30 formed on the first main surface 3 in the MISFET region 9.
  • the gate insulating film 30 contains silicon oxide in this form.
  • the gate insulating film 30 contains silicon oxide made of an oxide of the semiconductor chip 2 (second semiconductor region 7 and the like).
  • the thickness of the gate insulating film 30 may be 3 nm or more and 100 nm or less.
  • the gate insulating film 30 covers the region between the drain region 23 and the source region 24 on the first main surface 3 in the form of a film. Specifically, the gate insulating film 30 is formed on the first main surface 3 so as to straddle the source region 24 and the drain drift region 27 (drain well region 21), and the source region 24, the channel inversion region 26, and the drain drift are formed. It covers the region 27.
  • the gate insulating film 30 includes a first portion 31 and a second portion 32.
  • the first portion 31 covers a part of the second semiconductor region 7, the source well region 22, and the source region 24 on the first main surface 3. That is, the first portion 31 covers the channel inversion region 26 on the first main surface 3.
  • the first portion 31 preferably covers the entire area of the channel inversion region 26.
  • the first portion 31 is formed at a distance from the contact region 25 to the drain region 23 side in a plan view, and exposes the source region 24 and the contact region 25.
  • the first portion 31 exposes a part of the source region 24 and the entire contact region 25 in this form.
  • the first portion 31 has a first length L1 with respect to the first direction X.
  • the second portion 32 is drawn from the first portion 31 toward the drain region 23 and covers the drain well region 21 on the first main surface 3. That is, the second portion 32 covers the drain drift region 27 on the first main surface 3. Specifically, the second portion 32 is formed at a distance from the drain region 23 to the source region 24 side in a plan view, and is a part of the drain drift region 27 (specifically, the end portion on the fourth side surface 5D side). ) And the entire drain area 23 are exposed and partially cover the drain drift area 27.
  • the flat area of the second portion 32 may be equal to or greater than the flat area of the portion exposed from the second portion 32 in the drain drift region 27, or may be less than the flat area.
  • the second portion 32 has a second length L2 with respect to the first direction X.
  • the second length L2 may be the first length L1 or more, or may be less than the first length L1.
  • the MISFET cell 20 includes a field insulating film 35 formed on the first main surface 3 in the MISFET region 9.
  • the end portion (opening) of the field insulating film 35 is indicated by a thick broken line.
  • the field insulating film 35 is formed inside and outside the MISFET region 9, and covers the region outside the gate insulating film 30 inside the MISFET region 9.
  • the field insulating film 35 contains silicon oxide in this form.
  • the field insulating film 35 contains silicon oxide made of an oxide of the semiconductor chip 2 (second semiconductor region 7, etc.).
  • the field insulating film 35 may be a LOCOS film (local oxidation of silicon film).
  • the field insulating film 35 has a thickness different from that of the gate insulating film 30. Specifically, the thickness of the field insulating film 35 exceeds the thickness of the gate insulating film 30.
  • the thickness of the field insulating film 35 may be 50 nm or more and 500 nm or less.
  • the field insulating film 35 covers the second semiconductor region 7, the drain well region 21, and the source well region 22 in the MISFET region 9 so as to expose the drain region 23, the source region 24, and the contact region 25.
  • the field insulating film 35 surrounds the gate insulating film 30 in a plan view and is connected to the first portion 31 and the second portion 32 of the gate insulating film 30.
  • the field insulating film 35 covers the drain drift region 27 in the region between the drain region 23 and the second portion 32 of the gate insulating film 30, and is continuous with the second portion 32.
  • the field insulating film 35 may be formed of a part (that is, a thick film portion) of the gate insulating film 30. Further, the field insulating film 35 may be made of a part of another gate insulating film thicker than the gate insulating film 30.
  • the MISFET cell 20 may include an STI (Sallow Trench Isolation) structure instead of the field insulating film 35.
  • the STI structure includes a trench formed in the first main surface 3 and an insulator embedded in the trench.
  • the insulator may contain at least one of silicon oxide and silicon nitride.
  • the MISFET cell 20 includes a gate electrode 40 formed on the gate insulating film 30.
  • the gate electrode 40 is shown by hatching.
  • the gate electrode 40 forms a planar gate structure together with the gate insulating film 30.
  • the gate electrode 40 in this form, comprises conductive polysilicon.
  • the conductive polysilicon includes at least one of n-type polysilicon and p-type polysilicon.
  • the gate electrode 40 covers the region between the drain region 23 and the source region 24 in a film shape on the gate insulating film 30. Specifically, the gate electrode 40 is formed on the gate insulating film 30 so as to straddle the source region 24 and the drain drift region 27 (drain well region 21), and sandwiches the gate insulating film 30 into the drain drift region 27 and the channel. It covers the inversion region 26 and the source region 24.
  • the gate electrode 40 has a planar shape different from the planar shape of the gate insulating film 30.
  • the gate electrode 40 includes a first electrode portion 41 and a second electrode portion 42 formed in different regions on the gate insulating film 30 in different planar shapes.
  • the first electrode portion 41 is formed on the first portion 31 of the gate insulating film 30, and is one of the second semiconductor region 7, the source well region 22, and the source region 24 with the first portion 31 of the gate insulating film 30 interposed therebetween. It faces the part. That is, the first electrode portion 41 faces the channel inversion region 26 with the first portion 31 interposed therebetween.
  • the first electrode portion 41 faces the entire area of the channel inversion region 26 with the first portion 31 interposed therebetween.
  • the gate electrode 40 (first electrode portion 41) is drawn out to a region (above the field insulating film 35) outside the channel inversion region 26 across the peripheral edge of the channel inversion region 26 in the second direction Y in a plan view. Is preferable.
  • a portion of the gate electrode 40 that is drawn out in the second direction Y so as to reach a region outside the channel inversion region 26 may be formed as a connecting portion of the gate contact electrode (not shown).
  • the first electrode portion 41 is formed at a distance from the contact region 25 to the source region 24 side in a plan view, and exposes the source region 24 and the contact region 25.
  • the second electrode portion 42 is formed on the second portion 32 of the gate insulating film 30. Specifically, the second electrode portion 42 is pulled out from the first electrode portion 41 onto the second portion 32 so as to partially expose the second portion 32, and the drain drift region sandwiches the second portion 32. It faces a part of 27. The second electrode portion 42 is further pulled out from above the second portion 32 onto the field insulating film 35 so as to partially expose the field insulating film 35, and sandwiches the field insulating film 35 into the drain drift region 27. They are facing each other.
  • the second electrode portion 42 forms a gate drain capacitance Cgd with the drain drift region 27.
  • the gate drain capacitance Cgd is also referred to as a feedback capacitance Crss (feedback capacitance Crss).
  • the gate-drain capacity Cgd includes a first gate-drain capacity Cgd1 and a second gate-drain capacity Cgd2 connected in parallel to the first gate-drain capacity Cgd1.
  • the first gate drain capacitance Cgd1 is formed in a portion of the second electrode portion 42 facing the drain drift region 27 with the gate insulating film 30 interposed therebetween.
  • the second gate drain capacitance Cgd2 is formed in a portion of the second electrode portion 42 facing the drain drift region 27 with the field insulating film 35 interposed therebetween.
  • the gate-drain capacity Cgd includes a combined capacity of the first gate-drain capacity Cgd1 and the second gate-drain capacity Cgd2.
  • the second gate drain capacity Cgd2 may be equal to or less than the first gate drain capacity Cgd1 or may exceed the first gate drain capacity Cgd1.
  • the second electrode portion 42 has at least one (plural) drawer portions 43 drawn from the first electrode portion 41 onto the second portion 32 so as to partially expose the second portion 32. are doing.
  • the number of drawing portions 43 is appropriately adjusted according to the length of the gate electrode 40 (gate insulating film 30) in the second direction Y.
  • the plurality of drawer portions 43 are respectively drawn out from the first electrode portion 41 onto the second portion 32 in a strip shape toward the drain region 23 side in a plan view, and are arranged at intervals in the second direction Y. That is, the second electrode portion 42 (plurality of drawer portions 43) is drawn out from the first electrode portion 41 toward the drain region 23 side in a comb-teeth shape in a plan view. Further, the second electrode portion 42 (plurality of drawer portions 43) covers a plurality of portions of the second portion 32 at intervals in a row in the second direction Y in a plan view. The plurality of drawers 43 are preferably arranged at equal intervals in the second direction Y.
  • the plurality of drawer portions 43 each cover the second portion 32 with a space from the first portion 31 (channel inversion region 26) to the drain region 23 side in a plan view. That is, the plurality of extraction portions 43 cover only the second portion 32 with respect to the gate insulating film 30, and do not cover the first portion 31.
  • the plurality of drawer portions 43 each cover the second portion 32 at intervals from the drain region 23 to the first portion 31 (channel inversion region 26) side in a plan view.
  • the plurality of drawers 43 face the drain region 23 on one side of the first direction X and face the source region 24 (channel inversion region 26) on the other side of the first direction X in a plan view.
  • the plurality of drawers 43 include, in this embodiment, two outer drawers 43A arranged at both ends of the second direction Y, and a plurality of inner drawers 43B sandwiched between the two outer drawers 43A.
  • the outer lead-out portion 43A may be drawn out to a region (above the field insulating film 35) outside the drain drift region 27 across the peripheral edge of the drain drift region 27 in the second direction Y in a plan view.
  • the portion of the gate electrode 40 (outer lead-out portion 43A) drawn out to the region outside the channel inversion region 26 may be formed as a connection portion of the gate contact electrode (not shown).
  • the outer lead-out portion 43A may be formed only in the region surrounded by the peripheral edge of the drain well region 21 in a plan view.
  • the plurality of inner drawer portions 43B are formed only in the region surrounded by the peripheral edge of the drain well region 21 in a plan view. It is preferable that all of the plurality of inner drawer portions 43B face the drain region 23 on one side of the first direction X in a plan view. It is preferable that all of the plurality of inner drawer portions 43B face the source region 24 (channel inversion region 26) on the other side of the first direction X in a plan view.
  • the plurality of drawing portions 43 are further drawn out in a band shape from above the second portion 32 of the gate insulating film 30 toward the drain region 23 side on the field insulating film 35. That is, the plurality of drawer portions 43 continuously cover the second portion 32 and a part of the field insulating film 35, respectively.
  • the plurality of drawers 43 are formed on the field insulating film 35 at intervals in the second direction Y. That is, the second electrode portions 42 (plurality of drawer portions 43) cover a plurality of portions of the field insulating film 35 at intervals in a row in the second direction Y in a plan view.
  • the plurality of drawer portions 43 each have a constant first width W1 in the second direction Y.
  • the first width W1 may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the plurality of drawers 43 may have different first widths W1 from each other.
  • the plurality of drawing portions 43 face the drain drift region 27 with the gate insulating film 30 (second portion 32) interposed therebetween, and face the drain drift region 27 with the field insulating film 35 interposed therebetween. That is, the plurality of extraction portions 43 form the first gate drain capacity Cgd1 in the portion covering the gate insulating film 30 (second portion 32), and the second gate drain capacity Cgd2 in the portion covering the field insulating film 35. Is forming.
  • the second electrode portion 42 has at least one (plural) exposed portions 44 partitioned by at least one (plural in this form) drawer portion 43.
  • the exposed portion 44 is a portion where the second electrode portion 42 (gate electrode 40) is partially removed so as to partially expose the second portion 32, and may be referred to as a removing portion.
  • the number of exposed portions 44 is appropriately adjusted according to the number of drawer portions 43 and the length of the gate electrode 40 (gate insulating film 30) in the second direction Y.
  • the plurality of exposed portions 44 are partitioned between two adjacent drawer portions 43, respectively.
  • the plurality of exposed portions 44 are each partitioned by at least one (plural) sides extending in the opposite direction (first direction X) of the drain region 23 and the source region 24 on the second portion 32.
  • the plurality of exposed portions 44 are each partitioned by at least two sides extending in a direction intersecting each other in the second electrode portion 42.
  • the plurality of exposed portions 44 are partitioned by a side extending in the second direction Y and a side extending in the first direction X, respectively.
  • the side extending in the first direction X is formed by a plurality of drawer portions 43, respectively.
  • the side extending in the second direction Y is formed by the base end portions of the plurality of drawer portions 43, respectively. That is, the plurality of exposed portions 44 are each partitioned by a plurality of sides of the plurality of drawer portions 43.
  • the "side" here does not necessarily have to extend linearly in a plan view and may be curved.
  • the plurality of exposed portions 44 extend from the second portion 32 toward the drain region 23 side in a strip shape in a plan view, and are arranged at intervals in the second direction Y. That is, in this form, the plurality of exposed portions 44 are each composed of an open region (notch portion) of the second electrode portion 42, and are partitioned in a stripe shape extending in the first direction X as a whole in a plan view. It is preferable that the plurality of exposed portions 44 are arranged at equal intervals in the second direction Y.
  • the plurality of exposed portions 44 are located on the line when a line connecting the plurality of drawer portions 43 in the second direction Y is set. That is, the plurality of exposed portions 44 are arranged alternately with the plurality of drawer portions 43 at intervals in the second direction Y so as to sandwich one drawer portion 43.
  • the second electrode portion 42 (plurality of exposed portions 44) exposes a plurality of portions of the second portion 32 in a second direction Y at intervals in a row in a plan view.
  • the plurality of exposed portions 44 expose the second portion 32 at intervals from the first portion 31 to the drain region 23 side in a plan view. That is, the plurality of exposed portions 44 expose only the second portion 32 with respect to the gate insulating film 30, and do not expose the first portion 31.
  • the plurality of exposed portions 44 expose the second portion 32 at intervals from the drain region 23 to the second portion 32 side in a plan view. It is preferable that the plurality of exposed portions 44 are formed only in the region surrounded by the peripheral edge of the drain well region 21 in a plan view.
  • the plurality of exposed portions 44 face the drain region 23 on one side of the first direction X and face the source region 24 (channel inversion region 26) on the other side of the first direction X in a plan view. It is preferable that all of the plurality of exposed portions 44 face the drain region 23 on one side of the first direction X in a plan view. It is preferable that all of the plurality of exposed portions 44 face the source region 24 (channel inversion region 26) on the other side of the first direction X in a plan view.
  • the plurality of exposed portions 44 further partially expose a part of the field insulating film 35 in the region between the plurality of drawer portions 43. That is, the plurality of exposed portions 44 continuously expose the second portion 32 of the gate insulating film 30 and a part of the field insulating film 35, respectively.
  • the plurality of exposed portions 44 are each partitioned by at least one (plural) sides extending in the facing direction (first direction X) of the drain region 23 and the source region 24 on the field insulating film 35. ing.
  • the facing direction (first direction X) is also a direction in which the drain source current flows.
  • the sides extending in the opposite direction are each formed by a plurality of drawer portions 43.
  • the "side" here does not necessarily have to extend linearly in a plan view and may be curved.
  • the plurality of exposed portions 44 are each formed in a band shape continuously extending in the first direction X from the second portion 32 toward the field insulating film 35, and are formed at intervals in the second direction Y.
  • the plurality of exposed portions 44 are located on the field insulating film 35 when a line connecting the plurality of extraction portions 43 in the second direction Y is set. That is, the plurality of exposed portions 44 are alternately formed with the plurality of drawer portions 43 so as to sandwich one drawer portion 43 in the second direction Y even on the field insulating film 35.
  • the second electrode portion 42 (plurality of exposed portions 44) exposes a plurality of portions of the field insulating film 35 in a row at intervals in the second direction Y in a plan view.
  • the plurality of exposed portions 44 each have a constant second width W2 in the second direction Y.
  • the second width W2 may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the plurality of exposed portions 44 may have a second width W2 different from each other.
  • the second width W2 may be the first width W1 or more (W1 ⁇ W2) or less than the first width W1 (W1> W2).
  • the plurality of exposed portions 44 partially expose the gate insulating film 30 (second portion 32) and partially expose the field insulating film 35. Specifically, the plurality of exposed portions 44 partially expose the gate insulating film 30 (second portion 32) and the field insulating film 35 at a portion adjacent to the drawing portion 43 from the second direction Y. The plurality of exposed portions 44 reduce the first gate drain capacity Cgd1 in the portion where the gate insulating film 30 (second portion 32) is exposed, and lower the second gate drain capacity Cgd2 in the portion where the field insulating film 35 is exposed. ing.
  • the flat area (total flat area) of the plurality of exposed portions 44 may be equal to or larger than the flat area (total flat area) of the plurality of drawer portions 43, or less than the flat area (total flat area) of the plurality of drawer portions 43. It may be.
  • the flat area (total flat area) of the portion located in the field insulating film 35 in the plurality of exposed portions 44 is equal to or larger than the flat area (total flat area) of the portion located in the gate insulating film 30 in the plurality of exposed portions 44. Alternatively, it may be less than the flat area (total flat area) of the portion of the plurality of exposed portions 44 located on the gate insulating film 30.
  • the extraction portion 43 shields the electric field generated on the semiconductor chip 2 side, while the exposed portion 44 allows the electric field generated on the semiconductor chip 2 side to pass through. As a result, the electric field applied to the gate electrode 40 is thinned out, and the electric field applied to the gate electrode 40 is relaxed.
  • the first width W1 of the drawing portion 43 (the second width W2 of the exposed portion 44) is increased or decreased, the shielding effect of the electric field on the gate electrode 40 changes. As an example, assuming the same number of drawers 43 (for example, a single drawer 43), if the first width W1 of the drawers 43 is narrowed, the second width W2 of the exposed portions 44 expands.
  • the first gate drain capacity Cgd1 and the second gate drain capacity Cgd2 decrease. If the first width W1 is narrowed too much, the electric field passing through the exposed portion 44 increases, and as a result, the electric field may be concentrated on the gate electrode 40 in the vicinity of the channel inversion region 26.
  • the first width W1 of the plurality of drawer portions 43 is set to at least 0.5 ⁇ m (that is, 0.5 ⁇ m or more).
  • the second width W2 of the plurality of exposed portions 44 is set to 1 ⁇ m (that is, 1 ⁇ m or less) at the maximum.
  • the number of drawing portions 43, the planar shape, the first width W1, and the like are appropriately adjusted according to the electric field generated on the semiconductor chip 2 side. Further, the number of exposed portions 44, the planar shape, the second width W2, and the like are appropriately adjusted according to the electric field generated on the semiconductor chip 2 side.
  • the gate electrode 40 according to the second to fifth embodiments will be described with reference to FIGS. 7A to 7E.
  • FIG. 7A is an enlarged view showing the region II shown in FIG. 1 together with the gate electrode 40 according to the second embodiment.
  • the structures shown in FIGS. 1 to 6 are designated by the same reference numerals, and the description thereof will be omitted.
  • the second portion 32 of the gate electrode 40 according to the second embodiment includes an extension 45 extending in the second direction Y on the field insulating film 35.
  • the extension portion 45 is connected to a plurality of drawer portions 43.
  • the second portion 32 includes a plurality of exposed portions 44 partitioned by a plurality of drawer portions 43 and an extension portion 45 in a plan view.
  • the plurality of exposed portions 44 are each composed of a closed region (opening) of the second electrode portion 42.
  • FIG. 7B is an enlarged view showing the region II shown in FIG. 1 together with the gate electrode 40 according to the third embodiment.
  • the structures shown in FIGS. 1 to 6 are designated by the same reference numerals, and the description thereof will be omitted.
  • the second portion 32 of the gate electrode 40 includes two drawers 43 and one extension 45.
  • the two drawers 43 may be the inner drawer 43B.
  • the two drawing portions 43 are drawn out from both ends of the first portion 31 of the gate electrode 40 in the second direction Y toward the drain region 23 side.
  • One extension portion 45 is formed in a band shape extending in the second direction Y, and is connected to two drawer portions 43.
  • the second portion 32 includes a single exposed portion 44 partitioned by two drawers 43 and one extension 45 in plan view.
  • the single exposed portion 44 is formed from a closed region (opening) of the second electrode portion 42 and is formed in a band shape extending in the second direction Y.
  • the gate electrode 40 according to the third embodiment it can be considered that the annular (square annular in this embodiment) second electrode portion 42 is pulled out from the first electrode portion 41 in a plan view.
  • FIG. 7C is an enlarged view showing the region II shown in FIG. 1 together with the gate electrode 40 according to the fourth embodiment.
  • the structures shown in FIGS. 1 to 6 are designated by the same reference numerals, and the description thereof will be omitted.
  • the second portion 32 of the gate electrode 40 includes two drawers 43 and a plurality of extension 45s.
  • the outer drawer 43A is formed as the two drawers 43 is shown, but the two drawers 43 may be the inner drawer 43B.
  • the two drawing portions 43 are drawn out from both ends of the first portion 31 of the gate electrode 40 in the second direction Y toward the drain region 23 side.
  • the plurality of extension portions 45 are each formed in a band shape extending in the second direction Y at intervals in the first direction X, and are connected to the two drawer portions 43, respectively.
  • the second portion 32 includes a plurality of exposed portions 44 partitioned by two drawer portions 43 and a plurality of extension portions 45 in a plan view.
  • the plurality of exposed portions 44 each consist of a closed region (opening) of the second electrode portion 42, and are formed in a band shape extending in the second direction Y at intervals in the first direction X. That is, the plurality of exposed portions 44 are formed in a striped shape extending in the second direction Y in a plan view. At least one of the plurality of exposed portions 44 exposes at least the field insulating film 35.
  • the gate electrode 40 according to the fourth embodiment, it can be considered that the ladder-shaped second electrode portion 42 is pulled out from the first electrode portion 41 in a plan view.
  • FIG. 7D is an enlarged view showing the region II shown in FIG. 1 together with the gate electrode 40 according to the fifth embodiment.
  • the structures shown in FIGS. 1 to 6 are designated by the same reference numerals, and the description thereof will be omitted.
  • the second portion 32 of the gate electrode 40 includes a plurality of drawer portions 43 and a plurality of extension portions 45.
  • the plurality of drawer portions 43 are drawn out from the first portion 31 of the gate electrode 40 toward the drain region 23 side, as in the case of the first embodiment.
  • the plurality of extension portions 45 are each formed in a band shape extending in the second direction Y at intervals in the first direction X, and are connected to the plurality of drawer portions 43, respectively.
  • the second portion 32 includes a plurality of exposed portions 44 partitioned by a plurality of drawer portions 43 and a plurality of extension portions 45 in a plan view.
  • the plurality of exposed portions 44 are each composed of a closed region (opening) of the second electrode portion 42, and are arranged in a matrix at intervals in the first direction X and the second direction Y. At least one of the plurality of exposed portions 44 exposes at least the field insulating film 35.
  • the gate electrode 40 according to the fifth embodiment, it can be considered that the lattice-shaped second electrode portion 42 having a plurality of crossroads is pulled out from the first electrode portion 41 in a plan view.
  • FIG. 7E is an enlarged view showing the region II shown in FIG. 1 together with the gate electrode 40 according to the sixth embodiment.
  • the structures shown in FIGS. 1 to 6 are designated by the same reference numerals, and the description thereof will be omitted.
  • the second portion 32 of the gate electrode 40 includes a plurality of drawer portions 43 and a plurality of extension portions 45.
  • the plurality of drawer portions 43 are each drawn out in a strip shape from the first portion 31 of the gate electrode 40 toward the drain region 23 side in a plan view.
  • the plurality of drawer portions 43 are formed in a zigzag shape while being bent toward one side and the other side of the second direction Y in a plan view.
  • the plurality of extension portions 45 are each formed in a band shape extending in the second direction Y at intervals in the first direction X, and are connected to the plurality of drawer portions 43, respectively.
  • the second portion 32 includes a plurality of exposed portions 44 partitioned by a plurality of drawer portions 43 and a plurality of extension portions 45 in a plan view.
  • the plurality of exposed portions 44 are each composed of a closed region (opening) of the second electrode portion 42, and are arranged in a staggered manner at intervals in the first direction X and the second direction Y. At least one of the plurality of exposed portions 44 exposes at least the field insulating film 35.
  • the gate electrode 40 according to the sixth embodiment has a form in which a plurality of exposed portions 44 are arranged in a staggered manner at intervals in the first direction X and the second direction Y in the gate electrode 40 according to the fifth embodiment. It can be regarded as doing. Further, in the gate electrode 40 according to the sixth embodiment, it can be considered that the lattice-shaped second electrode portion 42 having a plurality of T-junctions is pulled out from the first electrode portion 41 in a plan view.
  • the semiconductor device 1 may have a gate electrode 40 that simultaneously includes at least two of the features of the gate electrode 40 according to the first to sixth embodiments.
  • the semiconductor device 1 includes a semiconductor chip 2, an n-type drain region 23, an n-type source region 24, a channel inversion region 26, a drain drift region 27, a gate insulating film 30, and a gate electrode 40.
  • the semiconductor chip 2 has a first main surface 3.
  • the drain region 23 is formed on the surface layer portion of the first main surface 3.
  • the source region 24 is formed on the surface layer portion of the first main surface 3 at a distance from the drain region 23.
  • the channel inversion region 26 is formed on the source region 24 side between the drain region 23 and the source region 24 in the surface layer portion of the first main surface 3.
  • the drain drift region 27 is formed in the region between the drain region 23 and the channel inversion region 26 in the surface layer portion of the first main surface 3.
  • the gate insulating film 30 includes a first portion 31 and a second portion 32.
  • the first portion 31 covers the channel inversion region 26 on the first main surface 3.
  • the second portion 32 covers the drain drift region 27 on the first main surface 3.
  • the gate electrode 40 includes a first electrode portion 41 and a second electrode portion 42.
  • the first electrode portion 41 covers the first portion 31 of the gate insulating film 30.
  • the second electrode portion 42 is pulled out from the first electrode portion 41 onto the second portion 32 so as to partially expose the second portion 32.
  • the second electrode portion 42 forms a gate-drain capacitance Cgd with the drain drift region 27 in the portion covering the second portion 32. Since the second electrode portion 42 partially exposes the second portion 32, the area facing the drain drift region 27 of the second electrode portion 42 can be reduced. Thereby, the gate drain capacity Cgd can be reduced. As a result, the switching delay of the MISFET 10 can be suppressed, so that the switching loss can be suppressed. Therefore, it is possible to provide the semiconductor device 1 capable of improving the electrical characteristics.
  • the second electrode portion 42 extends in the opposite direction (first direction X) of the drain region 23 and the source region 24, and has a side that partially exposes the second portion 32. It is preferable that the second electrode portion 42 extends in a direction intersecting each other in a plan view and has at least two sides that partially expose the second portion 32.
  • the second electrode portion 42 has a side extending in one direction (first direction X) and a side extending in an intersecting direction (second direction Y) intersecting in one direction on the second portion 32 in a plan view. Is preferable.
  • the first electrode portion 41 covers the entire area of the first portion 31 in a plan view.
  • the channel inversion region 26 can be appropriately controlled.
  • the second electrode portion 42 exposes the second portion 32 at a distance from the first portion 31 in a plan view.
  • the channel inversion region 26 can be appropriately controlled.
  • the second electrode portion 42 exposes the second portion 32 only in the region surrounded by the peripheral edge of the drain well region 21 in a plan view.
  • the gate drain capacity Cgd can be appropriately reduced. It is particularly preferable that the second electrode portion 42 exposes only the second portion 32 in the gate insulating film 30.
  • the first portion 31 covers the entire area of the channel inversion region 26 in a plan view
  • the second portion 32 does not cover the entire area of the drain drift region 27 in a plan view. That is, it is preferable that the second portion 32 partially exposes the drain drift region 27 and partially covers the drain drift region 27.
  • the channel inversion region 26 can be appropriately controlled, and the gate drain capacitance Cgd can be appropriately reduced.
  • the second electrode portion 42 exposes a plurality of portions of the second portion 32.
  • the electric field applied to the gate electrode 40 can be thinned out by the plurality of points of the second portion 32.
  • the electric field concentration on the gate electrode 40 can be relaxed and the withstand voltage (for example, breakdown voltage) can be improved.
  • the second electrode portions 42 are regularly arranged in a plan view as shown in FIGS. 2 and 7A to 7E.
  • the second electrode portion 42 may expose a plurality of portions of the second portion 32 in one or both of the first direction X and the second direction Y at intervals in a row.
  • the semiconductor device 1 preferably includes a field insulating film 35.
  • the field insulating film 35 preferably has a thickness different from that of the gate insulating film 30. In this case, it is particularly preferable that the field insulating film 35 has a thickness exceeding the thickness of the gate insulating film 30. According to this structure, the pressure resistance improving effect of the field insulating film 35 can be obtained. It is preferable that the field insulating film 35 covers the drain drift region 27 on the first main surface 3 so as to be continuous with at least the second portion 32. It is particularly preferable that the field insulating film 35 is continuous with the first portion 31 and the second portion 32.
  • the second electrode portion 42 is pulled out from above the second portion 32 onto the field insulating film 35 and faces the drain drift region 27 with the field insulating film 35 interposed therebetween. According to this structure, the gate drain capacity Cgd can be reduced in the structure having the field insulating film 35. In this case, it is preferable that the field insulating film 35 is partially exposed in the second electrode portion 42.
  • the second electrode portion 42 forms a gate drain capacitance Cgd with the drain drift region 27 in the portion covering the field insulating film 35. According to this structure, since the second electrode portion 42 partially exposes the field insulating film 35, the facing area of the second electrode portion 42 with respect to the drain drift region 27 can be reduced. As a result, the gate drain capacity Cgd can be reduced even in the portion of the second electrode portion 42 that covers the field insulating film 35.
  • the second electrode portion 42 Even if the second electrode portion 42 is pulled out from above the second portion 32 onto the field insulating film 35 so as to continuously expose the field insulating film 35 from the portion that partially exposes the second portion 32. good. It is preferable that the second electrode portion 42 extends in at least the opposite direction (first direction X) of the drain region 23 and the source region 24 in a plan view, and has a side that partially exposes the field insulating film 35.
  • the second electrode portion 42 exposes a plurality of portions of the field insulating film 35.
  • the electric field applied to the gate electrode 40 can be thinned out by a plurality of locations of the field insulating film 35.
  • the electric field concentration on the gate electrode 40 can be relaxed and the withstand voltage (for example, breakdown voltage) can be improved.
  • the second electrode portions 42 are regularly arranged on the field insulating film 35 in a plan view as shown in FIGS. 2 and 7A to 7E.
  • the second electrode portion 42 may expose a plurality of portions of the field insulating film 35 in one or both of the first direction X and the second direction Y at intervals in a row.
  • the semiconductor device 1 includes a p-type second semiconductor region 7 and an n-type drain well region 21.
  • the second semiconductor region 7 is formed on the surface layer portion of the first main surface 3.
  • the drain well region 21 is formed on the surface layer portion of the second semiconductor region 7.
  • the drain region 23 is formed on the surface layer portion of the drain well region 21.
  • the source region 24 is formed on the surface layer portion of the second semiconductor region 7 at a distance from the drain well region 21.
  • the channel inversion region 26 is formed in the region between the drain well region 21 and the source region 24.
  • the drain drift region 27 is formed in the drain well region 21.
  • the semiconductor device 1 may include a source well region 22 formed on the surface layer portion of the second semiconductor region 7 at a distance from the drain well region 21.
  • the source region 24 may be formed on the surface layer portion of the source well region 22.
  • the semiconductor device 1 may include a contact region 25 formed on the surface layer portion of the source well region 22.
  • FIG. 8 is a schematic diagram showing a semiconductor device 51 according to the second embodiment of the present invention.
  • FIG. 9 is an enlarged view showing the region IX shown in FIG. 8 together with the gate electrode 40 according to the first embodiment.
  • FIG. 10 is a cross-sectional view taken along the line XX shown in FIG.
  • FIG. 11 is a cross-sectional view taken along the line XI-XI shown in FIG.
  • the same reference numerals will be given to the structures corresponding to the structures described for the semiconductor device 1, and the description thereof will be omitted.
  • the semiconductor device 51 includes a semiconductor chip 2, a first semiconductor region 6, a second semiconductor region 7, a plurality of device regions 8 and the same as the semiconductor device 1 according to the first embodiment.
  • the region separation structure 11 is included.
  • the conductive type of the second semiconductor region 7 is changed from a p-type (first conductive type) to an n-type (second conductive type).
  • the concentration of n-type impurities in the second semiconductor region 7 may be 5 ⁇ 10 14 cm -3 or more and 5 ⁇ 10 15 cm -3 or less.
  • the thickness of the second semiconductor region 7 may be 3 ⁇ m or more and 15 ⁇ m or less.
  • the second semiconductor region 7 is formed by an n-type epitaxial layer in this form.
  • the region separation structure 11 includes a p-type first separation structure 12 and an n-type second separation structure 15.
  • the second separation structure 15 includes an n-type second buried region 16 and does not include an n-type second separation region 17.
  • the semiconductor device 51 includes at least one MISFET cell 20 formed in the MISFET region 9 as in the semiconductor device 1 according to the first embodiment.
  • the MISFET cell 20 includes a drain well region 21, a source well region 22, a drain region 23, a source region 24, a contact region 25, a channel inversion region 26, and a drain drift region 27.
  • the drain well region 21, the source well region 22, the drain region 23, the source region 24, and the contact region 25 are each formed in the same manner as the semiconductor device 1 according to the first embodiment.
  • the MISFET cell 20 includes a channel inversion region 26 formed in a region between the drain region 23 and the source region 24 in the surface layer portion of the first main surface 3.
  • the channel inversion region 26 is indicated by a thick dashed line.
  • the channel inversion region 26 is a region in which the conduction and interruption of the current path formed between the drain region 23 and the source region 24 are controlled.
  • the current flowing between the drain region 23 and the source region 24 is the drain source current.
  • the channel inversion region 26 is formed on the source region 24 side in the region between the drain region 23 and the source region 24.
  • the channel inversion region 26 is formed between the second semiconductor region 7 and the source region 24 in the surface layer portion of the source well region 22.
  • the channel inversion region 26 is formed in a strip shape extending in the second direction Y over the entire area between the peripheral edge of the source well region 22 and the source region 24 in a plan view.
  • the MISFET cell 20 includes a drain drift region 27 formed in a region between the drain region 23 and the channel inversion region 26 in the surface layer portion of the first main surface 3.
  • the drain drift region 27 is indicated by a thin dashed line.
  • the drain drift region 27 is a region that serves as a current path between the drain region 23 and the source region 24.
  • the current flowing between the drain region 23 and the source region 24 is the drain source current.
  • the drain drift region 27 is formed in the region between the source well region 22 and the drain region 23. That is, the drain drift region 27 is formed in the second semiconductor region 7 and the drain well region 21 located in the region between the source well region 22 and the drain region 23 in this form.
  • the drain drift region 27 is formed in a band shape extending in the second direction Y over the entire area of the facing region between the drain region 23 and the source well region 22 in a plan view.
  • the MISFET cell 20 includes a gate insulating film 30, a field insulating film 35, and a gate electrode 40 formed on the first main surface 3 in the MISFET region 9, similarly to the semiconductor device 1 according to the first embodiment.
  • the end of the field insulating film 35 is indicated by a thick broken line, and the gate electrode 40 is indicated by hatching.
  • the MISFET cell 20 includes the gate electrode 40 according to the first embodiment (see also FIG. 2 and the like).
  • the gate insulating film 30 covers the region between the drain region 23 and the source region 24 on the first main surface 3 in the form of a film. Specifically, the gate insulating film 30 is formed on the first main surface 3 so as to straddle the source region 24 and the drain drift region 27 (drain well region 21), and the second semiconductor region 7, the source region 24, and the channel. It covers the inversion region 26 and the drain drift region 27.
  • the gate insulating film 30 includes the first portion 31 and the second portion 32.
  • the first portion 31 covers a part of the source well region 22 and the source region 24 on the first main surface 3. That is, the first portion 31 covers the channel inversion region 26 on the first main surface 3.
  • the first portion 31 preferably covers the entire area of the channel inversion region 26.
  • the first portion 31 is formed at intervals from the contact region 25 to the source region 24 in a plan view, and exposes a part of the source region 24 and the entire contact region 25.
  • the first portion 31 has a first length L1 with respect to the first direction X.
  • the second portion 32 is drawn from the first portion 31 toward the drain region 23, and covers the second semiconductor region 7 and the drain well region 21 on the first main surface 3. That is, the second portion 32 covers the drain drift region 27 on the first main surface 3. Specifically, the second portion 32 is formed at a distance from the drain region 23 to the source region 24 side in a plan view, and is a part of the drain well region 21 (specifically, an end portion on the fourth side surface 5D side). ) And the entire drain region 23 are exposed and partially cover the drain drift region 27.
  • the flat area of the second portion 32 is preferably less than the flat area of the portion exposed from the second portion 32 in the drain drift region 27.
  • the second portion 32 has a second length L2 with respect to the first direction X.
  • the second length L2 preferably exceeds the first length L1 (L1 ⁇ L2).
  • the gate electrode 40 is formed on the gate insulating film 30 so as to straddle the source region 24 and the drain drift region 27 (drain well region 21), and the second semiconductor region 7 and the drain are sandwiched between the gate insulating film 30. It covers the drift region 27, the channel inversion region 26, and the source region 24.
  • the gate electrode 40 has a planar shape different from the planar shape of the gate insulating film 30.
  • the gate electrode 40 includes a first electrode portion 41 and a second electrode portion 42 formed in different planar shapes in different regions on the gate insulating film 30. ..
  • the first electrode portion 41 is formed on the first portion 31 of the gate insulating film 30 and faces the source well region 22 and a part of the source region 24 with the first portion 31 interposed therebetween. That is, the first electrode portion 41 faces the channel inversion region 26 with the first portion 31 interposed therebetween.
  • the first electrode portion 41 faces the entire area of the channel inversion region 26 with the first portion 31 interposed therebetween. It is preferable that the gate electrode 40 (first electrode portion 41) is drawn out to a region outside the channel inversion region 26 across the peripheral edge of the channel inversion region 26 in the second direction Y in a plan view. The portion of the gate electrode 40 drawn out to the region outside the channel inversion region 26 may be formed as a connecting portion of the gate contact electrode (not shown). The first electrode portion 41 is formed at a distance from the contact region 25 to the source region 24 side in a plan view, and exposes the source region 24 and the contact region 25.
  • the second electrode portion 42 is formed on the second portion 32 of the gate insulating film 30. Specifically, the second electrode portion 42 is pulled out from the first electrode portion 41 onto the second portion 32 so as to partially expose the second portion 32, and the drain drift region sandwiches the second portion 32. It faces a part of 27. The second electrode portion 42 is further pulled out from above the second portion 32 onto the field insulating film 35, and faces the drain drift region 27 with the field insulating film 35 interposed therebetween.
  • the second electrode portion 42 forms a gate drain capacitance Cgd with the drain drift region 27.
  • the gate-drain capacity Cgd includes a first gate-drain capacity Cgd1 and a second gate-drain capacity Cgd2 connected in parallel to the first gate-drain capacity Cgd1.
  • the first gate drain capacitance Cgd1 is formed in a portion of the second electrode portion 42 facing the second semiconductor region 7 and the drain well region 21 with the gate insulating film 30 interposed therebetween.
  • the second gate drain capacitance Cgd2 is formed in a portion of the second electrode portion 42 facing the drain well region 21 with the field insulating film 35 interposed therebetween.
  • the second electrode portion 42 has a second electrode portion 41 to a second portion so as to partially expose the second portion 32 with the first electrode portion 41. It has at least one (plural) drawers 43 drawn above the 32.
  • the plurality of drawers 43 are pulled out from the region between the drain well region 21 and the source well region 22 toward the drain region 23 side in a plan view. The plurality of drawer portions 43 are pulled out from positions spaced apart from the source well region 22 toward the drain well region 21.
  • the plurality of extraction portions 43 face the second semiconductor region 7 and the drain well region 21 with the gate insulating film 30 (second portion 32) interposed therebetween, and the second semiconductor region 7 with the field insulating film 35 interposed therebetween. And facing the drain well region 21. That is, the plurality of extraction portions 43 form the drain drift region 27 and the first gate drain capacitance Cgd1 in the portion covering the gate insulating film 30 (second portion 32). Further, the plurality of extraction portions 43 form a drain drift region 27 and a second gate drain capacity Cgd2 in a portion covering the field insulating film 35.
  • a plurality of drawing portions 43 face the second semiconductor region 7 with the second portion 32 interposed therebetween.
  • the plurality of drawers 43 do not necessarily have to face the second semiconductor region 7. That is, the plurality of drawing portions 43 may be drawn out from the second semiconductor region 7 at positions spaced apart from the drain well region 21 side, and may cover the drain well region 21 with the second portion 32 interposed therebetween.
  • the second electrode portion 42 may cover the entire portion of the second portion 32 that covers the second semiconductor region 7.
  • the second electrode portion 42 is partitioned by at least one (plural) drawing portions 43 so as to partially expose the second portion 32. It has one (plural) exposed portions 44 in this form.
  • the plurality of exposed portions 44 extend from the region between the drain well region 21 and the source well region 22 toward the drain region 23 side in a plan view.
  • the plurality of exposed portions 44 partially expose the portion of the second portion 32 that covers the second semiconductor region 7 and the drain well region 21, and partially expose the field insulating film 35. That is, the plurality of exposed portions 44 reduce the first gate drain capacity Cgd1 in the portion where the second semiconductor region 7 and the drain well region 21 are exposed, and the second gate drain capacity Cgd2 in the portion where the field insulating film 35 is exposed. It is decreasing.
  • the semiconductor device 51 can also exert the same effect as the effect described for the semiconductor device 1.
  • the semiconductor device 51 includes the gate electrode 40 according to the above-mentioned first embodiment.
  • the semiconductor device 51 may include any one of the gate electrodes 40 according to the second to sixth embodiments instead of the gate electrode 40 according to the first embodiment.
  • the semiconductor device 51 may have a gate electrode 40 that simultaneously includes at least two of the features of the gate electrode 40 according to the first to sixth embodiments described above.
  • the present invention can be implemented in still other forms.
  • the form in which the source well region 22 and the contact region 25 are removed may be adopted.
  • the channel inversion region 26 is formed on the surface layer portion of the second semiconductor region 7 in the region between the drain well region 21 and the source region 24.
  • the form in which the drain well region 21 is removed may be adopted.
  • the drain drift region 27 is formed in the second semiconductor region 7. That is, the second electrode portion 42 forms the first gate drain capacitance Cgd1 at the portion facing the second semiconductor region 7 with the gate insulating film 30 interposed therebetween, and faces the second semiconductor region 7 with the field insulating film 35 interposed therebetween.
  • the second gate drain capacitance Cgd2 may be formed in the portion to be formed.
  • the example in which the first conductive type is p type and the second conductive type is n type has been described, but the first conductive type may be n type and the second conductive type may be p type. ..
  • the specific configuration in this case is obtained by replacing the n-type region with the p-type region and replacing the p-type region with the n-type region in the above description and the accompanying drawings.
  • examples in which the p-type is expressed as the first conductive type and the n-type is expressed as the second conductive type have been described, but these are merely terms for clarifying the order of explanation.
  • P type may be expressed as a second conductive type
  • n type may be expressed as a first conductive type.
  • [A1] The chip (2) having the main surface (3), the drain region (23) formed on the surface layer portion of the main surface (3), and the main surface at intervals from the drain region (23).
  • the source region (24) side between the source region (24) formed on the surface layer portion of (3) and the drain region (23) and the source region (24) on the surface layer portion of the main surface (3).
  • the channel inversion region (26) formed in, the drift region formed in the region between the drain region (23) and the channel inversion region (26) on the surface layer portion of the main surface (3), and the main.
  • a gate having a first portion (31) covering the channel inversion region (26) on the surface (3) and a second portion (32) covering the drift region on the main surface (3).
  • the first electrode portion (41) so as to partially expose the insulating film (30), the first electrode portion (41) that covers the first portion (31), and the second portion (32).
  • a semiconductor device (1, 51) comprising a gate electrode (40) having a second electrode portion (42) drawn onto the second portion (32).
  • the second electrode portion (42) has a side extending in the opposite direction (X) of the drain region (23) and the source region (24) to partially expose the second portion.
  • the semiconductor device (1, 51) according to A1.
  • the second electrode portion (42) is attached to any one of A1 to A3, which exposes the second portion (32) at a distance from the first portion (31) in a plan view.
  • the semiconductor device (1, 51) according to the above.
  • the first portion (31) covers the entire area of the channel inversion region (26) in a plan view, and the second portion (32) partially exposes the drift region in a plan view.
  • the semiconductor device (1, 51) according to any one of A1 to A5, which partially covers the drift region.
  • the second electrode portion (42) is described in any one of A1 to A7, wherein a plurality of portions of the second portion (32) are exposed in a row at intervals in a plan view.
  • A9 Any of A1 to A8, which covers the drift region on the main surface (3) and further includes a field insulating film (35) having a thickness different from the thickness of the gate insulating film (30).
  • the semiconductor device (1, 51) according to one.
  • the field insulating film (35) is connected to the second portion (32), and the second electrode portion (42) is formed on the field insulating film (35) from above the second portion (32).
  • the second electrode portion (42) extends in the opposite direction (X) of the drain region (23) and the source region (24), and has a side that partially exposes the field insulating film (35).
  • the semiconductor device (1, 51) according to A11.
  • a region (21) is further included, and the drain region (23) of the second conductive type (n type) is formed on the surface layer portion of the drain well region (21), and the second conductive type (n type) is formed.
  • the source region (24) is formed on the surface layer portion of the semiconductor region at intervals from the drain well region (21), and the channel inversion region (26) is the drain well region (21) and the source region.
  • the semiconductor device (1) according to any one of A1 to A14, which is formed in the region between (24) and the drift region is formed in the drain well region (21).
  • the source region (24) further includes a first conductive type (p-type) source well region (22) formed on the surface layer portion of the semiconductor region at intervals from the drain well region (21). Is the semiconductor device (1) according to A15, which is formed on the surface layer portion of the source well region (22).
  • the semiconductor device (1) according to A16 further including a first conductive type (p type) contact region (25) formed on the surface layer portion of the source well region (22).
  • a region (22) is further included, and the drain region (23) of the first conductive type (n type) is formed on the surface layer portion of the semiconductor region at a distance from the source well region (22). 1
  • the conductive type (n type) source region (24) is formed on the surface layer portion of the source well region (22), and the channel inversion region (26) is formed on the surface layer portion of the source well region (22). Any of A1 to A14 formed between the semiconductor region and the source region (24), the drift region being formed in the region between the source well region (22) and the drain region (23).
  • the semiconductor device (51) according to one.
  • the drain well region (21) of the first conductive type (n type) formed on the surface layer portion of the semiconductor region at intervals from the source well region (22) is further included, and the drain region (23). Is the semiconductor device (51) according to A18, which is formed on the surface layer portion of the drain well region (21).
  • a chip (2) having a main surface (3), a first conductive type (p-type) semiconductor region formed on the surface layer portion of the main surface (3), and a surface layer portion of the semiconductor region.
  • a gate insulating film (30) having a second portion (32) covering the drain well region (21), a first electrode portion (41) covering the first portion (31), and the second portion.
  • a gate electrode (40) having a second electrode portion (42) drawn from the first electrode portion (41) onto the second portion (32) so as to partially expose the portion (32).
  • the source region (24) further includes a first conductive type (p-type) source well region (22) formed on the surface layer portion of the semiconductor region at intervals from the drain well region (21). Is the semiconductor device (1) according to B1, which is formed on the surface layer portion of the source well region (22).
  • [B4] B1 which covers the drain well region (21) on the main surface (3) and further includes a field insulating film (35) having a thickness different from the thickness of the gate insulating film (30).
  • the semiconductor device (1) according to any one of B3.
  • the field insulating film (35) is connected to the second portion (32), and the second electrode portion (42) is formed on the field insulating film (35) from above the second portion (32).
  • the semiconductor device (1) according to B4 which is pulled out upward and faces the drift region with the field insulating film (35) interposed therebetween.
  • a chip (2) having a main surface (3), a first conductive type (n type) semiconductor region formed on the surface layer portion of the main surface (3), and a surface layer portion of the semiconductor region.
  • the second conductive type (p type) source well region (22) and the first conductive type (n type) formed on the surface layer portion of the semiconductor region at intervals from the source well region (22).
  • a gate insulating film (30) having a second portion (32) covering the region between the source well region (22) and the drain region (23), and a first covering the first portion (31).
  • the second electrode portion (41) and the second electrode portion (32) pulled out from the first electrode portion (41) onto the second portion (32) so as to partially expose the electrode portion (41) and the second portion (32).
  • a semiconductor device (51) comprising a gate electrode (40) having 42).
  • the drain well region (21) of the first conductive type (n type) formed on the surface layer portion of the semiconductor region at intervals from the source well region (22) is further included, and the drain region (23). Is the semiconductor device (51) according to C1, which is formed on the surface layer portion of the drain well region (21).
  • [C4] C1 which covers the drain well region (21) on the main surface (3) and further includes a field insulating film (35) having a thickness different from the thickness of the gate insulating film (30).
  • the semiconductor device (51) according to any one of C3.
  • the field insulating film (35) is connected to the second portion (32), and the second electrode portion (42) is formed on the field insulating film (35) from above the second portion (32).
  • the semiconductor device (51) according to C4 which is pulled out upward and faces the drift region with the field insulating film (35) interposed therebetween.

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  • Insulated Gate Type Field-Effect Transistor (AREA)
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