WO2022091348A1 - 表示装置および表示装置の製造方法 - Google Patents
表示装置および表示装置の製造方法 Download PDFInfo
- Publication number
- WO2022091348A1 WO2022091348A1 PCT/JP2020/040839 JP2020040839W WO2022091348A1 WO 2022091348 A1 WO2022091348 A1 WO 2022091348A1 JP 2020040839 W JP2020040839 W JP 2020040839W WO 2022091348 A1 WO2022091348 A1 WO 2022091348A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- region
- transistor
- doped
- concentration
- adjacent
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 52
- 239000012535 impurity Substances 0.000 claims abstract description 45
- 229910052751 metal Inorganic materials 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 23
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 113
- 108091006146 Channels Proteins 0.000 description 51
- 239000010408 film Substances 0.000 description 40
- 239000011229 interlayer Substances 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 229910052814 silicon oxide Inorganic materials 0.000 description 12
- 238000000206 photolithography Methods 0.000 description 9
- 239000000758 substrate Substances 0.000 description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 239000013039 cover film Substances 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 238000007789 sealing Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- 239000002096 quantum dot Substances 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229920000178 Acrylic resin Polymers 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005401 electroluminescence Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000005525 hole transport Effects 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000005283 ground state Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000005984 hydrogenation reaction Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- SJCKRGFTWFGHGZ-UHFFFAOYSA-N magnesium silver Chemical compound [Mg].[Ag] SJCKRGFTWFGHGZ-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012044 organic layer Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B33/00—Electroluminescent light sources
- H05B33/02—Details
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B33/00—Electroluminescent light sources
- H05B33/12—Light sources with substantially two-dimensional radiating surfaces
- H05B33/14—Light sources with substantially two-dimensional radiating surfaces characterised by the chemical or physical composition or the arrangement of the electroluminescent material, or by the simultaneous addition of the electroluminescent material in or onto the light source
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
Definitions
- the present invention relates to a display device.
- Patent Document 1 discloses a method in which a drain region (impurity introduction region) is composed of a low concentration region (LDD region) and a high concentration region in the semiconductor layer of an electro-optic device.
- the display device includes a light emitting element and a pixel circuit including a transistor of the first structure, and the semiconductor layer of the transistor of the first structure has a first channel region and the first channel region.
- the first-doped region adjacent to the first channel region is composed of a high-concentration region and includes the first-doped region and the second-doped region, which are arranged on both sides of the above and are doped with impurities.
- the region is composed of a low concentration region adjacent to the first channel region and a high concentration region adjacent to the low concentration region, and the high concentration region included in the semiconductor layer of the transistor of the first structure is the semiconductor.
- the dope concentration is higher than the low concentration region contained in the layer, and the pixel circuit includes a drive transistor which is a transistor of the first structure and a capacitive element connected to a gate electrode of the drive transistor, and emits light. During the light emission period of the element, a drive current flows from the first-doped region of the drive transistor toward the second-doped region.
- FIG. 1 (a) is a cross-sectional view of the display device of the present embodiment including a transistor of the first structure and a transistor of the third structure
- FIG. 1 (b) is a second view of the display device of the present embodiment.
- It is sectional drawing which includes a transistor of a structure.
- It is a schematic plan view which shows the structure of the display device of this embodiment.
- It is a circuit diagram which shows an example of a pixel circuit.
- FIG. 4A is a cross-sectional view showing a configuration example of a portion of the pixel circuit including a drive transistor and a light emission control transistor
- FIG. 4B is a cross-sectional view showing a configuration example of a portion of the pixel circuit including a reset transistor.
- FIG. 4A is a cross-sectional view showing a configuration example of a portion of the pixel circuit including a drive transistor and a light emission control transistor
- FIG. 4B is a cross-sectional view showing a configuration example of a portion
- FIG 4 (c) is a cross-sectional view showing a configuration example of a portion of a pixel circuit including a threshold control transistor. It is a flowchart which shows the manufacturing method of the display device of Embodiment 1. It is sectional drawing which shows the manufacturing method of the transistor of 1st structure in Embodiment 1. FIG. It is sectional drawing which shows the manufacturing method of the transistor of the 2nd structure in Embodiment 1. FIG. It is sectional drawing which shows the manufacturing method of the transistor of the 3rd structure in Embodiment 1. FIG. It is a flowchart which shows the manufacturing method of the display device of Embodiment 2. It is sectional drawing which shows the manufacturing method of the transistor of 1st structure in Embodiment 2. It is sectional drawing which shows the manufacturing method of the transistor of the 2nd structure in Embodiment 2. It is sectional drawing which shows the manufacturing method of the transistor of the 3rd structure in Embodiment 2.
- FIG. 1 (a) is a cross-sectional view of the display device of the present embodiment including a transistor of the first structure and a transistor of the third structure
- FIG. 1 (b) is a second view of the display device of the present embodiment. It is sectional drawing which includes a transistor of a structure.
- FIG. 2 is a schematic plan view showing the configuration of the display device of the present embodiment.
- the substrate 2 As shown in FIGS. 1 to 2, in the display device 10, the substrate 2, the thin film transistor layer 4 including the pixel circuit PC, the light emitting element layer 5 including the top emission (light emitting to the upper layer side) type light emitting element ED, and the seal.
- the stop layer 6 is formed in this order, and the light emitting element ED and the pixel circuit PC are formed for each sub-pixel SP.
- the substrate 2 is a glass substrate or a flexible base material containing a resin such as polyimide as a main component.
- the substrate 2 can be composed of two layers of polyimide films and an inorganic film sandwiched between them. ..
- a base coat film (inorganic insulating film) that prevents foreign substances such as water and oxygen from entering may be provided on the upper surface (interface with the semiconductor layer SC) of the substrate 2.
- the thin film transistor layer 4 is formed on a semiconductor layer SC formed on the substrate 2, a gate insulating film 14 covering the semiconductor layer SC, and a layer above the gate insulating film 14, and forms a gate electrode GE.
- a flattening film 21 is provided.
- the semiconductor layer SC is composed of, for example, low-temperature-formed polysilicon (LTPS).
- LTPS low-temperature-formed polysilicon
- the portion superposed with the gate electrode GE functions as a semiconductor (channel), and the portion not superposed is made into a conductor by impurity doping or the like.
- the first metal layer, the second metal layer and the third metal layer are composed of a metal single layer film or a metal multi-layer film containing at least one of, for example, aluminum, tungsten, molybdenum, tantalum, chromium, titanium, and copper. Will be done.
- the gate insulating film 14 can be made of, for example, a silicon oxide (SiOx) film.
- the first interlayer insulating film 16 covering the gate electrode GE can be composed of, for example, a laminated film of silicon oxide (SiOx) and silicon nitride (SiNx).
- the second interlayer insulating film 20 can be composed of a single-layer film of silicon oxide (SiOx) or a laminated film of silicon oxide (SiOx) and silicon nitride (SiNx).
- the flattening film 21 can be made of a coatable organic material such as polyimide or acrylic resin.
- the light emitting element layer 5 includes a lower electrode 22, an insulating edge cover film 23 that covers the edge of the lower electrode 22, an EL (electroluminescence) layer 24 that is higher than the edge cover film 23, and an EL (electroluminescence) layer 24 that is higher than the EL layer 24. Includes the upper electrode 25 of.
- the edge cover film 23 is formed by applying an organic material such as polyimide or acrylic resin and then patterning by photolithography.
- each light emitting element includes an island-shaped lower electrode 22, an EL layer 24 including a light emitting layer, and an upper electrode 25.
- the upper electrode 25 is a solid common electrode common to a plurality of light emitting elements ED.
- the light emitting element ED may be, for example, an OLED (organic light emitting diode) including an organic layer as a light emitting layer, or a QLED (quantum dot light emitting diode) including a quantum dot layer as a light emitting layer.
- OLED organic light emitting diode
- QLED quantum dot light emitting diode
- the EL layer 24 is composed of, for example, laminating a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer in order from the lower layer side.
- the light emitting layer is formed in an island shape in the opening (for each sub-pixel) of the edge cover film 23 by a vapor deposition method, an inkjet method, or a photolithography method.
- the other layers are formed in an island shape or a solid shape (common layer).
- the hole injection layer, the hole transport layer, the electron transport layer, and the electron injection layer may be configured so as not to form one or more layers.
- the lower electrode 22 is a light reflecting electrode composed of, for example, a laminate of ITO (Indium Tin Oxide) and an alloy containing Ag (silver) or Ag.
- the upper electrode 25 is made of a metal thin film such as a magnesium-silver alloy and has light transmittance.
- the light emitting element ED When the light emitting element ED is an OLED, holes and electrons are recombined in the light emitting layer by the driving current between the lower electrode 22 and the upper electrode 25, and light is emitted in the process of transitioning the resulting excitons to the ground state. Will be done.
- the driving current between the lower electrode 22 and the upper electrode 25 causes holes and electrons to recombine in the light emitting layer, and the resulting excitons generate conduction band levels (conduction) of the quantum dots. Light is emitted in the process of transitioning from the band) to the valence band.
- the sealing layer 6 covering the light emitting element layer 5 is a layer for preventing foreign substances such as water and oxygen from penetrating into the light emitting element layer 5.
- the pixel circuit PC includes a transistor TA having a first structure, a transistor TB having a second structure, and a transistor TC having a third structure.
- the transistor TA of the first structure, the transistor TB of the second structure, and the transistor TC of the third structure are P-type transistors (P-type channel type), respectively, and the gate electrode is formed in a layer above the channel region. It is a type.
- the semiconductor layer SC of the transistor TA of the first structure includes a first channel region CH1 and a first doped region A1 and a second doped region A2 arranged on both sides of the first channel region CH1 and doped with impurities. ..
- the first channel region CH1 matches the gate electrode GE of the transistor TA.
- the semiconductor layer SC of the transistor TB having the second structure includes a second channel region CH2 and a third doped region A3 and a fourth doped region A4 arranged on both sides of the second channel region CH2 and doped with impurities. ..
- the second channel region CH2 matches the gate electrode GE of the transistor TB.
- the semiconductor layer SC of the transistor TC of the third structure includes a third channel region CH3 and a fifth doped region A5 and a sixth doped region A6 arranged on both sides of the third channel region CH3 and doped with impurities. ..
- the third channel region CH3 matches the gate electrode GE of the transistor TC.
- the first doped region A1 adjacent to one side of the first channel region CH1 is composed of the high concentration region aH, and the other side of the first channel region CH1.
- the second dope region A2 adjacent to the first channel region CH1 is composed of a low concentration region aL adjacent to the first channel region CH1 and a high concentration region aH adjacent to the low concentration region aL.
- the third doped region A3 adjacent to one side of the second channel region CH2 has a low concentration region aL adjacent to the second channel region CH2 and a high concentration region aL adjacent to the low concentration region aL.
- the fourth doped region A4 which is composed of the concentration region aH and is adjacent to the other side of the second channel region CH2, has a low concentration region aL adjacent to the second channel region CH2 and a high concentration region adjacent to the low concentration region aL. It is composed of the region aH.
- the fifth doped region A5 adjacent to one side of the third channel region CH3 is composed of the high concentration region aH
- the doping concentration in the high concentration region aH is 10 times or more the doping concentration in the low concentration region aL.
- FIG. 3 is a circuit diagram showing an example of a pixel circuit.
- the capacitive element Cp, the reset transistors T1x and T1y in which the gate electrode is connected to the scanning signal line Gn-1 in the previous stage (n-1 stage), and the gate electrode are in their own stage (n stage).
- the threshold control transistors T2x and T2y connected to the scanning signal line Gn of the above, the writing control transistor T3 in which the gate electrode is connected to the scanning signal line Gn of its own stage (n stage), and the drive for controlling the current of the light emitting element ED.
- the transistor T4 the power supply transistor T5 in which the gate electrode is connected to the light emission control line EM (n stages), the light emission control transistor T6 in which the gate electrode is connected to the light emission control line EM (n stages), and the gate electrode itself.
- the initialization transistor T7 connected to the scanning signal line Gn of the stage (n stage) is included.
- the scanning signal line Gn / Gn-1 and the light emission control line EM are included in the first metal layer, and the data signal line DL, the power supply line PL, and the initialization signal line are included in the third metal layer.
- a part of the scanning signal line Gn, a part of the scanning signal line Gn-1, or a part of the light emission control line EM may function as a gate electrode GE of each transistor other than the driving transistor T4.
- the drive transistor T4 is a transistor TA having a first structure
- the reset transistors T1x / T1y and the threshold control transistors T2x / T2y are transistors TB having a second structure, respectively, and are a write control transistor T3, a power supply transistor T5, and light emission control.
- the transistor T6 and the initialization transistor T7 are each a transistor TC having a third structure.
- the gate electrode GE of the drive transistor T4 is connected to the power supply line PL via the capacitive element Cp, and is also connected to the initialization signal line IL via the reset transistors T1x and T1y.
- a high voltage side power supply (EL VDD) is supplied to the power supply line PL, and for example, the same low voltage side power supply (ELVSS) is supplied to the cathode (upper electrode 25) of the initialization signal line IL and the light emitting element ED.
- the first doped region (source region) A1 of the drive transistor T4 is connected to the data signal line DL via the write control transistor T3, and is also connected to the power supply line PL via the power supply transistor T5.
- the second doped region (drain region) A2 of the drive transistor T4 is connected to the anode (lower electrode 22) of the light emitting element ED via the light emitting control transistor T6, and the two threshold control transistors T2x. It is connected to the gate electrode GE of the drive transistor T4 via T2y.
- the anode of the light emitting element ED is connected to the initialization signal line IL via the initialization transistor T7.
- FIG. 4A is a cross-sectional view showing a configuration example of a portion of the pixel circuit including a drive transistor and a light emission control transistor
- FIG. 4B is a cross-sectional view showing a configuration example of a portion of the pixel circuit including a reset transistor
- FIG. 4 (c) is a cross-sectional view showing a configuration example of a portion of a pixel circuit including a threshold control transistor.
- the capacitive element Cp is formed so as to include the gate electrode GE and the capacitive electrode CE of the drive transistor T4 (TA), and the capacitive electrode CE is a second interlayer insulating film. It is connected to the power supply line PL through the contact hole formed in 20.
- the second doped region A2 of the drive transistor T4 (TA) is connected to the lower electrode 22 (anode) of the light emitting element ED via the light emission control transistor T6 (TC).
- the drive current Id flows from the first doped region A1 which is the source region of the drive transistor T4 (TA) toward the second doped region A2 which is the drain region.
- the second-doped region A2 of the drive transistor T4 and the fifth-doped region A5 of the light emission control transistor T6 are connected to each other via the wiring region Aw of the semiconductor layer SC.
- the wiring region Aw is a conductor portion composed of the high concentration region aH.
- the drive current Id flows into the light emitting element ED through the wiring region Aw, the fifth doped region A5 of the light emitting control transistor T6, the third channel region CH3, and the sixth doped region A6.
- the drive transistor T4 is a transistor TA having the first structure, the first region A1 which is the source region is composed of the high concentration region aH, and the second region A2 which is the drain region is adjacent to the first channel region CH1.
- the low-concentration region aL and the high-concentration region aH it is possible to improve the drive capability of the drive transistor T4 and reduce the off-current at the same time.
- the paired reset transistors T1x and T1y are connected in series, and the reset transistor T1x has a fourth dope region A4 and the reset transistor T1y has a third dope region A3. Is connected via the wiring area Aw.
- the third doped region A3 of the reset transistor T1x is connected to the initialization signal line IL via the wiring region Aw of the semiconductor layer SC.
- the paired threshold control transistors T2x and T2y are connected in series, and the fourth dope region A4 of the threshold control transistor T2x and the third dope of the threshold control transistor T2y are connected.
- the area A3 is connected to the area A3 via the wiring area Aw.
- the third doped region A3 of the threshold control transistor T2x is connected to the upper layer wiring UW via the wiring region Aw of the semiconductor layer SC.
- the reset transistors T1x / T1y and the threshold control transistors T2x / T2y are used as the transistors TB having the second structure, and the third doped region A3 and the fourth doped region A4 are each in the low concentration region adjacent to the second channel region CH2.
- aL and the high concentration region aH it is possible to reduce the off-current of the reset transistor and the threshold control transistor.
- the write control transistor T3, the power supply transistor T5, the light emission control transistor T6, and the initialization transistor T7 are each used as a transistor TC having a third structure, and the fifth dope region A5 and the sixth dope region A6 adjacent to the third channel region CH3 are used. By configuring each of them in the high concentration region aH, it is possible to secure the ON currents of these transistors T3, T5, T6, and T7.
- the initialization transistor T7 may be a transistor TB having a second structure.
- the transistors T1 to T7 of the pixel circuit PC are divided into the transistor TA of the first structure, the second transistor TB, and the third transistor TC according to the function, thereby increasing the capacity of the transistors T1 to T7. It can be optimized, and a pixel circuit with high brightness and high reliability can be realized.
- FIG. 5 is a flowchart showing a manufacturing method of the display device of the first embodiment.
- FIG. 6 is a cross-sectional view showing a method of manufacturing a transistor having the first structure according to the first embodiment.
- FIG. 7 is a cross-sectional view showing a method of manufacturing a transistor having a second structure according to the first embodiment.
- FIG. 8 is a cross-sectional view showing a method of manufacturing a transistor having a third structure according to the first embodiment.
- step S1 the substrate 2 (including the base coat film) is formed.
- step S2 a film of amorphous silicon (amorphous silicon) is formed.
- step S3 the amorphous silicon is dehydrogenated by heat treatment.
- step S4 laser annealing is performed by an ELA (Exicimer Laser Anneling) method, and amorphous silicon is used as a semiconductor layer SC made of polysilicon.
- step S5 the semiconductor layer SC is patterned by a photolithography method.
- step S6 the gate insulating film 14 (for example, silicon oxide) is formed by using the CVA method.
- step S7 a first metal layer (molybdenum-based alloy such as molybdenum or MoW) is formed by using a sputtering method.
- step S8 patterning of the first metal layer (formation of the gate electrode GE or the like) is performed by a photolithography method.
- step S10f low-concentration doping of impurities is performed on the semiconductor layer SC using the gate electrode GE as a shield (see FIGS. 6 (b), 7 (b), and 8 (b)).
- the gate electrode GE as a shield
- the doping concentration is, for example, 3.0 ⁇ 10 16 to 2 ⁇ 10 17 [atoms / cm 3 ].
- a low concentration region aL is formed.
- step S10s high-concentration doping of impurities is performed on the semiconductor layer SC using the gate electrode GE and the mask MK as a shield (see FIGS. 6 (c), 7 (c), and 8 (c)).
- impurities for example, boron is used as the impurity, and the doping concentration is, for example, 1.0 ⁇ 10 19 to 1.0 ⁇ 10 21 [atoms / cm 3 ]. As a result, a high concentration region aH is formed.
- the semiconductor layer SC of the transistor TA (T4) having the first structure either the first portion P1 superimposed on the gate electrode GE or both sides of the gate electrode GE.
- the mask MK and the gate electrode GE are used as a shield, and the region is higher than the region not superimposed on the mask MK and the gate electrode GE in the semiconductor layer SC.
- Perform concentration doping As a result, the first channel region CH1, the first dope region A1 (source region) composed of the high concentration region aH, and the second dope region A2 (drain region) composed of the low concentration region aL and the high concentration region aH ) And are formed.
- a mask MK having a portion superimposed on the gate electrode GE and a portion superimposed on both sides of the gate electrode GE.
- the mask MK and the gate electrode GE as a shield, high-concentration doping is performed on the region of the semiconductor layer SC that does not overlap with either the mask MK and the gate electrode GE.
- the second channel region CH2 the third-doped region A3 composed of the low-concentration region aL and the high-concentration region aH, and the fourth-doped region A4 composed of the low-concentration region aL and the high-concentration region aH are formed. It is formed.
- step S11 the first interlayer insulating film 16 (for example, a laminated film of silicon oxide and silicon nitride) is formed by using the CVA method.
- step S12 hydrogenation annealing (heat treatment for the purpose of supplying hydrogen to the crystalline silicon semiconductor layer SC) is performed.
- step S13 the first interlayer insulating film 16 is patterned (opening formed) by a photolithography method.
- the second metal layer 19 (for example, a titanium / aluminum / titanium laminated film) is formed by using a sputtering method.
- patterning of the second metal layer (formation of the capacitive electrode CE or the like) is performed by a photolithography method.
- the second interlayer insulating film 20 (for example, a single layer film of silicon oxide or a laminated film of silicon nitride and silicon oxide) is formed by using the CVA method.
- the first interlayer insulating film 16, the second interlayer insulating film 20, and the gate insulating film 14 are patterned by a photolithography method.
- a third metal layer for example, a titanium / aluminum / titanium laminated film
- a sputtering method for example, a sputtering method
- patterning of the third metal layer is performed by a photolithography method.
- the light emitting element layer 5 is formed.
- the sealing layer 6 is formed.
- FIG. 9 is a flowchart showing a method of manufacturing the display device of the second embodiment.
- FIG. 10 is a cross-sectional view showing a method of manufacturing a transistor having the first structure according to the second embodiment.
- FIG. 11 is a cross-sectional view showing a method of manufacturing a transistor having a second structure according to the second embodiment.
- FIG. 12 is a cross-sectional view showing a method of manufacturing a transistor having a third structure according to the second embodiment.
- Steps S1 to S8 of FIG. 9 are the same as those of the first embodiment, and in step S9, the first metal layer is patterned by a photolithography method to form a gate layer ML.
- step S10d high-concentration doping of impurities is performed on the semiconductor layer SC using the gate layer ML as a shield (see FIGS. 10 (b), 11 (b), and 12 (b)).
- impurities for example, boron is used as the impurity, and the doping concentration is, for example, 1.0 ⁇ 10 19 to 1.0 ⁇ 10 21 [atoms / cm 3 ].
- a high concentration region aH is formed.
- step S10e the gate layer ML is thinned by etching to form a gate electrode GE (see FIGS. 10 (c), 11 (c), and 12 (c)).
- step S10f low-concentration doping of impurities is performed on the semiconductor layer SC using the gate electrode GE as a shield (FIGS. 10 (d), 11 (d), and 12 (d)). reference).
- the gate electrode GE as a shield
- the doping concentration is, for example, 3.0 ⁇ 10 16 to 2 ⁇ 10 17 [atoms / cm 3 ].
- a low concentration region aL is formed.
- step S10s similarly to the first embodiment, high-concentration doping of impurities is performed on the semiconductor layer SC using the gate electrode GE and the mask MK as a shield (FIGS. 10 (e), 11 (e), and 12 (FIG. 12). See (e).
- boron is used as the impurity, and the doping concentration is, for example, 1.0 ⁇ 10 19 to 1.0 ⁇ 10 21 [atoms / cm 3 ].
- a high concentration region aH is formed.
- Steps S11 to S21 of FIG. 9 are the same as those of the first embodiment.
- a light emitting element and a pixel circuit including a transistor of the first structure are provided.
- the semiconductor layer of the transistor of the first structure includes a first channel region, a first dope region adjacent to one side of the first channel region, and a second dope region adjacent to the other side of the first channel region.
- the first doped region is composed of a high concentration region in which impurities are heavily doped.
- the second-doped region is adjacent to the first channel region and is adjacent to the low-concentration region where impurities are doped at a low concentration, and the second-doped region is adjacent to the low-concentration region and is adjacent to the high-concentration region where impurities are doped at a high concentration.
- the pixel circuit includes a drive transistor which is a transistor having the first structure and a capacitive element connected to a gate electrode of the drive transistor.
- a display device in which a drive current flows from the first-doped region of the drive transistor toward the second-doped region during the light emitting period of the light-emitting element.
- the pixel circuit includes a transistor having a second structure.
- the semiconductor layer of the transistor of the second structure includes a second channel region, a third dope region adjacent to one side of the second channel region, and a fourth dope region adjacent to the other side of the second channel region.
- the third-doped region is adjacent to the second channel region and is adjacent to the low-concentration region where impurities are doped at a low concentration, and the third-doped region is adjacent to the low-concentration region and is adjacent to the high-concentration region where impurities are doped to a high concentration.
- the fourth-doped region is adjacent to the second channel region and is adjacent to the low-concentration region where impurities are doped at a low concentration, and the fourth-doped region is adjacent to the low-concentration region and is adjacent to the high-concentration region where impurities are doped to a high concentration.
- the display device according to, for example, the first aspect, which is configured.
- the pixel circuit includes a transistor having the second structure and a threshold control transistor connected to a scanning signal line of its own stage and a gate electrode of the drive transistor.
- the pixel circuit includes a transistor having a third structure.
- the semiconductor layer of the transistor having the third structure includes a third channel region, a fifth dope region adjacent to one side of the third channel region, and a sixth dope region adjacent to the other side of the third channel region.
- the display device according to any one of aspects 1 to 12, for example, the transistor having the first structure is a top gate type.
- the transistor of the first structure is a P-channel type and has a P-channel type.
- a method for manufacturing a display device including a transistor having a first structure including a semiconductor layer and a gate electrode.
- a mask having a first portion superimposed on the gate electrode and a second portion superimposed on any one of both sides of the gate electrode is used, and the mask and the gate electrode are used as a shield.
- a method for manufacturing a display device comprising a fourth step of doping a region not superimposed on either the mask or the gate electrode with impurities at a concentration higher than the low concentration.
- a gate layer which is a metal layer, is formed between the first step and the second step, the gate layer is used as a shield, and the concentration is higher than the low concentration with respect to a region of the semiconductor layer that does not overlap with the gate layer.
- the first doped region is composed of a high concentration region in which impurities are heavily doped.
- the second-doped region corresponds to the second portion of the mask, and includes a low-concentration region in which impurities are doped at a low concentration and a high-concentration region adjacent to the low-concentration region in which impurities are heavily doped.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Nonlinear Science (AREA)
- Chemical & Material Sciences (AREA)
- Mathematical Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Theoretical Computer Science (AREA)
- Optics & Photonics (AREA)
- Electroluminescent Light Sources (AREA)
- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
Description
図1~図2に示すように、画素回路PCは、第1構造のトランジスタTA、第2構造のトランジスタTB、および第3構造のトランジスタTCを含む。第1構造のトランジスタTA、第2構造のトランジスタTB、および第3構造のトランジスタTCはそれぞれ、P型トランジスタ(P型チャネル型)であり、ゲート電極がチャネル領域よりも上層に形成されるトップゲートタイプである。
図9は、実施形態2の表示装置の製造方法を示すフローチャートである。図10は、実施形態2における第1構造のトランジスタの製造方法を示す断面図である。図11は、実施形態2における第2構造のトランジスタの製造方法を示す断面図である。図12は、実施形態2における第3構造のトランジスタの製造方法を示す断面図である。
〔態様1〕
発光素子と、第1構造のトランジスタを含む画素回路とを備え、
前記第1構造のトランジスタの半導体層は、第1チャネル領域と、前記第1チャネル領域の一方側に隣接する第1ドープ領域と、前記第1チャネル領域の他方側に隣接する第2ドープ領域とを含み、
前記第1ドープ領域は、不純物が高濃度にドープされた高濃度領域で構成され、
前記第2ドープ領域は、前記第1チャネル領域に隣接し、不純物が低濃度にドープされた低濃度領域と、当該低濃度領域に隣接し、不純物が高濃度にドープされた高濃度領域とで構成され、
前記画素回路には、前記第1構造のトランジスタである駆動トランジスタと、前記駆動トランジスタのゲート電極に接続する容量素子とが含まれ、
前記発光素子の発光期間に、前記駆動トランジスタの前記第1ドープ領域から前記第2ドープ領域に向けて駆動電流が流れる表示装置。
前記画素回路には、第2構造のトランジスタが含まれ、
前記第2構造のトランジスタの半導体層は、第2チャネル領域と、前記第2チャネル領域の一方側に隣接する第3ドープ領域と、前記第2チャネル領域の他方側に隣接する第4ドープ領域とを含み、
前記第3ドープ領域が、前記第2チャネル領域に隣接し、不純物が低濃度にドープされた低濃度領域と、当該低濃度領域に隣接し、不純物が高濃度にドープされた高濃度領域とで構成され、
前記第4ドープ領域が、前記第2チャネル領域に隣接し、不純物が低濃度にドープされた低濃度領域と、当該低濃度領域に隣接し、不純物が高濃度にドープされた高濃度領域とで構成されている、例えば態様1に記載の表示装置。
前記画素回路には、前記第2構造のトランジスタであり、自段の走査信号線と前記駆動トランジスタのゲート電極とに接続する閾値制御トランジスタが含まれる、例えば態様2に記載の表示装置。
前記画素回路には、前記閾値制御トランジスタに直列に接続する前記第2構造のトランジスタが含まれる、例えば態様3に記載の表示装置。
前記画素回路には、前記第2構造のトランジスタであり、自段よりも前の段の走査信号線と初期化信号線とに接続するリセットトランジスタが含まれる、例えば態様2に記載の表示装置。
前記画素回路には、前記リセットトランジスタに直列に接続する前記第2構造のトランジスタが含まれる、例えば態様5に記載の表示装置。
前記画素回路には、第3構造のトランジスタが含まれ、
前記第3構造のトランジスタの半導体層は、第3チャネル領域と、前記第3チャネル領域の一方側に隣接する第5ドープ領域と、前記第3チャネル領域の他方側に隣接する第6ドープ領域とを含み、
前記第5ドープ領域および前記第6ドープ領域それぞれが、不純物が高濃度にドープされた高濃度領域で構成されている、例えば態様1~6のいずれか1つに記載の表示装置。
前記第1ドープ領域は、前記第3構造のトランジスタである電源制御トランジスタを介して電源に接続される、例えば態様7に記載の表示装置。
前記第2ドープ領域は、前記第3構造のトランジスタである発光制御トランジスタを介して前記発光素子に接続される、例えば態様7に記載の表示装置。
前記第1ドープ領域は、前記第3構造のトランジスタである書き込み制御トランジスタを介してデータ信号線に接続される、例えば態様7に記載の表示装置。
前記発光素子のアノードは、前記第3構造のトランジスタである初期化トランジスタを介して初期化信号線に接続される、例えば態様7に記載の表示装置。
前記第1構造のトランジスタのゲート電極と、前記第1チャネル領域とが整合する、例えば態様1~11のいずれか1つに記載の表示装置。
前記第1構造のトランジスタはトップゲート型である、例えば態様1~12のいずれか1つに記載の表示装置。
前記第1構造のトランジスタはPチャネル型であり、
前記第1ドープ領域はソース領域、前記第2ドープ領域はドレイン領域である、例えば態様1~13のいずれか1つに記載の表示装置。
前記半導体層が結晶性シリコンを含む、例えば態様1~14のいずれか1つに記載の表示装置。
半導体層およびゲート電極を含む第1構造のトランジスタを備える表示装置の製造方法であって、
前記半導体層を形成する第1工程と、
前記ゲート電極を形成する第2工程と、
前記ゲート電極を遮蔽体とし、前記半導体層におけるゲート電極と重畳しない領域に対して、低濃度で不純物をドープする第3工程と、
前記ゲート電極に重畳する第1部分と、前記ゲート電極の両サイドのいずれか1つに重畳する第2部分とを有するマスクを用い、前記マスクおよび前記ゲート電極を遮蔽体として、前記半導体層における前記マスクおよび前記ゲート電極のいずれにも重畳しない領域に対して、前記低濃度よりも高い濃度で不純物をドープする第4工程と、を含む表示装置の製造方法。
前記第1工程および前記第2工程の間に、金属層であるゲート層を形成し、前記ゲート層を遮蔽体とし、前記半導体層におけるゲート層と重畳しない領域に対して、前記低濃度よりも高い濃度で不純物をドープする工程を行い、
前記第2工程では、前記ゲート層をエッチングによって細らせて上記ゲート電極とする、例えば態様16に記載の表示装置の製造方法。
前記半導体層に、前記ゲート電極と重畳する第1チャネル領域と、前記第1チャネル領域の一方側に隣接する第1ドープ領域と、前記第1チャネル領域の他方側に隣接する第2ドープ領域とを含み、
前記第1ドープ領域は、不純物が高濃度にドープされた高濃度領域で構成され、
前記第2ドープ領域は、前記マスクの第2部分に対応し、不純物が低濃度にドープされた低濃度領域と、当該低濃度領域に隣接し、不純物が高濃度にドープされた高濃度領域とで構成されている、例えば態様16に記載の表示装置の製造方法。
4 薄膜トランジスタ層
5 発光素子層
6 封止層
10 表示装置
14 ゲート絶縁膜
16 第1層間絶縁膜
20 第2層間絶縁膜
ED 発光素子
SC 半導体層
GE ゲート電極
Cp 容量素子
CE 容量電極
TA 第1構造のトランジスタ
TB 第2構造のトランジスタ
TC 第3構造のトランジスタ
T4 駆動トランジスタ
CH1 第1チャネル領域
A1 第1ドープ領域
A2 第2ドープ領域
CH2 第2チャネル領域
A3 第3ドープ領域
A4 第4ドープ領域
CH3 第3チャネル領域
A5 第5ドープ領域
A6 第6ドープ領域
Claims (18)
- 発光素子と、第1構造のトランジスタを含む画素回路とを備え、
前記第1構造のトランジスタの半導体層は、第1チャネル領域と、前記第1チャネル領域の一方側に隣接する第1ドープ領域と、前記第1チャネル領域の他方側に隣接する第2ドープ領域とを含み、
前記第1ドープ領域は、不純物が高濃度にドープされた高濃度領域で構成され、
前記第2ドープ領域は、前記第1チャネル領域に隣接し、不純物が低濃度にドープされた低濃度領域と、当該低濃度領域に隣接し、不純物が高濃度にドープされた高濃度領域とで構成され、
前記画素回路には、前記第1構造のトランジスタである駆動トランジスタと、前記駆動トランジスタのゲート電極に接続する容量素子とが含まれ、
前記発光素子の発光期間に、前記駆動トランジスタの前記第1ドープ領域から前記第2ドープ領域に向けて駆動電流が流れる表示装置。 - 前記画素回路には、第2構造のトランジスタが含まれ、
前記第2構造のトランジスタの半導体層は、第2チャネル領域と、前記第2チャネル領域の一方側に隣接する第3ドープ領域と、前記第2チャネル領域の他方側に隣接する第4ドープ領域とを含み、
前記第3ドープ領域が、前記第2チャネル領域に隣接し、不純物が低濃度にドープされた低濃度領域と、当該低濃度領域に隣接し、不純物が高濃度にドープされた高濃度領域とで構成され、
前記第4ドープ領域が、前記第2チャネル領域に隣接し、不純物が低濃度にドープされた低濃度領域と、当該低濃度領域に隣接し、不純物が高濃度にドープされた高濃度領域とで構成されている請求項1に記載の表示装置。 - 前記画素回路には、前記第2構造のトランジスタであり、自段の走査信号線と前記駆動トランジスタのゲート電極とに接続する閾値制御トランジスタが含まれる請求項2に記載の表示装置。
- 前記画素回路には、前記閾値制御トランジスタに直列に接続する前記第2構造のトランジスタが含まれる請求項3に記載の表示装置。
- 前記画素回路には、前記第2構造のトランジスタであり、自段よりも前の段の走査信号線と初期化信号線とに接続するリセットトランジスタが含まれる請求項2に記載の表示装置。
- 前記画素回路には、前記リセットトランジスタに直列に接続する前記第2構造のトランジスタが含まれる請求項5に記載の表示装置。
- 前記画素回路には、第3構造のトランジスタが含まれ、
前記第3構造のトランジスタの半導体層は、第3チャネル領域と、前記第3チャネル領域の一方側に隣接する第5ドープ領域と、前記第3チャネル領域の他方側に隣接する第6ドープ領域とを含み、
前記第5ドープ領域および前記第6ドープ領域それぞれが、不純物が高濃度にドープされた高濃度領域で構成されている請求項1~6のいずれか1項に記載の表示装置。 - 前記第1ドープ領域は、前記第3構造のトランジスタである電源制御トランジスタを介して電源に接続される請求項7に記載の表示装置。
- 前記第2ドープ領域は、前記第3構造のトランジスタである発光制御トランジスタを介して前記発光素子に接続される請求項7に記載の表示装置。
- 前記第1ドープ領域は、前記第3構造のトランジスタである書き込み制御トランジスタを介してデータ信号線に接続される請求項7に記載の表示装置。
- 前記発光素子のアノードは、前記第3構造のトランジスタである初期化トランジスタを介して初期化信号線に接続される請求項7に記載の表示装置。
- 前記第1構造のトランジスタのゲート電極と、前記第1チャネル領域とが整合する請求項1~11のいずれか1項に記載の表示装置。
- 前記第1構造のトランジスタはトップゲート型である請求項1~12のいずれか1項に記載の表示装置。
- 前記第1構造のトランジスタはPチャネル型であり、
前記第1ドープ領域はソース領域、前記第2ドープ領域はドレイン領域である請求項1~13のいずれか1項に記載の表示装置。 - 前記半導体層が結晶性シリコンを含む請求項1~14のいずれか1項に記載の表示装置。
- 半導体層およびゲート電極を含む第1構造のトランジスタを備える表示装置の製造方法であって、
前記半導体層を形成する第1工程と、
前記ゲート電極を形成する第2工程と、
前記ゲート電極を遮蔽体とし、前記半導体層におけるゲート電極と重畳しない領域に対して、低濃度で不純物をドープする第3工程と、
前記ゲート電極に重畳する第1部分と、前記ゲート電極の両サイドのいずれか1つに重畳する第2部分とを有するマスクを用い、前記マスクおよび前記ゲート電極を遮蔽体として、前記半導体層における前記マスクおよび前記ゲート電極のいずれにも重畳しない領域に対して、前記低濃度よりも高い濃度で不純物をドープする第4工程と、を含む表示装置の製造方法。 - 前記第1工程および前記第2工程の間に、金属層であるゲート層を形成し、前記ゲート層を遮蔽体とし、前記半導体層におけるゲート層と重畳しない領域に対して、前記低濃度よりも高い濃度で不純物をドープする工程を行い、
前記第2工程では、前記ゲート層をエッチングによって細らせて上記ゲート電極とする請求項16に記載の表示装置の製造方法。 - 前記半導体層に、前記ゲート電極と重畳する第1チャネル領域と、前記第1チャネル領域の一方側に隣接する第1ドープ領域と、前記第1チャネル領域の他方側に隣接する第2ドープ領域とを含み、
前記第1ドープ領域は、不純物が高濃度にドープされた高濃度領域で構成され、
前記第2ドープ領域は、前記マスクの第2部分に対応し、不純物が低濃度にドープされた低濃度領域と、当該低濃度領域に隣接し、不純物が高濃度にドープされた高濃度領域とで構成されている請求項16に記載の表示装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2020/040839 WO2022091348A1 (ja) | 2020-10-30 | 2020-10-30 | 表示装置および表示装置の製造方法 |
US18/034,343 US20240306425A1 (en) | 2020-10-30 | 2020-10-30 | Display device and method for manufacturing display device |
JP2022558755A JP7492600B2 (ja) | 2020-10-30 | 2020-10-30 | 表示装置および表示装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2020/040839 WO2022091348A1 (ja) | 2020-10-30 | 2020-10-30 | 表示装置および表示装置の製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2022091348A1 true WO2022091348A1 (ja) | 2022-05-05 |
Family
ID=81382119
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2020/040839 WO2022091348A1 (ja) | 2020-10-30 | 2020-10-30 | 表示装置および表示装置の製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20240306425A1 (ja) |
JP (1) | JP7492600B2 (ja) |
WO (1) | WO2022091348A1 (ja) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006269808A (ja) * | 2005-03-24 | 2006-10-05 | Mitsubishi Electric Corp | 半導体装置および画像表示装置 |
JP2010113151A (ja) * | 2008-11-06 | 2010-05-20 | Hitachi Displays Ltd | 表示装置 |
WO2012160800A1 (ja) * | 2011-05-24 | 2012-11-29 | シャープ株式会社 | 半導体装置の製造方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105679250B (zh) | 2016-04-06 | 2019-01-18 | 京东方科技集团股份有限公司 | 一种像素电路及其驱动方法、阵列基板、显示面板和显示装置 |
CN111490068B (zh) | 2019-01-29 | 2022-07-26 | 京东方科技集团股份有限公司 | 显示面板及其制造方法、显示装置 |
-
2020
- 2020-10-30 WO PCT/JP2020/040839 patent/WO2022091348A1/ja active Application Filing
- 2020-10-30 JP JP2022558755A patent/JP7492600B2/ja active Active
- 2020-10-30 US US18/034,343 patent/US20240306425A1/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006269808A (ja) * | 2005-03-24 | 2006-10-05 | Mitsubishi Electric Corp | 半導体装置および画像表示装置 |
JP2010113151A (ja) * | 2008-11-06 | 2010-05-20 | Hitachi Displays Ltd | 表示装置 |
WO2012160800A1 (ja) * | 2011-05-24 | 2012-11-29 | シャープ株式会社 | 半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JPWO2022091348A1 (ja) | 2022-05-05 |
JP7492600B2 (ja) | 2024-05-29 |
US20240306425A1 (en) | 2024-09-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4490885B2 (ja) | エレクトロルミネセンス表示装置及びその製造方法 | |
JP4058440B2 (ja) | 有機電界発光表示装置およびその製造方法 | |
US6762564B2 (en) | Display apparatus | |
JP5595392B2 (ja) | El表示パネル、el表示装置及びel表示パネルの製造方法 | |
KR101671038B1 (ko) | 박막 트랜지스터 어레이 장치, 박막 트랜지스터 어레이 장치의 제조 방법 | |
JP2001109404A (ja) | El表示装置 | |
KR101685716B1 (ko) | 박막 트랜지스터 어레이 장치, 박막 트랜지스터 어레이 장치의 제조 방법 | |
JP2001100654A (ja) | El表示装置 | |
US20210351263A1 (en) | Display device | |
WO2019187139A1 (ja) | 表示デバイス | |
JP2001100655A (ja) | El表示装置 | |
WO2020217478A1 (ja) | 表示装置 | |
US8426859B2 (en) | Semiconductor device and light-emitting device using the same | |
WO2021240584A1 (ja) | 表示装置および表示装置の製造方法 | |
WO2019224917A1 (ja) | 表示装置 | |
WO2020213102A1 (ja) | 表示装置 | |
WO2020217477A1 (ja) | 表示装置 | |
KR102037487B1 (ko) | 유기전계 발광소자의 제조 방법 및 그 방법에 의해 제조된 유기전계 발광소자 | |
WO2022091348A1 (ja) | 表示装置および表示装置の製造方法 | |
WO2020217479A1 (ja) | 表示装置 | |
JP2001100663A (ja) | El表示装置 | |
WO2020208704A1 (ja) | 表示装置および製造方法 | |
WO2021053792A1 (ja) | 表示装置 | |
JP2022077412A (ja) | 薄膜トランジスタ回路 | |
WO2022168146A1 (ja) | 表示装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 20959866 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 2022558755 Country of ref document: JP Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 18034343 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 20959866 Country of ref document: EP Kind code of ref document: A1 |