WO2022089085A1 - 振荡器及时钟产生电路 - Google Patents

振荡器及时钟产生电路 Download PDF

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Publication number
WO2022089085A1
WO2022089085A1 PCT/CN2021/118858 CN2021118858W WO2022089085A1 WO 2022089085 A1 WO2022089085 A1 WO 2022089085A1 CN 2021118858 W CN2021118858 W CN 2021118858W WO 2022089085 A1 WO2022089085 A1 WO 2022089085A1
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Prior art keywords
inverter
oscillator
transmission speed
pull
nmos
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PCT/CN2021/118858
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English (en)
French (fr)
Inventor
汪玉霞
田凯
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Publication of WO2022089085A1 publication Critical patent/WO2022089085A1/zh
Priority to US17/812,813 priority Critical patent/US11855636B2/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/011—Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/017—Adjustment of width or dutycycle of pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/354—Astable circuits
    • H03K3/3545—Stabilisation of output, e.g. using crystal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L1/00—Stabilisation of generator output against variations of physical values, e.g. power supply
    • H03L1/02—Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L5/00—Automatic control of voltage, current, or power

Definitions

  • the embodiments of the present application relate to, but are not limited to, an oscillator and a clock generating circuit.
  • DRAM Dynamic Random Access Memory
  • a high-speed clock signal of a specific frequency is required for reading and writing and clock calibration.
  • a high-speed clock signal can be generated inside the DRAM through a ring oscillator to meet the above requirements.
  • the frequency of the oscillating signal generated by the current ring oscillator is low, and it is difficult to meet the high-speed demand; in addition, the frequency and duty cycle of the oscillating signal generated by the current ring oscillator are easily affected by the process, power supply voltage, temperature, clock load, etc. influence, thereby causing deviations in clock frequency and duty cycle.
  • An embodiment of the present application provides an oscillator, including: a first ring topology, which is connected end-to-end by a plurality of first inverters, and propagates an oscillating signal at a first transmission speed; a second ring topology, which is composed of a plurality of second inverters The phasers are connected end to end to propagate the oscillation signal at a second transmission speed; wherein the first ring topology is electrically connected to the second ring topology, and the second transmission speed is lower than the first transmission speed.
  • An embodiment of the present application further provides a clock generation circuit, including: the oscillator according to any one of the above; a frequency adjustment module, connected to the oscillator, and configured to adjust the frequency of the oscillator.
  • FIG. 1 is a schematic diagram of a circuit structure of an oscillator provided by an embodiment of the present application
  • FIG. 2 is a schematic diagram of another circuit structure of an oscillator provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a buffered inverter in the oscillator shown in FIG. 2;
  • FIG. 4 is a schematic structural diagram of a first inverter in the oscillator shown in FIG. 2;
  • FIG. 5 is a schematic structural diagram of a second inverter in the oscillator shown in FIG. 2;
  • Fig. 6 is another structural schematic diagram of the first inverter in the oscillator shown in Fig. 2;
  • Fig. 7 is another structural schematic diagram of the second inverter in the oscillator shown in Fig. 2;
  • FIG. 8 is a schematic structural diagram of a clock generation circuit provided by an embodiment of the present application.
  • FIG. 1 is a schematic diagram of a circuit structure of an oscillator provided by an embodiment of the present application.
  • the oscillator includes: a first ring topology, which is connected end-to-end by a plurality of first inverters 11 to propagate an oscillating signal at a first transmission speed; a second ring topology, which consists of a plurality of second inverters 12 Connected end to end, the oscillating signal is propagated at a second transmission speed; wherein, the first ring topology is electrically connected with the second ring topology, and the second transmission speed is lower than the first transmission speed.
  • the transmission speed refers to the time from the high level to the low level of the oscillation signal or the time from the low level to the high level.
  • the slower the transmission speed the longer the transmission time, the slower the oscillating signal flips, the longer the period of the oscillating signal, and the lower the frequency.
  • the faster the transmission speed the shorter the transmission time, the faster the oscillating signal flips, the shorter the period of the oscillating signal, and the higher the frequency.
  • the second transmission speed being smaller than the first transmission speed means that the transmission time of the oscillation signal through the second inverter 12 is shorter than the transmission time of the oscillation signal through the first inverter 11 .
  • the number of the first inverters 11 is N, and N is an integer greater than or equal to 4; correspondingly, the number of the second inverters 12 is M, and M is an integer greater than or equal to 2 .
  • each first inverter 11 Denotes the input end of each first inverter 11 as a first node, and the first ring topology has N first nodes, for example, the first nodes are clk360, clk270, clk180, and clk90 in FIG. 1; denote each The input end of the second inverter 12 is a second node, and the second ring topology has M second nodes, for example, the second nodes are clk360', clk180' in FIG. 1; at least two second nodes are connected to A corresponding number of first nodes are electrically connected, for example, clk360 ′ in FIG. 1 is connected to clk360 , and clk180 ′ is connected to clk180 .
  • each first node has a different phase.
  • the four first nodes on the oscillation path have a first phase respectively.
  • clk90, the second phase clk180, the third phase clk270 and the fourth phase clk360 the four first nodes form a 360-degree oscillation cycle, that is, each first node corresponds to a 90-degree phase shift; accordingly, the second ring topology
  • the structure has two second nodes, one second node clk180 ′ is electrically connected to the first node having the second phase clk180 , and the other second node clk360 ′ is electrically connected to the first node having the fourth phase clk360 .
  • the second transmission speed is less than the first transmission speed, and the second transmission speed is greater than or equal to 0.5 times the first transmission speed.
  • the transmission speed can be understood as being inversely proportional to the transmission delay of the inverter. For example, assuming that the transmission speed of the oscillating signal passing through the first inverter 11 is 100, then the transmission speed of the oscillating signal passing through the second inverter 12 is greater than or equal to 50 and less than 100. For another example, assuming that the propagation delay of the oscillating signal passing through the first inverter 11 is 100 ps (picoseconds), then the propagation delay of the oscillating signal passing through the second inverter 12 is greater than 100 ps and less than or equal to 200 ps. With this arrangement, the stability of the oscillator and the quality of the oscillating signal can be improved.
  • the oscillator may further include: a third ring topology, which is connected end-to-end by a plurality of third inverters 13 , and transmits the oscillation signal at a third transmission speed, the first ring topology is connected with the first ring topology.
  • the three ring topology structures are electrically connected, and the third transmission speed is lower than the first transmission speed.
  • the first ring topology is used as the outer ring topology
  • the second ring topology and the third ring topology are used as the inner ring topology.
  • the number of inverters with different ring topologies can be specifically as follows: the number of the first inverters 11 is U, where U is an integer greater than or equal to 4; the number of the second inverters 12 is V, and V is greater than or equal to 4. is an integer equal to 2; the number of the third inverters 13 is W, and W is an integer greater than or equal to 2.
  • each first inverter 11 Denotes the input end of each first inverter 11 as a first node, and the first ring topology has U first nodes, for example, the first nodes are clk360, clk270, clk180, clk90 in FIG. 2; denote each The input end of the second inverter 12 is a second node, and the second ring topology has V second nodes, for example, the second nodes are clk360', clk180' in FIG. 2; denote each third inverter
  • the input terminal of 13 is a third node, and the third ring topology has W third nodes, for example, the second nodes are clk270', clk90' in Fig.
  • One node is electrically connected, and at least two third nodes are electrically connected to a corresponding number of first nodes, for example, clk360' is connected to clk360, clk270' is connected to clk270, clk180' is connected to clk180, and clk90' is connected to clk90 in Fig. 2 connected.
  • the oscillating signals of different first nodes have more inversion times per unit time, thereby increasing the frequency of the propagating oscillating signals, thereby increasing the transmission speed of the oscillating signals.
  • the second transmission speed is less than the first transmission speed, and the second transmission speed is greater than or equal to 0.5 times the first transmission speed, and the third transmission speed is equal to the second transmission speed.
  • the transmission speed can be understood as being inversely proportional to the transmission delay of the inverter. For example, assuming that the transmission speed of the oscillating signal passing through the first inverter 11 is 100, then the transmission speed of the oscillating signal passing through the second inverter 12 is greater than or equal to 50 and less than 100.
  • the propagation delay of the oscillating signal passing through the first inverter 11 is 100 ps (picoseconds)
  • the propagation delay of the oscillating signal passing through the second inverter 12 is greater than 100 ps and less than or equal to 200 ps.
  • the oscillator further includes a buffered inverter 14, an input terminal of the buffered inverter 14 receives the oscillating signal, and an output terminal of the buffered inverter 14 outputs a clock signal.
  • the buffer inverter 14 is used to isolate the back-end circuit of the oscillator (eg, the duty cycle calibration circuit) as a load from the influence on the frequency of the oscillating signal, so that the oscillator maintains a high multiplexing rate.
  • the transfer speed of the buffered inverter 14 is adjustable. Exemplarily, by adjusting the pull-up capability and/or pull-down capability of the buffered inverter 14, the transmission speed of the buffered inverter 14 can be adjusted.
  • the pull-down capability of the buffer inverter 14 is weakened; when the pull-up capability of the buffer inverter 14 is weakened, the pull-down capability of the buffer inverter 14 is enhanced.
  • Pull-up capability refers to the ability to charge a low-level signal to a high-level signal
  • pull-down capability refers to the ability to discharge a high-level signal to a low-level signal.
  • a buffer inverter 14 can be connected to each first node, or a buffer inverter 14 can be connected in series between each first node and the back-end circuit to avoid the back-end circuit
  • the influence caused by the frequency of the oscillating signal ensures that each stage of the first inverter 11 of the oscillator has a high degree of load matching, thereby making the frequency of the oscillating signal of the oscillator more stable.
  • clk360 , clk270 , clk180 , and clk90 are all connected to a buffered inverter 14 .
  • the buffer inverter 14 includes: a first PMOS group 141 , including H PMOSs (MPH1 , MPH2 . . . MPHn), the sources of the H PMOSs are all connected to the power supply terminal Vcc; 142, including H NMOSs (MNH1, MNH2...MNHn), the sources of the H NMOSs are connected to the ground terminal Vss; the zeroth PMOS MPH0, the sources of which are connected to the drains of the H PMOSs; the zeroth NMOS MNH0, its sources The drains of the H NMOSs are connected; the drain of the zeroth PMOS MPH0 is connected to the drain of the zeroth NMOS MNH0 as the output end clkout of the buffer inverter 14; the gate of the zeroth PMOS MPH0 is connected to the gate of the zeroth NMOS MNH0
  • the poles are connected to each other and serve as the input terminal clkin of the buffer in
  • the duty cycle adjustment code group can be sent by a duty cycle adjustment module (not shown), and both the PMOS and the PMOS transistor are PMOS transistors.
  • the on-number of PMOS transistors in the first PMOS group 141 and/or the on-number of NMOS transistors in the first NMOS group 142 can be controlled by controlling the duty cycle to adjust the parameters of the encoding group, so as to adjust the buffer inversion.
  • the pull-up capability and/or pull-down capability of the phase converter 14 can be controlled by controlling the duty cycle to adjust the parameters of the encoding group, so as to adjust the buffer inversion.
  • the turn-on voltages of the PMOS transistor and the NMOS transistor are different.
  • the first adjustment code Dcc1 in the duty cycle adjustment code group is at a high level
  • the first NMOS transistor MNH1 is turned on and the first PMOS transistor MPH1 is turned off
  • the first adjustment code Dcc1 is at a low level
  • the first NMOS transistor MNH1 is turned on.
  • An NMOS transistor MNH1 is turned off and the first PMOS transistor MPH1 is turned on.
  • a duty ratio adjustment code controls the first PMOS group 141 and the first NMOS group 142 at the same time, the more the number of PMOS transistors in the first PMOS group 141 is turned on, the more the number of NMOS transistors in the first NMOS group 142 is turned on. less. And the more the number of PMOS transistors in the first PMOS group 141 is turned on, the smaller the load value of the first PMOS group 141 is, the faster the charging rate of the buffer inverter 14 is, and the higher the pull-up capability of the buffer inverter 14 is.
  • the pull-up capability of the buffer inverter 14 is weakened and the pull-down capability is enhanced, and the duty cycle of the clock signal output by the buffer inverter 14 is increased. decrease.
  • an initial PMOS transistor MPHs and an initial NMOS transistor MNHs are also provided.
  • the source of the initial PMOS transistor MPHs is connected to the power supply terminal Vcc, and the drain is connected to the zeroth PMOSMPH0 source and gate.
  • the first transmission speed of the first inverter 11 is adjustable.
  • the first transmission speed of the first inverter 11 can be adjusted by adjusting the pull-up capability and/or pull-down capability of the first inverter 11 .
  • the pull-up capability of the first inverter 11 when the pull-up capability of the first inverter 11 is enhanced, the pull-down capability of the first inverter 11 is enhanced; when the pull-up capability of the first inverter 11 is weakened, the pull-down capability of the first inverter 11 weaken. In this way, the frequency of the oscillating signal output by the oscillator can be adjusted to obtain an oscillating signal that meets the preset frequency requirement.
  • the first inverter 11 includes: a third PMOS group 111, including I PMOS (MPI1, MPI2 . . . MPIn), the sources of the I PMOSs are all connected to the power supply terminal Vcc; the third NMOS The group 112 includes 1 NMOS (MNI1, MNI2...MNIn), the source of the 1 NMOS is connected to the ground terminal Vss; the second PMOS MPI0, the source of which is connected to the drain of the 1 PMOS; the second NMOS MNI0, whose source The electrode is connected to the drain of 1 NMOS; the drain of the second PMOS MPI0 is connected to the drain of the second NMOS MNI0 as the output end of the first inverter 11; the gate of the second PMOS MPI0 is connected to the drain of the second NMOS MNI0 The gate is connected as the input end of the first inverter 11; the gates of one PMOS tube are controlled by the first inverse adjustment code group (enb11, enb12...enb
  • the turn-on number of PMOS transistors in the third PMOS group 111 can be controlled by controlling the parameters of the first inverse adjustment code group, so as to adjust the pull-up capability of the first inverter 11; and/or, by controlling The parameters of the first positive adjustment coding group control the conduction quantity of the NMOS transistors in the third NMOS group 112 , thereby adjusting the pull-down capability of the first inverter 11 .
  • the potentials of the first inverse adjustment code group and the first positive adjustment code group are opposite, that is, in opposite phases.
  • the first positive adjustment code en11 is at a high level
  • the first reverse adjustment code enb11 is at a low level
  • the first PMOS transistor MPI1 in the third PMOS group 111 is turned on
  • the first NMOS transistor MNI1 in the third NMOS group 112 is turned on.
  • the first positive adjustment code en11 is at a low level
  • the first reverse adjustment code enb11 is at a high level.
  • the first PMOS transistor MPI1 in the third PMOS group 111 is turned off
  • the third NMOS group 112 The first NMOS transistor MNI1 is turned off.
  • the frequency of the oscillating signal output by the first inverter 11 increases; accordingly, the smaller the number of conduction of the PMOS transistors in the third PMOS group 111, the less the number of conduction of the NMOS transistors in the third NMOS group 112,
  • the pull-up capability and pull-down capability of the first inverter 11 are weakened, and the frequency of the oscillation signal output by the first inverter 11 is reduced.
  • the first inverter 11 has an initial PMOS transistor MPIs for ensuring that the second PMOS MNI0 is in a working state, and an initial NMOS transistor MNIs for ensuring that the second NMOS MNI0 is in a working state.
  • the first transmission speed of the second inverter 12 is adjustable.
  • the first transmission speed of the second inverter 12 can be adjusted by adjusting the pull-up capability and/or pull-down capability of the second inverter 12 .
  • the pull-down capability of the second inverter 12 is enhanced; when the pull-up capability of the second inverter 12 is weakened, the pull-down capability of the second inverter 12 is weakened .
  • the second inverter 12 includes: a fifth PMOS group 121, including L PMOSs (MPL1, MPL2 . . . MPLn), the sources of the L PMOSs are all connected to the power supply terminal Vcc; the fifth NMOS
  • the group 122 includes L NMOSs (MNL1, MNL2...MNLn), the sources of the L NMOSs are connected to the ground terminal Vss; the fourth PMOSMPL0, the sources of which are connected to the drains of the L PMOSs; the fourth NMOSMNL0, the sources of which are connected to the ground terminal Vss
  • the drains of the L NMOSs; the drain of the fourth PMOS MPL0 is connected to the drain of the fourth NMOS MNL0 as the output terminal of the second inverter 12; the gate of the fourth PMOS MPL0 is connected to the gate of the fourth NMOS MNL0 connected as the input terminal of the second inverter 12; the gates of the L PMOS transistors are controlled by the second
  • the turn-on number of PMOS transistors in the fifth PMOS group 121 can be controlled by controlling the parameters of the second inverse adjustment code group, so as to adjust the pull-up capability of the second inverter 12; and/or, by controlling The parameters of the second positive adjustment coding group control the conduction number of NMOS transistors in the fifth NMOS group 122 , thereby adjusting the pull-down capability of the second inverter 12 .
  • the potentials of the second negative regulation coding group and the second positive regulating coding group are opposite.
  • the second positive adjustment code en21 is at a high level, and the second reverse adjustment code enb21 is at a low level, at this time, the first PMOS transistor MPL1 in the fifth PMOS group 121 is turned on, and the first NMOS transistor MNL1 in the fifth NMOS group 122 is turned on.
  • the second positive adjustment code en21 is low level
  • the second reverse adjustment code enb21 is high level, at this time, the first PMOS transistor MPL1 in the fifth PMOS group 121 is turned off, and the fifth NMOS group 122 The first NMOS transistor MNL1 is turned off.
  • the frequency of the oscillating signal output by the second inverter 12 increases; correspondingly, the smaller the number of conduction of the PMOS transistors in the fifth PMOS group 121, the less the number of conduction of the NMOS transistors in the fifth NMOS group 122, The pull-up capability and pull-down capability of the second inverter 12 are weakened, and the frequency of the oscillation signal output by the second inverter 12 is reduced.
  • the second inverter 12 has an initial PMOS transistor MPLs for ensuring that the fourth PMOS MPL0 is in an operating state, and an initial NMOS transistor MNLs for ensuring that the fourth NMOS MNL0 is in an operating state.
  • the first inverter 11 includes a plurality of first sub-inverters 113 , the input terminals of the plurality of first sub-inverters 113 are all electrically connected, and the plurality of first sub-inverters The output terminals of the device 113 are all electrically connected.
  • Each key node has a high load matching degree, which makes the delay of each stage of inverters equal; in addition, it is also beneficial to make the length of the connection between other components and the first sub-inverter 113 shorter, thereby reducing the The parasitic resistance and parasitic capacitance of the small wiring make the oscillator have good performance.
  • the number of the first sub-inverters 113 is an even number, which is beneficial to better design of symmetrical balance of the layout.
  • the second inverter 12 includes a plurality of second sub-inverters 123 , the input ends of the plurality of second sub-inverters 123 are all electrically connected, and the plurality of second sub-inverters The output terminals of the device 123 are all electrically connected. In this way, it is beneficial to improve the symmetrical balance of the oscillator layout.
  • the number of the second sub-inverters 123 is equal to the number of the first sub-inverters 113 . In this way, it is beneficial to improve the symmetrical balance of the oscillator layout, thereby obtaining an oscillator with better performance.
  • the first inverter 11 and the second inverter 12 can be set to the same structure and size, and then pass the first reverse adjustment code group and/or the second positive adjustment code
  • the group, the second inverse adjustment code group, and/or the second positive adjustment code group realize the difference in transmission rate.
  • the setting of the second ring topology can increase the number of inversions of the oscillation signal of the electrically connected nodes per unit time, thereby obtaining the high-speed oscillation signal.
  • FIG. 8 is a schematic structural diagram of a clock generation circuit provided by an embodiment of the present application.
  • the clock generation circuit will be described in detail below with reference to the accompanying drawings. For the same or corresponding parts as those of the foregoing embodiments, reference may be made to the descriptions of the foregoing embodiments, which will not be repeated below.
  • the clock generating circuit includes: an oscillator 20 ; a frequency adjustment module 21 , connected to the oscillator 20 , for adjusting the frequency of the oscillator 20 .
  • the frequency adjustment module 21 adjusts the frequency of the oscillation signal of the oscillator 20 by adjusting the first transmission speed and/or the second transmission speed.
  • the frequency adjustment module 21 can adjust the frequency of the oscillation signal of the oscillator 20 by adjusting the first transmission speed and the second transmission speed.
  • the frequency adjustment module 21 adjusts the first transmission speed of the first inverter 11 and the second transmission speed of the second inverter 12 to adjust the frequency of the oscillating signal of the oscillator 20, or the frequency adjustment module 21 can also adjust the frequency of the oscillating signal by adjusting the One of the transmission speed or the second transmission speed is used to adjust the frequency of the oscillation signal of the oscillator.
  • the frequency adjustment module 21 adjusts the first transmission speed of the first inverter 11 to adjust the frequency of the oscillation signal of the oscillator 20.
  • frequency, or the frequency adjustment module 21 adjusts the second transmission speed of the second inverter 12 to adjust the frequency of the oscillation signal of the oscillator 20 .
  • the frequency adjustment module 21 adjusts both the first transmission speed and the second transmission speed as an example.
  • the frequency adjustment module 21 is connected to the first inverter 11 and the second inverter 12.
  • the frequency adjustment module 21 can change the pull-up capability of the first inverter 11 by adjusting the first inverse adjustment code group, and adjust the The first positive adjustment code group changes the pull-down capability of the first inverter 11 , thereby adjusting the first transmission speed of the first inverter 11 , thereby adjusting the frequency of the oscillator 20 oscillating signal.
  • the frequency adjustment module 21 can change the pull-up capability of the second inverter 12 by adjusting the second inverse adjustment code group, and change the pull-down capability of the second inverter 12 by adjusting the second positive adjustment code group, thereby adjusting The second transmission speed of the second inverter 12, thereby adjusting the frequency of the oscillation signal of the oscillator 20.
  • the frequency adjustment module can be connected with the first inverter or the second inverter, and can only change the pull-up capability or pull-down capability of the first inverter, or only change the second inverter pull-up or pull-down capability.
  • the clock generation circuit further includes a duty cycle adjustment module 22 connected to the oscillator 20 for adjusting the duty cycle of the oscillating signal.
  • the oscillator 20 includes a buffered inverter 14, which is used for receiving the oscillation signal and outputting a clock signal.
  • the duty cycle adjustment module 22 is connected to the buffer inverter 14, and the duty cycle adjustment module 22 adjusts the duty cycle by adjusting the duty cycle.
  • the parameters of the duty ratio adjustment coding group adjust the pull-up capability and pull-down capability of the buffer inverter 14, so that the pull-up capability and pull-down capability of the buffer inverter 14 change to different regions, so as to realize the effect of adjusting the duty cycle of the clock signal .
  • the duty cycle adjustment module may also be connected to the first inverter and/or the second inverter to adjust the duty cycle of the oscillating signal output by the first inverter and/or the second inverter ratio, so that the oscillating signal output by the oscillator has a preset duty cycle requirement.
  • the clock generation circuit can reduce the influence of the clock load on the frequency and duty cycle of the high-speed clock signal, thereby outputting a clock signal that meets the preset frequency requirement and the preset duty cycle requirement.

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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Logic Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

提供一种振荡器及时钟产生电路，振荡器包括：第一环形拓扑结构，由多个第一反相器（11）首尾相连，以第一传输速度传播振荡信号；第二环形拓扑结构，由多个第二反相器（12）首尾相连，以第二传输速度传播申请振荡信号；其中，第一环形拓扑结构与第二环形拓扑结构电连接，第二传输速度小于第一传输速度。

Description

振荡器及时钟产生电路
交叉引用
本申请要求于2020年10月28日递交的名称为“振荡器及时钟产生电路”、申请号为202011173760.4的中国专利申请的优先权，其通过引用被全部并入本申请。
技术领域
本申请实施例涉及但不限于一种振荡器及时钟产生电路。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。在DRAM I/O电路中，需要一个特定频率的高速时钟信号进行读写及时钟校准。
可以通过环形振荡器(ring oscillator)在DRAM内部产生一个高速时钟信号，以满足上述需求。但是当前的环形振荡器所产生的振荡信号频率较低，难以满足高速需求；此外，当前环形振荡器所产生的振荡信号的频率和占空比容易受到工艺、电源电压、温度、时钟负载等的影响，从而使得时钟频率和占空比产生偏差。
申请内容
本申请实施例提供一种振荡器，包括：第一环形拓扑结构，由多个第一反相器首尾相连，以第一传输速度传播振荡信号；第二环形拓扑结构，由多个第二反相器首尾相连，以第二传输速度传播所述振荡信号；其中，所述第一环形拓扑结构与所述第二环形拓扑结构电连接，所述第二传输速度小于所述第一传输速度。
本申请实施例还提供一种时钟产生电路，包括：上述任一项所述的振荡器；频率调节模块，与所述振荡器连接，用于调节所述振荡器的频率。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些 示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1为本申请实施例提供的振荡器的一电路结构示意图；
图2为本申请实施例提供的振荡器的另一电路结构示意图；
图3为图2所示振荡器中缓冲反相器的结构示意图；
图4为图2所示振荡器中第一反相器的一结构示意图；
图5为图2所示振荡器中第二反相器的一结构示意图；
图6为图2所示振荡器中第一反相器的又一结构示意图；
图7为图2所述振荡器中第二反相器的又一结构示意图；
图8为本申请实施例提供的时钟产生电路的结构示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图1为本申请实施例提供的振荡器的一电路结构示意图。
参考图1，振荡器包括：第一环形拓扑结构，由多个第一反相器11首尾相连，以第一传输速度传播振荡信号；第二环形拓扑结构，由多个第二反相器12首尾相连，以第二传输速度传播振荡信号；其中，第一环形拓扑结构与第二环形拓扑结构电连接，第二传输速度小于第一传输速度。
其中，传输速度指的是振荡信号从高电平到低电平的时间或者从低电平到高电平的时间。传输速度越慢，传输时间越长，振荡信号翻转的越慢，振荡信号的周期就越长，频率就越低。传输速度越快，传输时间越短，振荡信号翻转的越快，振荡信号的周期就越短，频率就越高。第二传输速度小于第一传输速度意味着振荡信号经过第二反相器12的传输时间比振荡信号经过第一反相器11的传输时间短。
在一些实施例中，第一反相器11的个数为N个，N为大于等于4的整数；相应地，第二反相器12的个数为M个，M为大于等于2的整数。
记每一个第一反相器11的输入端为一个第一节点，第一环形拓扑结构具有N个第一节点，例如第一节点为图1中的clk360、clk270、clk180、clk90；记每一个第二反相器12的输入端为一个第二节点，第二环形拓扑结构具有M个第二节点，例如第二节点为图1中的clk360’、clk180’；至少有两个第二节点与对应个数的第一节点电连接，例如图1中的clk360’与clk360相连、clk180’与clk180相连。
其中，在第一环形拓扑结构的振荡路径上，每一第一节点具有不同的相位，以4个第一反相器11的数量为例，振荡路径上四个第一节点分别具有第一相位clk90、第二相位clk180、第三相位clk270以及第四相位clk360，四个第一节点构成一个360度的振荡循环，即每一第一节点对应90度的相位位移；相应地，第二环形拓扑结构具有两个第二节点，一第二节点clk180’与具有第二相位clk180的第一节点电连接，另一第二节点clk360’与具有第四相位clk360的第一节点电连接。
在一些实施例中，第二传输速度小于第一传输速度，且第二传输速度大于等于0.5倍的第一传输速度。传输速度可以理解为与反相器的传输延迟成反比。例如，假设振荡信号经过第一反相器11的传输速度为100，那么振荡信号经过第二反相器12的传输速度则为大于等于50且小于100。再例如，假设振荡信号经过第一反相器11的传输延迟为100ps(皮秒)，那么振荡信号经过第二反相器12的传输延迟则大于100ps且小于等于200ps。如此设置，可以提高振荡器的稳定性和振荡信号的质量。
在一些实施例中，参考图2，振荡器还可以包括：第三环形拓扑结构，由多个第三反相器13首尾相连，以第三传输速度传输振荡信号，第一环形拓扑结构与第三环形拓扑结构电连接，第三传输速度小于第一传输速度。
其中，第一环形拓扑结构作为外圈拓扑结构，第二环形拓扑结构和第三环形拓扑结构作为内圈拓扑结构。不同环形拓扑结构的反相器数量可具体如下：第一反相器11的个数为U个，U为大于等于4的整数；第二反相器12的个数为V个，V为大于等于2的整数；第三反相器13的个数为W个，W为大于等 于2的整数。
记每一个第一反相器11的输入端为一个第一节点，第一环形拓扑结构具有U个第一节点，例如第一节点为图2中的clk360、clk270、clk180、clk90；记每一个第二反相器12的输入端为一个第二节点，第二环形拓扑结构具有V个第二节点，例如第二节点为图2中的clk360’、clk180’；记每一个第三反相器13的输入端为一个第三节点，第三环形拓扑结构具有W个第三节点，例如第二节点为图2中的clk270’、clk90’；至少有两个第二节点与对应个数的第一节点电连接，至少有两个第三节点与对应个数的第一节点电连接，例如图2中的clk360’与clk360相连、clk270’与clk270相连、clk180’与clk180相连、clk90’与clk90相连。如此，有利于使得不同第一节点的振荡信号在单位时间内均具有更多的翻转次数，进而提升传播的振荡信号的频率，从而提升振荡信号的传输速度。
在一些实施例中，第二传输速度小于第一传输速度，且第二传输速度大于等于0.5倍的第一传输速度，第三传输速度等于第二传输速度。传输速度可以理解为与反相器的传输延迟成反比。例如，假设振荡信号经过第一反相器11的传输速度为100，那么振荡信号经过第二反相器12的传输速度则为大于等于50且小于100。再例如，假设振荡信号经过第一反相器11的传输延迟为100ps(皮秒)，那么振荡信号经过第二反相器12的传输延迟则大于100ps且小于等于200ps。如此设置，可以提高振荡器的稳定性和振荡信号的质量。
在一些实施例中，振荡器还包括缓冲反相器14，缓冲反相器14的输入端接收振荡信号，缓冲反相器14的输出端输出时钟信号。缓冲反相器14用于隔绝振荡器的后端电路(例如占空比校准电路)作为负载对振荡信号频率造成的影响，使振荡器保持较高的复用率。
在一些实施例中，缓冲反相器14的传输速度可调。示例性地，通过调节缓冲反相器14的上拉能力和/或下拉能力来实现缓冲反相器14的传输速度可调。
其中，当缓冲反相器14的上拉能力增强时，缓冲反相器14的下拉能力减弱；当缓冲反相器14的上拉能力减弱时，缓冲反相器14的下拉能力增强。
上拉能力指的是将低电平信号充电到高电平信号的能力，下拉能力指的是将高电平信号放电到低电平信号的能力。当上拉能力增强而下拉能力减弱时，缓冲反相器14输出的时钟信号的占空比增大；当上拉能力减弱而下拉能力增强 时，缓冲反相器14输出的时钟信号的占空比减小。也就是说，可通过控制缓冲反相器14的上拉能力和下拉能力朝不同的趋势变化，实现时钟信号占空比的可调，进而使得时钟信号的占空比满足预设要求。需要说明的是，每一第一节点都可以连接一缓冲反相器14，或者说每一第一节点与后端电路之间都可以串接一缓冲反相器14，以避免后端电路对振荡信号频率造成的影响，以保证振荡器的每一级第一反相器11具有较高的负载匹配度，进而使得振荡器的振荡信号频率更为稳定。例如图2中，clk360、clk270、clk180、clk90均连接一缓冲反相器14。
示例性地，参考图3，缓冲反相器14包括：第一PMOS组141，包括H个PMOS(MPH1、MPH2…MPHn)，H个PMOS的源极均连接于电源端Vcc；第一NMOS组142，包括H个NMOS(MNH1、MNH2…MNHn)，H个NMOS的源极连接于接地端Vss；第零PMOS MPH0，其源极连接H个PMOS的漏极；第零NMOS MNH0，其源极连接H个NMOS的漏极；第零PMOS MPH0的漏极与第零NMOS MNH0的漏极连接，作为缓冲反相器14的输出端clkout；第零PMOS MPH0的栅极与第零NMOS MNH0的栅极连接，作为缓冲反相器14的输入端clkin；H个PMOS的栅极和H个NMOS的栅极均由一占空比调节编码组(Dcc1、Dcc2…Dccn)控制。
其中，占空比调节编码组可由占空比调节模块(未图示)发出，PMOS以及PMOS管均为PMOS晶体管。
在一些实施例中，可通过控制占空比调节编码组的参数控制第一PMOS组141中PMOS管的导通数量和/或第一NMOS组142中NMOS管的导通数量，从而调整缓冲反相器14的上拉能力和/或下拉能力。
需要说明的是，PMOS管和NMOS管的开启电压不同。示例性地，当占空比调节编码组中第一调节编码Dcc1为高电平时，第一NMOS管MNH1导通而第一PMOS管MPH1关断；当第一调节编码Dcc1为低电平时，第一NMOS管MNH1关断而第一PMOS管MPH1导通。
由于一占空比调节编码同时控制第一PMOS组141和第一NMOS组142，因此，第一PMOS组141中PMOS管的导通数量越多，第一NMOS组142中NMOS管的导通数量就越少。而第一PMOS组141中PMOS管的导通数量越多， 第一PMOS组141的负载值较越小，缓冲反相器14的充电速率就越快，缓冲反相器14的上拉能力就越强；相应地，第一NMOS组142中NMOS管的导通数量越少，第一NMOS组142的负载值就越大，缓冲反相器14的放电速率就越慢，缓冲反相器14的下拉能力就越弱。如此，当PMOS管的导通数量较多而NMOS管的导通数量较少时，缓冲反相器14输出的时钟信号的占空比增大。
相应地，当PMOS管的导通数量较少而NMOS管的导通数量较多时，缓冲反相器14的上拉能力减弱而下拉能力增强，缓冲反相器14输出的时钟信号的占空比减小。
为保证第零PMOS MPH0以及第零NMOS MNH0正常工作，还设置有初始PMOS管MPHs以及初始NMOS管MNHs，初始PMOS管MPHs的源极连接电源端Vcc，漏极连接第零PMOSMPH0源极，栅极连接接地端Vss，即初始PMOS管MPHs处于导通状态；初始NMOS管MNHs的源极连接接地端Vss，漏极连接第零NMOS MNH0源极，栅极连接电源端Vcc，即初始NMOS管MNHs处于导通状态。
在一些实施例中，第一反相器11的第一传输速度可调。其中，通过调节第一反相器11的上拉能力和/或下拉能力来实现第一反相器11的第一传输速度可调。
其中，当第一反相器11的上拉能力增强时，第一反相器11的下拉能力增强；当第一反相器11的上拉能力减弱时，第一反相器11的下拉能力减弱。如此，可对振荡器输出的振荡信号的频率进行调整，以获取满足预设频率要求的振荡信号。
示例性地，参考图4，第一反相器11包括：第三PMOS组111，包括I个PMOS(MPI1、MPI2…MPIn)，I个PMOS的源极均连接于电源端Vcc；第三NMOS组112，包括I个NMOS(MNI1、MNI2…MNIn)，I个NMOS的源极连接于接地端Vss；第二PMOS MPI0，其源极连接I个PMOS的漏极；第二NMOS MNI0，其源极连接I个NMOS的漏极；第二PMOS MPI0的漏极与第二NMOS MNI0的漏极连接，作为第一反相器11的输出端；第二PMOS MPI0的栅极与第二NMOS MNI0的栅极连接，作为第一反相器11的输入端；I个PMOS管的栅极由第一反调节编码组(enb11、enb12…enb1n)控制，I个NMOS的栅极由 第一正调节编码组(en11、en12…en1n)控制；通过改变第一反调节编码组和/或第一正调节编码组实现第一传输速度可调。
在一些实施例中，可通过控制第一反调节编码组的参数控制第三PMOS组111中PMOS管的导通数量，从而调整第一反相器11的上拉能力；和/或，通过控制第一正调节编码组的参数控制第三NMOS组112中NMOS管的导通数量，从而调整第一反相器11的下拉能力。
需要说明的是，第一反调节编码组与第一正调节编码组的电位相反，即反相。当第一正调节编码en11为高电平时，第一反调节编码enb11为低电平，此时第三PMOS组111中第一PMOS管MPI1导通，第三NMOS组112中第一NMOS管MNI1导通；相应地，当第一正调节编码en11为低电平时，第一反调节编码enb11为高电平，此时第三PMOS组111中第一PMOS管MPI1关断，第三NMOS组112中第一NMOS管MNI1关断。
也就是说，第三PMOS组111中PMOS管的导通数量越多，第三NMOS组112中NMOS管的导通数量就越多，第一反相器11的上拉能力增强且下拉能力增强，第一反相器11输出的振荡信号的频率增大；相应地，第三PMOS组111中PMOS管的导通数量越少，第三NMOS组112中NMOS管的导通数量就越少，第一反相器11的上拉能力减弱且下拉能力减弱，第一反相器11输出的振荡信号的频率减小。
此外，第一反相器11具有用于保证第二PMOS MPI0处于工作状态的初始PMOS管MPIs，以及用于保证第二NMOS MNI0处于工作状态的初始NMOS管MNIs。
在一些实施例中，第二反相器12的第一传输速度可调。其中，通过调节第二反相器12的上拉能力和/或下拉能力来实现第二反相器12的第一传输速度可调。
其中，当第二反相器12的上拉能力增强时第二反相器12的下拉能力增强；当第二反相器12的上拉能力减弱时，第二反相器12的下拉能力减弱。
示例性地，参考图5，第二反相器12包括：第五PMOS组121，包括L个PMOS(MPL1、MPL2…MPLn)，L个PMOS的源极均连接于电源端Vcc；第五NMOS组122，包括L个NMOS(MNL1、MNL2…MNLn)，L个NMOS 的源极连接于接地端Vss；第四PMOSMPL0，其源极连接L个PMOS的漏极；第四NMOSMNL0，其源极连接L个NMOS的漏极；第四PMOS MPL0的漏极与第四NMOS MNL0的漏极连接，作为第二反相器12的输出端；第四PMOS MPL0的栅极与第四NMOS MNL0的栅极连接，作为第二反相器12的输入端；L个PMOS管的栅极由第二反调节编码组(enb21、enb22…enb2n)控制，L个NMOS的栅极由第二正调节编码组(en21、en22…en2n)控制；通过改变第二反调节编码组和/或第二正调节编码组实现第一传输速度可调。
在一些实施例中，可通过控制第二反调节编码组的参数控制第五PMOS组121中PMOS管的导通数量，从而调整第二反相器12的上拉能力；和/或，通过控制第二正调节编码组的参数控制第五NMOS组122中NMOS管的导通数量，从而调整第二反相器12的下拉能力。
需要说明的是，第二反调节编码组与第二正调节编码组的电位相反。当第二正调节编码en21为高电平时，第二反调节编码enb21为低电平，此时第五PMOS组121中第一PMOS管MPL1导通，第五NMOS组122中第一NMOS管MNL1导通；相应地，当第二正调节编码en21为低电平时，第二反调节编码enb21为高电平，此时第五PMOS组121中第一PMOS管MPL1关断，第五NMOS组122中第一NMOS管MNL1关断。
也就是说，第五PMOS组121中PMOS管的导通数量越多，第五NMOS组122中NMOS管的导通数量就越多，第二反相器12的上拉能力增强且下拉能力增强，第二反相器12输出的振荡信号的频率增大；相应地，第五PMOS组121中PMOS管的导通数量越少，第五NMOS组122中NMOS管的导通数量就越少，第二反相器12的上拉能力减弱且下拉能力减弱，第二反相器12输出的振荡信号的频率减小。
此外，第二反相器12具有用于保证第四PMOS MPL0处于工作状态的初始PMOS管MPLs，以及用于保证第四NMOS MNL0处于工作状态的初始NMOS管MNLs。
在一些实施例中，参考图6，第一反相器11包括多个第一子反相器113，多个第一子反相器113的输入端均电连接，多个第一子反相器113的输出端均电连接。如此，有利于控制振荡器版图设计中其他元件与第一子反相器113之 间的连线长度相近或相等，使得振荡器版图具有较好地对称平衡性，从而使得版图中振荡器的每个关键节点有较高的负载匹配度，进而使得每一级反相器的延迟相等；此外，还有利于使得其他元件与第一子反相器113之间的连线长度较短，从而减小连线的寄生电阻和寄生电容，使得振荡器具有良好性能。
其中，第一子反相器113的数量是偶数，如此，有利于更好地进行版图的对称平衡设计。
在一些实施例中，参考图7，第二反相器12包括多个第二子反相器123，多个第二子反相器123的输入端均电连接，多个第二子反相器123的输出端均电连接。如此，有利于提高振荡器版图的对称平衡性。
其中，第二子反相器123的数量与第一子反相器113的数量相等。如此，有利于提高振荡器版图的对称平衡性，进而获得性能更好的振荡器。
参考图4、图5、图6和图7，第一反相器11和第二反相器12可以设置成相同结构和尺寸，然后通过第一反调节编码组和/或第二正调节编码组、第二反调节编码组和/或第二正调节编码组实现传输速率的不同。
在一些实施例中，相对于仅通过第一环形拓扑结构传播振荡信号，第二环形拓扑结构的设置可增加电连接节点的振荡信号在单位时间内的反相次数，从而获取高速振荡信号。
相应地，本申请实施例还提供一种时钟产生电路，包括上述任一实施例提供的振荡器。图8为本申请实施例提供的时钟产生电路的结构示意图。以下将结合附图对时钟产生电路进行详细说明，与前述实施例相同或者相应的部分，可参考前述实施例的描述，以下将不做赘述。
参考图8，时钟产生电路包括：振荡器20；频率调节模块21，与振荡器20连接，用于调节振荡器20的频率。
其中，频率调节模块21通过调节第一传输速度和/或第二传输速度来调节振荡器20的振荡信号的频率。
可以理解的是，频率调节模块21可通过调节第一传输速度和第二传输速度来调节振荡器20的振荡信号的频率。频率调节模块21调节第一反相器11的第一传输速度以及第二反相器12的第二传输速度来调节振荡器20的振荡信号 的频率，或者，频率调节模块21也可通过调节第一传输速度或者第二传输速度中的一者来调节振荡器的振荡信号的频率，相应的，频率调节模块21调节第一反相器11的第一传输速度来调节振荡器20的振荡信号的频率，或者，频率调节模块21调节第二反相器12的第二传输速度来调节振荡器20的振荡信号的频率。
在一些实施例中，以频率调节模块21既调节第一传输速度又调节第二传输速度作为示例。其中，频率调节模块21与第一反相器11和第二反相器12连接，频率调节模块21可通过调整第一反调节编码组改变第一反相器11的上拉能力，以及通过调整第一正调节编码组改变第一反相器11的下拉能力，从而调节第一反相器11的第一传输速度，进而调节振荡器20振荡信号的频率。相应地，频率调节模块21可通过调整第二反调节编码组改变第二反相器12的上拉能力，以及通过调整第二正调节编码组改变第二反相器12的下拉能力，从而调节第二反相器12的第二传输速度，进而调节振荡器20振荡信号的频率。
在其他实施例中，频率调节模块可与第一反相器或第二反相器连接，且可仅改变第一反相器的上拉能力或下拉能力，或者，仅改变第二反相器的上拉能力或下拉能力。
在一些实施例中，时钟产生电路还包括占空比调节模块22，与振荡器20连接，用于调节振荡信号的占空比。其中，振荡器20包括缓冲反相器14，缓冲反相器14用于接收振荡信号并输出时钟信号，占空比调节模块22与缓冲反相器14连接，占空比调节模块22通过调节占空比调节编码组的参数调节缓冲反相器14的上拉能力和下拉能力，使得缓冲反相器14的上拉能力和下拉能力朝不同的区域变动，从而实现调节时钟信号占空比的效果。
在其他实施例中，占空比调节模块还可以与第一反相器和/或第二反相器连接，调节第一反相器和/或第二反相器输出的振荡信号的占空比，从而使得振荡器输出的振荡信号具有满足预设占空比要求。
在一些实施例中，时钟产生电路能够降低时钟负载对高速时钟信号的频率和占空比的影响，从而输出满足预设频率要求和预设占空比要求的时钟信号。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离 本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。

Claims (28)

  1. 一种振荡器，包括：
    第一环形拓扑结构，由多个第一反相器首尾相连，以第一传输速度传播振荡信号；
    第二环形拓扑结构，由多个第二反相器首尾相连，以第二传输速度传播所述振荡信号；
    其中，所述第一环形拓扑结构与所述第二环形拓扑结构电连接，所述第二传输速度小于所述第一传输速度。
  2. 如权利要求1所述的振荡器，其中，所述第一反相器的个数为N个，所述N为大于等于4的整数。
  3. 如权利要求2所述的振荡器，其中，所述第二反相器的个数为M个，所述M为大于等于2的整数。
  4. 如权利要求3所述的振荡器，其中，记每一个所述第一反相器的输入端为一个第一节点，所述第一环形拓扑结构具有N个所述第一节点；记每一个所述第二反相器的输入端为一个第二节点，所述第二环形拓扑结构具有M个所述第二节点；至少有两个所述第二节点与对应个数的所述第一节点电连接。
  5. 如权利要求4所述的振荡器，其中，所述第二传输速度大于等于0.5倍的所述第一传输速度。
  6. 如权利要求1所述的振荡器，还包括：
    第三环形拓扑结构，由多个第三反相器首尾相连，以第三传输速度传输所述振荡信号，所述第一环形拓扑结构与所述第三环形拓扑结构电连接，所述第三传输速度小于等于所述第一传输速度。
  7. 如权利要求6所述的振荡器，其中，所述第一反相器的个数为U个，所述U为大于等于4的整数；所述第二反相器的个数为V个，所述V为大于等于2的整数；所述第三反相器的个数为W个，所述W为大于等于2的整数。
  8. 如权利要求7所述的振荡器，其中，记每一个所述第一反相器的输入端为一个第一节点，所述第一环形拓扑结构具有U个所述第一节点；记每一个所述 第二反相器的输入端为一个第二节点，所述第二环形拓扑结构具有V个所述第二节点；记每一个所述第三反相器的输入端为一个第三节点，所述第三环形拓扑结构具有W个所述第三节点；至少有两个所述第二节点与对应个数的所述第一节点电连接，至少有两个所述第三节点与对应个数的所述第一节点电连接。
  9. 如权利要求8所述的振荡器，其中，所述第二传输速度小于所述第一传输速度，且所述第二传输速度大于等于0.5倍的所述第一传输速度；所述第三传输速度等于所述第二传输速度。
  10. 如权利要求1所述的振荡器，还包括：
    缓冲反相器，所述缓冲反相器的输入端接收所述振荡信号，所述缓冲反相器的输出端输出时钟信号。
  11. 如权利要求10所述的振荡器，其中，所述缓冲反相器的传输速度可调。
  12. 如权利要求11所述的振荡器，其中，通过调节所述缓冲反相器的上拉能力和/或下拉能力来实现所述缓冲反相器的传输速度可调。
  13. 如权利要求12所述的振荡器，其中，当所述缓冲反相器的上拉能力增强时，所述缓冲反相器的下拉能力减弱；当所述缓冲反相器的上拉能力减弱时，所述缓冲反相器的下拉能力增强。
  14. 如权利要求12所述的振荡器，其中，所述缓冲反相器包括：
    第一PMOS组，包括H个PMOS，所述H个PMOS的源极均连接于电源端；
    第一NMOS组，包括H个NMOS，所述H个NMOS的源极均连接于接地端；
    第零PMOS，其源极连接所述H个PMOS的漏极；
    第零NMOS，其源极连接所述H个NMOS的漏极；
    所述第零PMOS的漏极与所述第零NMOS的漏极连接，作为所述缓冲反相器的输出端；
    所述第零PMOS的栅极与所述第零NMOS的栅极连接，作为所述缓冲反相器的输入端；
    所述H个PMOS的栅极和所述H个NMOS的栅极均由一占空比调节编码组 控制。
  15. 如权利要求1所述的振荡器，其中，所述第一传输速度可调。
  16. 如权利要求15所述的振荡器，其中，通过调节所述第一反相器的上拉能力和/或下拉能力来实现所述第一传输速度可调。
  17. 如权利要求15所述的振荡器，其中，当所述第一反相器的上拉能力增强时，所述第一反相器的下拉能力增强；当所述第一反相器的上拉能力减弱时，所述第一反相器的下拉能力减弱。
  18. 如权利要求17所述的振荡器，其中，所述第一反相器包括：
    第三PMOS组，包括I个PMOS，所述I个PMOS的源极均连接于电源端；
    第三NMOS组，包括I个NMOS，所述I个NMOS的源极均连接于接地端；
    第二PMOS，其源极连接所述I个PMOS的源极；
    第二NMOS，其源极连接所述I个NMOS的漏极；
    所述第二PMOS的漏极与所述第二NMOS的漏极连接，作为所述第一反相器的输出端；
    所述第二PMOS的栅极与所述第二NMOS的栅极连接，作为所述第一反相器的输入端；
    所述I个PMOS管的栅极由第一反调节编码组控制，所述I个NMOS的栅极由第一正调节编码组控制；
    通过改变所述第一反调节编码组和/或所述第一正调节编码组实现所述第一传输速度可调。
  19. 如权利要求1所述的振荡器，其中，所述第二传输速度可调。
  20. 如权利要求19所述的振荡器，其中，通过调节所述第二反相器的上拉能力和/或下拉能力来实现所述第二传输速度可调。
  21. 如权利要求20所述的振荡器，其中，当所述第二反相器的上拉能力增强时，所述第二反相器的下拉能力增强；当所述第二反相器的上拉能力减弱时，所述第二反相器的下拉能力减弱。
  22. 如权利要求21所述的振荡器，其中，所述第二反相器包括：
    第五PMOS组，包括L个PMOS，所述L个PMOS的源极均连接于电源端；
    第五NMOS组，包括L个NMOS，所述L个NMOS的源极均连接于接地端；
    第四PMOS，其源极连接所述L个PMOS的漏极；
    第四NMOS，其源极连接所述L个NMOS的漏极；
    所述第四PMOS的漏极与所述第四NMOS的漏极连接，作为所述第二反相器的输出端；
    所述第四PMOS的栅极与所述第四NMOS的栅极连接，作为所述第二反相器的输入端；
    所述L个PMOS的栅极由第二反调节编码组控制，所述L个NMOS的栅极由第二正调节编码组控制；
    通过改变所述第二反调节编码组和/或所述第二正调节编码组实现所述第二传输速度可调。
  23. 如权利要求1所述的振荡器，其中，所述第一反相器包括多个第一子反相器，多个所述第一子反相器的输入端均电连接，多个所述第一子反相器的输出端均电连接。
  24. 如权利要求1所述的振荡器，其中，所述第二反相器包括多个第二子反相器，多个所述第二子反相器的输入端均电连接，多个所述第二子反相器的输出端均电连接。
  25. 一种时钟产生电路，包括：
    如权利要求1至24中任一项所述的振荡器；
    频率调节模块，与所述振荡器连接，用于调节所述振荡器的频率。
  26. 如权利要求25所述的时钟产生电路，其中，所述频率调节模块通过调节所述第一传输速度和/或所述第二传输速度来调节所述振荡器的振荡信号的频率。
  27. 如权利要求25所述的时钟产生电路，其中，所述频率调节模块调节所述第一反相器的所述第一传输速度和/或所述第二反相器的所述第二传输速度来调节所述振荡器的振荡信号的频率。
  28. 如权利要求25所述的时钟产生电路，还包括：占空比调节模块，与所述振荡器连接，用于调节所述振荡信号的占空比。
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