WO2022087909A1 - 显示装置、电压采集电路和方法 - Google Patents

显示装置、电压采集电路和方法 Download PDF

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Publication number
WO2022087909A1
WO2022087909A1 PCT/CN2020/124498 CN2020124498W WO2022087909A1 WO 2022087909 A1 WO2022087909 A1 WO 2022087909A1 CN 2020124498 W CN2020124498 W CN 2020124498W WO 2022087909 A1 WO2022087909 A1 WO 2022087909A1
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WIPO (PCT)
Prior art keywords
reference voltage
circuit
value
sampling
display device
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Application number
PCT/CN2020/124498
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English (en)
French (fr)
Inventor
金台镇
鲍文超
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2020/124498 priority Critical patent/WO2022087909A1/zh
Priority to US17/416,561 priority patent/US11749201B2/en
Priority to CN202080002512.5A priority patent/CN114787906A/zh
Publication of WO2022087909A1 publication Critical patent/WO2022087909A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display device, a voltage collection circuit and a method.
  • external compensation may be performed on the display panel during the display process of the display panel.
  • Embodiments of the present disclosure provide a display device, a voltage collection circuit, and a method.
  • Embodiments of the present disclosure provide a display device, including:
  • a display panel comprising a plurality of sub-pixels and a plurality of sensing lines, the sub-pixels are connected to the sensing lines;
  • a reference voltage providing circuit configured to provide the reference voltage
  • a sampling circuit which is electrically connected to the sensing line and the reference voltage supplying circuit, respectively, and is configured to collect the voltage on the sensing line to obtain a first sampling value, and collect the reference provided by the reference voltage supplying circuit voltage to obtain the second sampling value;
  • a processing circuit electrically connected to the sampling circuit, is configured to correct the first sampling value according to the second sampling value and the reference voltage.
  • the sampling circuit includes: a calibration pin and an analog-to-digital converter, the calibration pin is electrically connected to the reference voltage supply circuit, and the analog-to-digital converter is respectively connected to the calibration pin and the The sense lines are electrically connected.
  • the display device further includes a chip-on-film COF, the sampling circuit is located on the COF, and the COF has a first side connected to the display panel and a side opposite to the first side. On the second side, the calibration pins are located on the second side of the COF.
  • the sampling circuit is integrated on the display panel, and the calibration pins are located on the first side of the display panel.
  • one calibration pin there is one calibration pin, and one of the calibration pins is located at one end or the middle of the side where it is located.
  • the processing circuit is configured to obtain a difference between the second sampling value and the reference voltage, and subtract the difference from the first sampling value to obtain a modified first sampling value.
  • the two calibration pins are located at two ends of the side where they are located.
  • the display panel has at least two sensing regions, the sensing regions are in one-to-one correspondence with the calibration pins, and the arrangement direction of the sensing regions is the same as the arrangement direction of the calibration pins ;
  • the processing circuit is configured to correct the target first sample value according to the difference between the target second sample value and the reference voltage, and the calibration pin corresponding to the target second sample value is the same as the target first sample value.
  • the sensing area corresponding to the sensing line corresponding to the sampled value corresponds.
  • the reference voltage providing circuit and the processing circuit are integrated on a logic board.
  • the value of the reference voltage is an intermediate value between the upper limit and the lower limit of the measurement range of the sampling circuit.
  • Embodiments of the present disclosure also provide a voltage collection circuit for a display panel, including:
  • a reference voltage providing circuit configured to provide the reference voltage
  • a sampling circuit which is respectively electrically connected to the sensing line of the display panel and the reference voltage supply circuit, and is configured to collect the voltage on the sensing line to obtain a first sampling value, and collect the reference voltage provided by the reference voltage supply circuit , get the second sampling value;
  • a processing circuit electrically connected to the sampling circuit, is configured to correct the first sampling value according to the second sampling value and the reference voltage.
  • Embodiments of the present disclosure also provide a voltage collection method for a display panel, including:
  • the first sampled value is corrected according to the second sampled value and the reference voltage.
  • the modifying the first sampling value according to the second sampling value and the reference voltage includes:
  • FIG. 1 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a circuit structure of a sub-pixel and a sampling circuit provided by an embodiment of the present disclosure
  • FIG. 4 is a driving timing diagram of a sub-pixel in an external compensation process provided by an embodiment of the present disclosure
  • Fig. 5 is a partial enlarged structural schematic diagram of the display device shown in Fig. 2;
  • FIG. 6 is a schematic cross-sectional structure diagram of a chip-on-chip film
  • FIG. 7 is a schematic diagram of the distribution of a calibration pin provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of the distribution of a calibration pin provided by an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of the distribution of another calibration pin provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of another display device provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of a voltage acquisition circuit provided by an embodiment of the present disclosure.
  • FIG. 12 is a schematic flowchart of a voltage acquisition method provided by an embodiment of the present disclosure.
  • Words like "connected” or “connected” are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Up”, “Down”, “Left”, “Right”, etc. are only used to indicate the relative positional relationship, and when the absolute position of the described object changes, the relative positional relationship may also change accordingly.
  • the external compensation process for the display panel includes: a data driving circuit receives a sensed voltage from each sub-pixel through a sensing line, converts the sensed voltage into a digital sensing value, and then senses the digital sensing value. The value is sent to the logic board.
  • the logic board modulates the digital video data according to the sensed value to compensate for changes in the electrical characteristics of the driving transistors in the corresponding sub-pixels.
  • the digital sensing value obtained by the data driving circuit may be inaccurate, which affects the effect of external compensation.
  • An embodiment of the present disclosure provides a display device, which can be any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display device which can be any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • FIG. 1 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • the display device includes: a display panel 10 , a reference voltage supply circuit 20 , a sampling circuit 30 and a processing circuit 40 .
  • the sampling circuit 30 is electrically connected to the reference voltage supply circuit 20 , the processing circuit 40 and the sensing lines of the display panel 10 , respectively.
  • the reference voltage supply circuit 20 is configured to supply a reference voltage.
  • the sampling circuit 30 is configured to collect the voltage on the sensing line to obtain a first sampled value, and to collect the reference voltage provided by the reference voltage supply circuit 20 to obtain a second sampled value.
  • the processing circuit 40 is configured to modify the first sampled value with the second sampled value.
  • the sampling circuit not only collects the voltage on the sensing line, but also collects the reference voltage of the reference voltage providing circuit, so that the processing circuit can sense the sampling according to the second sampling value obtained by sampling the reference voltage and the reference voltage.
  • the first sampled value obtained from the voltage on the measuring line is corrected to remove noise components in the first sampled value to obtain a sensed voltage value, thereby improving the accuracy and reliability of the sensed voltage value.
  • the compensation voltage calculated according to the sensed voltage value is more accurate, and using a more accurate compensation voltage to perform external compensation on the corresponding sub-pixel can improve the display effect of the display panel.
  • the reference voltage may be set according to actual needs, which is not limited in the present disclosure.
  • the display panel 10 may be any display panel that requires external compensation, including but not limited to an OLED display panel.
  • an OLED display panel will be taken as an example to illustrate the embodiments of the present disclosure.
  • the display device is a display device using a chip on film (Chip On Film, COF) packaging process or a display device using a chip on panel (Chip On Panel, COP) packaging process.
  • COF Chip On Film
  • COF Chip On Panel
  • COP Chip On Panel
  • FIG. 2 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • the display device includes a display panel 10 and a COF 50 , and the COF 50 is bound to the display panel 10 . That is, the display device shown in FIG. 2 adopts the COF packaging process, and the driving integrated circuit (Integrated Circuit, IC) is located on the COF 50 ; one end of the COF 50 is bound and connected to the display panel 10 , and the other end of the COF 50 is bound to the circuit board 70 . connect.
  • the circuit board 70 may include a printed circuit board (Printed Circuit Board, PCB), or at least one of a flexible printed circuit board (Flexible Printed Circuit, FPC).
  • the display panel 10 has a display area 1 and a peripheral area 2 surrounding the display area 1 .
  • the display area 1 includes a plurality of sub-pixels 11 , a plurality of gate lines 12 , a plurality of data lines 13 and a plurality of sensing lines 14 .
  • a plurality of gate lines 12 and a plurality of data lines 13 intersect to form a plurality of sub-pixel regions, and one sub-pixel 11 is arranged in each sub-pixel region.
  • Each sub-pixel 11 is connected to the corresponding gate line 12 and data line 13, respectively.
  • the extending direction of the sensing line 14 is the same as the extending direction of the data line 13 , and each sub-pixel 11 is connected to the corresponding sensing line 14 .
  • the peripheral area 2 is used for arranging a gate driver (English: Gate Driver On Array, GOA for short) circuit and various signal lines and signal pins.
  • gate lines 12 extend in a first direction
  • data lines 13 and sense lines 14 extend in a second direction.
  • first direction is the row direction
  • second direction is the column direction
  • one column of sub-pixels 11 is connected to the same sensing line 14, or two columns of sub-pixels 11 are connected to one sensing line 14, as long as each sub-pixel 11 can
  • the voltage sensing can be performed solely through the connected sensing line 14 .
  • a sub-pixel includes a light-emitting device and a sub-pixel circuit.
  • the scan signal is provided to the sub-pixel circuit through the gate line, and the data signal is provided to the sub-pixel circuit through the data line, so that the corresponding light-emitting device is controlled to emit light through the sub-pixel circuit, thereby realizing picture display.
  • FIG. 3 is a schematic diagram of a circuit structure of a sub-pixel and a sampling circuit according to an embodiment of the present disclosure.
  • the sub-pixel 11 includes a light-emitting device 11 and a sub-pixel circuit 112
  • the sub-pixel circuit 112 includes a first thin film transistor T1 , a second thin film transistor T2 , a third thin film transistor T3 and a capacitor C.
  • the control electrode of the first thin film transistor T1 is connected to the first gate line G1
  • the first electrode of the first thin film transistor T1 is connected to the data line
  • the second electrode of the first thin film transistor T1 is connected to one end of the capacitor C and the second thin film transistor T2 control pole connection.
  • the first pole of the second thin film transistor T2 is connected to the first power line ELVDD
  • the second pole of the second thin film transistor T2 is connected to the other end of the capacitor
  • the cathode of the device is connected to the second power supply line ELVSS.
  • the control electrode of the third thin film transistor T3 is connected to the second gate line G2, and the second electrode of the third thin film transistor T3 is connected to the sensing line.
  • the sampling circuit includes a switch SW1, a sampling capacitor Csmp and an analog-to-digital converter (Analog-to-digital Converter, ADC).
  • ADC Analog-to-digital Converter
  • One end of the switch SW1 is connected to the sensing line L, and the other end of the switch SW1 is respectively connected to one end of the sampling capacitor Csmp and the ADC.
  • the input end of the ADC is connected, the other end of the sampling capacitor Csmp is grounded, and the output end of the ADC is connected to the logic board.
  • control electrode is the gate electrode
  • the first electrode is one of the source electrode and the drain electrode
  • the second electrode is the other one of the source electrode and the drain electrode.
  • the voltage supplied by the first power supply line ELVDD is higher than the voltage supplied by the second power supply line ELVSS.
  • FIG. 3 only takes a 3T1C circuit (ie, a sub-pixel circuit including three transistors and one capacitor) as an example to describe the embodiment of the present disclosure, which is not limited by the embodiment of the present disclosure.
  • FIG. 4 is a timing diagram of driving signals of the circuit structure shown in FIG. 3 during an external compensation process. The working process of the sub-pixel in FIG. 3 will be described below with reference to FIG. 4 .
  • both the first gate line G1 and the second gate line G2 provide a high level, and the first thin film transistor T1 and the third thin film transistor T3 are turned on.
  • the data line D writes a data voltage, and at the same time, the second pole of the second thin film transistor T2 is reset through the sensing line L, and the voltage difference between the two ends of the capacitor C is VAS.
  • both the first gate line G1 and the second gate line G2 provide a low level
  • the first thin film transistor T1 and the third thin film transistor T3 are turned off
  • the data line D stops writing data voltage
  • the voltage across the capacitor C constant.
  • the first gate line G1 provides a low level
  • the first thin film transistor T1 is turned off
  • the second gate line G2 provides a high level
  • the third thin film transistor T3 is turned on
  • the sensing line L is switched to floating state
  • the sensing line L is charged.
  • Csense in FIG. 4 represents the potential of the sensing line L.
  • the potential on the sensing line L gradually increases.
  • the switch control line (not shown in the figure) provides a high level, the switch SW1 is turned on, and the sampling capacitor Csmp is charged.
  • both the first gate line G1 and the second gate line G2 provide a low level
  • the first thin film transistor T1 and the third thin film transistor T3 are turned off
  • the ADC collects the voltage on the sampling capacitor Csmp, that is, the sensing line is collected
  • the first sampled value is obtained from the voltage on L, and the first sampled value is transmitted to the logic board, and the logic board calculates the compensation voltage according to the first sampled value.
  • both the first gate line G1 and the second gate line G2 provide a high level, the first thin film transistor T1 and the third thin film transistor T3 are turned on, and the data line D writes a compensation voltage to point A, the compensation voltage
  • the second thin film transistor T2 is turned on, and the light emitting device 111 emits light.
  • the stable phase t2 in FIG. 4 may be removed, and the charging phase t3 is directly entered after the writing phase t1.
  • FIG. 5 is a schematic diagram of a part of the enlarged structure in FIG. 2 , showing the structure of the part of the dotted line in FIG. 2 . 2 and 5, optionally, the sampling circuit 30 includes a calibration pin 31 and an ADC32, the calibration pin 31 is electrically connected to the reference voltage supply circuit 20, and the ADC32 is respectively connected to the calibration pin 31 It is electrically connected to the sensing line 14 .
  • the sampling circuit 30 also includes a switch and a sampling capacitor connected between the calibration pin 31 and the ADC32 to control the sampling of the ADC32.
  • a switch and a sampling capacitor connected between the calibration pin 31 and the ADC32 to control the sampling of the ADC32.
  • the ADC is generally integrated in the driving IC of the display panel, while in the display device shown in FIG. 2 and FIG. 5 , the driving IC is integrated in the COF. Therefore, in the embodiment shown in FIG. 2 , the sampling circuit 30 is located on the COF 50 . In addition to the sampling circuit, the driving IC also includes a digital-to-analog converter and the like for supplying data voltages to the data lines.
  • the value of the reference voltage is an intermediate value between the upper limit and the lower limit of the measurement range of the sampling circuit.
  • the value of the reference voltage is 2.5V.
  • the measurement range of the sampling circuit is determined by the range of the ADC. When the measurement value is at the end of the range of the ADC, the measurement error is larger than that in the middle of the range of the ADC, so the reference voltage is taken as It is the middle value of the upper limit and lower limit of the measurement range, which is beneficial to improve the accuracy of the reference voltage measurement result.
  • FIG. 6 is a schematic diagram of the cross-sectional structure of the COF in FIG. 5 , showing the cross-sectional structure of the COF along the line I-I in FIG. 5 .
  • the COF 50 includes a flexible substrate 51 , a driving IC 52 , a plurality of first pins 53 and a plurality of second pins 54 .
  • the driving IC 52 , the plurality of first pins 53 and the plurality of second pins 54 are all located on the flexible substrate 51 , and the driving IC 52 is electrically connected to the first pins 53 and the second pins 54 respectively.
  • the flexible substrate 51 may be a single-layer substrate or a multi-layer substrate.
  • the flexible substrate 51 includes alternately stacked insulating medium layers and conductive layers.
  • a plurality of signal lines connected between the driver IC 52 and the first pin 53, and a plurality of signal lines (not shown) connected between the driver IC 52 and the second pin 54 may be located in the same conductive layer, or Can be in different conductive layers.
  • the number of the first pins 53 and the second pins 54 is large, more signal lines need to be arranged, and a multi-layer substrate is used, and the signal lines are arranged in a plurality of conductive layers, which can facilitate the arrangement of the signal lines.
  • the chip on film 50 has opposite first sides 50a and second sides 50b, a plurality of first pins 53 are arranged along the first side 50a, and a plurality of second pins 54 are arranged along the second side 50b arrangement.
  • the first pins 53 include sensing pins, data pins and other pins that are connected to the circuit structure in the display panel 10, the sensing pins are connected to the sensing lines 14 in the display panel, and the data pins are connected to the display panel 10.
  • the data line 13 in the panel is connected.
  • the second pins 54 include the calibration pins 31 and the like.
  • the chip on film 50 and the display panel 10 are usually connected in an Outer Lead Bonding (OLB) process.
  • OLB Outer Lead Bonding
  • an ACF Anisotropic Conductive Film
  • anisotropic conductive adhesive film is set between the chip on film 50 and the surface to be contacted with the display panel 10 .
  • anisotropic conductive adhesive film is set between the chip on film 50 and the surface to be contacted with the display panel 10 .
  • anisotropic conductive adhesive film anisotropic conductive adhesive film
  • a plurality of first pins 53 are connected with corresponding pins on the display panel 10 through the ACF.
  • the plurality of second pins 54 can be connected to other structures, such as a printed circuit board (PCB), in an Inner Lead Bonding (ILB) process.
  • PCB printed circuit board
  • ILB Inner Lead Bonding
  • the calibration pin 31 is located at at least one end of the side where it is located and/or at the middle of the side where it is located.
  • FIG. 5 is a schematic structural diagram of a COF according to an embodiment of the present disclosure.
  • the COF 50 has two calibration pins 31 , and the two calibration pins 31 are located at two ends of the second side 50 b respectively.
  • the other second pins 54 other than the calibration pins 31 are located in the middle of the two calibration pins 31 . In this way, it is easy to realize adding calibration pins without changing the arrangement order of other second pins.
  • FIG. 7 is a schematic structural diagram of a COF according to an embodiment of the present disclosure.
  • the COF 50 has a calibration pin 31 , and the calibration pin 31 is located at one end of the second side 50 b.
  • the other second pins 54 except the calibration pin 31 are located on one side of the calibration pin 31 . In this way, it is easy to realize adding calibration pins without changing the arrangement order of other second pins.
  • FIG. 8 is a schematic structural diagram of another COF according to an embodiment of the present disclosure.
  • the COF 50 has a calibration pin 31 , and the calibration pin 31 is located in the middle of the second side 50 b .
  • other second pins 54 except the calibration pin 31 are distributed on both sides of the calibration pin 31 .
  • FIG. 9 is a schematic structural diagram of another COF according to an embodiment of the present disclosure.
  • the COF 50 has three calibration pins 31 , and among the three calibration pins 31 , two calibration pins 31 are respectively located on the second side 50 b . At both ends, a calibration pin 31 is located in the middle of the second side 50b. In this case, other second pins 54 other than the calibration pins 31 are distributed among the three calibration pins 54 .
  • the processing circuit 40 is configured to modify the first sampled value according to the difference between the second sampled value and the reference voltage.
  • the processing circuit 40 is configured to obtain a difference between the second sampled value and the reference voltage, and subtract the difference from the first sampled value to obtain a modified first sampled value. That is, the processing circuit 40 corrects the first sampled value according to formula (1), and the corrected first sampled value is the sensing voltage.
  • V is the sensing voltage
  • A is the first sampling value
  • B is the second sampling value
  • V0 is the reference voltage
  • B-V0 represents external noise
  • the first sampling values corresponding to all the sensing lines are corrected using the second sampling values corresponding to the same calibration pin.
  • the display panel has at least two sensing regions, and the first sampling values corresponding to the sensing lines in different sensing regions adopt different first sampling values.
  • the second sampling value corresponding to the calibration pin is corrected.
  • the number of sensing regions is the same as the number of calibration pins.
  • the arrangement direction of the sensing regions is the same as the arrangement direction of the calibration pins, and the sensing regions and the calibration pins are in one-to-one correspondence according to the arrangement direction.
  • different sensing regions correspond to different sensing pin groups, and the sensing pin groups are in one-to-one correspondence with the sensing regions.
  • the sensing pins in each sensing pin group are connected to the sensing lines in the corresponding sensing area, so that the sampling circuit can obtain the corresponding sensing lines in different sensing areas through different sensing pin groups the first sample value of .
  • the processing circuit 40 is configured to correct the target first sample value according to the difference between the target second sample value and the reference voltage, and the calibration pin corresponding to the target second sample value is the same as the target first sample value.
  • the sensing area corresponding to the sensing line corresponding to the sampled value corresponds.
  • the display panel has two sensing areas, which are located on both sides of the dotted line O, that is, they are arranged in the left and right directions in FIG. 2 .
  • the pin 31 corresponds to the sensing area on the left side of the dotted line O
  • the calibration pin 31 on the right corresponds to the sensing area on the right side of the dotted line O.
  • the second sampling value collected through the calibration pin 31 on the left is used for correction.
  • the first sampling value on the sensing line is corrected by the second sampling value collected through the calibration pin 31 on the right.
  • the second sampling values on different calibration pins are used since the interference on the sensing line and the calibration pin that are close to each other is more likely to be close to each other, the second sampling value at the corresponding position is used to correct the first sampling value, which is beneficial to further improve the obtained sense.
  • the accuracy of the voltage measurement is improved, thereby further improving the compensation effect of the display panel.
  • the display device further includes a logic board 60 , the reference voltage supply circuit 20 and the processing circuit 40 are integrated on the logic board 60 , and the second side 50 b of the COF 50 is connected to the through circuit board.
  • 70 is connected to the logic board 60, so that the calibration pin is electrically connected to the reference voltage supply circuit 20 in the logic board 60, and the ADC is electrically connected to the processing circuit 40, so that the processing circuit 40 can obtain the first sample collected by the sampling circuit 30. value and the second sample value.
  • the second side 50b of the COF 50 may also be directly connected to the logic board 60 by binding.
  • the display device further includes a PCB, an FPC, and a logic board
  • the reference voltage supply circuit 20 is located on the PCB
  • the second side of the COF is connected to the PCB, thereby connecting the calibration pins to the reference voltage.
  • Electrical connections to circuit 20 are provided.
  • the processing circuit 40 is integrated on the logic board, and the logic board is sequentially connected to the COF through the flexible circuit board and the printed circuit board, so that the processing circuit 40 on the logic board is electrically connected with the sampling circuit 30 on the COF, so that the processing circuit 40 can obtain The first sample value and the second sample value collected by the sampling circuit 30 .
  • the processing circuit 40 is a Field-Programmable Gate Array (FPGA) on a logic board.
  • the calibration voltage is pre-stored in the FPGA, so that after the first sampling value and the second sampling value are obtained, the first sampling value can be corrected according to the second sampling value and the reference voltage.
  • FIG. 10 is a schematic structural diagram of another display device according to an embodiment of the present disclosure.
  • the COF is not included, and the driver IC 52 is provided on the display panel 10 , and the package form of the driver IC is called COP.
  • the sampling circuit is integrated on the display panel 10 , that is, the calibration pin 31 and the ADC 32 are both located on the display panel 10 .
  • the calibration pins 31 are located on the first side of the display panel 10 , that is, the side of the display panel for connecting with the logic board 60 . Refer to FIG. 5 to FIG. 8 for the number and arrangement of the calibration pins 31 , and the detailed description is omitted here. It should be noted that, in addition to the calibration pin 31, a plurality of other pins are also arranged on the first side.
  • the pins may also be referred to as pads, and the logic board may also be referred to as a timing controller (Timing Controller, T-CON) board.
  • Timing Controller T-CON
  • FIG. 11 is a schematic structural diagram of a voltage acquisition circuit according to an embodiment of the present disclosure.
  • the voltage acquisition circuit 110 includes a reference voltage supply circuit 20 , a sampling circuit 30 and a processing circuit 40 .
  • the reference voltage supply circuit 20 is configured to supply a reference voltage.
  • the sampling circuit 30 is configured to be electrically connected to the sensing line of the display panel and the reference voltage supply circuit, respectively.
  • the sampling circuit 30 is configured to collect the voltage on the sensing line to obtain a first sampling value, and to collect the reference voltage to provide The reference voltage provided by the circuit is used to obtain the second sampling value.
  • the processing circuit 40 is electrically connected to the sampling circuit 30, and the processing circuit 40 is configured to modify the first sampling value according to the second sampling value and the reference voltage.
  • the reference voltage supply circuit is located on a printed circuit board or logic board.
  • the sampling circuit is integrated in the data driving IC, and the driving IC adopts the COF packaging form or the COF packaging form.
  • the processing circuitry is located on the logic board.
  • sampling circuit 30 For the structure of the sampling circuit 30, refer to the foregoing display device embodiments, and the detailed description is omitted here.
  • Embodiments of the present disclosure also provide a voltage collection method, which is applicable to any of the foregoing display devices.
  • the voltage acquisition method may be performed by the logic board of the display device.
  • FIG. 12 is a schematic flowchart of a voltage acquisition method provided by an embodiment of the present disclosure. As shown in Figure 12, the method includes:
  • step 1201 the voltage on the sensing line of the display panel is collected to obtain a first sampling value
  • step 1202 collecting the reference voltage provided by the reference voltage providing circuit to obtain a second sample value
  • step 1203 the first sampled value is corrected according to the second sampled value and the reference voltage.
  • both the first sample value and the second sample value are collected by a sampling circuit (eg ADC) in the driver IC.
  • a sampling circuit eg ADC
  • step 1203 reference is made to the foregoing embodiment of the display device for the way of modifying the first sample value, and the detailed description is omitted here.
  • a computer-readable storage medium is also provided, the computer-readable storage medium is a non-volatile storage medium, and a computer program is stored in the computer-readable storage medium, when the computer-readable storage medium is stored When the computer program in the medium is executed by the processor, the voltage acquisition method provided by the embodiments of the present disclosure can be executed.
  • a computer program product is also provided, and the computer program product stores instructions, when running on a computer, enabling the computer to execute the voltage acquisition method provided by the embodiments of the present disclosure.
  • a chip is also provided, the chip includes a programmable logic circuit and/or program instructions, and when the chip is running, the voltage acquisition method provided by the embodiment of the present disclosure can be executed.

Abstract

一种显示装置、电压采集电路和方法，属于显示技术领域。该显示装置包括：显示面板（10），包括多个子像素（11）以及多根感测线（14），所述子像素（11）与所述感测线（14）连接；基准电压提供电路（20），被配置为提供基准电压；采样电路（30），分别与所述感测线（14）和所述基准电压提供电路（20）电连接，被配置为采集所述感测线（14）上的电压，得到第一采样值，以及采集所述基准电压提供电路（20）提供的基准电压，得到第二采样值；处理电路（40），与所述采样电路（30）电连接，被配置为根据所述第二采样值和所述基准电压，对所述第一采样值进行修正。有利于提高显示装置的显示效果。

Description

显示装置、电压采集电路和方法 技术领域
本公开涉及显示技术领域，特别涉及一种显示装置、电压采集电路和方法。
背景技术
为了提高显示面板的显示效果，可以在显示面板的显示过程中，对显示面板进行外部补偿。
发明内容
本公开实施例提供了一种显示装置、电压采集电路和方法。
本公开实施例提供了一种显示装置，包括：
显示面板，包括多个子像素以及多根感测线，所述子像素与所述感测线连接；
基准电压提供电路，被配置为提供基准电压；
采样电路，分别与所述感测线和所述基准电压提供电路电连接，被配置为采集所述感测线上的电压，得到第一采样值，以及采集所述基准电压提供电路提供的基准电压，得到第二采样值；
处理电路，与所述采样电路电连接，被配置为根据所述第二采样值和所述基准电压，对所述第一采样值进行修正。
可选地，所述采样电路包括：校准引脚和模数转换器，所述校准引脚与所述基准电压提供电路电连接，所述模数转换器分别与所述校准引脚和所述感测线电连接。
可选地，所述显示装置还包括覆晶薄膜COF，所述采样电路位于所述COF上，所述COF具有与所述显示面板连接的第一侧边和与所述第一侧边相对的第二侧边，所述校准引脚位于所述COF的第二侧边。
可选地，所述采样电路集成在所述显示面板上，所述校准引脚位于所述显示面板的第一侧边。
在一些实施例中，所述校准引脚有1个，1个所述校准引脚位于所在侧边的 一端或者中部。
可选地，所述处理电路，被配置为获取所述第二采样值和所述基准电压的差值，并采用所述第一采样值减去所述差值，得到修正后的第一采样值。
在一些实施例中，所述校准引脚有2个，2个所述校准引脚位于所在侧边的两端。
在又一些实施例中，所述校准引脚有3个，1个校准引脚位于所在侧边的中部，另外2个校准引脚位于所在侧边的两端。
可选地，所述显示面板具有至少两个感测区域，所述感测区域与所述校准引脚一一对应，且所述感测区域的排列方向与所述校准引脚的排列方向相同；
所述处理电路，被配置为根据目标第二采样值和所述基准电压的差值，对目标第一采样值进行修正，所述目标第二采样值对应的校准引脚与所述目标第一采样值对应的感测线所在的感测区域对应。
可选地，所述基准电压提供电路和所述处理电路集成在逻辑板上。
可选地，所述基准电压的取值为所述采样电路的测量范围的上限和下限的中间值。
本公开实施例还提供了一种显示面板的电压采集电路，包括：
基准电压提供电路，被配置为提供基准电压；
采样电路，分别与显示面板的感测线和所述基准电压提供电路电连接，被配置为采集所述感测线上的电压，得到第一采样值，以及采集基准电压提供电路提供的基准电压，得到第二采样值；
处理电路，与所述采样电路电连接，被配置为根据所述第二采样值和所述基准电压，对所述第一采样值进行修正。
本公开实施例还提供了一种显示面板的电压采集方法，包括：
采集显示面板的感测线上的电压，得到第一采样值；
采集基准电压提供电路提供的基准电压，得到第二采样值；
根据所述第二采样值和所述基准电压，对所述第一采样值进行修正。
可选地，所述根据所述第二采样值和所述基准电压，对所述第一采样值进行修正，包括：
获取所述第二采样值和所述基准电压的差值，并采用所述第一采样值减去所述差值，得到修正后的第一采样值。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种显示装置的结构示意图；
图2是本公开实施例提供的一种显示装置的结构示意图；
图3是本公开实施例提供的一种子像素以及采样电路的电路结构示意图；
图4是本公开实施例提供的子像素在外部补偿过程的驱动时序图；
图5是图2所示显示装置的部分放大结构示意图；
图6是覆晶薄膜的截面结构示意图；
图7是本公开实施例提供的一种校准引脚的分布示意图；
图8是本公开实施例提供的一种校准引脚的分布示意图；
图9是本公开实施例提供的另一种校准引脚的分布示意图；
图10是本公开实施例提供的另一显示装置的结构示意图；
图11是本公开实施例提供的一种电压采集电路的结构示意图；
图12是本公开实施例提供的一种电压采集方法的流程示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权利要求书中使用的“第一”、“第二”、“第三”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元 件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则所述相对位置关系也可能相应地改变。
相关技术中，对显示面板进行外部补偿过程包括：数据驱动电路通过感测线从各个子像素接收感测到的电压，将所感测到的电压转换为数字感测值，然后将该数字感测值发送到逻辑板。逻辑板根据该感测值调制数字视频数据，以补偿对应的子像素中的驱动晶体管的电特性的变化。
然而，由于外部噪声的影响，数据驱动电路获得的数字感测值可能不准确，影响外部补偿的效果。
本公开实施例提供了一种显示装置，该显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
图1是本公开实施例提供的一种显示装置的结构示意图。参见图1，显示装置包括：显示面板10、基准电压提供电路20、采样电路30和处理电路40。采样电路30分别与基准电压提供电路20、处理电路40和显示面板10的感测线电连接。
基准电压提供电路20被配置为提供基准电压。采样电路30被配置为采集所述感测线上的电压，得到第一采样值，以及采集所述基准电压提供电路20提供的基准电压，得到第二采样值。处理电路40被配置为采用所述第二采样值对所述第一采样值进行修正。
在本公开实施例中，采样电路除了采集感测线上的电压之外，还采集基准电压提供电路的基准电压，从而处理电路能够根据采样基准电压得到的第二采样值和基准电压对采样感测线上的电压得到的第一采样值进行修正，以去除第一采样值中的噪声分量，得到感测电压值，从而提高感测电压值的准确度和可靠性。根据该感测电压值计算得到的补偿电压更加准确，采用更加准确的补偿电压对对应的子像素进行外部补偿能够提高显示面板的显示效果。
在本公开实施例中，该基准电压可以根据实际需要设置，本公开对此不作限制。
在本公开实施例中，显示面板10可以为任何需要进行外部补偿的显示面板，包括但不限于OLED显示面板。下文中将以OLED显示面板为例，对本公开实 施例进行示例性说明。
可选地，在本公开实施例中，显示装置为采用覆晶薄膜(Chip On Film，COF)封装工艺的显示装置或者采用面板上芯片(Chip On Panel，COP)封装工艺的显示装置。对于采用不同封装工艺的显示装置，采样电路所处的位置不同。下面结合图2和图10对这两种显示装置分别进行说明。
图2是本公开实施例提供的一种显示装置的结构示意图。如图2所示，该显示装置包括显示面板10和COF50，COF50绑定在显示面板10上。也即是，图2所示显示装置为采用COF封装工艺，驱动集成电路(Integrated Circuit，IC)位于COF50上；COF50的一端与显示面板10绑定连接，COF50的另一端与电路板70绑定连接。该电路板70可以包括印刷线路板(Printed Circuit Board，PCB)，也可以是柔性电路板(Flexible Printed Circuit，FPC)中的至少一种。
如图2所示，显示面板10具有显示区域1和围绕显示区域1的外围区域2。显示区域1包括多个子像素11、多根栅线12、多根数据线13以及多根感测线14。多根栅线12和多根数据线13交叉，形成多个子像素区域，每个子像素区域内布置有一个子像素11。每个子像素11分别与对应的栅线12和数据线13连接。感测线14的延伸方向与数据线13的延伸方向相同，每个子像素11与对应的感测线14连接。外围区域2用于布置栅极驱动(英文：Gate Driver On Array，简称：GOA)电路以及各种信号线以及信号引脚等。
在一些示例中，栅线12沿第一方向延伸，数据线13和感测线14沿第二方向延伸。假设第一方向为行方向，第二方向为列方向，一列子像素11与同一根感测线14连接，或者，两列子像素11与一根感测线14连接，只要每个子像素11都能够通过所连接的感测线14单独进行电压感测即可。
对于OLED显示面板而言，子像素包括发光器件和子像素电路。通过栅线向子像素电路提供扫描信号，通过数据线向子像素电路提供数据信号，从而通过子像素电路控制对应的发光器件发光，进而实现画面显示。
图3为本公开实施例提供的一种子像素以及采样电路的电路结构示意图。如图3所示，子像素11包括发光器件11和子像素电路112，子像素电路112包括第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3和电容C。第一薄膜晶体管T1的控制极与第一栅线G1连接，第一薄膜晶体管T1的第一极与数据线连接，第一薄膜晶体管T1的第二极与电容C的一端和第二薄膜晶体管T2的控制极连接。第二薄膜晶体管T2的第一极与第一电源线ELVDD连接，第 二薄膜晶体管T2的第二极分别与电容的另一端、第三薄膜晶体管T3的第一极和发光器件的阳极连接，发光器件的阴极与第二电源线ELVSS连接。第三薄膜晶体管T3的控制极与第二栅线G2连接，第三薄膜晶体管T3的第二极与感测线连接。
采样电路包括开关SW1、采样电容Csmp和模数转换器(Analog-to-digital Converter，ADC)，开关SW1的一端与感测线L连接，开关SW1的另一端分别与采样电容Csmp的一端和ADC的输入端连接，采样电容Csmp的另一端接地，ADC的输出端与逻辑板连接。
在本公开实施例中，控制极为栅极，第一极为源极和漏极中的一个，第二极为源极和漏极中的另一个。第一电源线ELVDD提供的电压高于第二电源线ELVSS提供的电压。
需要说明的是，图3仅以3T1C电路(即包括3个晶体管和1个电容的子像素电路)为例对本公开实施例进行说明，本公开实施例对此不作限制。
图4为图3所示电路结构在外部补偿过程的驱动信号时序图。下面结合图4对图3中子像素的工作过程进行说明。
在写入阶段t1，第一栅线G1和第二栅线G2均提供高电平，第一薄膜晶体管T1和第三薄膜晶体管T3打开。数据线D写入数据电压，同时，通过感测线L将第二薄膜晶体管T2的第二极复位，电容C两端的电压差为VAS。
在稳定阶段t2，第一栅线G1和第二栅线G2均提供低电平，第一薄膜晶体管T1和第三薄膜晶体管T3关断，数据线D停止写入数据电压，电容C两端的电压保持不变。
在充电阶段t3，第一栅线G1提供低电平，第一薄膜晶体管T1关断，第二栅线G2提供高电平，第三薄膜晶体管T3打开，感测线L切换到悬浮(floating)状态，感测线L充电。图4中的Csense表示感测线L的电位，从图4可以看出，在充电阶段t3，感测线L上的电位逐渐升高。在充电阶段t3的最后一段时间，开关控制线(图中未示出)提供高电平，开关SW1导通，给采样电容Csmp充电。
在采样阶段t4，第一栅线G1和第二栅线G2均提供低电平，第一薄膜晶体管T1和第三薄膜晶体管T3关断，ADC采集采样电容Csmp上的电压，即采集感测线L上的电压，得到第一采样值，并将第一采样值传递至逻辑板，由逻辑板根据该第一采样值计算补偿电压。
在写回阶段t5，第一栅线G1和第二栅线G2均提供高电平，第一薄膜晶体管T1和第三薄膜晶体管T3打开，数据线D将补偿电压写入A点，该补偿电压使得第二薄膜晶体管T2导通，发光器件111发光。
需要说明的是，在一些实施例中，图4中稳定阶段t2可以去掉，在写入阶段t1之后直接进入充电阶段t3。
图5为图2中部分放大结构示意图，显示了图2中虚线框部分的结构。结合图2和图5，可选地，所述采样电路30包括校准引脚31和ADC32，所述校准引脚31与所述基准电压提供电路20电连接，ADC32分别与所述校准引脚31和所述感测线14电连接。
该采样电路30还包括连接在校准引脚31和ADC32之间的开关和采样电容，以控制ADC32的采样，开关和采样电容的连接方式和控制过程参见图3和图4相关描述，在此省略详细描述。
在本公开实施例中，ADC通常集成在显示面板的驱动IC中，而在图2和图5所示的显示装置中，驱动IC集成在COF中。因此，在图2所示实施例中，采样电路30位于该COF50上。除了采样电路之外，驱动IC还包括用于向数据线提供数据电压的数模转换器等。
示例性地，该基准电压的取值为采样电路的测量范围的上限和下限的中间值。例如，测量范围的下限为1V，上限为4V，则该基准电压的取值为2.5V。采样电路的测量范围由ADC的量程决定，当测量值在ADC的量程的端部区域时，相对于测量值在ADC的量程的中间区域而言，产生的测量误差较大，所以将基准电压取为测量范围的上限和下限的中间值，有利于提高基准电压测量结果的准确度。
图6为图5中COF的截面结构示意图，显示了COF沿图5中I-I线的截面结构。结合图5和图6，COF50包括柔性基板51、驱动IC52、多个第一引脚53和多个第二引脚54。驱动IC52、多个第一引脚53和多个第二引脚54均位于柔性基板51上，且驱动IC52分别与第一引脚53和第二引脚54电连接。
可选地，柔性基板51可以是单层基板或者多层基板。当柔性基板51为多层基板时，柔性基板51包括交替堆叠的绝缘介质层和导电层。连接在驱动IC52和第一引脚53之间的多条信号线、以及连接在驱动IC52和第二引脚54之间的多条信号线(图未示)可以位于相同的导电层中，也可以位于不同的导电层中。在第一引脚53和第二引脚54数量较多时，需要布置的信号线也较多，采用多 层基板，将信号线设置在多个导电层中，可以方便信号线的布置。
示例性地，覆晶薄膜50具有相对的第一侧边50a和第二侧边50b，多个第一引脚53沿第一侧边50a排列，多个第二引脚54沿第二侧边50b排列。其中，第一引脚53包括感测引脚、数据引脚等与显示面板10中的电路结构连接的引脚，感测引脚与显示面板中的感测线14连接，数据引脚与显示面板中的数据线13连接。第二引脚54包括校准引脚31等。
覆晶薄膜50与显示面板10通常在外引脚结合(Outer Lead Bonding，OLB)制程中连接，在OLB制程中，覆晶薄膜50和显示面板10待接触的表面之间会设置ACF(Anisotropic Conductive Film，异方性导电胶膜)，多个第一引脚53通过ACF与显示面板10上对应的引脚连接。多个第二引脚54可以在内引脚结合(Inner Lead Bonding，ILB)制程中与其他结构，例如印刷电路板(Printed Circuit Board，PCB)连接。
可选地，校准引脚31位于所在侧边的至少一端和/或位于所在侧边的中部。
图5为本公开实施例提供的一种COF的结构示意图。如图5所示，在本公开实施例的又一种实施方式中，COF50具有两个校准引脚31，两个校准引脚31分别位于第二侧边50b的两端。在这种情况下，除了校准引脚31之外的其他第二引脚54位于该两个校准引脚31的中间。这样，增加校准引脚而无需改变其他第二引脚的排列顺序，容易实现。
图7为本公开实施例提供的一种COF的结构示意图。在本公开实施例的一种实施方式中，如图7所示，COF50具有一个校准引脚31，该校准引脚31位于第二侧边50b的一端。在这种情况下，除了校准引脚31之外的其他第二引脚54均位于该校准引脚31的一侧。这样，增加校准引脚而无需改变其他第二引脚的排列顺序，容易实现。
图8为本公开实施例提供的另一COF的结构示意图。如图8所示，在本公开实施例的另一种实施方式中，COF50具有一个校准引脚31，该校准引脚31位于第二侧边50b的中部。在这种情况下，除了校准引脚31之外的其他第二引脚54分布在该校准引脚31的两侧。
图9为本公开实施例提供的另一COF的结构示意图。如图9所示，在本公开实施例的又一种实施方式中，COF50具有三个校准引脚31，三个校准引脚31中，两个校准引脚31分别位于第二侧边50b的两端，一个校准引脚31位于第二侧边50b的中部。在这种情况下，除了校准引脚31之外的其他第二引脚54 分布于这三个校准引脚54之间。
需要说明的是，图5至图8中所示的第一引脚53和第二引脚54的数量仅为示例，可以根据实际需要设置，本公开对此不做限制。
在本公开实施例中，所述处理电路40被配置为根据所述第二采样值和所述基准电压的差值，对所述第一采样值进行修正。
示例性地，处理电路40被配置为获取所述第二采样值和所述基准电压的差值，采用所述第一采样值减去所述差值，得到修正后的第一采样值。也即是，处理电路40根据公式(1)对第一采样值进行修正，修正后的第一采样值即为感测电压。
V＝A-(B-V0)  (1)
公式(1)中，V为感测电压，A为第一采样值，B为第二采样值，V0为基准电压。B-V0表示外部噪声。
对于具有一个校准引脚的情况(例如图6或图7)，所有的感测线对应的第一采样值均采用同一个校准引脚对应的第二采样值进行修正。
对于具有至少两个校准引脚的情况(例如图5或图9)，所述显示面板具有至少两个感测区域，不同的感测区域中的感测线对应的第一采样值采用不同的校准引脚对应的第二采样值进行修正。
当采样电路具有至少两个校准引脚时，感测区域的数量与校准引脚的数量相同。并且，感测区域的排列方向与校准引脚的排列方向相同，且所述感测区域与所述校准引脚按照所述排列方向一一对应。对于COF而言，不同的感测区域对应不同的感测引脚组，感测引脚组与感测区域一一对应。每个感测引脚组中的感测引脚与对应的感测区域中的感测线连接，从而采样电路能够通过不同的感测引脚组获得不同的感测区域中的感测线对应的第一采样值。
所述处理电路40被配置为根据目标第二采样值和所述基准电压的差值，对目标第一采样值进行修正，所述目标第二采样值对应的校准引脚与所述目标第一采样值对应的感测线所在的感测区域对应。
例如，如图2所示，显示面板具有2个感测区域，分别位于虚线O的两侧，即沿图2中的左右方向排列，结合图5，校准引脚31有2个，左边的校准引脚31对应虚线O左侧的感测区域，右边的校准引脚31对应虚线O右侧的感测区域。对于虚线O左侧的感测区域中的感测线上的第一采样值，采用通过左边的校准引脚31采集到的第二采样值进行修正，对于虚线O左侧的感测区域中的感 测线上的第一采样值，采用通过右边的校准引脚31采集到的第二采样值进行修正。
在本公开实施例中，当校准引脚有多个时，通过划分感测区域，对于不同感测区域中的感测线上的第一采样值，采用不同的校准引脚上的第二采样值进行修正，由于相互靠近的感测线和校准引脚上受到的干扰接近的可能性较大，所以采用对应位置的第二采样值对第一采样值进行修正，有利于进一步提高获得的感测电压的准确度，进而进一步提高显示面板的补偿效果。
可选地，如图2所示，该显示装置还包括逻辑板60，所述基准电压提供电路20和所述处理电路40集成在逻辑板60上，COF50的第二侧边50b与通过电路板70与逻辑板60连接，从而实现校准引脚与逻辑板60中的基准电压提供电路20电连接，以及ADC与处理电路40电连接，使得处理电路40能够获得采样电路30采集到的第一采样值和第二采样值。
可替代地，在其他实施例中，COF50的第二侧边50b也可以直接与逻辑板60绑定连接。
可替代地，在其他实施例中，该显示装置还包括PCB、FPC和逻辑板，基准电压提供电路20位于PCB上，COF的第二侧边与该PCB连接，从而将校准引脚与基准电压提供电路20电连接。处理电路40集成在逻辑板上，逻辑板依次通过柔性电路板和该印刷电路板与COF连接，从而将逻辑板上的处理电路40与COF上的采样电路30电连接，使得处理电路40能够获得采样电路30采集到的第一采样值和第二采样值。
示例性地，处理电路40为逻辑板上的现场可编程门阵列(Field-Programmable Gate Array，FPGA)。该FPGA中预先保存有校准电压，从而在获得第一采样值和第二采样值之后，能够根据所述第二采样值和所述基准电压，对所述第一采样值进行修正。
图10为本公开实施例提供的另一显示装置的结构示意图。与图2所示的显示装置的区别在于，在图10所示的显示装置中，不包括COF，驱动IC52设置在显示面板10上，该驱动IC的封装形式被称为COP。相应地，采样电路集成在显示面板10上，也即是，校准引脚31和ADC32均位于显示面板10上。
在图10所示的显示装置中，校准引脚31位于显示面板10的第一侧边，即显示面板用于与逻辑板60连接的一侧边。校准引脚31的数量和排布方式参见图5至图8，在此省略详细描述。需要说明的是，除了校准引脚31之外，第一 侧边还布置有多个其他的引脚。
在本公开实施例中，引脚也可以称为焊盘，逻辑板也可以称为时序控制器(Timing Controller，T-CON)板。
此外，本公开实施例还提供了一种电压采集电路，该电压采集电路适用于需要进行外部补偿的显示面板。图11为本公开实施例提供的一种电压采集电路的结构示意图。如图11所示，该电压采集电路110包括基准电压提供电路20、采样电路30和处理电路40。
基准电压提供电路20被配置为提供基准电压。采样电路30用于分别与显示面板的感测线和所述基准电压提供电路电连接，采样电路30被配置为采集所述感测线上的电压，得到第一采样值，以及采集基准电压提供电路提供的基准电压，得到第二采样值。处理电路40与所述采样电路30电连接，处理电路40被配置为根据所述第二采样值和所述基准电压，对所述第一采样值进行修正。
示例性地，如前所述，基准电压提供电路位于印刷电路板或者逻辑板上。采样电路集成在数据驱动IC中，驱动IC采用COF封装形式或者采用COF封装形式。处理电路位于逻辑板上。
采样电路30的结构参见前述显示装置实施例，在此省略详细描述。
本公开实施例还提供了一种电压采集方法，适用于前述任一种显示装置。该电压采集方法可以由显示装置的逻辑板执行。图12为本公开实施例提供的一种电压采集方法的流程示意图。如图12所示，该方法包括：
在步骤1201中，采集显示面板的感测线上的电压，得到第一采样值；
在步骤1202中，采集基准电压提供电路提供的基准电压，得到第二采样值；
在步骤1203中，根据所述第二采样值和所述基准电压，对所述第一采样值进行修正。
在步骤1201和1202中，第一采样值和第二采样值均通过驱动IC中的采样电路(例如ADC)采集得到。
在步骤1203中，对第一采样值进行修正的方式参见前述显示装置实施例，在此省略详细描述。
在示例性实施例中，还提供了一种计算机可读存储介质，该计算机可读存 储介质为非易失性存储介质，该计算机可读存储介质中存储有计算机程序，当该计算机可读存储介质中的计算机程序由处理器执行时，能够执行本公开实施例提供的电压采集方法。
在示例性实施例中，还提供了一种计算机程序产品，该计算机程序产品中存储有指令，当其在计算机上运行时，使得计算机能够执行本公开实施例提供的电压采集方法。
在示例性的实施例中，还提供了一种芯片，该芯片包括可编程逻辑电路和/或程序指令，当该芯片运行时能够执行本公开实施例提供的电压采集方法。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (14)

  1. 一种显示装置，其特征在于，包括：
    显示面板(10)，包括多个子像素(11)以及多根感测线(14)，所述子像素(11)与所述感测线(14)连接；
    基准电压提供电路(20)，被配置为提供基准电压；
    采样电路(30)，分别与所述感测线(14)和所述基准电压提供电路(20)电连接，被配置为采集所述感测线(14)上的电压，得到第一采样值，以及采集所述基准电压提供电路(20)提供的基准电压，得到第二采样值；
    处理电路(40)，与所述采样电路(30)电连接，被配置为根据所述第二采样值和所述基准电压，对所述第一采样值进行修正。
  2. 根据权利要求1所述的显示装置，其特征在于，所述采样电路(30)包括：校准引脚(31)和模数转换器(32)，所述校准引脚(31)与所述基准电压提供电路(20)电连接，所述模数转换器(32)分别与所述校准引脚(31)和所述感测线(14)电连接。
  3. 根据权利要求2所述的显示装置，其特征在于，所述显示装置还包括覆晶薄膜(50)，所述采样电路位于所述覆晶薄膜(50)上，所述覆晶薄膜具有与所述显示面板(10)连接的第一侧边(50a)和与所述第一侧边(50a)相对的第二侧边(50b)，所述校准引脚(31)位于所述覆晶薄膜(50)的第二侧边。
  4. 根据权利要求2所述的显示装置，其特征在于，所述采样电路(30)集成在所述显示面板(10)上，所述校准引脚(31)位于所述显示面板(10)的第一侧边。
  5. 根据权利要求3或4所述的显示装置，其特征在于，所述校准引脚有1个，1个所述校准引脚(31)位于所在侧边的一端或者中部。
  6. 根据权利要求5所述的显示装置，其特征在于，所述处理电路(40)，被配置为获取所述第二采样值和所述基准电压的差值，采用所述第一采样值减去所述差值，得到修正后的第一采样值。
  7. 根据权利要求3或4所述的显示装置，其特征在于，所述校准引脚(31)有2个，2个所述校准引脚(31)沿所在侧边排列且位于所在侧边的两端。
  8. 根据权利要求3或4所述的显示装置，其特征在于，所述校准引脚(31) 有3个，3个所述校准引脚(31)沿所在侧边排列，且3个校准引脚(31)中的1个校准引脚(31)位于所在侧边的中部，3个校准引脚(31)中的另外2个校准引脚(31)位于所在侧边的两端。
  9. 根据权利要求7或8所述的显示装置，其特征在于，所述显示面板(10)具有至少两个感测区域，所述感测区域与所述校准引脚(31)一一对应，且所述感测区域的排列方向与所述校准引脚(31)的排列方向相同；
    所述处理电路(40)，被配置为根据目标第二采样值和所述基准电压的差值，对目标第一采样值进行修正，所述目标第二采样值对应的校准引脚(31)与所述目标第一采样值对应的感测线(14)所在的感测区域对应。
  10. 根据权利要求1至9任一项所述的显示装置，其特征在于，所述显示装置还包括逻辑板(60)，所述基准电压提供电路(20)和所述处理电路(40)集成在所述逻辑板(60)上。
  11. 根据权利要求1至10任一项所述的显示装置，其特征在于，所述基准电压的取值为所述采样电路的测量范围的上限和下限的中间值。
  12. 一种显示面板的电压采集电路，其特征在于，包括：
    基准电压提供电路，被配置为提供基准电压；
    采样电路，分别与显示面板的感测线和所述基准电压提供电路电连接，被配置为采集所述感测线上的电压，得到第一采样值，以及采集基准电压提供电路提供的基准电压，得到第二采样值；
    处理电路，与所述采样电路电连接，被配置为根据所述第二采样值和所述基准电压，对所述第一采样值进行修正。
  13. 一种显示面板的电压采集方法，其特征在于，包括：
    采集显示面板的感测线上的电压，得到第一采样值；
    采集基准电压提供电路提供的基准电压，得到第二采样值；
    根据所述第二采样值和所述基准电压，对所述第一采样值进行修正。
  14. 根据权利要求13所述的电压采集方法，其特征在于，所述根据所述第二采样值和所述基准电压，对所述第一采样值进行修正，包括：
    获取所述第二采样值和所述基准电压的差值，并采用所述第一采样值减去所述差值，得到修正后的第一采样值。
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