WO2022083000A1 - 阵列基板以及显示面板 - Google Patents

阵列基板以及显示面板 Download PDF

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Publication number
WO2022083000A1
WO2022083000A1 PCT/CN2020/140479 CN2020140479W WO2022083000A1 WO 2022083000 A1 WO2022083000 A1 WO 2022083000A1 CN 2020140479 W CN2020140479 W CN 2020140479W WO 2022083000 A1 WO2022083000 A1 WO 2022083000A1
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WIPO (PCT)
Prior art keywords
signal line
display area
array substrate
reset signal
gate
Prior art date
Application number
PCT/CN2020/140479
Other languages
English (en)
French (fr)
Inventor
全海燕
Original Assignee
Tcl华星光电技术有限公司
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Filing date
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Publication of WO2022083000A1 publication Critical patent/WO2022083000A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate and a display panel.
  • LCD Liquid Crystal Display
  • a liquid crystal display device usually has a gate driving circuit, and the gate driving circuit can generate a scanning signal so that the liquid crystal display device can realize display scanning.
  • the gate driving circuit is usually arranged in the peripheral frame area of the array substrate, so that the liquid crystal display device has a frame area with a larger area.
  • Embodiments of the present application provide an array substrate and a display panel, which can reduce the frame area of the array substrate.
  • An embodiment of the present application provides an array substrate, including a display area and a reset signal line, the reset signal line is disposed in the display area, the reset signal line is kept at a low potential when the display area is in a display state, and A pulse signal is generated when the display area is in a blanking state.
  • the array substrate further includes a plurality of pixel units arranged in an array, the plurality of pixel units are arranged in the display area, and the plurality of pixel units are arranged in an array cloth, each of the pixel units has a dark pattern area, and a part of the reset signal line is located in the dark pattern area of at least one of the pixel units.
  • the array substrate includes a plurality of GOA units, the plurality of GOA units are disposed outside the display area, and each of the GOA units is connected to the reset signal line.
  • the array substrate includes a plurality of GOA units, the plurality of GOA units are disposed in the display area, and each of the GOA units is connected to the reset signal line.
  • the GOA unit includes a first transistor and a second transistor, a spaced region is formed between the first transistor and the second transistor, and a part of the reset signal line is located on the In the spaced region, the reset signal line is connected to the gate of the second transistor.
  • the GOA unit further includes a clock signal line, a gate-on voltage control line, and at least one scan line, and the clock signal line, the gate-on voltage control line, and the at least one scan line are all Extends from the display area to the outside of the display area.
  • the clock signal line and the gate-on voltage control line are arranged parallel to each other.
  • the array substrate further includes a clock control bus, a gate-on voltage control bus, and a common electrode line, and the clock control bus, the gate-on voltage control bus, and the common electrode line are arranged Outside the display area, the clock control bus is connected to the clock signal line, and the gate-on voltage control bus is connected to the gate-on voltage control line.
  • the CF substrate common electrode line, the clock control bus line, the gate-on voltage control bus line, and the common electrode line are directed from the outside of the display area to the outer side of the display area.
  • the directions are arranged one after the other and set in parallel.
  • the display area includes a first side and a second side arranged oppositely, the number of the reset signal lines is two, and one of the reset signal lines is close to the The first side is arranged, and the other reset signal line is arranged close to the second side.
  • the embodiments of the present application further provide a display panel, which includes the array substrate, a color filter substrate and a liquid crystal layer as described in the above embodiments of the application, the color filter substrate is disposed on one side of the array substrate, and the liquid crystal layer sandwiches It is arranged between the array substrate and the color filter substrate.
  • the color filter substrate includes a CF common electrode line, and the CF common electrode line is disposed outside the display area.
  • the array substrate further includes a plurality of pixel units arranged in an array, the plurality of pixel units are arranged in the display area, and the plurality of pixel units are arranged in an array cloth, each of the pixel units has a dark pattern area, and a part of the reset signal line is located in the dark pattern area of at least one of the pixel units.
  • the array substrate includes a plurality of GOA units, the plurality of GOA units are disposed outside the display area, and each of the GOA units is connected to the reset signal line.
  • the array substrate includes a plurality of GOA units, the plurality of GOA units are disposed in the display area, and each of the GOA units is connected to the reset signal line.
  • the GOA unit includes a first transistor and a second transistor, a spaced region is formed between the first transistor and the second transistor, and a part of the reset signal line is located in the In the spaced region, the reset signal line is connected to the gate of the second transistor.
  • the GOA unit further includes a clock signal line, a gate-on voltage control line, and at least one scan line, and the clock signal line, the gate-on voltage control line, and the at least one scan line are all Extends from the display area to the outside of the display area.
  • the clock signal line and the gate-on voltage control line are arranged in parallel with each other.
  • the array substrate further includes a clock control bus, a gate-on voltage control bus and a common electrode line, and the clock control bus, the gate-on voltage control bus and the common electrode line are arranged Outside the display area, the clock control bus is connected to the clock signal line, and the gate-on voltage control bus is connected to the gate-on voltage control line.
  • the reset signal lines By arranging the reset signal lines in the display area of the array substrate of the embodiments of the present application, compared with directly disposing the reset signal lines in the peripheral border area of the array substrate, the occupation of the peripheral border area of the array substrate by the reset signal lines can be reduced. Thereby, the peripheral frame area of the array substrate is narrowed.
  • FIG. 1 is a schematic diagram of a first structure of an array substrate provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a second structure of an array substrate provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a pixel unit and a GOA unit in the array substrate shown in FIG. 2 .
  • FIG. 4 is a schematic diagram of a third structure of an array substrate provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of the pixel unit shown in FIG. 3 and the GOA unit in the GOA unit.
  • FIG. 6 is a schematic diagram of a fourth structure of the array substrate provided by the embodiment of the present application.
  • FIG. 7 is a schematic diagram of a fifth structure of the array substrate provided by the embodiment of the present application.
  • FIG. 8 is a schematic diagram of a first structure of a display panel according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a second structure of a display panel according to an embodiment of the present application.
  • An embodiment of the present application provides an array substrate, which includes a display area and a reset signal line, the reset signal line is disposed in the display area, and the reset signal line is kept at a low potential when the display area is in a display state, And a pulse signal is generated when the display area is in a blanking state.
  • the array substrate further includes a plurality of pixel units arranged in an array, the plurality of pixel units are arranged in the display area, and the plurality of pixel units are arranged in an array
  • each of the pixel units has a dark pattern area, and a part of the reset signal line is located in the dark pattern area of at least one of the pixel units.
  • the array substrate includes a plurality of GOA units, the plurality of GOA units are disposed outside the display area, and each of the GOA units is connected to the reset signal line .
  • the array substrate includes a plurality of GOA units, the plurality of GOA units are disposed in the display area, and each of the GOA units is connected to the reset signal line.
  • the GOA unit includes a first transistor and a second transistor, a spaced region is formed between the first transistor and the second transistor, and a part of the reset signal line is located in the in the spaced region, and the reset signal line is connected to the gate of the second transistor.
  • the GOA unit further includes a clock signal line, a gate-on voltage control line and at least one scan line, the clock signal line, the gate-on voltage control line and at least one scan line Both extend from the display area to the outside of the display area.
  • the clock signal line and the gate-on voltage control line are arranged in parallel with each other.
  • the array substrate further includes a clock control bus, a gate-on voltage control bus, and a common electrode line, the clock control bus, the gate-on voltage control bus, and the common electrode line It is arranged outside the display area, the clock control bus is connected with the clock signal line, and the gate-on voltage control bus is connected with the gate-on voltage control line.
  • the CF substrate common electrode line, the clock control bus, the gate-on voltage control bus, and the common electrode line face the display area from the outside of the display area
  • the directions are arranged in sequence and parallel.
  • the display area includes a first side and a second side that are oppositely arranged, the number of the reset signal lines is two, and one of the reset signal lines is close to all the reset signal lines.
  • the first side is arranged, and the other reset signal line is arranged close to the second side.
  • the number of the GOA units is two, one of the GOA units is disposed close to the first side, and the other GOA unit is disposed close to the second side side settings.
  • Embodiments of the present application also provide a display panel, including:
  • an array substrate comprising a display area and a reset signal line
  • the reset signal line is arranged in the display area, the reset signal line is kept at a low potential when the display area is in a display state, and is in a blanking state in the display area generate a pulse signal;
  • a color filter substrate disposed on one side of the array substrate
  • the liquid crystal layer is sandwiched between the array substrate and the color filter substrate.
  • the color filter substrate includes a CF common electrode line, and the CF common electrode line is disposed outside the display area.
  • the array substrate further includes a plurality of pixel units arranged in an array, the plurality of pixel units are arranged in the display area, and the plurality of pixel units are arranged in an array
  • each of the pixel units has a dark pattern area, and a part of the reset signal line is located in the dark pattern area of at least one of the pixel units.
  • the array substrate includes a plurality of GOA units, the plurality of GOA units are disposed outside the display area, and each of the GOA units is connected to the reset signal line .
  • the array substrate includes a plurality of GOA units, the plurality of GOA units are disposed in the display area, and each of the GOA units is connected to the reset signal line.
  • the GOA unit includes a first transistor and a second transistor, a spaced region is formed between the first transistor and the second transistor, and a part of the reset signal line is located in the in the spaced region, and the reset signal line is connected to the gate of the second transistor.
  • the GOA unit further includes a clock signal line, a gate-on voltage control line and at least one scan line, the clock signal line, the gate-on voltage control line and at least one scan line Both extend from the display area to the outside of the display area.
  • the clock signal line and the gate-on voltage control line are arranged in parallel with each other.
  • the array substrate further includes a clock control bus, a gate-on voltage control bus, and a common electrode line, the clock control bus, the gate-on voltage control bus, and the common electrode line It is arranged outside the display area, the clock control bus is connected with the clock signal line, and the gate-on voltage control bus is connected with the gate-on voltage control line.
  • FIG. 1 is a schematic diagram of a first structure of the array substrate provided by the embodiment of the present application.
  • the array substrate 200 may include a display area 210, and the display area 210 may be used for displaying pictures.
  • the display area 210 is an active display area (Active Area, AA) of the array substrate 200, and the display area 210 may be provided with a pixel array, and the pixel array includes a plurality of pixel units arranged in a matrix.
  • Active Area AA
  • the array substrate 200 may further include a GOA (Gate Driver on Array) circuit 220 , and the GOA circuit 220 is a circuit structure formed by directly manufacturing the driver circuit on the array substrate using the GOA technology.
  • the GOA circuit 220 may include a reset signal line 221.
  • the reset signal line 221 is disposed in the display area 210.
  • the reset signal line 221 is kept at a low level when the display area 210 is in a display state (such as when a screen is displayed), and is in the off state when the display area 210 is in a display state.
  • a pulse signal is generated to drive the GOA circuit to reset.
  • a blanking time (Blanking Time) is set between two adjacent display frames.
  • the reset signal line 221 generates a pulse signal during the blanking time, and when the display area 210 is in the display state, the reset signal line 221 is always at a low potential to avoid affecting the frame displayed in the display area 210. 210 can be displayed normally.
  • the reset signal line 221 is usually disposed outside the display area 210 , or in the non-display area of the array substrate 200 , which will lead to a larger area of the non-display area of the array substrate 200 .
  • the border becomes wider.
  • the embodiment of the present application sets the reset signal line 221 in the GOA circuit 220 in the display area 210.
  • the occupied area of at least one signal line can be reduced in the non-display area of the array substrate 200. , thereby reducing the occupied area of the array substrate 200 by the non-display area of the array substrate 200 , so as to achieve the purpose of narrowing the frame of the array substrate 200 .
  • FIG. 2 is a schematic diagram of a second structure of an array substrate provided by an embodiment of the present application
  • FIG. 3 is a schematic structural diagram of a pixel unit and a GOA unit in the array substrate shown in FIG. 2
  • the array substrate 200 may further include a plurality of pixel units 230, the plurality of pixel units 230 are arranged in the display area 210, the plurality of pixel units 230 are arranged in an array, each pixel unit 230 has a dark pattern area 232, a reset signal A portion of the line 221 is located within the dark pattern area 232 of the at least one pixel unit 230 .
  • TFT Thin Film Transistor, thin film transistor
  • CF Color Filter, color filter
  • ITO Indium Due to the dual effects of the fringe electric field of Tin Oxide, indium tin oxide, some dark alignment regions are formed inside the pixel unit 230 .
  • a part of the reset signal line 221 is arranged in the dark pattern area 232 of at least one pixel unit 230, for example, a part of the reset signal line 221 can be arranged in one pixel unit 230, two pixel units 230, five pixel units 230 or ten
  • the dark pattern area 232 of the pixel unit 230 other parts are arranged in the outer area of the pixel unit 230 , such as the area between two adjacent pixel units 230 .
  • the GOA circuit 220 may further include multiple GOA units 222 , the multiple GOA units 222 may be cascaded with each other, and the multiple GOA units 222 are disposed outside the display area 210 .
  • the display area 210 may be in a regular shape, for example, the display area 210 may be in a rectangular shape, the display area 210 may have a first side 212 and a second side 214 arranged oppositely, the array substrate 200 may have a first non-display area 240, A non-display area 240 is disposed at the edge of the display area 210 and is close to the first side 212 relative to the second side 214 .
  • the multiple GOA units 222 are all disposed in the first non-display area 240, and the multiple GOA units 222 can be cascaded with each other.
  • each GOA unit 222 is connected to the reset signal line 221 , and the reset signal line 221 can control the GOA unit 222 to control the reset of the GOA unit 222 .
  • each GOA unit 222 may be provided with a reset signal terminal 2221, each GOA unit 222 is connected to the reset signal line 221 through the reset signal terminal 2221, and the reset signal line 221 may generate a pulse signal when the display area 210 is in a blanking state And the pulse signal is input into the GOA unit 222 through the reset signal terminal 2221 to control the reset of the GOA unit 222 .
  • FIG. 4 is a schematic diagram of the third structure of the array substrate provided by the embodiment of the present application.
  • a plurality of GOA units 222 may be disposed within the display area 210 . Multiple GOA units 222 may be cascaded to each other.
  • Each GOA unit 222 is connected to a reset signal line 221 , and the reset signal line 221 can control the GOA unit 222 to control the reset of the GOA unit 222 .
  • the reset signal line 221 and the GOA unit 222 in the GOA circuit 220 are both disposed in the display area 210, and they can be directly connected to each other in the display area 210.
  • the application embodiment can reduce the aperture ratio of the display area 210, and can also reduce the connection line between the GOA unit and the reset signal line 221 shown in FIG. 230 penetration rate.
  • FIG. 5 is a schematic structural diagram of the pixel unit shown in FIG. 3 and the GOA unit in the GOA unit.
  • the GOA unit 222 may include a plurality of transistors, for example, the GOA unit 222 may include a first transistor T1 and a second transistor T2, and the first transistor T1 and the second transistor T2 are arranged in the display area 210 at intervals, or the first transistor T1 and the second transistor T2 There is a spacer region 2222 between the two transistors T2, and a part of the reset signal line 221 is located in the spacer region 2222. For example, after the reset signal line 221 can pass through the dark stripe region 232 of the pixel unit 230, it can be routed to the position of the second transistor T2 in the spaced region 2222 and connected to the gate of the second transistor T2.
  • the GOA unit may further include a third transistor T3, a fourth transistor T4, a fifth transistor T51, a sixth transistor T52, a seventh transistor T53, an eighth transistor T54, a ninth transistor T6, a tenth transistor T7, and an eleventh transistor T8 and capacitor Cb.
  • the gate of the first transistor T1 and the drain of the first transistor T1 are both connected to the scan signal line G(n-1) of the n-1 th GOA unit 222 to receive the input of the scan line of the n-th GOA unit signal, the source of the first transistor T1 is connected to the drain of the second transistor T2 and the node Q(n) of the nth GOA unit 222, and the source of the second transistor T2 is connected to the negative power supply voltage VSS.
  • the gate of the fifth transistor T51, the drain of the fifth transistor T51 and the drain of the seventh transistor T53 are all connected to the gate-on voltage control line, the source of the fifth transistor T51 is connected to the gate of the seventh transistor T53, and the The source of the seventh transistor T53 is connected to the drain of the eighth transistor T54 and the gate of the ninth transistor T6, and the gate of the eighth transistor T54 and the gate of the sixth transistor T52 are both connected to the node Q of the nth stage GOA unit 222 (n) connection, the drain of the sixth transistor T52 is connected to the gate of the seventh transistor T53, the source of the sixth transistor T52 and the source of the eighth transistor T54 are both connected to the negative power supply voltage VSS, the ninth transistor T6 The source and the source of the tenth transistor T7 are both connected to the negative power supply voltage VSS, and the drain of the ninth transistor T6 is connected to the scan signal line G(n) of the nth GOA unit to output to the scan signal line G(n) signal, the gate of the
  • circuit structure of the GOA unit 222 shown in FIG. 5 is only exemplary, and the circuit structure of the GOA unit 222 in the embodiment of the present application may also be other structures.
  • the GOA unit 222 may further include a clock signal line (CK) 2225 , a gate-on voltage control line (VGH) 2226 and at least one scan line 2227 (such as scan line G(n ⁇ 1), scan line G(n ⁇ 1), scan line Line G(n) and scan line G(n+1)), clock signal line (CK) 2225, gate-on voltage control line (VGH) 2226 and at least one scan line 2227 are arranged in parallel with each other.
  • CK clock signal line
  • VGH gate-on voltage control line
  • the clock signal line 2225 , the gate-on voltage control line (VGH) 2226 and the at least one scan line 2227 all extend from the display area 210 to the outside of the display area 210 (for example, extend to the first non-display area 240 ), and corresponding signal lines connect. In order to save the occupied space of the display area 210 .
  • the GOA circuit 220 may further include a clock control bus (CK) 223 and a gate-on voltage control bus (VGH) 224 , both of which are disposed on the display area 210
  • the clock control bus (CK) 223 and the gate-on voltage control bus (VGH) 224 can be arranged in the first non-display area 240, and the clock control bus (CK) 223 and the gate-on voltage control bus (VGH) 224 are mutually Parallel setup.
  • the clock control bus (CK) 223 can transmit a clock signal, which can be connected to the clock signal line (CK) 2225 of each GOA unit 222 to control each GOA unit 222, and then control each pixel unit 230 according to The clock signal is used to display the frame picture.
  • a gate-on voltage control bus (VGH) 224 may be used to transmit a gate-on voltage signal, which may be connected to a gate-on voltage control line (VGH) 2226 of each GOA cell 222 to control each GOA cell 222, the gate The on-voltage signal may provide a voltage signal for the transistor in each GOA unit 222 to turn on the transistor in each GOA unit 222, thereby controlling the pixel unit 230 to display a picture or not to display a picture.
  • the GOA circuit 220 further includes a common electrode line (ACOM) 225 , which are disposed outside the display area 210 (eg, disposed in the first non-display area 240 ), please continue to refer to FIG. 2 .
  • the clock control bus (CK) 223 , the gate-on voltage control bus (VGH) 224 and the common electrode line (ACOM) 225 are arranged in order from the outside of the display area 210 toward the direction of the display area 210 , and the clock control bus (CK) 223 , the gate-on voltage control bus (VGH) 224 and the common electrode line (ACOM) 225 are arranged parallel to each other from the display area 210 to reduce the wiring of the GOA circuit 220 to the outside of the display area 210 (such as the first non-display area 240 ) It is beneficial to reduce the area of the edge area of the display area 210 (such as the first non-display area 240 ), so as to have the effect of narrowing the frame.
  • FIG. 6 is a schematic diagram of a fourth structure of an array substrate provided by an embodiment of the present application
  • FIG. 7 is a schematic diagram of a fifth structure of an array substrate provided by an embodiment of the present application.
  • the number of GOA circuits 220 in this embodiment of the present application may be two, one of the GOA circuits 220 may be disposed close to the first side 212 , and the other GOA circuit 220 may be disposed close to the second side 214 .
  • the array substrate 200 may include a display area 210 , a first non-display area 240 and a second non-display area 250 .
  • the first non-display area 240 is arranged at the edge of the first side 212
  • the second non-display area 250 is arranged at the second side.
  • one GOA circuit 220 is disposed in the first non-display area 240
  • the other GOA circuit 220 is disposed in the second non-display area 250
  • the two GOA circuits 220 jointly control the multi-row pixel units 230.
  • one of the GOA circuits 220 may be responsible for controlling pixel units 230 in odd rows
  • the other GOA circuit 220 may be responsible for controlling pixel units in even rows.
  • the design method of the embodiment of the present application is more reasonable and more convenient for wiring.
  • each GOA circuit 220 includes one reset signal line 221 , that is, the number of reset signal lines 221 in this embodiment of the present application is two, and one reset signal line 221 is disposed in the display area 210 close to the first reset signal line 221 . At the position of the side edge 212 , another reset signal line 221 is arranged in a position close to the second side edge 214 in the display area.
  • the embodiment of the present application further provides a display panel, exemplarily, the display panel 20 shown in FIG. 8 , which is a first structural schematic diagram of the display panel provided by the embodiment of the present application.
  • the display panel 20 includes an array substrate 200 , a color filter substrate 400 and a liquid crystal layer 600 .
  • the array substrate 200 is the array substrate described in the embodiments of the above application.
  • FIG. 9 is a schematic diagram of a second structure of a display panel provided by an embodiment of the present application.
  • the color filter substrate 400 includes a CF common electrode line (CFCOM) 420 , the CF common electrode line (CFCOM) 420 is disposed outside the display area 210 , the CF common electrode line (CFCOM) 420 , the clock control bus (CK) 223 , the gate-on voltage
  • the control bus line (VGH) 224 and the common electrode line (ACOM) 225 are arranged in order from the outside of the display area 210 toward the direction of the display area 210 and are arranged in parallel.

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  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
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  • General Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
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  • Computer Hardware Design (AREA)
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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

本申请实施例提供一种阵列基板以及显示面板，阵列基板包括显示区域和复位信号线，所述复位信号线设置于所述显示区域，所述复位信号线在所述显示区域处于显示状态时保持在低电位，且在显示区域处于消隐状态时产生脉冲信号。本申请实施例的阵列基板通过将复位信号线设置于显示区域，相比于直接将复位信号线设置在阵列基板的周边边框区域，可以减小复位信号线对阵列基板的周边边框区域的占用，从而减窄阵列基板的周边边框区域。

Description

阵列基板以及显示面板 技术领域
本申请涉及显示技术领域，特别涉及一种阵列基板以及显示面板。
 背景技术
液晶显示装置(Liquid Crystal Display，LCD)，由于其具有机身轻薄、耗能少、工作电压低且无辐射等优点，在计算机屏幕、电视机屏幕、移动数字电话等领域得到了广泛的应用。
液晶显示装置通常具有栅极驱动电路，栅极驱动电路可产生扫描信号使得液晶显示装置实现显示扫描。
 技术问题
相关技术中，通常将栅极驱动电路设置在阵列基板的周边边框区域，使得液晶显示装置具有较大面积的边框区域。
 技术解决方案
本申请实施例提供一种阵列基板以及显示面板，可以减窄阵列基板的边框区域。
本申请实施例提供一种阵列基板，包括显示区域和复位信号线，所述复位信号线设置于所述显示区域，所述复位信号线在所述显示区域处于显示状态时保持在低电位，且在显示区域处于消隐状态时产生脉冲信号。
在本申请实施例的阵列基板中，所述阵列基板还包括多个呈阵列式排布的像素单元，所述多个像素单元设置于所述显示区域，所述多个像素单元呈阵列式排布，每一所述像素单元均具有暗纹区域，所述复位信号线的一部分位于至少一个所述像素单元的暗纹区域内。
在本申请实施例的阵列基板中，所述阵列基板包括多个GOA单元，所述多个GOA单元设置于所述显示区域的外侧，每一所述GOA单元均与所述复位信号线连接。
在本申请实施例的阵列基板中，所述阵列基板包括多个GOA单元，所述多个GOA单元设置于所述显示区域，每一所述GOA单元均与所述复位信号线连接。
在本申请实施例的阵列基板中，所述GOA单元包括第一晶体管和第二晶体管，所述第一晶体管和所述第二晶体管之间具有间隔区域，所述复位信号线的一部分位于所述间隔区域内，且所述复位信号线与所述第二晶体管的栅极连接。
在本申请实施例的阵列基板中，所述GOA单元还包括时钟信号线、栅开电压控制线和至少一条扫描线，所述时钟信号线、所述栅开电压控制线和至少一条扫描线均从所述显示区域延伸至所述显示区域的外侧。
在本申请实施例的阵列基板中，所述时钟信号线和所述栅开电压控制线相互平行设置。
在本申请实施例的阵列基板中，所述阵列基板还包括时钟控制总线、栅开电压控制总线和公共电极线，所述时钟控制总线、所述栅开电压控制总线和所述公共电极线设置于所述显示区域的外侧，且所述时钟控制总线与所述时钟信号线连接，所述栅开电压控制总线与所述栅开电压控制线连接。
在本申请实施例的阵列基板中，所述CF基板公共电极线、所述时钟控制总线、所述栅开电压控制总线和所述公共电极线从所述显示区域的外侧朝所述显示区域的方向依次排列且平行设置。
在本申请实施例的阵列基板中，所述显示区域包括相对设置的第一侧边和第二侧边，所述复位信号线的个数为两条，其中一条所述复位信号线靠近所述第一侧边设置，另一个所述复位信号线靠近所述第二侧边设置。
本申请实施例还提供一种显示面板，其包括如上申请实施例所述的阵列基板、彩膜基板和液晶层，所述彩膜基板设置于所述阵列基板的一侧，所述液晶层夹设于阵列基板和所述彩膜基板之间。
在本申请实施例的显示面板中，所述彩膜基板包括CF公共电极线，所述CF公共电极线设置于所述显示区域的外侧。
在本申请实施例的显示面板中，所述阵列基板还包括多个呈阵列式排布的像素单元，所述多个像素单元设置于所述显示区域，所述多个像素单元呈阵列式排布，每一所述像素单元均具有暗纹区域，所述复位信号线的一部分位于至少一个所述像素单元的暗纹区域内。
在本申请实施例的显示面板中，所述阵列基板包括多个GOA单元，所述多个GOA单元设置于所述显示区域的外侧，每一所述GOA单元均与所述复位信号线连接。
在本申请实施例的显示面板中，所述阵列基板包括多个GOA单元，所述多个GOA单元设置于所述显示区域，每一所述GOA单元均与所述复位信号线连接。
在本申请实施例的显示面板中，所述GOA单元包括第一晶体管和第二晶体管，所述第一晶体管和所述第二晶体管之间具有间隔区域，所述复位信号线的一部分位于所述间隔区域内，且所述复位信号线与所述第二晶体管的栅极连接。
在本申请实施例的显示面板中，所述GOA单元还包括时钟信号线、栅开电压控制线和至少一条扫描线，所述时钟信号线、所述栅开电压控制线和至少一条扫描线均从所述显示区域延伸至所述显示区域的外侧。
在本申请实施例的显示面板中，所述时钟信号线和所述栅开电压控制线相互平行设置。
在本申请实施例的显示面板中，所述阵列基板还包括时钟控制总线、栅开电压控制总线和公共电极线，所述时钟控制总线、所述栅开电压控制总线和所述公共电极线设置于所述显示区域的外侧，且所述时钟控制总线与所述时钟信号线连接，所述栅开电压控制总线与所述栅开电压控制线连接。
 有益效果
本申请实施例的阵列基板通过将复位信号线设置于显示区域，相比于直接将复位信号线设置在阵列基板的周边边框区域，可以减小复位信号线对阵列基板的周边边框区域的占用，从而减窄阵列基板的周边边框区域。
 附图说明
图1为本申请实施例提供的阵列基板的第一种结构示意图。
图2为本申请实施例提供的阵列基板的第二种结构示意图。
图3为图2所示阵列基板中像素单元以及GOA单元的结构示意图。
图4为本申请实施例提供的阵列基板的第三种结构示意图。
图5为图3所示像素单元以及GOA单元中GOA单元的结构示意图。
图6为本申请实施例提供的阵列基板的第四种结构示意图。
图7为本申请实施例提供的阵列基板的第五种结构示意图。
图8为本申请实施例提供的显示面板的第一种结构示意图。
图9为本申请实施例提供的显示面板的第二种结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请实施例提供一种阵列基板，其包括显示区域和复位信号线，所述复位信号线设置于所述显示区域，所述复位信号线在所述显示区域处于显示状态时保持在低电位，且在显示区域处于消隐状态时产生脉冲信号。
本申请的一种可选实施例中，所述阵列基板还包括多个呈阵列式排布的像素单元，所述多个像素单元设置于所述显示区域，所述多个像素单元呈阵列式排布，每一所述像素单元均具有暗纹区域，所述复位信号线的一部分位于至少一个所述像素单元的暗纹区域内。
本申请的一种可选实施例中，所述阵列基板包括多个GOA单元，所述多个GOA单元设置于所述显示区域的外侧，每一所述GOA单元均与所述复位信号线连接。
本申请的一种可选实施例中，所述阵列基板包括多个GOA单元，所述多个GOA单元设置于所述显示区域，每一所述GOA单元均与所述复位信号线连接。
本申请的一种可选实施例中，所述GOA单元包括第一晶体管和第二晶体管，所述第一晶体管和所述第二晶体管之间具有间隔区域，所述复位信号线的一部分位于所述间隔区域内，且所述复位信号线与所述第二晶体管的栅极连接。
本申请的一种可选实施例中，所述GOA单元还包括时钟信号线、栅开电压控制线和至少一条扫描线，所述时钟信号线、所述栅开电压控制线和至少一条扫描线均从所述显示区域延伸至所述显示区域的外侧。
本申请的一种可选实施例中，所述时钟信号线和所述栅开电压控制线相互平行设置。
本申请的一种可选实施例中，所述阵列基板还包括时钟控制总线、栅开电压控制总线和公共电极线，所述时钟控制总线、所述栅开电压控制总线和所述公共电极线设置于所述显示区域的外侧，且所述时钟控制总线与所述时钟信号线连接，所述栅开电压控制总线与所述栅开电压控制线连接。
本申请的一种可选实施例中，所述CF基板公共电极线、所述时钟控制总线、所述栅开电压控制总线和所述公共电极线从所述显示区域的外侧朝所述显示区域的方向依次排列且平行设置。
本申请的一种可选实施例中，所述显示区域包括相对设置的第一侧边和第二侧边，所述复位信号线的个数为两条，其中一条所述复位信号线靠近所述第一侧边设置，另一个所述复位信号线靠近所述第二侧边设置。
本申请的一种可选实施例中，所述GOA单元的个数为两个，一个所述GOA单元靠近所述第一侧边设置，所述另一个所述GOA单元靠近所述第二侧边设置。
本申请实施例还提供一种显示面板，其中，包括：
阵列基板，包括显示区域和复位信号线，所述复位信号线设置于所述显示区域，所述复位信号线在所述显示区域处于显示状态时保持在低电位，且在显示区域处于消隐状态时产生脉冲信号；
彩膜基板，设置于所述阵列基板的一侧；以及
液晶层，夹设于阵列基板和所述彩膜基板之间。
本申请的一种可选实施例中，所述彩膜基板包括CF公共电极线，所述CF公共电极线设置于所述显示区域的外侧。
本申请的一种可选实施例中，所述阵列基板还包括多个呈阵列式排布的像素单元，所述多个像素单元设置于所述显示区域，所述多个像素单元呈阵列式排布，每一所述像素单元均具有暗纹区域，所述复位信号线的一部分位于至少一个所述像素单元的暗纹区域内。
本申请的一种可选实施例中，所述阵列基板包括多个GOA单元，所述多个GOA单元设置于所述显示区域的外侧，每一所述GOA单元均与所述复位信号线连接。
本申请的一种可选实施例中，所述阵列基板包括多个GOA单元，所述多个GOA单元设置于所述显示区域，每一所述GOA单元均与所述复位信号线连接。
本申请的一种可选实施例中，所述GOA单元包括第一晶体管和第二晶体管，所述第一晶体管和所述第二晶体管之间具有间隔区域，所述复位信号线的一部分位于所述间隔区域内，且所述复位信号线与所述第二晶体管的栅极连接。
本申请的一种可选实施例中，所述GOA单元还包括时钟信号线、栅开电压控制线和至少一条扫描线，所述时钟信号线、所述栅开电压控制线和至少一条扫描线均从所述显示区域延伸至所述显示区域的外侧。
本申请的一种可选实施例中，所述时钟信号线和所述栅开电压控制线相互平行设置。
本申请的一种可选实施例中，所述阵列基板还包括时钟控制总线、栅开电压控制总线和公共电极线，所述时钟控制总线、所述栅开电压控制总线和所述公共电极线设置于所述显示区域的外侧，且所述时钟控制总线与所述时钟信号线连接，所述栅开电压控制总线与所述栅开电压控制线连接。
本申请实施例提供一种阵列基板，如图1所示，图1为本申请实施例提供的阵列基板的第一种结构示意图。阵列基板200可以包括显示区域210，显示区域210可以用于显示画面。可以理解的是，显示区域210为阵列基板200的有效显示区域(Active Area，AA)，显示区域210可以设置有像素阵列，像素阵列包括多个以矩阵方式排布的像素单元。
阵列基板200还可以包括GOA（Gate Driver on Array，阵列基板栅极驱动）电路220，GOA电路220是将采用GOA技术将驱动电路直接制造在阵列(Array)基板上所形成的电路结构。GOA电路220可以包括复位信号线221，复位信号线221设置于显示区域210，复位信号线221在显示区域210处于显示状态时（比如显示画面时）保持在低电位，且在显示区域210处于消隐状态时产生脉冲信号，以驱动GOA电路复位。一般在相邻两个显示帧之间会设置有消隐时间（Blanking time），复位信号线221在消隐时间产生脉冲信号，而在显示区域210处于显示状态时，复位信号线221始终处于低电位，避免对显示区域210所显示的帧画面产生影响，使得显示区域210可以正常显示。
相关技术中，通常将复位信号线221设置于显示区域210的外侧，或者说阵列基板200的非显示区域中，这样会导致阵列基板200的非显示区域的面积较大，从而使得阵列基板200的边框变宽。本申请实施例从实际应用出发，将GOA电路220中的复位信号线221设置于显示区域210，相比于相关技术，在阵列基板200的非显示区域中可以至少减少一根信号线的占用面积，从而缩小阵列基板200的非显示区域对阵列基板的占用面积，以达到减窄阵列基板200的边框的目的。
结合图2和图3所示，图2为本申请实施例提供的阵列基板的第二种结构示意图，图3为图2所示阵列基板中像素单元以及GOA单元的结构示意图。阵列基板200还可以包括多个像素单元230，多个像素单元230设置于显示区域210内，多个像素单元230呈阵列式排布设置，每一像素单元230均具有暗纹区域232，复位信号线221的一部分位于至少一个像素单元230的暗纹区域232内。
可以理解的是，由于受到TFT（Thin Film Transistor，薄膜晶体管）和CF（Color Filter，彩色滤光片）两侧的光配向和ITO（Indium Tin Oxide，铟锡氧化物）边缘电场的双重作用，像素单元230内部会形成一些配向暗纹区域。复位信号线221的一部分设置于至少一个像素单元230的暗纹区域232内，比如可以将复位信号线221的一部分设置于一个像素单元230、两个像素单元230、五个像素单元230或十个像素单元230的暗纹区域232内，并将其他部分设置于像素单元230的外部区域，比如相邻两个像素单元230之间的区域。本申请实施例中对复位信号线221穿设于多少个像素单元230的暗纹区域232并不予以限定。
请继续参阅图2，GOA电路220还可以包括多个GOA单元222，多个GOA单元222可以相互级联，多个GOA单元222均设置于显示区域210的外侧。显示区域210可以为规则形状，比如显示区域210可以为矩形形状，显示区域210可以具有相对设置的第一侧边212和第二侧边214，阵列基板200可以具有第一非显示区域240，第一非显示区域240设置于显示区域210的边缘且相对于第二侧边214靠近第一侧边212。多个GOA单元222均设置于第一非显示区域240，多个GOA单元222可以相互级联。
其中，每一GOA单元222均与复位信号线221连接，复位信号线221可以对GOA单元222进行控制，以控制GOA单元222复位。比如，每一GOA单元222可以均设置有复位信号端2221，每一GOA单元222通过复位信号端2221与复位信号线221连接，复位信号线221可以在显示区域210处于消隐状态时产生脉冲信号并通过复位信号端2221将该脉冲信号输入至GOA单元222中，以控制GOA单元222复位。
需要说明的是，GOA单元222的设置位置并不限于此，替代性地，比如，如图4所示，图4为本申请实施例提供的阵列基板的第三种结构示意图。多个GOA单元222可以设置于显示区域210内。多个GOA单元222可以相互级联。每一GOA单元222均与复位信号线221连接，复位信号线221可以对GOA单元222进行控制，以控制GOA单元222复位。
本申请实施例中，GOA电路220中的复位信号线221和GOA单元222均设置于显示区域210内，其可以直接在显示区域210内相互连接，相比于图3所示的阵列基板，本申请实施例可以减少显示区域210的开口率，而且还可以减少图3所示中GOA单元和复位信号线221之间的连接线，进而减少GOA电路220对显示区域210的占用空间，提升像素单元230的穿透率。
结合图3和图5所示，图5为图3所示像素单元以及GOA单元中GOA单元的结构示意图。GOA单元222可以包括多个晶体管，比如GOA单元222可以包括第一晶体管T1和第二晶体管T2，第一晶体管T1和第二晶体管T2间隔设置在显示区域210内，或者说第一晶体管T1和第二晶体管T2之间具有间隔区域2222，复位信号线221的一部分位于间隔区域2222内。比如复位信号线221可以穿设过像素单元230的暗纹区域232后，再在间隔区域2222走线至第二晶体管T2的位置，并与第二晶体管T2的栅极连接。
GOA单元还可以包括第三晶体管T3、第四晶体管T4，第五晶体管T51、第六晶体管T52、第七晶体管T53、第八晶体管T54、第九晶体管T6、第十晶体管T7、第十一晶体管T8和电容Cb。
其中，第一晶体管T1的栅极和第一晶体管T1的漏极均与第n-1级GOA单元222的扫描信号线G（n-1）连接以接收第n级GOA单元的扫描线的输入信号，第一晶体管T1的源极与第二晶体管T2的漏极以及第n级GOA单元222的节点Q(n)连接，第二晶体管T2的源极与电源负电压VSS连接。第五晶体管T51的栅极、第五晶体管T51的漏极和第七晶体管T53的漏极均与栅开电压控制线连接，第五晶体管T51的源极与第七晶体管T53的栅极连接，第七晶体管T53的源极与第八晶体管T54的漏极和第九晶体管T6的栅极连接，第八晶体管T54的栅极和第六晶体管T52的栅极均与第n级GOA单元222的节点Q(n)连接，第六晶体管T52的漏极与第七晶体管T53的栅极连接，第六晶体管T52的源极、第八晶体管T54的源极均与电源负电压VSS连接，第九晶体管T6的源极、第十晶体管T7的源极均与电源负电压VSS连接，第九晶体管T6的漏极与第n级GOA单元的扫描信号线G（n）连接以向扫描信号线G（n）输出信号，第十晶体管T7与栅极与第七晶体管T53的源极连接，第十晶体管T7的漏极与第n级GOA单元222的节点Q(n)连接，第三晶体管T3的栅极和第四晶体管T4的栅极均与第n+1级GOA单元222的扫描信号线G（n+1）连接以接收第n+1级GOA单元222的扫描线的输入信号，第三晶体管T3的源极和第四晶体管T4的源极均与电源负电压VSS连接，第三晶体管T3的漏极与第n级GOA单元的扫描信号线G（n）连接以向扫描信号线G（n）输出信号，第四晶体管T4的漏极与第n级GOA单元222的节点Q(n)连接，第十一晶体管T8的栅极与第四晶体管T4的漏极连接，第十一晶体管T8的漏极与第n级GOA单元222的时钟信号线CK（n）连接，第十一晶体管T8的源极与第n级GOA单元的扫描信号线G（n）连接以向扫描信号线G（n）输出信号，电容Cb并联连接在第十一晶体管T8的栅极和第十一晶体管T8的源极之间。
需要说明的是，图5所示的GOA单元222的电路结构仅为示例性的，本申请实施例的GOA单元222的电路结构也可以为其他结构。
请继续参阅图2和图3，GOA单元222还可以包括时钟信号线（CK）2225、栅开电压控制线（VGH）2226和至少一条扫描线2227（诸如扫描线G（n-1）、扫描线G（n）和扫描线G（n+1）），时钟信号线（CK）2225、栅开电压控制线（VGH）2226和至少一条扫描线2227相互平行设置。时钟信号线2225、栅开电压控制线（VGH）2226和至少一条扫描线2227均从显示区域210延伸至显示区域210的外侧（比如延伸至第一非显示区域240），并与其对应的信号线连接。以节省对显示区域210的占用空间。
例如，GOA电路220还可以包括时钟控制总线（CK）223和栅开电压控制总线（VGH）224，时钟控制总线（CK）223和栅开电压控制总线（VGH）224均设置于显示区域210的外侧，比如时钟控制总线（CK）223和栅开电压控制总线（VGH）224均可以设置在第一非显示区域240，且时钟控制总线（CK）223和栅开电压控制总线（VGH）224相互平行设置。其中时钟控制总线（CK）223可以传输时钟信号，其可以与每一GOA单元222的时钟信号线（CK）2225连接，以对每一GOA单元222进行控制，进而控制每一像素单元230可以根据时钟信号进行帧画面的显示。栅开电压控制总线（VGH）224可以用于传输栅开电压信号，其可以与每一GOA单元222的栅开电压控制线（VGH）2226连接，以对每一GOA单元222进行控制，该栅开电压信号可以为每一GOA单元222中的晶体管提供电压信号，以打开每一GOA单元222中的晶体管，从而控制像素单元230显示画面或不显示画面。
GOA电路220还包括公共电极线（ACOM）225，请继续参阅图2均设置于所述显示区域210的外侧（比如设置于第一非显示区域240）。其中，时钟控制总线（CK）223、栅开电压控制总线（VGH）224和公共电极线（ACOM）225从显示区域210的外侧朝显示区域210的方向依次排列设置，而且时钟控制总线（CK）223、栅开电压控制总线（VGH）224和公共电极线（ACOM）225从显示区域210相互平行设置，以减小GOA电路220的走线对显示区域210外侧（诸如第一非显示区域240）的占用空间，有利于减小显示区域210边缘区域（诸如第一非显示区域240）的面积，以起到减窄边框的效果。
如图6和图7所示，图6为本申请实施例提供的阵列基板的第四种结构示意图，图7为本申请实施例提供的阵列基板的第五种结构示意图。本申请实施例的GOA电路220的个数可以为两个，其中一个GOA电路220可以靠近第一侧边212设置，另一个GOA电路220可以靠近第二侧边214设置。比如阵列基板200可以包括显示区域210、第一非显示区域240和第二非显示区域250，第一非显示区域240设置在第一侧边212的边缘，第二非显示区域250设置在第二侧边214的边缘，其中一个GOA电路220设置于第一非显示区域240内，另一个GOA电路220设置于第二非显示区域250内，两个GOA电路220共同对多行像素单元230进行控制，比如其中一个GOA电路220可以负责控制奇数行的像素单元230，另一个GOA电路220可以负责控制偶数行的像素单元。相比于只在第一非显示区域240设置GOA电路，本申请实施例的设计方式更合理，也更方便走线。
可以理解的是，每一GOA电路220均包括一条复位信号线221，即本申请实施例的复位信号线221的条数为两条，其中一条复位信号线221设置于显示区域210中靠近第一侧边212的位置，另一条复位信号线221设置于显示区域中靠近所述第二侧边214的位置。
本申请实施例还提供一种显示面板，示例性地，如图8所示的显示面板20，图8为本申请实施例提供的显示面板的第一种结构示意图。显示面板20包括阵列基板200、彩膜基板400和液晶层600，彩膜基板400设置于阵列基板200的一侧，液晶层600夹设于阵列基板200和彩膜基板400之间。阵列基板200为如上申请实施例所述的阵列基板。
如图9所示，图9为本申请实施例提供的显示面板的第二种结构示意图。彩膜基板400包括CF公共电极线（CFCOM）420，CF公共电极线（CFCOM）420设置于显示区域210的外侧，CF公共电极线（CFCOM）420、时钟控制总线（CK）223、栅开电压控制总线（VGH）224和公共电极线（ACOM）225从显示区域210的外侧朝显示区域210的方向依次排列且平行设置。
以上对本申请实施例提供的阵列基板以及显示面板进行了详细介绍。本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请。同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种阵列基板，其中，包括显示区域和复位信号线，所述复位信号线设置于所述显示区域，所述复位信号线在所述显示区域处于显示状态时保持在低电位，且在显示区域处于消隐状态时产生脉冲信号。
  2. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括多个呈阵列式排布的像素单元，所述多个像素单元设置于所述显示区域，所述多个像素单元呈阵列式排布，每一所述像素单元均具有暗纹区域，所述复位信号线的一部分位于至少一个所述像素单元的暗纹区域内。
  3. 根据权利要求2所述的阵列基板，其中，所述阵列基板包括多个GOA单元，所述多个GOA单元设置于所述显示区域的外侧，每一所述GOA单元均与所述复位信号线连接。
  4. 根据权利要求2所述的阵列基板，其中，所述阵列基板包括多个GOA单元，所述多个GOA单元设置于所述显示区域，每一所述GOA单元均与所述复位信号线连接。
  5. 根据权利要求4所述的阵列基板，其中，所述GOA单元包括第一晶体管和第二晶体管，所述第一晶体管和所述第二晶体管之间具有间隔区域，所述复位信号线的一部分位于所述间隔区域内，且所述复位信号线与所述第二晶体管的栅极连接。
  6. 根据权利要求5所述的阵列基板，其中，所述GOA单元还包括时钟信号线、栅开电压控制线和至少一条扫描线，所述时钟信号线、所述栅开电压控制线和至少一条扫描线均从所述显示区域延伸至所述显示区域的外侧。
  7. 根据权利要求6所述的阵列基板，其中，所述时钟信号线和所述栅开电压控制线相互平行设置。
  8. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括时钟控制总线、栅开电压控制总线和公共电极线，所述时钟控制总线、所述栅开电压控制总线和所述公共电极线设置于所述显示区域的外侧，且所述时钟控制总线与所述时钟信号线连接，所述栅开电压控制总线与所述栅开电压控制线连接。
  9. 根据权利要求8所述的阵列基板，其中，所述CF基板公共电极线、所述时钟控制总线、所述栅开电压控制总线和所述公共电极线从所述显示区域的外侧朝所述显示区域的方向依次排列且平行设置。
  10. 根据权利要求3所述的阵列基板，其中，所述显示区域包括相对设置的第一侧边和第二侧边，所述复位信号线的个数为两条，其中一条所述复位信号线靠近所述第一侧边设置，另一个所述复位信号线靠近所述第二侧边设置。
  11. 根据权利要求10所述的阵列基板，其中，所述GOA单元的个数为两个，一个所述GOA单元靠近所述第一侧边设置，所述另一个所述GOA单元靠近所述第二侧边设置。
  12. 一种显示面板，其中，包括：
    阵列基板，包括显示区域和复位信号线，所述复位信号线设置于所述显示区域，所述复位信号线在所述显示区域处于显示状态时保持在低电位，且在显示区域处于消隐状态时产生脉冲信号；
    彩膜基板，设置于所述阵列基板的一侧；以及
    液晶层，夹设于阵列基板和所述彩膜基板之间。
  13. 根据权利要求12所述的显示面板，其中，所述彩膜基板包括CF公共电极线，所述CF公共电极线设置于所述显示区域的外侧。
  14. 根据权利要求12所述的显示面板，其中，所述阵列基板还包括多个呈阵列式排布的像素单元，所述多个像素单元设置于所述显示区域，所述多个像素单元呈阵列式排布，每一所述像素单元均具有暗纹区域，所述复位信号线的一部分位于至少一个所述像素单元的暗纹区域内。
  15. 根据权利要求14所述的显示面板，其中，所述阵列基板包括多个GOA单元，所述多个GOA单元设置于所述显示区域的外侧，每一所述GOA单元均与所述复位信号线连接。
  16. 根据权利要求14所述的显示面板，其中，所述阵列基板包括多个GOA单元，所述多个GOA单元设置于所述显示区域，每一所述GOA单元均与所述复位信号线连接。
  17. 根据权利要求16所述的显示面板，其中，所述GOA单元包括第一晶体管和第二晶体管，所述第一晶体管和所述第二晶体管之间具有间隔区域，所述复位信号线的一部分位于所述间隔区域内，且所述复位信号线与所述第二晶体管的栅极连接。
  18. 根据权利要求17所述的显示面板，其中，所述GOA单元还包括时钟信号线、栅开电压控制线和至少一条扫描线，所述时钟信号线、所述栅开电压控制线和至少一条扫描线均从所述显示区域延伸至所述显示区域的外侧。
  19. 根据权利要求18所述的显示面板，其中，所述时钟信号线和所述栅开电压控制线相互平行设置。
  20. 根据权利要求12所述的显示面板，其中，所述阵列基板还包括时钟控制总线、栅开电压控制总线和公共电极线，所述时钟控制总线、所述栅开电压控制总线和所述公共电极线设置于所述显示区域的外侧，且所述时钟控制总线与所述时钟信号线连接，所述栅开电压控制总线与所述栅开电压控制线连接。
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