WO2022082919A1 - 基于布谷鸟算法的自适应抗老化传感器 - Google Patents

基于布谷鸟算法的自适应抗老化传感器 Download PDF

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WO2022082919A1
WO2022082919A1 PCT/CN2020/130804 CN2020130804W WO2022082919A1 WO 2022082919 A1 WO2022082919 A1 WO 2022082919A1 CN 2020130804 W CN2020130804 W CN 2020130804W WO 2022082919 A1 WO2022082919 A1 WO 2022082919A1
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terminal
voltage
output
circuit
output terminal
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PCT/CN2020/130804
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English (en)
French (fr)
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汪鹏君
张海明
张跃军
李刚
陈博
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温州大学
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Priority to US17/801,799 priority Critical patent/US11722131B2/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/14—Modifications for compensating variations of physical values, e.g. of temperature
    • H03K17/145—Modifications for compensating variations of physical values, e.g. of temperature in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/02—Details
    • H03B5/04—Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/08—Output circuits
    • H03K21/12—Output circuits with parallel read-out
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop

Definitions

  • the invention relates to an anti-aging sensor, in particular to an adaptive anti-aging sensor based on a cuckoo algorithm.
  • the integrated circuit (IC) process has entered the deep sub-micron stage, which has significant advantages in performance and area.
  • the parasitic effects that can be ignored become more and more serious, which aggravates the aging of integrated circuits.
  • the aging effect has an increasingly prominent impact on the reliability of integrated circuits.
  • the threshold voltage of transistors in the integrated circuit increases, the switching speed of logic gates slows down, and the delay increases, which in turn leads to timing violations and failure of integrated circuits.
  • the Negative Bias Temperature Instability (NBTI) NBTI has become a key factor causing the aging effect.
  • Stable performance is a key indicator of the reliability of IC equipment. Therefore, maintaining the excellent performance of the integrated circuit in the normal life and delaying the aging of the integrated circuit are the key technologies that need to be realized urgently under the current nanotechnology.
  • Document 1 "Gate recognition algorithm for anti-aging gate replacement technology” proposes a key gate recognition algorithm and applies it to the gate replacement technology in the anti-aging scheme, and obtains the signal duty cycle and internal signal through the logic simulation of the circuit netlist node information, and determine the anti-aging effect brought by gate replacement to identify key gates, and obtain a set of key gates that meet the requirements for replacement, so as to improve the anti-aging capability of the integrated circuit.
  • this method requires that the key gates need to be replaced at the beginning of the design on the basis of satisfying the timing margin, and different timing margins correspond to different sets of key gates, so the positions, quantities and types of key gates corresponding to different aging degrees are also different. , can not meet the aging repair of integrated circuits under different aging degrees, and the scope of application is limited.
  • the voltage-controlled oscillator in the integrated circuit has always been in a high-frequency working state, which is more prone to aging than other circuit modules in the integrated circuit, which in turn leads to the degradation of the performance of the entire integrated circuit, or even failure. Therefore, the aging degree of the integrated circuit can be reflected by monitoring the aging degree of the voltage-controlled oscillator, and repairing the aging state of the voltage-controlled oscillator can slow down the aging of the integrated circuit, and finally achieve the purpose of anti-aging of the integrated circuit.
  • the technical problem to be solved by the present invention is to provide an adaptive anti-aging sensor based on the cuckoo algorithm.
  • the adaptive anti-aging sensor reflects the aging degree of the integrated circuit by monitoring the aging degree of the voltage-controlled oscillator in the integrated circuit, and can According to the aging state of the voltage-controlled oscillator in the integrated circuit, the optimal operating voltage of the voltage-controlled oscillator in the integrated circuit is adaptively adjusted, and the adaptive aging repair of the voltage-controlled oscillator in the integrated circuit can meet the requirements of integration under different aging degrees.
  • the repair of circuit aging can finally achieve the purpose of anti-aging of integrated circuits, and has a wide range of applications.
  • an adaptive anti-aging sensor based on the cuckoo algorithm comprising a control module, a reference voltage-controlled oscillator, two shaping circuits with the same structure, a frequency difference circuit, a resolution A regulating circuit, a 16-bit counter, a parallel-to-serial circuit, an adaptive module and a digital-to-analog converter;
  • the control module has a feedback terminal, a first voltage output terminal, a second voltage output terminal and a control signal output terminal.
  • the reference voltage controlled oscillator and each of the shaping circuits respectively have an input terminal and an output terminal
  • the frequency difference circuit has a digital terminal, a clock terminal and an output terminal
  • the resolution adjustment circuit has an input terminal and an output terminal.
  • the 16-bit counter has a set terminal, a reset terminal and a 16-bit parallel output terminal
  • the adaptive module has a control terminal, a 16-bit parallel input terminal and a 16-bit parallel output terminal
  • the The digital-to-analog converter has a 16-bit parallel input terminal and an output terminal
  • the parallel-to-serial module has a clock terminal, a 16-bit parallel input terminal and an output terminal.
  • the two described shaping circuits are respectively referred to as the first shaping circuit and the The second shaping circuit
  • the voltage-controlled oscillator in the integrated circuit is called the voltage-controlled oscillator under test
  • the reference voltage-controlled oscillator is exactly the same as the voltage-controlled oscillator under test
  • the first voltage of the control module The output end is used to connect the input end of the voltage controlled oscillator under test
  • the second voltage output end of the control module is connected to the input end of the reference voltage controlled oscillator
  • the control signal output end of the control module are respectively connected with the control end of the resolution adjusting circuit and the control end of the adaptive module
  • the input end of the first shaping circuit is used to connect the output end of the voltage-controlled oscillator under test
  • the The output end of the reference voltage controlled oscillator is connected to the input end of the second shaping circuit
  • the output end of the first shaping circuit is connected to the number-setting end of the frequency difference circuit
  • the second shaping circuit The output end of the circuit is respectively connected with the clock end of the frequency difference circuit
  • the input end of the resolution adjustment circuit is connected, the output end of the resolution adjustment circuit is connected with the reset end of the 16-bit counter, and the 16-bit parallel output end of the 16-bit counter is respectively connected with the
  • the 16-bit parallel input terminal of the parallel-to-serial module is connected with the 16-bit parallel input terminal of the adaptive module, and the 16-bit parallel output terminal of the adaptive module is connected with the 16-bit parallel input terminal of the digital-to-analog converter.
  • the output end of the digital-to-analog converter is connected with the feedback end of the control module;
  • the control module generates two voltage signals and one level control signal, wherein the first voltage signal is the aging voltage signal VDC, which is output through the first voltage output terminal, and the second voltage signal is the reference voltage signal VDD, which is output through the first voltage output terminal. Its second voltage output terminal outputs, the level control signal is high level or low level, output through its control signal output terminal, the initial state of the level control signal is low level, the aging voltage signal VDC passes through the
  • the voltage-controlled oscillator generates an aging frequency signal A
  • the reference voltage signal VDD passes through the reference voltage-controlled oscillator to generate a reference frequency signal B
  • the aging frequency signal A is shaped by the first shaping circuit to obtain a first frequency signal f ctr
  • the reference frequency signal B is shaped by the second shaping circuit to obtain the second frequency signal f ref
  • the frequency difference circuit obtains the beat frequency signal f out by comparing the first frequency signal f ctr and the second frequency signal f ref
  • the frequency signal f out is the
  • the 16-bit parallel data Q0-Q15 is output at its 16-bit parallel output terminal, and the parallel-to-serial circuit converts the 16-bit parallel data Q0-Q1 output by the 16-bit counter under the action of the first frequency signal f ref Q15 is converted into serial data Q[0:15] and output at its output;
  • the self-adaptive module is pre-stored with a look-up table, and the look-up table is obtained by artificially simulating the aging process of the voltage-controlled oscillator under test by simulating the self-adaptive anti-aging sensor.
  • the specific simulation process is: The first voltage output end is connected with the input end of the voltage-controlled oscillator under test, the input end of the first shaping circuit is connected with the output end of the voltage-controlled oscillator under test, and the parameters of the voltage-controlled oscillator under test and the reference voltage-controlled oscillator are connected.
  • the parameters of the oscillator are initialized and set: the threshold voltage VTP of the PMOS transistor is 0.7V, the threshold voltage VTN of the NMOS transistor is 0.3V, and the process parameter ⁇ of the PMOS and NMOS transistors is 0.9, and then the measured voltage control is determined by the Cadence software.
  • the delay time Time of the oscillator under different parameters.
  • the parameters of the reference VCO always keep the initial value unchanged, and the adjustment range of the threshold voltage V TP of the PMOS transistor of the VCO under test is 0.6V -0.8V, the single adjustment amount is 1mV, the adjustment range of the threshold voltage V TN of the NMOS transistor is 0.2V-0.4V, the single adjustment amount is 1mV, the adjustment range of the process parameter ⁇ of the PMOS and NMOS transistors is 0.8-1, The single adjustment amount is 0.001.
  • the aging voltage signal VDC and the reference voltage signal VDD are both set to 1.2V.
  • the level control signal S output by the control module is low level, and the 16-bit counter is determined at this time.
  • decimal value corresponding to the output 16-bit parallel output signal Q0-Q15 is less than 40, if it is less than 40, keep other conditions unchanged, adjust the level control signal S to a high level, and record the 16 output of the 16-bit counter at this time.
  • Bit parallel output signal Q0-Q15 if it is greater than or equal to 40, directly record the 16-bit parallel output signal Q0-Q15 output by the 16-bit counter at this time, and use the 16-bit parallel output signal Q0-Q15 output by the currently recorded 16-bit counter as An index address of the look-up table, and the corresponding threshold voltage V TP , the threshold voltage V TN and the process parameters ⁇ of the PMOS and NMOS transistors are stored in the look-up table as the storage data of the index address at this time, and the above determination process is repeated.
  • the index addresses in the look-up table described at this time have 301, which are respectively 16-bit binary data corresponding to 0 to 300;
  • the adaptive module When the 16-bit parallel data Q0-Q15 output by the 16-bit counter is input into the adaptive module, the adaptive module first obtains the 16-bit parallel data whose index address is currently input in the lookup table The stored data V TP , V TN , ⁇ and Time of Q0-Q15, and then based on the obtained data V TP , V TN , ⁇ and Time, the Cuckoo algorithm is used to determine the current optimal working voltage of the voltage-controlled oscillator under test.
  • step C-5 Determine whether Diff s [i] is equal to 0 or whether s is equal to 1000. If one of them is satisfied, the global optimal solution V after the s-th iteration is taken as the optimal working voltage V DC 0-V DC 15 from The 16-bit parallel output terminal of the described adaptive module is output, and the iterative process ends, and if both are not satisfied, then enter step C-6;
  • the digital-to-analog converter converts the optimal working voltage V DC 0-V DC 15 output by the adaptive module into an analog voltage and outputs it to the feedback terminal of the control module, and the control module converts its first
  • the size of the aging voltage signal VDC output by an output terminal is adjusted to the size of the analog voltage output by the output terminal of the analog-to-digital converter.
  • Each of the shaping circuits respectively includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor and a first inverter; the source of the first PMOS transistor and the first The sources of the two PMOS transistors are all connected to the power supply, the gate of the first PMOS transistor, the drain of the second PMOS transistor and the drain of the second NMOS transistor are connected and the connection ends are The output end of the shaping circuit, the drain of the first PMOS transistor, the gate of the second PMOS transistor are connected to the drain of the first NMOS transistor, and the drain of the first NMOS transistor is connected.
  • the gate is connected to the input end of the first inverter and the connection end is the input end of the shaping circuit, the output end of the first inverter and the gate of the second NMOS transistor
  • the source electrode of the first NMOS transistor and the source electrode of the second NMOS transistor are both grounded.
  • the frequency difference circuit is realized by a first D flip-flop, the first D flip-flop has an input terminal, a clock terminal and an output terminal, and the input terminal of the first D flip-flop is the frequency difference circuit
  • the set terminal of the first D flip-flop is the clock terminal of the frequency difference circuit
  • the output terminal of the first D flip-flop is the output terminal of the frequency difference circuit.
  • the resolution adjustment circuit includes a first two-to-one selector, a second D flip-flop and a third D flip-flop, and the first two-to-one selector has a first input end, a second input end, a selection terminal and output terminal, the second D flip-flop and the third D flip-flop respectively have an input terminal, a clock terminal, an output terminal and an inverting output terminal; the input terminal of the second D flip-flop and The inverting output terminal of the second D flip-flop is connected, the clock terminal of the second D flip-flop is the input terminal of the resolution adjusting circuit, the output terminal of the second D flip-flop, The clock terminal of the third D flip-flop is connected to the first input terminal of the first two-to-one selector, and the input terminal of the third D flip-flop is connected to the input terminal of the third D flip-flop.
  • the inverting output terminal is connected, the output terminal of the third D flip-flop is connected to the second input terminal of the first two-to-one selector, and the selection terminal of the first two-to-one selector is the The control end of the resolution adjusting circuit, and the output end of the first two-to-one selector is the output end of the resolution adjusting circuit.
  • the 16-bit counter includes 16 D flip-flops and 16 inverters, each of the D flip-flops has an input terminal, a clock terminal, a reset terminal and an output terminal, respectively.
  • the reset terminal is connected and its connection terminal is the reset terminal of the 16-bit counter
  • the output terminals of the h D flip-flops, the input terminals of the h th inverter are connected to the clock terminal of the h+1 th D flip-flop
  • the first output terminal to the sixteenth output terminal of the 16-bit counter constitute the 16-bit parallel output terminal of the 16-bit counter.
  • the present invention has the advantages of using a control module, a reference voltage-controlled oscillator, two shaping circuits with the same structure, a frequency difference circuit, a resolution adjusting circuit, a 16-bit counter, a parallel-to-serial circuit, and an adaptive circuit.
  • the module and the digital-to-analog converter build an adaptive anti-aging sensor.
  • the adaptive module is pre-stored with a look-up table.
  • the look-up table is obtained by artificially simulating the aging process of the voltage-controlled oscillator under test by simulating the adaptive anti-aging sensor.
  • the adaptive module When the voltage-controlled oscillator is used for aging monitoring, when the 16-bit parallel data Q0-Q15 output by the 16-bit counter is input into the adaptive module, the adaptive module first obtains the 16-bit parallel data whose index address is currently input in the look-up table.
  • the size of the aging voltage signal VDC output by the first output terminal is adjusted to the size of the analog voltage output by the output terminal of the analog-to-digital converter, thereby changing the input voltage of the voltage-controlled oscillator of the integrated circuit.
  • the sensor reflects the aging degree of the integrated circuit by monitoring the aging degree of the voltage-controlled oscillator in the integrated circuit, and can adaptively adjust the optimal working voltage of the voltage-controlled oscillator in the integrated circuit according to the aging state of the voltage-controlled oscillator in the integrated circuit.
  • the self-adaptive aging repair of the voltage-controlled oscillator in the integrated circuit can meet the aging repair of the integrated circuit under different aging degrees, and finally achieve the purpose of anti-aging of the integrated circuit, and has a wide range of applications.
  • Fig. 1 is the structural block diagram of the adaptive anti-aging sensor based on the cuckoo algorithm of the present invention
  • Fig. 2 is the circuit diagram of the shaping circuit of the adaptive anti-aging sensor based on the cuckoo algorithm of the present invention
  • Fig. 3 is the circuit diagram of the frequency difference circuit of the adaptive anti-aging sensor based on the cuckoo algorithm of the present invention
  • Fig. 4 is the circuit diagram of the resolution adjustment circuit of the adaptive anti-aging sensor based on the cuckoo algorithm of the present invention
  • Fig. 5 is the circuit diagram of the 16-bit counter of the adaptive anti-aging sensor based on the cuckoo algorithm of the present invention
  • FIG. 6 is a simulation diagram of the adaptive anti-aging sensor based on the cuckoo algorithm of the present invention.
  • an adaptive anti-aging sensor based on the cuckoo algorithm includes a control module, a reference voltage-controlled oscillator, two shaping circuits with the same structure, a frequency difference circuit, a resolution adjustment circuit, 16 A bit counter, a parallel-to-serial circuit, an adaptive module and a digital-to-analog converter;
  • the control module has a feedback terminal, a first voltage output terminal, a second voltage output terminal and a control signal output terminal, a reference voltage controlled oscillator and each shaping circuit It has an input terminal and an output terminal respectively.
  • the frequency difference circuit has a number setting terminal, a clock terminal and an output terminal.
  • the resolution adjusting circuit has an input terminal, an output terminal and a control terminal.
  • the 16-bit counter has a number setting terminal, a reset terminal and a 16-bit parallel terminal.
  • Output terminal the adaptive module has a control terminal, a 16-bit parallel input terminal and a 16-bit parallel output terminal
  • the digital-to-analog converter has a 16-bit parallel input terminal and an output terminal
  • the parallel-to-serial module has a clock terminal, 16-bit parallel input terminal and
  • the two shaping circuits are respectively called the first shaping circuit and the second shaping circuit
  • the voltage-controlled oscillator in the integrated circuit is called the measured voltage-controlled oscillator
  • the reference voltage-controlled oscillator and the measured voltage-controlled oscillator The first voltage output terminal of the control module is used to connect the input terminal of the voltage controlled oscillator under test
  • the second voltage output terminal of the control module is connected to the input terminal of the reference voltage controlled oscillator
  • the control signal output of the control module The terminals are respectively connected with the control terminal of the resolution adjustment circuit and the control terminal of the adaptive module.
  • the input terminal of the first shaping circuit is used to connect the output terminal of the voltage-controlled oscillator under test, the output terminal of the reference voltage-controlled oscillator and the second
  • the input terminal of the shaping circuit is connected, the output terminal of the first shaping circuit is connected to the number-setting terminal of the frequency difference circuit, and the output terminal of the second shaping circuit is respectively connected to the clock terminal of the frequency difference circuit, the clock terminal of the parallel-to-serial module and the 16-bit
  • the set terminal of the counter is connected, the output terminal of the frequency difference circuit is connected to the input terminal of the resolution adjustment circuit, the output terminal of the resolution adjustment circuit is connected to the reset terminal of the 16-bit counter, and the 16-bit parallel output terminal of the 16-bit counter is respectively connected with
  • the 16-bit parallel input terminal of the parallel-to-serial module is connected to the 16-bit parallel input terminal of the adaptive module, the 16-bit parallel output terminal of the adaptive module is connected to the 16-bit parallel input terminal of the digital-to-analog converter, and the output
  • the terminal is connected to the feedback terminal of the control module; the control module generates two voltage signals and one level control signal, wherein the first voltage signal is the aging voltage signal VDC, which is output through its first voltage output terminal, and the second voltage signal is The reference voltage signal VDD is output through its second voltage output terminal, the level control signal is high level or low level, and is output through its control signal output terminal, the initial state of the level control signal is low level, and the aging voltage signal VDC passes through the measured voltage-controlled oscillator to generate the aging frequency signal A, the reference voltage signal VDD passes through the reference voltage-controlled oscillator to generate the reference frequency signal B, and the aging frequency signal A is shaped by the first shaping circuit to obtain the first frequency signal f ctr , the reference The frequency signal B is shaped by the second shaping circuit to obtain the second frequency signal f ref , and the frequency difference circuit compares the first frequency signal f ctr with the second frequency signal f ref obtains the beat signal f out , the beat signal f out is the
  • Frequency division signal when the level control signal connected to the control terminal of the resolution adjustment circuit is high, the set signal rst is a 4-frequency division signal of the beat frequency signal f out , and the reset terminal of the 16-bit counter is connected to set Signal rst, the 16-bit counter counts the number of the second frequency signal f ref connected to its set terminal within the period of the set signal rst, and then the count value is 16-bit parallel data Q0-Q15 in binary form in its 16-bit
  • the parallel output terminal outputs, and the parallel-to-serial circuit converts the 16-bit parallel data Q0-Q15 output by the 16-bit counter into serial data Q[0:15] under the action of the first frequency signal f ref and outputs at its output terminal;
  • a look-up table is pre-stored in the adaptive module, and the look-up table is obtained by simulating the aging process of the voltage-controlled oscillator under test artificially by simulating the adaptive anti-aging sensor.
  • the input end of the voltage controlled oscillator is connected, the input end of the first shaping circuit is connected with the output end of the voltage controlled oscillator under test, and the parameters of the voltage controlled oscillator under test and the parameters of the reference voltage controlled oscillator are initialized and set: PMOS
  • the threshold voltage V TP of the transistor is 0.7V
  • the threshold voltage V TN of the NMOS transistor is 0.3V
  • the process parameter ⁇ of the PMOS and NMOS transistors is 0.9
  • the Cadence software is used to measure the delay time of the VCO under different parameters.
  • the adjustment range of the threshold voltage V TP of the PMOS transistor of the voltage-controlled oscillator under test is 0.6V-0.8V
  • the single adjustment amount is 1mV
  • the adjustment range of the threshold voltage V TN of the NMOS transistor is 0.2V-0.4V
  • the single adjustment is 1mV
  • the adjustment range of the process parameter ⁇ of the PMOS and NMOS transistors is 0.8-1
  • the single adjustment is 0.001
  • both the aging voltage signal VDC and the reference voltage signal VDD are set to 1.2V
  • the level control signal S output by the control module is set to a low level, and it is determined that the 16-bit parallel output signal Q0- Whether the decimal value corresponding to Q15 is less than 40, if it is less than 40, keep other conditions unchanged, adjust the level control signal S to high level and record the 16-bit parallel output signals Q0-Q15 output by the 16-bit counter at this time,
  • the self-adaptive module When the 16-bit parallel data Q0-Q15 output by the 16-bit counter is input into the self-adaptive module, the self-adaptive module first obtains in the look-up table the stored data V TP whose index address is the 16-bit parallel data Q0-Q15 currently input into it, V TN , ⁇ and Time, and then based on the acquired data V TP , V TN , ⁇ and Time using the cuckoo algorithm to determine the current optimal working voltage of the voltage-controlled oscillator under test, the specific process is as follows:
  • step C-5 Determine whether Diff s [i] is equal to 0 or whether s is equal to 1000. If one of them is satisfied, the global optimal solution V after the s-th iteration is taken as the optimal working voltage V DC 0-V DC 15 from The 16-bit parallel output terminal of the adaptive module is output, and the iterative process ends. If both are not satisfied, enter step C-6;
  • the digital-to-analog converter converts the optimal working voltage V DC 0-V DC 15 output by the adaptive module into an analog voltage and outputs it to the feedback terminal of the control module, and the control module adjusts the size of the aging voltage signal VDC output by its first output terminal to The magnitude of the analog voltage output at the output of the analog-to-digital converter.
  • each shaping circuit includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, and a first inverter A1; the first The source of the PMOS transistor P1 and the source of the second PMOS transistor P2 are both connected to the power supply, the gate of the first PMOS transistor P1, the drain of the second PMOS transistor P2 and the drain of the second NMOS transistor N2 are connected and connected The terminal is the output terminal of the shaping circuit, the drain of the first PMOS transistor P1, the gate of the second PMOS transistor P2 and the drain of the first NMOS transistor N1 are connected, and the gate of the first NMOS transistor N1 is connected to the first inverter
  • the input end of A1 is connected and its connection end is the input end of the shaping circuit, the output end of the first inverter A1 is connected to the gate of the second NMOS transistor N2, and the source of the first NMOS transistor N1 is connected to the second
  • the frequency difference circuit is implemented by a first D flip-flop DFF1
  • the first D flip-flop DFF1 has an input terminal, a clock terminal and an output terminal
  • the input terminal of the first D flip-flop DFF1 is a frequency
  • the set terminal of the difference circuit, the clock terminal of the first D flip-flop DFF1 is the clock terminal of the frequency difference circuit, and the output terminal of the first D flip-flop DFF1 is the output terminal of the frequency difference circuit.
  • the resolution adjustment circuit includes a first one-of-two selector MUX1, a second D-flip-flop DFF2 and a third D-flip-flop DFF3, and the first-two selector MUX1 has a first An input end, a second input end, a selection end and an output end, the second D flip-flop DFF2 and the third D flip-flop DFF3 respectively have an input end, a clock end, an output end and an inverting output end;
  • the input terminal is connected to the inverted output terminal of the second D flip-flop DFF2, the clock terminal of the second D flip-flop DFF2 is the input terminal of the resolution adjustment circuit, the output terminal of the second D flip-flop DFF2, the third D flip-flop DFF3
  • the clock terminal is connected to the first input terminal of the first two-to-one selector MUX1, the input terminal of the third D flip-flop DFF3 is connected to the inverting output terminal of the third D flip-flop DFF3, and the
  • the terminal is connected with the second input terminal of the first two-to-one selector MUX1, the selection terminal of the first two-to-one selector MUX1 is the control terminal of the resolution adjustment circuit, and the output terminal of the first two-to-one selector MUX1 is the resolution the output of the rate adjustment circuit.
  • the 16-bit counter includes 16 D flip-flops DFF4-DFF19 and 16 inverters A2-A17, and each D flip-flop has an input terminal, a clock terminal, a reset terminal and an output respectively.
  • the reset terminal of the 16 D flip-flops is connected and the connection terminal is the reset terminal of the 16-bit counter
  • f ctr is the output obtained after the aging frequency generated by the measured VCO is shaped by the first shaping circuit
  • f ref is the output obtained after the reference frequency generated by the reference VCO is shaped by the first shaping circuit
  • OUT ⁇ 1>, OUT ⁇ 2>, ..., OUT ⁇ 9> are the 16-bit parallel data output by the 16-bit counter respectively
  • Z ⁇ 1>, Z ⁇ 2>, ..., Z ⁇ 9> are the adaptive modules respectively
  • the optimal working voltage of the output, V OUT is the analog voltage output by the digital-to-analog converter after digital-to-analog conversion.
  • Fig. 6 shows that the aging monitoring and repairing process is roughly divided into two stages: the first stage: the adaptive module provides the optimal adjustment voltage required to restore its performance according to the current aging degree of the voltage-controlled oscillator under test (that is, the most The second stage: adjust the voltage of the voltage-controlled oscillator under test according to the optimal adjustment voltage, so as to realize the adaptive repair of the performance degradation of the integrated circuit caused by the aging effect.
  • the specific simulation process is as follows: in the simulation state, the reference VCO generates a reference frequency signal of 500M, and the VCO under test generates an aging frequency signal of 490M.
  • the VCO under test has 2 % frequency degradation
  • the decimal number corresponding to the 16-bit data output by the 16-bit parallel output terminal of the 16-bit counter is 80, that is, the output of the 16-bit counter is 80, and the output of the 16-bit counter is used as the input of the adaptive module.
  • the bird algorithm is optimized to obtain the optimal working voltage of 1.28V under the current aging state, and the optimal working voltage is output to the control module as the feedback voltage of the voltage-controlled oscillator under test, and the control module adjusts the work of the voltage-controlled oscillator under test accordingly.
  • the output of the 16-bit counter is 275 at this time, the output frequency of the voltage-controlled oscillator under test is 499.2M, and the frequency of the reference voltage-controlled oscillator is downgraded to 0.16%, and the output voltage is 1.23V.
  • the simulation results show that the aging frequency output of the tested voltage-controlled oscillator optimized by the adaptive algorithm increases, the performance of the integrated circuit recovers significantly, and the adaptive anti-aging function of the integrated circuit can be realized.

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Abstract

一种基于布谷鸟算法的自适应抗老化传感器，包括控制模块、参考压控振荡器、两个整形电路、频差电路、分辨率调节电路、16位计数器、并转串电路、自适应模块和数模转换器，自适应模块内预存有查找表，在对集成电路的压控振荡器进行老化监测时，自适应模块采用布谷鸟算法确定当前被测压控振荡器的最优工作电压，控制模块据此改变集成电路的压控振荡器的输入电压；优点是通过监测集成电路中压控振荡器的老化程度来反映集成电路的老化程度，并自适应去调整集成电路中压控振荡器的最优工作电压，对集成电路中压控振荡器的进行自适应老化修复，能够满足不同老化程度下集成电路老化的修复，最终实现集成电路抗老化的目的，应用范围广。

Description

基于布谷鸟算法的自适应抗老化传感器 技术领域
本发明涉及一种抗老化传感器，尤其是涉及一种基于布谷鸟算法的自适应抗老化传感器。
背景技术
随着半导体技术的发展，集成电路(Integrated Circuit,IC)工艺进入深亚微米阶段，在性能和面积等方面具有显著的优势。然而集成电路器件在尺寸缩小和电路集成度提高的同时，原本可以忽略的寄生效应变得愈发严重，加剧了集成电路老化。老化效应对集成电路可靠性影响日益突出，在其作用下集成电路内晶体管阈值电压升高，逻辑门翻转速度减慢，延迟增加，进而导致时序违规，引发集成电路失效。在工艺进入深纳米阶段，负偏置温度不稳定效应(Negative Bias Temperature Instability，NBTI)NBTI已成为引起老化效应的关键因素。性能稳定是IC设备可靠性的关键指标，因此维持集成电路在正常寿命内的优良性能，延缓集成电路老化是当前纳米工艺下亟需实现的关键技术。
目前，国内外研究机构对集成电路抗老化技术进行深入研究，并取得一定研究成果。文献1《针对抗老化门替换技术的关建门识别算法》提出关键门识别算法并将其应用于抗老化方案中的门替换技术中，通过对电路网表逻辑仿真得到信号占空比和内部节点信息，并判断门替换带来的抗老化效果来识别关键门，得到满足要求的关键门集合进行替换，以此提高集成电路抗老化能力。但该方法要求在设计初期就需在满足时序余量基础上对关键门进行替换，而不同时序余量对应不同的关键门集合，因此不同老化程度对应的关键门位置、数量和种类也是不同的，不能满足不同老化程度下集成电路老化的修复，应用范围具有局限性。
众所周知，集成电路中压控振荡器作为频率产生单元，一直处于高频工作状态，相比集成电路中其他电路模块更易发生老化，进而导致整个集成电路性能下降，甚至失效。因此可以通过监测压控振荡器的老化程度来反映集成电路的老化程度，而对压控振荡器的老化状态进行修复能减缓集成电路的老化，最终实现集 成电路抗老化的目的。
发明内容
本发明所要解决的技术问题是提供一种基于布谷鸟算法的自适应抗老化传感器，该自适应抗老化传感器通过监测集成电路中压控振荡器的老化程度来反映集成电路的老化程度，并能根据集成电路中压控振荡器的老化状态自适应去调整集成电路中压控振荡器的最优工作电压，对集成电路中压控振荡器的进行自适应老化修复，能够满足不同老化程度下集成电路老化的修复，最终实现集成电路抗老化的目的，应用范围广。
本发明解决上述技术问题所采用的技术方案为：一种基于布谷鸟算法的自适应抗老化传感器，包括控制模块、参考压控振荡器、结构相同的两个整形电路、频差电路、分辨率调节电路、16位计数器、并转串电路、自适应模块和数模转换器；所述的控制模块具有反馈端、第一电压输出端、第二电压输出端和控制信号输出端，所述的参考压控振荡器和每个所述的整形电路分别具有输入端和输出端，所述的频差电路具有置数端、时钟端和输出端，所述的分辨率调节电路具有输入端、输出端和控制端，所述的16位计数器具有置数端、复位端和16位并行输出端，所述的自适应模块具有控制端、16位并行输入端和16位并行输出端，所述的数模转换器具有16位并行输入端和输出端，所述的并转串模块具有时钟端、16位并行输入端和输出端，将两个所述的整形电路分别称为第一整形电路和第二整形电路，将集成电路中的压控振荡器称为被测压控振荡器，所述的参考压控振荡器与被测压控振荡器完全相同，所述的控制模块的第一电压输出端用于连接被测压控振荡器的输入端，所述的控制模块的第二电压输出端和所述的参考压控振荡器的输入端连接，所述的控制模块的控制信号输出端分别与所述的分辨率调节电路的控制端和所述的自适应模块的控制端连接，所述的第一整形电路的输入端用于连接被测压控振荡器的输出端，所述的参考压控振荡器的输出端和所述的第二整形电路的输入端连接，所述的第一整形电路的输出端和所述的频差电路的置数端连接，所述的第二整形电路的输出端分别与所述的频差电路的时钟端、所述的并转串模块的时钟端和所述的16位计数器的置数端连接，所述的频差电路的输出端和所述的分辨率调节电路的输入端连接，所述的分辨率调节电路的输出端和所述的16位计数器的复位端连接，所述的16位 计数器的16位并行输出端分别与所述的并转串模块的16位并行输入端和所述的自适应模块的16位并行输入端连接，所述的自适应模块的16位并行输出端和所述的数模转换器的16位并行输入端连接，所述的数模转换器的输出端和所述的控制模块的反馈端连接；
所述的控制模块产生两路电压信号和一路电平控制信号，其中第一路电压信号为老化电压信号VDC，通过其第一电压输出端输出，第二路电压信号为基准电压信号VDD，通过其第二电压输出端输出，电平控制信号为高电平或者低电平，通过其控制信号输出端输出，电平控制信号的初始状态为低电平，老化电压信号VDC经过所述的被测压控振荡器产生老化频率信号A，基准电压信号VDD经过所述的参考压控振荡器产生基准频率信号B，老化频率信号A经所述的第一整形电路整形后得到第一频率信号f ctr，基准频率信号B经所述的第二整形电路整形后得到第二频率信号f ref，频差电路通过比较第一频率信号f ctr和第二频率信号f ref得到拍频信号f out，拍频信号f out为第二频率信号f ref和第一频率信号f ctr之间的差值，拍频信号f out从所述的频差电路的输出端输出至所述的分辨率调节电路的输入端，所述的分辨率调节电路的输出端输出置位信号rst，当所述的分辨率调节电路的控制端接入的电平控制信号为低电平时，置位信号rst为拍频信号f out的2分频信号，当所述的分辨率调节电路的控制端接入的电平控制信号为高电平时，置位信号rst为拍频信号f out的4分频信号，所述的16位计数器的复位端接入置位信号rst，所述的16位计数器在置位信号rst周期内计数其置数端接入的第二频率信号f ref的个数，然后将计数值以二进制形式的16位并行数据Q0-Q15在其16位并行输出端进行输出，所述的并转串电路在第一频率信号f ref作用下，将所述的16位计数器输出的16位并行数据Q0-Q15转换为串行数据Q[0:15]在其输出端输出；
所述的自适应模块内预存有查找表，所述的查找表通过对所述的自适应抗老化传感器进行仿真来人为模拟被测压控振荡器老化过程得到，具体仿真过程为：将控制模块的第一电压输出端与被测压控振荡器的输入端连接，第一整形电路的输入端与被测压控振荡器的输出端连接，对被测压控振荡器的参数和参考压控振荡器的参数进行初始化设置：PMOS晶体管的阈值电压V TP为0.7V、NMOS晶体管的阈值电压V TN为0.3V以及PMOS和NMOS晶体管的工艺参数α为0.9，后续通过Cadence软件测定被测压控振荡器在不同参数下的延迟时间Time，在测定过程中，参考压控振荡器的参数始终保持初始值不变，被测压控振荡器的PMOS晶体管的阈值电压V TP的调节范围为0.6V-0.8V，单次调节量 为1mV，NMOS晶体管的阈值电压V TN的调节范围为0.2V-0.4V，单次调节量为1mV、PMOS和NMOS晶体管的工艺参数α的调节范围0.8-1，单次调节量为0.001，每次测定时，老化电压信号VDC和基准电压信号VDD均设定为1.2V，先使控制模块输出的电平控制信号S为低电平，判定此时16位计数器输出的16位并行输出信号Q0-Q15对应的十进制值是否小于40，如果小于40，则保持其他条件不变，将电平控制信号S调整为高电平后记录此时16位计数器输出的16位并行输出信号Q0-Q15，如果大于等于40,则直接记录此时16位计数器输出的16位并行输出信号Q0-Q15，将当前记录的16位计数器输出的16位并行输出信号Q0-Q15作为查找表的一个索引地址，并将此时对应的阈值电压V TP，阈值电压V TN以及PMOS和NMOS晶体管的工艺参数α作为该索引地址的存储数据存入查找表中，重复上述测定过程，后续测定过程中若存在相同的16位并行输出信号Q0-Q15，则只记录一组对应的参数，直到16位计数器输出的16位并行输出信号Q0-Q15对应的十进制数从0至300都出现，完成查找表的建立并将查找表存放于自适应模块中，此时所述的查找表中的索引地址有301个，分别为0至300对应的16位二进制数据；
当所述的16位计数器输出的16位并行数据Q0-Q15输入所述的自适应模块中时，所述的自适应模块首先在查找表中获取索引地址为当前输入其内的16位并行数据Q0-Q15的存储数据V TP、V TN、α以及Time，然后基于获取的数据V TP、V TN、α以及Time采用布谷鸟算法确定当前被测压控振荡器的最优工作电压，具体过程为：
A、将设定布谷鸟算法最大迭代次数记为n，n＝1000，设定全局最优解V；
B、设定迭代变量，将其记为s，对s进行初始化，令s＝1；
C、进行第s次迭代，具体为：
C-1、采用随机函数产生100个位于0-2000mV范围内，且采用16位二进制数据表示的电压数据，将产生的第m个电压数据记为
Figure PCTCN2020130804-appb-000001
m＝1，2，…，100；判定
Figure PCTCN2020130804-appb-000002
是否等于V TN或V TP，如果等于，则认为
Figure PCTCN2020130804-appb-000003
为坏值，淘汰该值并重新随机产生一个新的
Figure PCTCN2020130804-appb-000004
直到得到100个不等于V TN或V TP的电压数据
Figure PCTCN2020130804-appb-000005
C-2、将
Figure PCTCN2020130804-appb-000006
依次代入公式
Figure PCTCN2020130804-appb-000007
中，计算得到
Figure PCTCN2020130804-appb-000008
其中
Figure PCTCN2020130804-appb-000009
表示第m个老化延迟时间；
C-3、分别计算
Figure PCTCN2020130804-appb-000010
与Time的差值的绝对值，将
Figure PCTCN2020130804-appb-000011
与Time的差值的绝对值记为Diff s[m]，从Diff s[1]～Diff s[100]找出最小值，如果出现多个相同的最小值，则随机选择一个最小值，该最小值记为Diff s[i]，i为大于等于1且小于等于100的整数，将Diff s[i]对应的电压数据
Figure PCTCN2020130804-appb-000012
作为当代个体最优解
Figure PCTCN2020130804-appb-000013
C-4、如果s的当前值为1，则将当代个体最优解
Figure PCTCN2020130804-appb-000014
的值赋值给全局最优解V，对全局最优解V进行第s次更新，得到第s次迭代后的全局最优解V；
如果s的当前值不等于1，则对
Figure PCTCN2020130804-appb-000015
和第s-1次迭代后的全局最优解V进行比较，如果
Figure PCTCN2020130804-appb-000016
小于第s-1次迭代后的全局最优解V，则采用
Figure PCTCN2020130804-appb-000017
的值更新V，得到第s次迭代后的全局最优解V，如果
Figure PCTCN2020130804-appb-000018
大于等于第s-1次迭代后的全局最优解V，则V的取值不变，第s-1次迭代后的全局最优解V直接作为第s次迭代后的全局最优解V；
C-5、判断Diff s[i]是否等于0或者s是否等于1000，如果满足其一，则将第s次迭代后的全局最优解V作为最优工作电压V DC0-V DC15从所述的自适应模块的16位并行输出端输出，迭代过程结束，如果两个都不满足，则进入步骤C-6；
C-6、采用公式
Figure PCTCN2020130804-appb-000019
更新产生第s+1代的电压数据
Figure PCTCN2020130804-appb-000020
其中，λ为采用RC4算法产生的大于等于0且小于等于3的随机数，每次产生电压数据时，λ都需要重新产生，
Figure PCTCN2020130804-appb-000021
为步长控制量，
Figure PCTCN2020130804-appb-000022
为点对点乘法，Levy(λ)为随机搜索路径，Levy(λ)＝s -λ，判定
Figure PCTCN2020130804-appb-000023
是否等于V TN或V TP，如果等于，则认为
Figure PCTCN2020130804-appb-000024
为坏值，淘汰该值并通过公式
Figure PCTCN2020130804-appb-000025
重新随机产生一个新的
Figure PCTCN2020130804-appb-000026
直到得到100个不等于V TN或V TP的电压数据
Figure PCTCN2020130804-appb-000027
Figure PCTCN2020130804-appb-000028
C-7、采用s的当前值加1的和更新s的值，从步骤C-2开始重复，进行下一次迭代，直至迭代过程结束，得到最优工作电压V DC0-V DC15从所述的自适应模块的16位并行输出端输出；
所述的数模转换器将所述的自适应模块输出的最优工作电压V DC0-V DC15转换为模拟电压输出至所述的控制模块的反馈端，所述的控制模块将其第一输出端输出的老化电压信号VDC大小调整为所述的模数转换器的输出端输出的模拟电压大小。
每个所述的整形电路分别包括第一PMOS管、第二PMOS管、第一NMOS管、第二NMOS管和第一反相器；所述的第一PMOS管的源极和所述的第二PMOS管的源极均接入电源，所述的第一PMOS管的栅极、所述的第二PMOS管的漏极和所述的第二NMOS管的漏极连接且其连接端为所述的整形电路的输出端，所述的第一PMOS管的漏极、所述的第二PMOS管的栅极和所述的第一NMOS管的漏极连接，所述的第一NMOS管的栅极和所述的第一反相器的输入端连接且其连接端为所述的整形电路的输入端，所述的第一反相器的输出端和所述的第二NMOS管的栅极连接，所述的第一NMOS管的源极和所述的第二NMOS管的源极均接地。
所述的频差电路采用第一D触发器实现，所述的第一D触发器具有输入端、时钟端和输出端，所述的第一D触发器的输入端为所述的频差电路的置位端，所述的第一D触发器的时钟端为所述的频差电路的时钟端，所述的第一D触发器的输出端为所述的频差电路的输出端。
所述的分辨率调节电路包括第一二选一选择器、第二D触发器和第三D触发器，所述的第一二选一选择器具有第一输入端、第二输入端、选择端和输出端，所述的第二D触发器和所述的第三D触发器分别具有输入端、时钟端、输出端和反相输出端；所述的第二D触发器的输入端和所述的第二D触发器的反相输出端连接，所述的第二D触发器的时钟端为所述的分辨率调节电路的输入端，所述的第二D触发器的输出端、所述的第三D触发器的时钟端和所述的第一二选一选择器的第一输入端连接，所述的第三D触发器的输入端和所述的第三D触发器的反相输出端连接，所述的第三D触发器的输出端和所述的第一二选一选择器的第二输入端连接，所述的第一二选一选择器的选择端为所述的分辨率调节电路的控制端，所述的第一二选一选择器的输出端为所述的分辨率调节电路的输出端。
所述的16位计数器包括16个D触发器和16个反相器，每个所述的D触发器分别具有输入端、时钟端、复位端和输出端，16个所述的D触发器的复位端连接且其连接端为所述的16位计数器的复位端，第k个D触发器的输入端和第k个反相器的输出端连接，k＝1，2，…，16，第h个D触发器的输出端、第h个反相器的输入端和第h+1个D触发器的时钟端连接且其连接端为所述的16位计数器的第h个输出端，h＝1，2，…，15，第16个D触发器的输出端和第16个反相器的输入端连接且其连接端为所述的16位计数器的第16个输 出端，所述的16位计数器的第1个输出端～第16个输出端构成所述的16位计数器的16位并行输出端。
与现有技术相比，本发明的优点在于通过控制模块、参考压控振荡器、结构相同的两个整形电路、频差电路、分辨率调节电路、16位计数器、并转串电路、自适应模块和数模转换器构建自适应抗老化传感器，自适应模块内预存有查找表，查找表通过对自适应抗老化传感器进行仿真来人为模拟被测压控振荡器老化过程得到，在对集成电路的压控振荡器进行老化监测时，16位计数器输出的16位并行数据Q0-Q15输入自适应模块中时，自适应模块首先在查找表中获取索引地址为当前输入其内的16位并行数据Q0-Q15的存储数据V TP、V TN、α以及Time，然后基于获取的数据V TP、V TN、α以及Time采用布谷鸟算法确定当前被测压控振荡器的最优工作电压，并将最优工作电压V DC0-V DC15输送给数模转化器，数模转化器将最优工作电压V DC0-V DC15转换为模拟电压输出至控制模块的反馈端，控制模块将其第一输出端输出的老化电压信号VDC大小调整为模数转换器的输出端输出的模拟电压大小，由此改变集成电路的压控振荡器的输入电压，由此，本发明的自适应抗老化传感器通过监测集成电路中压控振荡器的老化程度来反映集成电路的老化程度，并能根据集成电路中压控振荡器的老化状态自适应去调整集成电路中压控振荡器的最优工作电压，对集成电路中压控振荡器的进行自适应老化修复，能够满足不同老化程度下集成电路老化的修复，最终实现集成电路抗老化的目的，应用范围广。
附图说明
图1为本发明的基于布谷鸟算法的自适应抗老化传感器的结构框图；
图2为本发明的基于布谷鸟算法的自适应抗老化传感器的整形电路的电路图；
图3为本发明的基于布谷鸟算法的自适应抗老化传感器的频差电路的电路图；
图4为本发明的基于布谷鸟算法的自适应抗老化传感器的分辨率调节电路的电路图；
图5为本发明的基于布谷鸟算法的自适应抗老化传感器的16位计数器的电路图；
图6为本发明的基于布谷鸟算法的自适应抗老化传感器的模拟仿真图。
具体实施方式
以下结合附图实施例对本发明作进一步详细描述。
实施例：如图1所示，一种基于布谷鸟算法的自适应抗老化传感器，包括控制模块、参考压控振荡器、结构相同的两个整形电路、频差电路、分辨率调节电路、16位计数器、并转串电路、自适应模块和数模转换器；控制模块具有反馈端、第一电压输出端、第二电压输出端和控制信号输出端，参考压控振荡器和每个整形电路分别具有输入端和输出端，频差电路具有置数端、时钟端和输出端，分辨率调节电路具有输入端、输出端和控制端，16位计数器具有置数端、复位端和16位并行输出端，自适应模块具有控制端、16位并行输入端和16位并行输出端，数模转换器具有16位并行输入端和输出端，并转串模块具有时钟端、16位并行输入端和输出端，将两个整形电路分别称为第一整形电路和第二整形电路，将集成电路中的压控振荡器称为被测压控振荡器，参考压控振荡器与被测压控振荡器完全相同，控制模块的第一电压输出端用于连接被测压控振荡器的输入端，控制模块的第二电压输出端和参考压控振荡器的输入端连接，控制模块的控制信号输出端分别与分辨率调节电路的控制端和自适应模块的控制端连接，第一整形电路的输入端用于连接被测压控振荡器的输出端，参考压控振荡器的输出端和第二整形电路的输入端连接，第一整形电路的输出端和频差电路的置数端连接，第二整形电路的输出端分别与频差电路的时钟端、并转串模块的时钟端和16位计数器的置数端连接，频差电路的输出端和分辨率调节电路的输入端连接，分辨率调节电路的输出端和16位计数器的复位端连接，16位计数器的16位并行输出端分别与并转串模块的16位并行输入端和自适应模块的16位并行输入端连接，自适应模块的16位并行输出端和数模转换器的16位并行输入端连接，数模转换器的输出端和控制模块的反馈端连接；控制模块产生两路电压信号和一路电平控制信号，其中第一路电压信号为老化电压信号VDC，通过其第一电压输出端输出，第二路电压信号为基准电压信号VDD，通过其第二电压输出端输出，电平控制信号为高电平或者低电平，通过其控制信号输出端输出，电平控制信号的初始状态为低电平，老化电压信号VDC经过被测压控振荡器产生老化频率信号A，基准电压信号VDD经过参考压控振荡器产生基准频率信号B，老化频率信号A经第一整形电路整形后得到第一频率信号f ctr，基准频率信号B经第二整形电路整形后得到第二频率信号f ref，频差电路通过比较第一频率信号f ctr和第二频率信号f ref得到拍频信号f out， 拍频信号f out为第二频率信号f ref和第一频率信号f ctr之间的差值，拍频信号f out从频差电路的输出端输出至分辨率调节电路的输入端，分辨率调节电路的输出端输出置位信号rst，当分辨率调节电路的控制端接入的电平控制信号为低电平时，置位信号rst为拍频信号f out的2分频信号，当分辨率调节电路的控制端接入的电平控制信号为高电平时，置位信号rst为拍频信号f out的4分频信号，16位计数器的复位端接入置位信号rst，16位计数器在置位信号rst周期内计数其置数端接入的第二频率信号f ref的个数，然后将计数值以二进制形式的16位并行数据Q0-Q15在其16位并行输出端进行输出，并转串电路在第一频率信号f ref作用下，将16位计数器输出的16位并行数据Q0-Q15转换为串行数据Q[0:15]在其输出端输出；
自适应模块内预存有查找表，查找表通过对自适应抗老化传感器进行仿真来人为模拟被测压控振荡器老化过程得到，具体仿真过程为：将控制模块的第一电压输出端与被测压控振荡器的输入端连接，第一整形电路的输入端与被测压控振荡器的输出端连接，对被测压控振荡器的参数和参考压控振荡器的参数进行初始化设置：PMOS晶体管的阈值电压V TP为0.7V、NMOS晶体管的阈值电压V TN为0.3V以及PMOS和NMOS晶体管的工艺参数α为0.9，后续通过Cadence软件测定被测压控振荡器在不同参数下的延迟时间Time，在测定过程中，参考压控振荡器的参数始终保持初始值不变，被测压控振荡器的PMOS晶体管的阈值电压V TP的调节范围为0.6V-0.8V，单次调节量为1mV，NMOS晶体管的阈值电压V TN的调节范围为0.2V-0.4V，单次调节量为1mV、PMOS和NMOS晶体管的工艺参数α的调节范围0.8-1，单次调节量为0.001，每次测定时，老化电压信号VDC和基准电压信号VDD均设定为1.2V，先使控制模块输出的电平控制信号S为低电平，判定此时16位计数器输出的16位并行输出信号Q0-Q15对应的十进制值是否小于40，如果小于40，则保持其他条件不变，将电平控制信号S调整为高电平后记录此时16位计数器输出的16位并行输出信号Q0-Q15，如果大于等于40,则直接记录此时16位计数器输出的16位并行输出信号Q0-Q15，将当前记录的16位计数器输出的16位并行输出信号Q0-Q15作为查找表的一个索引地址，并将此时对应的阈值电压V TP，阈值电压V TN以及PMOS和NMOS晶体管的工艺参数α作为该索引地址的存储数据存入查找表中，重复上述测定过程，后续测定过程中若存在相同的16位并行输出信号Q0-Q15，则只记录一组对应的参数，直到16位计数器输出的16位并行输出信号Q0-Q15对应的十进制数从0至300都出现，完成查找表的建立并将查找表存放于自适应模块中， 此时查找表中的索引地址有301个，分别为0至300对应的16位二进制数据；
当16位计数器输出的16位并行数据Q0-Q15输入自适应模块中时，自适应模块首先在查找表中获取索引地址为当前输入其内的16位并行数据Q0-Q15的存储数据V TP、V TN、α以及Time，然后基于获取的数据V TP、V TN、α以及Time采用布谷鸟算法确定当前被测压控振荡器的最优工作电压，具体过程为：
A、将设定布谷鸟算法最大迭代次数记为n，n＝1000，设定全局最优解V；
B、设定迭代变量，将其记为s，对s进行初始化，令s＝1；
C、进行第s次迭代，具体为：
C-1、采用随机函数产生100个位于0-2000mV范围内，且采用16位二进制数据表示的电压数据，将产生的第m个电压数据记为
Figure PCTCN2020130804-appb-000029
m＝1，2，…，100；判定
Figure PCTCN2020130804-appb-000030
是否等于V TN或V TP，如果等于，则认为
Figure PCTCN2020130804-appb-000031
为坏值，淘汰该值并重新随机产生一个新的
Figure PCTCN2020130804-appb-000032
直到得到100个不等于V TN或V TP的电压数据
Figure PCTCN2020130804-appb-000033
C-2、将
Figure PCTCN2020130804-appb-000034
依次代入公式
Figure PCTCN2020130804-appb-000035
中，计算得到
Figure PCTCN2020130804-appb-000036
其中
Figure PCTCN2020130804-appb-000037
表示第m个老化延迟时间；
C-3、分别计算
Figure PCTCN2020130804-appb-000038
与Time的差值的绝对值，将
Figure PCTCN2020130804-appb-000039
与Time的差值的绝对值记为Diff s[m]，从Diff s[1]～Diff s[100]找出最小值，如果出现多个相同的最小值，则随机选择一个最小值，该最小值记为Diff s[i]，i为大于等于1且小于等于100的整数，将Diff s[i]对应的电压数据
Figure PCTCN2020130804-appb-000040
作为当代个体最优解
Figure PCTCN2020130804-appb-000041
C-4、如果s的当前值为1，则将当代个体最优解
Figure PCTCN2020130804-appb-000042
的值赋值给全局最优解V，对全局最优解V进行第s次更新，得到第s次迭代后的全局最优解V；
如果s的当前值不等于1，则对
Figure PCTCN2020130804-appb-000043
和第s-1次迭代后的全局最优解V进行比较，如果
Figure PCTCN2020130804-appb-000044
小于第s-1次迭代后的全局最优解V，则采用
Figure PCTCN2020130804-appb-000045
的值更新V，得到第s次迭代后的全局最优解V，如果
Figure PCTCN2020130804-appb-000046
大于等于第s-1次迭代后的全局最优解V，则V的取值不变，第s-1次迭代后的全局最优解V直接作为第s次迭代后的全局最优解V；
C-5、判断Diff s[i]是否等于0或者s是否等于1000，如果满足其一，则将第s次迭 代后的全局最优解V作为最优工作电压V DC0-V DC15从自适应模块的16位并行输出端输出，迭代过程结束，如果两个都不满足，则进入步骤C-6；
C-6、采用公式
Figure PCTCN2020130804-appb-000047
更新产生第s+1代的电压数据
Figure PCTCN2020130804-appb-000048
其中，λ为采用RC4算法产生的大于等于0且小于等于3的随机数，每次产生电压数据时，λ都需要重新产生，
Figure PCTCN2020130804-appb-000049
为步长控制量，
Figure PCTCN2020130804-appb-000050
为点对点乘法，Levy(λ)为随机搜索路径，Levy(λ)＝s -λ，判定
Figure PCTCN2020130804-appb-000051
是否等于V TN或V TP，如果等于，则认为
Figure PCTCN2020130804-appb-000052
为坏值，淘汰该值并通过公式
Figure PCTCN2020130804-appb-000053
重新随机产生一个新的
Figure PCTCN2020130804-appb-000054
直到得到100个不等于V TN或V TP的电压数据
Figure PCTCN2020130804-appb-000055
Figure PCTCN2020130804-appb-000056
C-7、采用s的当前值加1的和更新s的值，从步骤C-2开始重复，进行下一次迭代，直至迭代过程结束，得到最优工作电压V DC0-V DC15从自适应模块的16位并行输出端输出；
数模转换器将自适应模块输出的最优工作电压V DC0-V DC15转换为模拟电压输出至控制模块的反馈端，控制模块将其第一输出端输出的老化电压信号VDC大小调整为模数转换器的输出端输出的模拟电压大小。
本实施例中，如图2所示，每个整形电路分别包括第一PMOS管P1、第二PMOS管P2、第一NMOS管N1、第二NMOS管N2和第一反相器A1；第一PMOS管P1的源极和第二PMOS管P2的源极均接入电源，第一PMOS管P1的栅极、第二PMOS管P2的漏极和第二NMOS管N2的漏极连接且其连接端为整形电路的输出端，第一PMOS管P1的漏极、第二PMOS管P2的栅极和第一NMOS管N1的漏极连接，第一NMOS管N1的栅极和第一反相器A1的输入端连接且其连接端为整形电路的输入端，第一反相器A1的输出端和第二NMOS管N2的栅极连接，第一NMOS管N1的源极和第二NMOS管N2的源极均接地。
本实施例中，如图3所示，频差电路采用第一D触发器DFF1实现，第一D触发器DFF1具有输入端、时钟端和输出端，第一D触发器DFF1的输入端为频差电路的置位端，第一D触发器DFF1的时钟端为频差电路的时钟端，第一D触发器DFF1的输出端为频差电路的输出端。
本实施例中，如图4所示，分辨率调节电路包括第一二选一选择器MUX1、第二D触发器DFF2和第三D触发器DFF3，第一二选一选择器MUX1具有第一输入端、第二输入端、选择端和输出端，第二D触发器DFF2和第三D触发器DFF3分别具有输入端、时钟端、输出端和反相输出端；第二D触发器DFF2的输入端和第二D触发器DFF2的反相输出端连接，第二D触发器DFF2的时钟端为分辨率调节电路的输入端，第二D触发器DFF2的输出端、第三D触发器DFF3的时钟端和第一二选一选择器MUX1的第一输入端连接，第三D触发器DFF3的输入端和第三D触发器DFF3的反相输出端连接，第三D触发器DFF3的输出端和第一二选一选择器MUX1的第二输入端连接，第一二选一选择器MUX1的选择端为分辨率调节电路的控制端，第一二选一选择器MUX1的输出端为分辨率调节电路的输出端。
本实施例中，如图5所示，16位计数器包括16个D触发器DFF4～DFF19和16个反相器A2～A17，每个D触发器分别具有输入端、时钟端、复位端和输出端，16个D触发器的复位端连接且其连接端为16位计数器的复位端，第k个D触发器的输入端和第k个反相器的输出端连接，k＝1，2，…，16，第h个D触发器的输出端、第h个反相器的输入端和第h+1个D触发器的时钟端连接且其连接端为16位计数器的第h个输出端，h＝1，2，…，15，第16个D触发器的输出端和第16个反相器的输入端连接且其连接端为16位计数器的第16个输出端，16位计数器的第1个输出端～第16个输出端构成16位计数器的16位并行输出端。
对本发明的基于布谷鸟算法的自适应抗老化传感器的老化监测过程进行仿真，其模拟仿真曲线如图6所示。图6中f ctr为被测压控振荡器产生的老化频率经第一整形电路整形后得到的输出，f ref为参考压控振荡器产生的基准频率经第一整形电路整形后得到的输出，OUT<1>、OUT<2>、…、OUT<9>分别为16位计数器的输出的16位并行数据，Z<1>、Z<2>、…、Z<9>分别为自适应模块输出的最优工作电压，V OUT为数模转换器进行数模转化后输出的模拟电压。分析图6中可知：该老化监测修复过程大致分为两个阶段：第一阶段：自适应模块根据当前被测压控振荡器老化程度给出恢复其性能所需的最优调节电压(即最优工作电压)，第二阶段：根据最优调节电压去调节被测压控振荡器的电压，实现对老化效应引起的集成电路性能退化的自适应修复。具体仿真过程为：在模拟状态下，参考压控振荡器产生500M的基准频率信号，被测压控振荡器产生490M的老化频率信号，被测压控振荡器相对于参考压控振荡器有2％的频率退化，此时16位 计数器的16位并行输出端输出的16位数据对应的十进制数是80，即16位计数器输出为80，将16计数器的输出作为自适应模块的输入，通过布谷鸟算法优化得到当前老化状态下最优工作电压1.28V，并将该最优工作电压作为被测压控振荡器的反馈电压输出至控制模块，控制模块据此调节被测压控振荡器的工作电压后，此时16位计数器的输出为275，被测压控振荡器输出频率为499.2M，相对参考压控振荡器频率降级为0.16％，输出电压为1.23V。仿真结果表明，经自适应算法优化后的被测压控振荡器老化频率输出增加，集成电路性能显著恢复，可实现集成电路自适应抗老化功能。

Claims (5)

  1. 一种基于布谷鸟算法的自适应抗老化传感器，其特征在于包括控制模块、参考压控振荡器、结构相同的两个整形电路、频差电路、分辨率调节电路、16位计数器、并转串电路、自适应模块和数模转换器；所述的控制模块具有反馈端、第一电压输出端、第二电压输出端和控制信号输出端，所述的参考压控振荡器和每个所述的整形电路分别具有输入端和输出端，所述的频差电路具有置数端、时钟端和输出端，所述的分辨率调节电路具有输入端、输出端和控制端，所述的16位计数器具有置数端、复位端和16位并行输出端，所述的自适应模块具有控制端、16位并行输入端和16位并行输出端，所述的数模转换器具有16位并行输入端和输出端，所述的并转串模块具有时钟端、16位并行输入端和输出端，将两个所述的整形电路分别称为第一整形电路和第二整形电路，将集成电路中的压控振荡器称为被测压控振荡器，所述的参考压控振荡器与被测压控振荡器完全相同，所述的控制模块的第一电压输出端用于连接被测压控振荡器的输入端，所述的控制模块的第二电压输出端和所述的参考压控振荡器的输入端连接，所述的控制模块的控制信号输出端分别与所述的分辨率调节电路的控制端和所述的自适应模块的控制端连接，所述的第一整形电路的输入端用于连接被测压控振荡器的输出端，所述的参考压控振荡器的输出端和所述的第二整形电路的输入端连接，所述的第一整形电路的输出端和所述的频差电路的置数端连接，所述的第二整形电路的输出端分别与所述的频差电路的时钟端、所述的并转串模块的时钟端和所述的16位计数器的置数端连接，所述的频差电路的输出端和所述的分辨率调节电路的输入端连接，所述的分辨率调节电路的输出端和所述的16位计数器的复位端连接，所述的16位计数器的16位并行输出端分别与所述的并转串模块的16位并行输入端和所述的自适应模块的16位并行输入端连接，所述的自适应模块的16位并行输出端和所述的数模转换器的16位并行输入端连接，所述的数模转换器的输出端和所述的控制模块的反馈端连接；所述的控制模块产生两路电压信号和一路电平控制信号，其中第一路电压信号为老化电压信号VDC，通过其第一电压输出端输出，第二路电压信号为基准电压信号VDD，通过其第二电压输出端输出，电平控制信号为高电平或者低电平，通过其控制信号输出端输出，电平控制信号的初始状态为低电平，老化电压信号VDC经过所述的被测压控振荡器产生老化频率信号A，基准电压信号VDD经过所述的参考压控振荡器产生基准频率信号B，老化频率信号A 经所述的第一整形电路整形后得到第一频率信号f ctr，基准频率信号B经所述的第二整形电路整形后得到第二频率信号f ref，频差电路通过比较第一频率信号f ctr和第二频率信号f ref得到拍频信号f out，拍频信号f out为第二频率信号f ref和第一频率信号f ctr之间的差值，拍频信号f out从所述的频差电路的输出端输出至所述的分辨率调节电路的输入端，所述的分辨率调节电路的输出端输出置位信号rst，当所述的分辨率调节电路的控制端接入的电平控制信号为低电平时，置位信号rst为拍频信号f out的2分频信号，当所述的分辨率调节电路的控制端接入的电平控制信号为高电平时，置位信号rst为拍频信号f out的4分频信号，所述的16位计数器的复位端接入置位信号rst，所述的16位计数器在置位信号rst周期内计数其置数端接入的第二频率信号f ref的个数，然后将计数值以二进制形式的16位并行数据Q0-Q15在其16位并行输出端进行输出，所述的并转串电路在第一频率信号f ref作用下，将所述的16位计数器输出的16位并行数据Q0-Q15转换为串行数据Q[0:15]在其输出端输出；
    所述的自适应模块内预存有查找表，所述的查找表通过对所述的自适应抗老化传感器进行仿真来人为模拟被测压控振荡器老化过程得到，具体仿真过程为：将控制模块的第一电压输出端与被测压控振荡器的输入端连接，第一整形电路的输入端与被测压控振荡器的输出端连接，对被测压控振荡器的参数和参考压控振荡器的参数进行初始化设置：PMOS晶体管的阈值电压V TP为0.7V、NMOS晶体管的阈值电压V TN为0.3V以及PMOS和NMOS晶体管的工艺参数α为0.9，后续通过Cadence软件测定被测压控振荡器在不同参数下的延迟时间Time，在测定过程中，参考压控振荡器的参数始终保持初始值不变，被测压控振荡器的PMOS晶体管的阈值电压V TP的调节范围为0.6V-0.8V，单次调节量为1mV，NMOS晶体管的阈值电压V TN的调节范围为0.2V-0.4V，单次调节量为1mV、PMOS和NMOS晶体管的工艺参数α的调节范围0.8-1，单次调节量为0.001，每次测定时，老化电压信号VDC和基准电压信号VDD均设定为1.2V，先使控制模块输出的电平控制信号S为低电平，判定此时16位计数器输出的16位并行输出信号Q0-Q15对应的十进制值是否小于40，如果小于40，则保持其他条件不变，将电平控制信号S调整为高电平后记录此时16位计数器输出的16位并行输出信号Q0-Q15，如果大于等于40,则直接记录此时16位计数器输出的16位并行输出信号Q0-Q15，将当前记录的16位计数器输出的16位并行输出信号Q0-Q15作为查找表的一个索引地址，并将此时对应的阈值电压V TP，阈值电压V TN以及PMOS和NMOS晶体管的工艺参数α作为该索引地址的 存储数据存入查找表中，重复上述测定过程，后续测定过程中若存在相同的16位并行输出信号Q0-Q15，则只记录一组对应的参数，直到16位计数器输出的16位并行输出信号Q0-Q15对应的十进制数从0至300都出现，完成查找表的建立并将查找表存放于自适应模块中，此时所述的查找表中的索引地址有301个，分别为0至300对应的16位二进制数据；
    当所述的16位计数器输出的16位并行数据Q0-Q15输入所述的自适应模块中时，所述的自适应模块首先在查找表中获取索引地址为当前输入其内的16位并行数据Q0-Q15的存储数据V TP、V TN、α以及Time，然后基于获取的数据V TP、V TN、α以及Time采用布谷鸟算法确定当前被测压控振荡器的最优工作电压，具体过程为：
    A、将设定布谷鸟算法最大迭代次数记为n，n＝1000，设定全局最优解V；
    B、设定迭代变量，将其记为s，对s进行初始化，令s＝1；
    C、进行第s次迭代，具体为：
    C-1、采用随机函数产生100个位于0-2000mV范围内，且采用16位二进制数据表示的电压数据，将产生的第m个电压数据记为
    Figure PCTCN2020130804-appb-100001
    m＝1，2，…，100；判定
    Figure PCTCN2020130804-appb-100002
    是否等于V TN或V TP，如果等于，则认为
    Figure PCTCN2020130804-appb-100003
    为坏值，淘汰该值并重新随机产生一个新的
    Figure PCTCN2020130804-appb-100004
    直到得到100个不等于V TN或V TP的电压数据
    Figure PCTCN2020130804-appb-100005
    C-2、将
    Figure PCTCN2020130804-appb-100006
    依次代入公式
    Figure PCTCN2020130804-appb-100007
    中，计算得到
    Figure PCTCN2020130804-appb-100008
    其中
    Figure PCTCN2020130804-appb-100009
    表示第m个老化延迟时间；
    C-3、分别计算
    Figure PCTCN2020130804-appb-100010
    与Time的差值的绝对值，将
    Figure PCTCN2020130804-appb-100011
    与Time的差值的绝对值记为Diff s[m]，从Diff s[1]～Diff s[100]找出最小值，如果出现多个相同的最小值，则随机选择一个最小值，该最小值记为Diff s[i]，i为大于等于1且小于等于100的整数，将Diff s[i]对应的电压数据
    Figure PCTCN2020130804-appb-100012
    作为当代个体最优解
    Figure PCTCN2020130804-appb-100013
    C-4、如果s的当前值为1，则将当代个体最优解
    Figure PCTCN2020130804-appb-100014
    的值赋值给全局最优解V，对全局最优解V进行第s次更新，得到第s次迭代后的全局最优解V；
    如果s的当前值不等于1，则对
    Figure PCTCN2020130804-appb-100015
    和第s-1次迭代后的全局最优解V进行比较，如 果
    Figure PCTCN2020130804-appb-100016
    小于第s-1次迭代后的全局最优解V，则采用
    Figure PCTCN2020130804-appb-100017
    的值更新V，得到第s次迭代后的全局最优解V，如果
    Figure PCTCN2020130804-appb-100018
    大于等于第s-1次迭代后的全局最优解V，则V的取值不变，第s-1次迭代后的全局最优解V直接作为第s次迭代后的全局最优解V；
    C-5、判断Diff s[i]是否等于0或者s是否等于1000，如果满足其一，则将第s次迭代后的全局最优解V作为最优工作电压V DC0-V DC15从所述的自适应模块的16位并行输出端输出，迭代过程结束，如果两个都不满足，则进入步骤C-6；
    C-6、采用公式
    Figure PCTCN2020130804-appb-100019
    更新产生第s+1代的电压数据
    Figure PCTCN2020130804-appb-100020
    其中，λ为采用RC4算法产生的大于等于0且小于等于3的随机数，每次产生电压数据时，λ都需要重新产生，
    Figure PCTCN2020130804-appb-100021
    为步长控制量，
    Figure PCTCN2020130804-appb-100022
    Figure PCTCN2020130804-appb-100023
    为点对点乘法，Levy(λ)为随机搜索路径，Levy(λ)＝s -λ，判定
    Figure PCTCN2020130804-appb-100024
    是否等于V TN或V TP，如果等于，则认为
    Figure PCTCN2020130804-appb-100025
    为坏值，淘汰该值并通过公式
    Figure PCTCN2020130804-appb-100026
    重新随机产生一个新的
    Figure PCTCN2020130804-appb-100027
    直到得到100个不等于V TN或V TP的电压数据
    Figure PCTCN2020130804-appb-100028
    Figure PCTCN2020130804-appb-100029
    C-7、采用s的当前值加1的和更新s的值，从步骤C-2开始重复，进行下一次迭代，直至迭代过程结束，得到最优工作电压V DC0-V DC15从所述的自适应模块的16位并行输出端输出；
    所述的数模转换器将所述的自适应模块输出的最优工作电压V DC0-V DC15转换为模拟电压输出至所述的控制模块的反馈端，所述的控制模块将其第一输出端输出的老化电压信号VDC大小调整为所述的模数转换器的输出端输出的模拟电压大小。
  2. 根据权利要求1所述的一种基于查找表的电路老化检测传感器，其特征在于每个所述的整形电路分别包括第一PMOS管、第二PMOS管、第一NMOS管、第二NMOS管和第一反相器；所述的第一PMOS管的源极和所述的第二PMOS管的源极均接入电源，所述的第一PMOS管的栅极、所述的第二PMOS管的漏极和所述的第二NMOS管的漏极连接且其连接端为所述的整形电路的输出端，所述的第一PMOS管的漏极、所述的第二PMOS管的栅极和所述的第一NMOS管的漏极连接，所述的第一NMOS管的栅极和所述的第一反相器的输入端连接且其连接端为所述的整形电路的输入端，所述的第一反相器的输出端和所述的第二NMOS管的栅极连接，所述的第一NMOS管的源极和 所述的第二NMOS管的源极均接地。
  3. 根据权利要求1所述的一种基于查找表的电路老化检测传感器，其特征在于所述的频差电路采用第一D触发器实现，所述的第一D触发器具有输入端、时钟端和输出端，所述的第一D触发器的输入端为所述的频差电路的置位端，所述的第一D触发器的时钟端为所述的频差电路的时钟端，所述的第一D触发器的输出端为所述的频差电路的输出端。
  4. 根据权利要求1所述的一种基于查找表的电路老化检测传感器，其特征在于所述的分辨率调节电路包括第一二选一选择器、第二D触发器和第三D触发器，所述的第一二选一选择器具有第一输入端、第二输入端、选择端和输出端，所述的第二D触发器和所述的第三D触发器分别具有输入端、时钟端、输出端和反相输出端；所述的第二D触发器的输入端和所述的第二D触发器的反相输出端连接，所述的第二D触发器的时钟端为所述的分辨率调节电路的输入端，所述的第二D触发器的输出端、所述的第三D触发器的时钟端和所述的第一二选一选择器的第一输入端连接，所述的第三D触发器的输入端和所述的第三D触发器的反相输出端连接，所述的第三D触发器的输出端和所述的第一二选一选择器的第二输入端连接，所述的第一二选一选择器的选择端为所述的分辨率调节电路的控制端，所述的第一二选一选择器的输出端为所述的分辨率调节电路的输出端。
  5. 根据权利要求1所述的一种基于查找表的电路老化检测传感器，其特征在于所述的16位计数器包括16个D触发器和16个反相器，每个所述的D触发器分别具有输入端、时钟端、复位端和输出端，16个所述的D触发器的复位端连接且其连接端为所述的16位计数器的复位端，第k个D触发器的输入端和第k个反相器的输出端连接，k＝1，2，…，16，第h个D触发器的输出端、第h个反相器的输入端和第h+1个D触发器的时钟端连接且其连接端为所述的16位计数器的第h个输出端，h＝1，2，…，15，第16个D触发器的输出端和第16个反相器的输入端连接且其连接端为所述的16位计数器的第16个输出端，所述的16位计数器的第1个输出端～第16个输出端构成所述的16位计数器的16位并行输出端。
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