WO2022110235A1 - 芯片及时钟检测方法 - Google Patents

芯片及时钟检测方法 Download PDF

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Publication number
WO2022110235A1
WO2022110235A1 PCT/CN2020/132967 CN2020132967W WO2022110235A1 WO 2022110235 A1 WO2022110235 A1 WO 2022110235A1 CN 2020132967 W CN2020132967 W CN 2020132967W WO 2022110235 A1 WO2022110235 A1 WO 2022110235A1
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Prior art keywords
circuit
delay
output
signal
clock signal
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PCT/CN2020/132967
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English (en)
French (fr)
Inventor
商新超
童海涛
黄涛
余芳
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华为技术有限公司
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Priority to CN202080104997.9A priority Critical patent/CN116097106A/zh
Priority to PCT/CN2020/132967 priority patent/WO2022110235A1/zh
Publication of WO2022110235A1 publication Critical patent/WO2022110235A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

Definitions

  • the present application relates to the field of computer technology, and in particular, to a chip and a clock detection method.
  • the stability of the clock in the chip affects the system stability of the chip to a certain extent. In order to ensure the system stability of the chip, it is usually necessary to detect the clock in the chip to determine whether the clock in the chip is in a stable working state.
  • a reference clock is configured on the chip, and the frequency of the reference clock is the same as the theoretical operating frequency of the clock in the chip.
  • the embodiments of the present application provide a chip and a clock detection method, which can reduce the overhead required for detecting a clock on a chip, thereby saving chip resources.
  • the present application provides a chip, the chip includes a processor and a clock, the clock is used to generate a clock signal, and the chip further includes at least one of a reference clock generation circuit, a glitch detection circuit or a duty cycle detection circuit.
  • the processor is configured to detect the clock signal based on at least one of the following: detect the frequency of the clock signal based on the reference clock signal generated by the reference clock generation circuit; or, detect whether the clock signal contains a glitch based on the glitch detection circuit; or, based on the duty cycle
  • the ratio detection circuit detects the duty cycle of the clock signal.
  • the frequency of the on-chip clock signal can be detected based on the reference clock generation circuit, thereby avoiding the need to detect the on-chip clock signal when detecting the on-chip clock signal.
  • An additional standard reference clock needs to be drawn through the analog circuit, thus saving chip resources.
  • the detection of the burr included in the clock signal and the duty cycle of the clock signal on the same chip can also be realized, which improves the flexibility of detecting the clock signal.
  • the reference clock generation circuit includes P cascaded delay circuits, and each delay circuit in the P cascaded delay circuits includes a control terminal, The control terminal is used to input a control signal to control the corresponding delay circuit to be turned on or off, and P is a positive integer greater than 1.
  • the first stage delay circuit in the P cascaded delay circuits includes a first input end and a first output end.
  • the first input terminal of the first-stage delay circuit is used for inputting an initial clock signal, and the initial clock signal is output from the first output terminal of the first-stage delay circuit after passing through at least one stage of the conduction delay circuit.
  • the first output end of the first stage delay circuit is connected to the output end of the reference clock generating circuit, and the output end of the reference clock generating circuit is used for outputting the reference clock signal.
  • the frequency of the reference clock signals output by the reference clock generation circuit can be different. Therefore, the reference clock generating circuit can be trained based on the ideal operating frequency of the clock on the chip in advance, until the reference clock signal output by the reference clock generating circuit satisfies the aforementioned ideal operating frequency. Therefore, the reference clock circuit provided by the embodiments of the present application can be adapted to be used for clocks on different chips, and the application flexibility of the chips provided by the embodiments of the present application is improved.
  • each delay circuit in the P cascaded delay circuits includes a first input end, a second input end, a first output end, and a second output.
  • the second output terminal of the first stage delay circuit is connected to the first input terminal of the second stage delay circuit, and the second input terminal of the first stage delay circuit is connected to the first output of the second stage delay circuit end.
  • the first input terminal of the last stage delay circuit in the P cascaded delay circuits is connected to the second output terminal of the previous stage delay circuit of the last stage delay circuit; the second output terminal of the last stage delay circuit The output end is connected to the second input end of the last stage delay circuit; the first output end of the last stage delay circuit is connected to the second input end of the previous stage delay circuit of the last stage delay circuit.
  • the first input end of the intermediate delay circuit in the P cascaded delay circuits is connected to the upper stage of the delay circuit of the intermediate delay circuit. second output.
  • the first output terminal of the intermediate delay circuit is connected to the second input terminal of the upper stage delay circuit of the intermediate delay circuit.
  • the second output terminal of the intermediate delay circuit is connected to the first input terminal of the next stage delay circuit of the intermediate delay circuit.
  • the second input terminal of the intermediate delay circuit is connected to the first output terminal of the next stage delay circuit of the intermediate delay circuit.
  • the intermediate delay circuit is any one of the P cascaded delay circuits except the first-stage delay circuit and the last-stage delay circuit.
  • the above are respectively used to describe the input and output of the first-stage delay circuit in the P cascaded delay circuits, the input and output of the last-stage delay circuit, and the intermediate delay in the P cascaded delay circuits.
  • the input and output of the circuit Through the above connection relationship, the control signals of each delay circuit can be controlled to control the number of delay circuits connected in series, and the frequency of the reference clock signal output by the reference clock generation circuit can be different. Therefore, the reference clock circuit provided by the embodiments of the present application can be adapted to be used for clocks on different chips, and the application flexibility of the chips provided by the embodiments of the present application is improved.
  • first target circuit configuration information is stored on the chip, and the first target circuit configuration information indicates control signals corresponding to respective delay circuits in the reference clock generation circuit configuration.
  • the control signals corresponding to each delay circuit in the reference clock generation circuit are set according to the configuration information of the first target circuit, the frequency of the reference clock signal output by the reference clock generation circuit is the ideal working frequency, and the ideal working frequency is the ideal working frequency of the clock signal. working frequency.
  • the training process for the reference clock generation circuit may be completed before the chip leaves the factory.
  • the first target circuit configuration information obtained after training is written into the chip. In order to facilitate subsequent rapid detection of the frequency of the clock signal to be detected based on the configuration information of the first target circuit.
  • the first target circuit configuration information indicates that the control signals corresponding to each delay circuit are high level or low level respectively.
  • the control signal corresponding to any delay circuit in the P cascaded delay circuits is at a high level, the path from any delay circuit to the next-level delay circuit is turned on, and the corresponding control signal of any delay circuit is turned on.
  • the control signal is at a low level, the path from any delay circuit to the next-stage delay circuit is disconnected.
  • each delay circuit in the reference clock generation circuit can be turned on and off through a high and low level control signal, which improves the flexibility of controlling the reference clock generation circuit.
  • the reference clock generation circuit further includes a gating circuit, and the gating circuit includes a control terminal.
  • the first output end of the first stage delay circuit is connected with the output end of the reference clock generating circuit through the gate control circuit.
  • the control terminal of the gate control circuit is used to input the gate control enable signal, and the gate control enable signal is used to deduct one or more pulses in the clock signal output by the first output terminal of the first stage delay circuit to obtain the reference clock Signal.
  • the reference clock generating circuit further includes a NAND gate, and the NAND gate includes a first input terminal, a second input terminal, and an output terminal.
  • the first input end of the NAND gate is used for inputting an enable signal, and the enable signal instructs to turn on or off the reference clock generating circuit.
  • the second input terminal of the NAND gate is connected with the first output terminal of the first stage delay circuit.
  • the output end of the NAND gate is connected with the first input end of the first stage delay circuit.
  • the enable signal input on the NAND gate can also be used to control the turn-on and turn-off of the reference clock generation circuit, which improves the application flexibility of the reference clock generation circuit.
  • any delay circuit in the P delay circuits includes a first NAND gate, a second NAND gate, a third NAND gate, and an inverter , any one of the first NAND gate, the second NAND gate and the third NAND gate includes a first input terminal, a second input terminal and an output terminal.
  • the first input terminal of the delay circuit is connected to the first input terminals of the first NAND gate and the second NAND gate.
  • the second input terminal of the delay circuit is connected to the second input terminal of the third NAND gate.
  • the first output terminal of the delay circuit is connected to the output terminal of the third NAND gate.
  • the second output terminal of the delay circuit is connected to the output terminal of the first NAND gate.
  • the control terminal of the delay circuit is connected to the second input terminal of the first NAND gate and the input terminal of the inverter.
  • the output terminal of the inverter is connected to the second input terminal of the second NAND gate.
  • the output terminal of the second NAND gate is connected to the first input terminal of the third NAND gate.
  • the above is the specific structure of the delay circuit in the reference clock generation circuit provided by the embodiment of the present application. Through the combination of the above several simple logic gates, the delay circuit in the reference clock generation circuit provided by the embodiment of the present application can be realized. function of the time circuit. The complexity of the reference clock circuit provided by the embodiments of the present application is reduced, thereby improving the production efficiency of the chips provided by the embodiments of the present application.
  • the glitch detection circuit includes N cascaded delay circuits, N AND gates, N+1 flip-flops, and each AND of the N AND gates
  • the gate includes a first input end, a second input end and an output end, each of the N+1 flip-flops includes an input end, an output end and a control end, and N is a positive integer greater than 1.
  • the input terminal of the first-stage delay circuit in the N cascaded delay circuits and the second input terminal of each AND gate of the N AND gates are used for inputting a clock signal.
  • the output end of each delay circuit except the last stage delay circuit is connected to the input end of the next stage delay circuit.
  • each delay circuit in the N delay circuits is respectively connected with the first input end of an AND gate.
  • the control terminal of the first flip-flop among the N+1 flip-flops is used to input the clock signal, and the control terminals of the N flip-flops except the first flip-flop among the N+1 flip-flops are connected to the outputs of the N AND gates terminal, where one AND gate corresponds to one flip-flop.
  • the output of each of the N+1 flip-flops is connected to the input of the same flip-flop through an inverter.
  • the output signals of the output terminals of the N+1 flip-flops are used to detect whether the clock signal contains glitches.
  • the second target circuit configuration information is stored on the chip.
  • the second target circuit configuration information indicates which one of the N flip-flops the target flip-flop is.
  • the output signal of the target flip-flop and the output signal of the first flip-flop are used to detect whether the clock signal contains a glitch.
  • the configuration information of the second target circuit may be written into the chip before the chip leaves the factory. In order to quickly detect whether the clock signal contains a glitch based on the configuration information of the second target circuit subsequently.
  • the N delay circuits are delay circuits with the same structure, and the target trigger is based on the glitch detection range and a single delay circuit in the N delay circuits. Determined by the delay time, the glitch detection range indicates the pulse width of the glitch contained in the clock signal.
  • the glitch detection circuit includes multiple flip-flops, the glitch detection circuit provided by the embodiments of the present application can be applied in different glitch detection ranges, which improves the application flexibility of the chip provided by the implementation of the present application.
  • any delay circuit in the N delay circuits includes a first NAND gate, a second NAND gate, a third NAND gate, and an inverter , any one of the first NAND gate, the second NAND gate and the third NAND gate includes a first input terminal, a second input terminal and an output terminal.
  • the input terminal of the delay circuit is connected to the first input terminal of the first NAND gate and the second NAND gate.
  • the output end of the delay circuit is connected to the input end of the next stage delay circuit.
  • the control terminal of the delay circuit is connected to the second input terminal of the first NAND gate and the input terminal of the inverter.
  • the output terminal of the inverter is connected to the second input terminal of the second NAND gate.
  • the output terminal of the second NAND gate is connected to the first input terminal of the third NAND gate.
  • the output terminal of the first NAND gate is connected to the second input terminal of the third NAND gate.
  • the above is the specific structure of the delay circuit in the glitch detection circuit provided by the embodiment of the present application.
  • the delay circuit in the glitch detection circuit provided by the embodiment of the present application can be realized. Function.
  • the complexity of the burr detection circuit provided by the embodiment of the present application is reduced, thereby improving the production efficiency of the chip provided by the embodiment of the present application.
  • the duty cycle detection circuit includes a first delay adjustment circuit, a second delay adjustment circuit, and M cascaded third delay adjustment circuits, a division Frequency converter, first inverter, second inverter, first two-level register and M+1 second two-level register, M+1 XOR gate and M+1 flip-flop, M is greater than 1 positive integer of .
  • any one of the first two-level register and the M+1 second two-level registers includes a first input terminal, a second input terminal and an output terminal
  • each XOR gate in the M+1 XOR gates includes a first input terminal, a second input terminal and an output terminal.
  • each of the M+1 flip-flops includes an input end, an output end and a control end
  • the frequency divider includes an input end, an output end and a control end.
  • the control end of the frequency divider is used to input the clock signal
  • the input end of the frequency divider and the output end of the frequency divider are connected through a second inverter, and the output end of the frequency divider and the input of the first delay adjustment circuit
  • the output end of the first delay adjustment circuit is connected to the input end of the second delay adjustment circuit, and the output end of the second delay adjustment circuit is connected to the first stage of the cascaded M third delay adjustment circuits.
  • the input terminals of the three delay adjustment circuits are connected, and the output terminals of each third delay adjustment circuit except the last stage of the third delay adjustment circuit in the cascaded M third delay adjustment circuits are connected to the next stage of the third delay adjustment circuit.
  • the input terminals of the three delay adjustment circuits are connected.
  • the output end of the second delay adjustment circuit and the output end of each third delay adjustment circuit of the cascaded M third delay adjustment circuits are connected to the first one of the M+1 second two-stage registers in a one-to-one correspondence. input.
  • the second input terminals of the M+1 second two-level registers are all connected to the output terminal of the first inverter, and the input terminal of the first inverter is used to input the clock signal.
  • the output terminals are connected with the first input terminals of the M+1 XOR gates in a one-to-one correspondence.
  • the outputs of the M+1 XOR gates are connected to the inputs of the M+1 flip-flops in one-to-one correspondence.
  • the output end of the first inverter is also connected to the first input end of the first two-stage register, the output end of the frequency divider is connected to the second input end of the first two-stage register, and the output end of the first two-stage register is connected to the second input end of the first two-stage register.
  • the second input terminals of the M+1 XOR gates are connected.
  • the output signals of the output terminals of the M+1 flip-flops are used to detect the duty cycle of the clock signal.
  • the duty cycle of the clock signal can be detected, so that the chip provided by the embodiment of the present application can be applied in different test scenarios.
  • the application flexibility of the chip provided by the embodiment of the present application is improved.
  • any third delay adjustment circuit in the M third delay adjustment circuits includes k cascaded delay circuits, and the k cascaded delay circuits
  • Each delay circuit in the time circuit includes a control terminal, and the control terminal is used for inputting a control signal to control the corresponding delay circuit to be turned on or off, and k is a positive integer greater than 1.
  • the first stage delay circuit in the k cascaded delay circuits includes a first input end and a first output end. The first input end of the first stage delay circuit is connected with the input end of the third delay adjustment circuit. The first output end of the first stage delay circuit is connected with the output end of the third delay adjustment circuit.
  • the third delay adjustment module in the duty cycle detection circuit can be realized through k cascaded delay circuits, and the third delay adjustment module can be flexibly adjusted according to different needs based on the control signals corresponding to each delay circuit delay time. It not only reduces the complexity of the duty cycle detection circuit on the chip, but also improves the application flexibility of the chip.
  • each delay circuit in the k cascaded delay circuits includes a first input end, a second input end, a first output end, and a second output.
  • the second output end of the first stage delay circuit is connected to the first input end of the second stage delay circuit, and the second input end of the first stage delay circuit is connected to the first output end of the second stage delay circuit.
  • the first input terminal of the last stage delay circuit in the k cascaded delay circuits is connected to the second output terminal of the previous stage delay circuit of the last stage delay circuit; the second output terminal of the last stage delay circuit The output end is connected to the second input end of the last stage delay circuit; the first output end of the last stage delay circuit is connected to the second input end of the previous stage delay circuit of the last stage delay circuit.
  • the first input terminal of the intermediate delay circuit in the k cascaded delay circuits is connected to the upper stage of the delay circuit of the intermediate delay circuit. second output.
  • the first output terminal of the intermediate delay circuit is connected to the second input terminal of the upper stage delay circuit of the intermediate delay circuit.
  • the second output terminal of the intermediate delay circuit is connected to the first input terminal of the next stage delay circuit of the intermediate delay circuit.
  • the second input terminal of the intermediate delay circuit is connected to the first output terminal of the next stage delay circuit of the intermediate delay circuit.
  • the intermediate delay circuit is any delay circuit except the first-stage delay circuit and the last-stage delay circuit among the k cascaded delay circuits.
  • any delay circuit in the k delay circuits includes a first NAND gate, a second NAND gate, a third NAND gate, and an inverter , any one of the first NAND gate, the second NAND gate and the third NAND gate includes a first input terminal, a second input terminal and an output terminal.
  • the first input terminal of the delay circuit is connected to the first input terminals of the first NAND gate and the second NAND gate.
  • the second input terminal of the delay circuit is connected to the second input terminal of the third NAND gate.
  • the first output terminal of the delay circuit is connected to the output terminal of the third NAND gate.
  • the second output terminal of the delay circuit is connected to the output terminal of the first NAND gate.
  • the control terminal of the delay circuit is connected to the second input terminal of the first NAND gate and the input terminal of the inverter.
  • the output terminal of the inverter is connected to the second input terminal of the second NAND gate.
  • the output terminal of the second NAND gate is connected to the first input terminal of the third NAND gate.
  • connection mode between the above k delay circuits and the internal structure of the delay circuit are consistent with the relevant content in the aforementioned reference clock generation circuit, and the corresponding technical effects are not repeated here.
  • third target circuit configuration information is stored on the chip, wherein the third target circuit configuration information indicates the delay of series conduction in the k delay circuits The number of circuits, and the delay duration of the first delay adjustment circuit and the second delay adjustment circuit.
  • the second delay adjustment circuit and the third delay adjustment circuit are set according to the third target circuit configuration information, if a clock signal with a duty cycle of 50% is input to the duty cycle detection circuit , then half of the output signals of the output terminals of the M+1 flip-flops are high-level signals and half are low-level signals.
  • the configuration information of the third target circuit may be written into the chip before the chip leaves the factory. In order to facilitate subsequent rapid detection of the duty cycle of the clock signal based on the third target circuit configuration information.
  • the k delay circuits are delay circuits with the same structure, and the number of delay circuits that are connected in series in the k delay circuits is based on the duty cycle
  • the allowable range is determined by the delay duration of a single delay circuit in the k delay circuits, and the allowable range of the duty cycle indicates the allowable floating range of the duty cycle of the clock signal.
  • the delay circuits that are connected in series among the k delay circuits can be set through the allowable duty cycle range.
  • the duty cycle detection circuit provided by the embodiment of the present application can be applied to different allowable duty cycle ranges, which improves the application flexibility of the chip provided by the implementation of the present application.
  • a clock detection method is provided.
  • the method is used to explain the working process of each circuit on the chip provided by the above-mentioned first aspect, so as to realize the detection function of each of the above-mentioned circuits.
  • the method is applied to a processor on a chip, the chip further includes a clock for generating a clock signal, and the chip further includes at least one of a reference clock generation circuit, a glitch detection circuit or a duty cycle detection circuit.
  • the processor detects the clock signal based on at least one of the following: detecting the frequency of the clock signal based on the reference clock signal generated by the reference clock generating circuit; or detecting whether the clock signal contains a glitch based on the glitch detection circuit; or based on the duty cycle
  • the duty cycle detection circuit detects the duty cycle of the clock signal.
  • the above-mentioned implementation process of detecting the frequency of the clock signal based on the reference clock signal generated by the reference clock generation circuit may be: controlling the output frequency of the reference clock generation circuit to be ideal
  • the reference clock signal of the working frequency, the ideal working frequency is the ideal working frequency of the clock signal; if the actual working frequency of the clock signal and the frequency of the reference clock signal are different, it is determined that the frequency of the clock signal is unstable.
  • the reference clock generation circuit includes P cascaded delay circuits, the chip stores first target circuit configuration information, and the first target circuit configuration The information indicates the configuration of each delay circuit in the reference clock generation circuit corresponding to the control signal respectively.
  • the implementation process of controlling the reference clock signal whose output frequency is the ideal operating frequency of the reference clock generating circuit may be: based on the configuration information of the first target circuit, controlling the control signals corresponding to each delay circuit in the reference clock generating circuit to Make the reference clock generating circuit output the reference clock signal whose frequency is the ideal working frequency.
  • the glitch detection circuit includes N cascaded delay circuits and N+1 flip-flops.
  • the implementation process of detecting whether the clock signal contains a glitch based on the glitch detection circuit can be as follows: input the clock signal into the first flip-flop to obtain the first output signal; the first flip-flop is any one of the N+1 flip-flops.
  • the clock signal is input to the X+1th flip-flop after passing through X cascaded delay circuits, and the X+1th output signal is obtained; wherein, X takes each positive integer from 1 to N in turn; obtain the glitch detection circuit In the output signal and the first output signal of the target flip-flop, the target flip-flop is a flip-flop except the first flip-flop among the N+1 flip-flops; If the output signal is different during the period, it is determined that the clock signal contains glitches.
  • second target circuit configuration information is stored on the chip, wherein the second target circuit configuration information indicates that the target flip-flops are N+1 flip-flops which one.
  • the implementation process of acquiring the output signal of the target flip-flop in the glitch detection circuit may be: based on the configuration information of the second target circuit, acquiring the output signal of the target flip-flop in the glitch detection circuit.
  • the duty cycle detection circuit includes a frequency divider, a first inverter and M+1 flip-flops.
  • the implementation process of detecting the duty cycle of the clock signal based on the duty cycle detection circuit may be: inputting the clock signal to the input end of the frequency divider and the first inverter; The output signals of the output terminals of the M+1 flip-flops; if the output signals of the output terminals of the M+1 flip-flops include a high-level signal and a low-level signal, the first duty cycle prompt signal is output, and the first duty cycle The ratio prompt signal is used to indicate that the duty cycle of the clock signal is within the allowable duty cycle range.
  • a second duty cycle prompt signal is output, and the second duty cycle prompt signal is output.
  • the duty cycle prompt signal indicates that the duty cycle of the clock signal is not within the allowable duty cycle range, and the proportion of the low-level signal in the clock signal exceeds the allowable duty cycle range.
  • a third duty cycle prompt signal is output, and the third duty cycle prompt signal indicates that the duty cycle of the clock signal is not within the allowable duty cycle range within the clock signal, and the proportion of the high-level signal in the clock signal exceeds the allowable range of the duty cycle.
  • the method is applied to the chip provided above, where third target circuit configuration information is stored on the chip, wherein the third target circuit configuration information indicates that The number of delay circuits connected in series among the k delay circuits included in any third delay adjustment circuit, and the delay time lengths of the first delay adjustment circuit and the second delay adjustment circuit.
  • the duty cycle detection circuit may also be configured based on the configuration information of the third target circuit.
  • a computer-readable storage medium where instructions are stored in the computer-readable storage medium, and when the instructions are executed on a computer, make the computer execute the clock detection method described in the second aspect above.
  • a computer program product containing instructions, when the instructions are run on a computer, the computer causes the computer to execute the clock detection method described in the first aspect.
  • FIG. 1 is a schematic structural diagram of a chip provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a reference clock generation circuit provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another reference clock generation circuit provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of another reference clock generation circuit provided by an embodiment of the present application.
  • FIG. 5 is a schematic flowchart of a training reference clock generation circuit provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a glitch detection circuit provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a pulse sequence in a glitch detection circuit provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of the connection relationship of each delay circuit in a glitch detection circuit provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of pulse timing of output signals of each circuit in a duty cycle detection circuit provided by an embodiment of the present application.
  • FIG. 11 is a flowchart of a clock detection method provided by an embodiment of the present application.
  • FIG. 13 is a schematic diagram of a complete flow of a training and detection clock frequency provided by an embodiment of the present application.
  • FIG. 16 is a detection result of a duty cycle detection circuit provided in an embodiment of the present application in a case where a low level ratio is too large, and a detection result of a duty cycle detection circuit in a case where a high level ratio is too large.
  • references herein to "a plurality” means two or more.
  • “/” means or means, for example, A/B can mean A or B;
  • "and/or” in this text is only a relationship to describe the related objects, Indicates that three relationships can exist, for example, A and/or B, can represent: A alone exists, A and B exist at the same time, and B exists alone.
  • words such as “first” and “second” are used to distinguish the same or similar items with basically the same function and effect. Those skilled in the art can understand that the words “first”, “second” and the like do not limit the quantity and execution order, and the words “first”, “second” and the like are not necessarily different.
  • the output signal of the clock on the chip is simply referred to as the clock signal of the chip.
  • the clock signal in the chip is an indispensable signal in the chip system.
  • the frequency and duty cycle of the clock signal may change.
  • the clock signal may introduce glitches. These conditions may cause the chip to not work properly.
  • it is usually necessary to detect the clock signal of the chip.
  • the clock detection method provided by the embodiment of the present application is applied to the above scenario of detecting the clock signal of the chip.
  • the clock signal on the chip can be detected without introducing an external standard reference clock, thereby avoiding the waste of resources on the chip.
  • FIG. 1 is a schematic structural diagram of a chip provided by an embodiment of the present application.
  • the chip 100 includes a processor 101 , an interface circuit 102 , a clock 103 , a reference clock generation circuit 104 , a glitch detection circuit 105 and a duty cycle detection circuit 106 .
  • the interface circuit 102 is used to receive instructions and transmit them to the processor 101, and the processor 101 is used to execute the instructions.
  • the clock 103 is a circuit capable of outputting a pulse signal of a certain frequency.
  • the clock 103 is used to input a clock signal to the processor 101, and control the operating frequency of the processor 101 through the clock signal.
  • the processor 101 is further configured to execute the clock detection method provided by the embodiment of the present application to complete the detection of the clock 103 on the same chip.
  • FIG. 1 is only an optional structure of the chip involved in the embodiment of the present application.
  • the embodiments of the present application do not limit the specific structure of the chip. Any chip configured with a clock is within the protection scope of the chip involved in the embodiments of the present application.
  • the digital circuit on the chip is improved in advance, so as to facilitate the subsequent analysis of the chip based on the improved digital circuit. detected on the clock signal.
  • Specific improvements include the following aspects.
  • the reference clock generation circuit 104 is configured on the chip.
  • the reference clock generating circuit 104 is used for outputting a reference clock signal required for detecting the clock signal of the chip.
  • a standard reference clock is simulated by the reference clock generating circuit 104 .
  • the reference clock generation circuit is an all-digital circuit, and the digital circuit is based on binary, the small fluctuation of the power supply voltage has basically no effect on the stability, and the temperature and process deviation have less influence on the reliability of the digital circuit than the analog circuit.
  • analog circuits digital circuits have the advantages of high reliability and good stability.
  • digital circuit design is easier to carry out process migration. When changing different processes, digital circuits can quickly complete the design.
  • the reference clock generation circuit provided by the embodiments of the present application has the characteristics of high reliability and good stability.
  • An all-digital circuit means that the circuit is composed of multiple logic gates, and the function of the reference clock generation circuit is realized through the connection of multiple logic gates.
  • the reference clock generating circuit includes P cascaded delay circuits, each delay circuit is used to perform certain delay processing on the input signal, and P is a positive integer greater than 1.
  • each delay circuit in the P cascaded delay circuits includes a control terminal, and the control terminal is used for inputting a control signal to control the corresponding delay circuit to be turned on or off.
  • Each of the P cascaded delay circuits includes a first input end, a second input end, a first output end and a second output end.
  • the first input terminal of the first-stage delay circuit is used for inputting an initial clock signal, and the initial clock signal is output from the first output terminal of the first-stage delay circuit after passing through at least one stage of the conduction delay circuit.
  • the first output end of the first stage delay circuit is connected to the output end of the reference clock generating circuit, and the output end of the reference clock generating circuit is used for outputting the reference clock signal.
  • the input and output of the first stage delay circuit and the input and output of the last stage delay circuit are as follows:
  • the second output end of the first stage delay circuit is connected to the first input end of the second stage delay circuit, and the second input end of the first stage delay circuit is connected to the first output end of the second stage delay circuit.
  • the first input terminal of the last stage delay circuit is connected to the second output terminal of the upper stage delay circuit of the last stage delay circuit.
  • the second output terminal of the last stage delay circuit is connected to the second input terminal of the last stage delay circuit.
  • the first output terminal of the last stage delay circuit is connected to the second input terminal of the previous stage delay circuit of the last stage delay circuit.
  • the input and output of the intermediate delay circuit in the P cascaded delay circuits are as follows (the intermediate delay circuit is the first stage delay circuit and the last stage delay circuit in the P cascaded delay circuits except the first stage delay circuit and the last stage delay circuit. any delay circuit):
  • the first input terminal of the intermediate delay circuit in the P cascaded delay circuits is connected to the second output terminal of the upper stage delay circuit of the intermediate delay circuit.
  • the first output terminal of the intermediate delay circuit is connected to the second input terminal of the upper stage delay circuit of the intermediate delay circuit.
  • the second output terminal of the intermediate delay circuit is connected to the first input terminal of the next stage delay circuit of the intermediate delay circuit.
  • the second input terminal of the intermediate delay circuit is connected to the first output terminal of the next stage delay circuit of the intermediate delay circuit.
  • FIG. 2 is a schematic structural diagram of a reference clock generating circuit 200 provided by an embodiment of the present application.
  • the reference clock generating circuit 200 includes P cascaded delay circuits.
  • the P cascaded delay circuits are sequentially connected from left to right.
  • each delay circuit includes a control terminal, and the control terminal is used for inputting a control signal.
  • the first input terminal of the first stage delay circuit from left to right is used to input an initial clock signal, and the initial clock signal passes through at least one stage delay circuit among the P delay circuits shown in FIG. 2 .
  • the signal is output from the first input terminal of the first stage delay circuit, and then the reference clock signal is output from the output terminal of the reference clock generating circuit.
  • connection relationship between each input terminal and the input terminal from the first stage delay circuit to the last stage delay circuit is as shown in FIG. 2 .
  • the specific connection relationship has been described in detail in the above embodiments, and will not be repeated here.
  • each delay circuit in the P cascaded delay circuits includes a control terminal, and the control terminal is used for inputting a control signal to control the corresponding delay circuit to be turned on or off. It can be seen from this that the control terminals of each delay circuit in the P delay circuits are respectively used to input a control signal, and the path from each delay circuit connected in series to the next stage delay circuit is opened by the corresponding control signal or off.
  • each delay circuit corresponds to one control signal
  • the path of each delay circuit leading to the next stage delay circuit can be opened or closed by the control signal. For example, when the control signal corresponding to a certain delay circuit is at a high level, the path of the delay circuit leading to the next stage delay circuit is turned on. When the control signal corresponding to a certain delay circuit is at a low level, the path of the delay circuit leading to the next stage delay circuit is disconnected.
  • the number of delay circuits connected in series can be controlled by controlling the control signals of each delay circuit, and the number of delay circuits connected in series can be called the number of series stages.
  • the frequencies of the reference clock signals output by the clock generating circuits are different. Therefore, the reference clock generation circuit can be trained based on the ideal working parameters of the clock on the chip in advance.
  • the training process includes: continuously adjusting the control signals corresponding to each delay circuit until the reference clock signal output by the reference clock generation circuit satisfies the aforementioned ideal. working parameters. For example, starting from the first delay circuit, the control signal corresponding to the delay circuit can be set to a high level in turn, until the clock signal output by the reference clock generation circuit meets the ideal working parameters.
  • the configuration information of the control signal corresponding to each delay circuit may be referred to as target circuit configuration information of the reference clock generating circuit.
  • the target circuit configuration information may also be referred to as a configuration level or a configuration codeword, and so on.
  • the configuration information of the control signal may specifically indicate whether the control signal is at a high level or a low level, or indicate the number of delay circuits that are connected in series in the reference clock generating circuit.
  • the target circuit configuration information obtained by training the reference clock generation circuit may also be referred to as the first target circuit configuration information.
  • any delay circuit in the above-mentioned reference clock generation circuit may include a first NAND gate, a second NAND gate, a third NAND gate and an inverter, and the first NAND gate Any one of the second NAND gate and the third NAND gate includes a first input terminal, a second input terminal and an output terminal, and the inverter includes an input terminal and an output terminal.
  • the first input terminal of the delay circuit is connected to the first input terminals of the first NAND gate and the second NAND gate.
  • the second input terminal of the delay circuit is connected to the second input terminal of the third NAND gate.
  • the first output terminal of the delay circuit is connected to the output terminal of the third NAND gate.
  • the second output terminal of the delay circuit is connected to the output terminal of the first NAND gate.
  • the control terminal of the delay circuit is connected to the second input terminal of the first NAND gate and the input terminal of the inverter.
  • the output terminal of the inverter is connected to the second input terminal of the second NAND gate.
  • the output terminal of the second NAND gate is connected to the first input terminal of the third NAND gate.
  • serial connection manner of each delay circuit in the reference clock generation circuit can be specifically expressed as follows.
  • the first input end of the first NAND gate in the first delay circuit connected in series is used for inputting a signal to be modulated, and the signal to be modulated is the above-mentioned initial clock signal.
  • the first input terminal of the first NAND gate in the delay circuits except the first delay circuit is connected with the output terminal of the first NAND gate in the upper stage delay circuit connected in series.
  • the second input terminal of the first NAND gate and the input terminal of the inverter in any delay circuit are used to input control signals corresponding to any delay circuit.
  • the output terminal of the inverter in any delay circuit is connected to the second input terminal of the second NAND gate in the same delay circuit, and the first input terminal of the second NAND gate in any delay circuit is connected to the same
  • the input signal of the first input terminal of the first NAND gate in the delay circuit is the same
  • the output terminal of the second NAND gate in any delay circuit is connected to the first input terminal of the third NAND gate in the same delay circuit.
  • the second input terminal of the third NAND gate in the last delay circuit after the series connection is connected to the output terminal of the first NAND gate in the same delay circuit, and other delays except the last delay circuit after the series connection
  • the second input terminal of the third NAND gate in the circuit is connected with the output terminal of the third NAND gate in the next stage delay circuit.
  • the output end of the third NAND gate in the first delay circuit connected in series is used to output a clock signal after the frequency of the signal to be modulated is adjusted, thereby obtaining a reference clock signal.
  • FIG. 3 is a schematic structural diagram of a reference clock generating circuit according to an embodiment of the present application.
  • the reference clock generating circuit 200 includes P delay circuits 201 , and each delay circuit 201 includes three NAND gates 2011 - 2013 and an inverter 2014 .
  • Each delay circuit corresponds to a control signal, and the control signal is marked as SEL in FIG. 3 .
  • a NAND gate has two inputs and one output.
  • the output signal of the output terminal is low level.
  • the output terminal output signal is high level.
  • the inverter can invert the phase of the input signal by 180 degrees.
  • any of the NAND gates 2011-2013 includes a first input terminal, a second input terminal and an output terminal.
  • the number 1 is used to mark the first input terminal of the NAND gate.
  • the number 2 marks the second input of the NAND gate.
  • Inverter 2014 includes an input terminal and an output terminal.
  • the first input terminals of the NAND gate 2011 and the NAND gate 2012 are both used for the input signal a, and the input signal a is the initial clock signal.
  • the second input terminal of the NAND gate 2011 is used to input the control signal SEL, and the output terminal of the NAND gate 2011 is connected to the first input terminal of the NAND gate 2011 in the next stage delay circuit.
  • the input terminal of the inverter 2014 is used to input the control signal SEL.
  • the output terminal of the inverter 2014 is connected to the second input terminal of the NAND gate 2012 .
  • the first input terminal of the NAND gate 2012 and the input signal of the first input terminal of the NAND gate 2011 in the same delay circuit are the same.
  • the output terminal of the NAND gate 2012 is connected to the first input terminal of the NAND gate 2013, and the second input terminal of the NAND gate 2013 is connected to the output terminal of the NAND gate 2013 in the next stage delay circuit.
  • the signal a is a pulse signal of a certain frequency
  • the first delay circuit is taken as an example to illustrate the process of each delay circuit processing the signal.
  • the signal a is input to the first delay circuit
  • the signal a is input to the first input terminal of the NAND gate 2011 and the first input terminal of the NAND gate 2012 .
  • the output of the NAND gate 2011 is a pulse signal with a certain delay, which indicates that the path to the next stage delay circuit is opened.
  • the output signal of the inverter 2014 is a low-level signal
  • the output signal of the NAND gate 2012 is a high-level signal
  • the output signal of the NAND gate 2012 is input to the first input terminal of the NAND gate 2013, and the next stage The output signal of the NAND gate 2013 in the delay circuit is input to the second input terminal of the NAND gate 2013. Since the output of the NAND gate 2012 is a high level signal, the output of the NAND gate 2013 is relative to the next The output signal of the NAND gate 2013 in the stage delay circuit has a certain delay output signal.
  • the output of the NAND gate 2011 is a high level signal, indicating that the path leading to the next-stage delay circuit is closed.
  • the NAND gate 2013 of the next-stage delay circuit is closed.
  • the output is also a high level signal.
  • the NAND gate 2012 inputs the signal a
  • the NAND gate 2012 outputs a pulse signal with a certain delay relative to the signal a
  • the output signal of 2013 is input to the NAND gate 2013 of the delay circuit of this stage. Since the output signal of the NAND gate 2013 in the next stage delay circuit is a high-level signal, the output signal of the NAND gate 2013 is a pulse signal with a certain delay relative to the output signal of the NAND gate 2012 .
  • the delay circuit provided in the embodiment of the present application includes two paths, one path leads to the next stage delay circuit, and the other path leads to the output end of the current stage delay circuit.
  • the control signal of the delay circuit When the control signal of the delay circuit is at a high level, the path leading to the next stage of the delay circuit is turned on, and the signal a is input to the next stage of the delay circuit to achieve further delay; when the control signal of the delay circuit is at a low level
  • the level is high, the path through the delay circuit of the next stage is disconnected, and the signal a returns to the delay circuit of the previous stage from the output end of the delay circuit of this stage after passing through the NAND gate 2012 and the NAND gate 2013 of the delay circuit of this stage .
  • the output terminal of the NAND gate 2011 of the last stage delay circuit is connected to the second input terminal of the NAND gate 2013 of the last stage delay circuit.
  • FIG. 4 is a schematic structural diagram of another reference clock generation circuit provided by an embodiment of the present application.
  • the reference clock generation circuit further includes a NAND gate 2000 , and the NAND gate 2000 is used to generate an enable signal and a reference clock generation circuit
  • the signal a is obtained, and the signal a is input to the first delay circuit, so as to facilitate the subsequent adjustment of the signal a through each delay circuit Frequency of.
  • the first input terminal of the NAND gate 2000 is used to input an enable signal, and the enable signal instructs to turn on or off the reference clock generating circuit.
  • the second input terminal of the NAND gate 2000 is connected to the first output terminal of the first stage delay circuit.
  • the output terminal of the NAND gate 2000 is connected to the first input terminal of the first stage delay circuit.
  • the enable signal when the enable signal is at a high level, it indicates that the reference clock generation circuit is turned on. At this time, the reference clock generation circuit is driven by the enable signal, and the first output terminal of the first-stage delay circuit is at the input of the enable signal. At the initial moment, a clock signal of a certain frequency is output first.
  • the clock signal and the enable signal pass through the NAND gate 2000 and then output the signal a, and then the signal a passes through the cascaded P delay circuits from the first stage of the first stage delay circuit.
  • the output terminal finally outputs a clock signal with a stable frequency.
  • the enable signal is at a low level, it indicates that the reference clock generating circuit is turned off, and the first output end of the first-stage delay circuit will not output a clock signal of a certain frequency at this time.
  • any delay circuit if the corresponding SEL signal is at a high level, it indicates that the path of the delay circuit to the next delay circuit is opened , so that the pulse signal can continue to be delayed by the next delay circuit. If the corresponding SEL signal is at a low level, it indicates that the path from the delay circuit to the next delay circuit is closed.
  • adjusting the SEL signal of each delay circuit specifically refers to how many consecutive delay circuits have control signals of high level from the first stage delay circuit.
  • the configuration information of the control signals of each delay circuit from left to right shown in any one of FIG. 2 to FIG. 4 may be [1, 1, 1, 0, 0, 0, 0..., 0], "1" means high level, "0" means low level, it means that the first three delay circuits lead to the next level is opened, and the subsequent The path of each delay circuit to the next stage delay circuit is closed.
  • the control signal SEL corresponding to each delay circuit is adjusted, the frequency of the input pulse signal a can be adjusted. Therefore, the reference clock generating circuit can be trained based on the ideal operating parameters of the clock on the chip in advance, so that the reference clock generating circuit outputs a reference clock signal satisfying the ideal operating frequency. Then, the configuration information of each control signal SEL in the reference clock generation circuit at this time is written into the chip as the target circuit configuration information for use in subsequent clock detection.
  • the target circuit configuration information at this time specifically refers to: the control signals corresponding to the P delay circuits are high level or low level. For example, a high level is 1 and a low level is 0.
  • the above process of training the reference clock generation circuit may be: adjusting the control signals of each delay circuit in the reference clock generation circuit, after adjusting the control signals of each delay circuit of the reference clock generation circuit, in the first Count the number of pulses in the output signal of the reference clock generating circuit within a timing period, if the difference between the number of pulses counted within the first timing period and the first theoretical value is within the first reference difference, then based on this The control signal of each delay circuit after the second adjustment determines the configuration information of the target circuit. If the difference between the number of pulses counted in the first timing period and the first theoretical value exceeds the first reference difference, continue to adjust the control signals of each delay circuit of the reference clock generating circuit.
  • the first theoretical value indicates the number of pulses in the pulse signal whose frequency is the ideal working frequency within the first timing period.
  • the ideal operating frequency of the clock on the chip is 24 megahertz (MHz)
  • the reference clock generating circuit shown in any of Figures 2 to 4 it is assumed that the target circuit configuration information is [1, 1, 1, 1, 0, 0, 0..., 0], it means that the first four delay circuits from left to right in Figure 2 are opened in turn through the series connection between the delay circuits in the next stage, and the other delay circuits pass through the next stage.
  • the frequency of the reference clock signal output by the reference clock generation circuit is 24MHz.
  • the reference clock generation circuit After adjusting the control signals of each delay circuit in the reference clock generation circuit each time, in order to make the reference clock generation circuit generate a stable clock signal, after adjusting the control signals of each delay circuit, wait for a few seconds. cycle (cycle) period, so that the reference clock generating circuit outputs a stable clock signal.
  • the ring formed by the NAND gate 2000 and the subsequent delay circuits in the reference clock generation circuit is also called an oscillation ring.
  • the reference clock generation circuit After waiting for several cycles, the reference clock generation circuit outputs a stable clock signal, which is an oscillation ring. A stable clock signal is output.
  • the above-mentioned adjustment of the control signal of each delay circuit in the reference clock generation circuit can be realized by the method of dichotomy, thereby speeding up the above-mentioned training process. That is, if the frequency of the clock signal output by the reference clock generation circuit after adjustment this time does not meet the ideal operating frequency, then based on the control signals of each delay circuit adjusted last time and the dichotomy method, each time that needs to be adjusted next time is obtained. Control signal for the delay circuit.
  • the reference clock generation circuit shown in any of Figures 2 to 4 includes 60 delay circuits. It is assumed that the control signals corresponding to the first 30 delay circuits are at high level, and the control signals corresponding to the last 30 delay circuits are assumed to be high. is low level, and then determines the frequency of the clock signal output by the reference clock generation circuit at this time. Based on the frequency and the ideal operating frequency, determine whether the number of targets is within 30 or more than 30.
  • the target number specifically refers to: when the frequency of the clock signal output by the reference clock generation circuit conforms to the ideal operating frequency, the reference clock generates The number of delay circuits connected in the circuit.
  • the target number is within 30, continue to assume that the control signals corresponding to the first 15 delay circuits are high, and the control signals corresponding to the last 45 delay circuits are low, and then determine the output of the reference clock generation circuit at this time. The frequency of the clock signal. The above process is repeated until the determined frequency of the clock signal output by the reference clock generating circuit is substantially the same as the ideal operating frequency.
  • the reference clock generating circuit may further include a gating circuit, wherein the gating circuit is connected to the first output end of the first delay circuit connected in series.
  • the gate control enable signal is used to deduct one or P pulses of the clock signal output by the second output terminal of the first delay circuit after the series connection, so as to realize Buckle pulse.
  • the above-mentioned gating circuit can be specifically implemented by a flip-flop, and the embodiment of the present application does not limit the internal structure of the gating circuit.
  • the gate control circuit includes an input terminal, an output terminal and a control terminal.
  • the input end of the gate control circuit is connected with the first output end of the first stage delay circuit, and the output end of the gate control circuit is connected with the output end of the reference clock generating circuit, that is, the first output end of the first stage delay circuit
  • the terminal is connected through the gating circuit and the output terminal of the reference clock generating circuit.
  • the control terminal of the gate control circuit is used to input the gate control enable signal.
  • the control terminal of the gate control circuit is marked with a number "1"
  • the input terminal in the gate control circuit is marked with a number "2”
  • the output terminal of the gate control circuit is marked with a number "3".
  • the target circuit configuration information not only includes whether the control signal corresponding to each delay circuit is high or low, but also includes the configuration information of the gating enable signal.
  • FIG. 5 is a schematic flowchart of a training reference clock generating circuit provided by an embodiment of the present application.
  • the training starts, first set the configuration stages of the reference clock generation circuit and the number of deduction pulses.
  • the configuration stages are used to indicate whether the control signal corresponding to each delay circuit is high or not as mentioned above low level.
  • the clock signal output by the reference clock generating circuit shown in FIG. 2 After waiting for the clock signal output by the reference clock generating circuit shown in FIG. 2 to circulate for several cycles, count the number of pulses of the reference clock generating circuit within the first timing duration to obtain the counting result. Then, it is judged whether the counting result conforms to the first theoretical value, and the first theoretical value indicates the number of pulses of the pulse signal whose frequency is the ideal working frequency within the first timing period.
  • the current configuration stage number is taken as the final configuration stage number, so as to obtain the target circuit configuration information. If the counting result does not conform to the first theoretical value, change the number of configuration stages by dichotomy, change the number of deduction pulses accordingly, and return to the process of recounting until the final configuration stage is obtained.
  • FIG. 3 and FIG. 4 are only a circuit structure of an optional delay circuit provided by the embodiment of the present application. Any other circuit structures with the same function are also within the protection scope of the delay circuit involved in the embodiments of the present application, and will not be described one by one here.
  • the glitch detection circuit 105 is arranged on the chip.
  • the glitch detection circuit in order to facilitate the subsequent detection of the burr signal in the clock signal of the chip.
  • the glitch detection circuit can also be preconfigured on the chip.
  • the glitch detection circuit is an all-digital circuit, and the advantages of the all-digital circuit are not repeated here.
  • detecting a glitch in the clock signal in the embodiment of the present application may also be referred to as detecting a glitch in the clock signal, that is, "glitch signal” and “glitch” are used to refer to the same concept in the embodiment of the present application.
  • the glitch detection circuit includes N delay circuits, N AND gates, and N+1 flip-flops.
  • Each delay circuit includes an input end and an output end
  • each AND gate includes a first input end, a second input end and an output end
  • each flip-flop includes an input end, an output end and a control end.
  • N is a positive integer greater than 1.
  • N delay circuits are connected in series, and after the series connection, the output end of each delay circuit except the last delay circuit is connected to the input end of the next stage delay circuit, and each of the N delay circuits is connected in series.
  • the output terminal of the delay circuit is also connected with the first input terminal of an AND gate.
  • the input terminal of the first delay circuit connected in series and the second input terminal of each AND gate are used for inputting the clock signal of the chip to be detected. Subsequently, the clock signal of the chip to be detected is simply referred to as the clock signal to be detected.
  • each flip-flop in the N+1 flip-flops is connected inversely to the input terminal of the same flip-flop, and the control terminals of the N flip-flops in the N+1 flip-flops are respectively connected to the output terminal of an AND gate.
  • the control terminals of the remaining flip-flops in the +1 flip-flops except the aforementioned N flip-flops are used to input the clock signal to be detected.
  • the remaining flip-flops except the aforementioned N flip-flops may also be referred to as first flip-flops.
  • each AND gate will output the AND signal between the clock signal to be detected and the clock signal to be detected after a certain delay, and input the clock to be detected after the delay of each AND gate The delay time of the signal is gradually increased.
  • a target flip-flop can be selected from N flip-flops connected to each AND gate based on the glitch detection range, and then the output signal of the target flip-flop can be compared with the output signal of the flip-flop inputting the clock signal to be detected. Determine if there is a glitch in the clock signal to be detected. That is, the glitch signal in the clock signal to be detected can be detected based on the output signals of the output terminals of the N+1 flip-flops.
  • the glitch detection circuit includes N cascaded delay circuits, N AND gates, and N+1 flip-flops, and each AND gate of the N AND gates includes A first input end, a second input end and an output end, each of the N+1 flip-flops includes an input end, an output end and a control end, and the N is a positive integer greater than 1.
  • the input terminal of the first-stage delay circuit in the N cascaded delay circuits and the second input terminal of each AND gate of the N AND gates are used for inputting a clock signal.
  • the output end of each delay circuit except the last stage delay circuit is connected to the input end of the next stage delay circuit.
  • the output end of each delay circuit in the N delay circuits is respectively connected with the first input end of an AND gate.
  • the control terminal of the first flip-flop among the N+1 flip-flops is used to input the clock signal, and the control terminals of the N flip-flops except the first flip-flop among the N+1 flip-flops are connected to the outputs of the N AND gates terminal, where one AND gate corresponds to one flip-flop.
  • the output of each of the N+1 flip-flops is connected to the input of the same flip-flop through an inverter.
  • the output signals of the output terminals of the N+1 flip-flops are used to detect whether the clock signal contains glitches.
  • FIG. 6 is a schematic structural diagram of a glitch detection circuit provided by an embodiment of the present application.
  • N delay circuits are connected in series, and the output end of each delay circuit in the first N ⁇ 1 delay circuits after the series connection is connected to the input end of the next delay circuit.
  • the output terminal of each delay circuit is also connected to the first input terminal of an AND gate.
  • the first input terminal of the AND gate is marked as 1, and the second input terminal of the AND gate is marked as number 2.
  • the second input terminal of each AND gate is used for inputting the clock signal to be detected.
  • FIG. 7 is a schematic diagram of a pulse sequence in a glitch detection circuit provided by an embodiment of the present application. As shown in FIG. 7 , the detected clock signal is marked as clk, and the pulse distribution of clk is shown in FIG. 7 . Label the output signal of the first delay circuit as clk-dly1, label the output signal of the second delay circuit as clk-dly2, ..., label the output signal of the Nth delay circuit as clk-dlyN.
  • the pulse distribution of clk-dly1, clk-dly2, ..., clk-dlyN is shown in Fig. 7.
  • the AND gate When the output signal of each delay circuit and the clock signal to be detected are input to the corresponding AND gate, the AND gate outputs a signal that is an AND of the clock signal to be detected and the delayed clock signal to be detected.
  • clk-det1 is the output signal after clk-dly1 and clk pass through the AND gate
  • clk-det2 is the output signal after clk-dly2 and clk pass through the AND gate
  • ..., clk-detN is clk-dlyN and The output signal of clk after the AND gate.
  • the pulse distribution corresponding to clk-det1 has one more pulse at the position of the elliptical frame line in Fig. 7 than the position corresponding to clk-detN.
  • the pulse is the pulse corresponding to the glitch signal in the output signal of the detected clock.
  • the pulse distribution in the output signal of each AND gate in FIG. 7 can be sampled and determined by a flip-flop.
  • a flip-flop is connected to the output of each AND gate.
  • the flip-flop in FIG. 6 may include a control terminal (marked as CP in FIG. 6 ), an input terminal (marked as D in FIG. 6 ), and an output terminal (marked as Q in FIG. 6 ).
  • the output terminal of each AND gate in FIG. 6 is connected to the control terminal of a flip-flop. In this way, the flip-flop can acquire data on the rising edge of the output signal of the AND gate.
  • the input terminal of the flip-flop in FIG. 6 is used as the input signal after inverting the signal of the output terminal of the flip-flop. Therefore, the flip-flop shown in Figure 6 can change the output state on every rising edge of the output signal of the AND gate.
  • the stored 1 is converted into 0, and 0 is stored, and at the second rising edge of the output signal of the AND gate, the stored 0 is changed into 1, and 1 is stored. Therefore, through the 1 and 0 recorded by the flip-flop, the pulse distribution on each clock cycle in the output signal of the AND gate can be determined.
  • a target flip-flop is selected from the N flip-flops connected to each AND gate, and then the output signal of the target flip-flop is compared with the output signal of the flip-flop inputting the clock signal to be detected, which specifically refers to: comparing The distribution of 1s and 0s collected in each clock cycle can determine whether there is a glitch in the clock signal to be detected.
  • the fourth flip-flop For example, for each flip-flop shown in Figure 6 from top to bottom, select the data collected by the fourth flip-flop based on the glitch detection range to determine whether the clock signal to be detected has a glitch signal, and the fourth flip-flop is at a certain clock
  • the distribution of 1s and 0s collected in the cycle is 1000, but the distribution of 1s and 0s collected during the clock cycle of the last trigger (the clock signal to be detected) is 1010, which indicates that the clock cycle There is a glitch in the clock signal to be detected.
  • the above-mentioned selecting a target flip-flop from N flip-flops connected to each AND gate based on the glitch detection range specifically refers to: determining the delay time length of the output signal of each delay circuit relative to the clock signal to be detected, from the delay time The delay circuit corresponding to the minimum delay time is selected from each delay time whose duration exceeds the glitch detection range, and the trigger connected to the selected delay circuit is used as the target trigger.
  • the inherent delay time of each delay circuit shown in FIG. 6 is the same, and the inherent delay time of the delay circuit refers to the output signal of the delay circuit relative to the input signal of the delay circuit itself delay time.
  • the above-mentioned selecting a target trigger from N flip-flops connected to each AND gate based on the glitch detection range specifically refers to dividing the glitch detection range and the inherent delay time of a single delay circuit, and dividing the The value of is an integer, and if the integer is i, the trigger connected to the i-th delay circuit among the N delay circuits connected in series is taken as the target trigger.
  • the internal structure of the delay circuit included in the glitch detection circuit configured on the chip may be a delay circuit of the same structure as the internal structure of the delay circuit included in the aforementioned reference clock generation circuit, but the connection relationship between the respective delay circuits In this way, the inherent delay time of each delay circuit in the glitch detection circuit is the same as the inherent delay time of the delay circuit in the reference clock generation circuit. So that after the reference clock generation circuit is trained, the above target trigger can be determined based on the inherent delay duration and glitch detection range of the delay circuit in the trained reference clock generation circuit.
  • the glitch detection circuit does not need to be pre-trained, and it can be determined that it needs to be used only according to the inherent delay duration and glitch detection range of a single delay circuit in the trained reference clock generation circuit.
  • Which flip-flop in the glitch detection circuit is the target flip-flop.
  • the inherent delay duration of a single delay circuit in the trained reference clock generating circuit is determined, and then the upper limit of the glitch detection range is determined. Based on the upper limit of the glitch detection range and the aforementioned inherent delay time, the above target trigger can be configured.
  • FIG. 8 is a schematic diagram of a connection relationship of each delay circuit in a glitch detection circuit provided by an embodiment of the present application.
  • any one of the N delay circuits 601 includes a first NAND gate, a second NAND gate, a third NAND gate and an inverter, the first NAND gate, the second NAND gate Any of the NOT gate and the third NAND gate includes a first input terminal, a second input terminal and an output terminal, and the inverter includes an input terminal and an output terminal.
  • the first NAND gate is marked as 6011
  • the second NAND gate is marked as 6012
  • the third NAND gate is marked as 6013
  • the inverter is marked as 6014.
  • the first input of each NAND gate is marked with the number "1" and the second input of each NAND gate is marked with the number "2".
  • the first input terminal of the first NAND gate 6011 is the input terminal of the delay circuit 601
  • the output terminal of the third NAND gate 6013 is the output terminal of the delay circuit 601 , wherein N delays
  • the series connection of circuits specifically means that the output end of the first delay circuit 601 is connected to the input end of the second delay circuit 601 , and the output end of the second delay circuit 601 is connected to the output end of the third delay circuit 601 .
  • the input terminal, and so on, until the output terminal of the N-1th delay circuit 601 is connected to the input terminal of the Nth delay circuit 601 . That is, the input terminal of each stage delay circuit is connected to the output terminal of the previous stage delay circuit, and the output terminal of each stage delay circuit is connected to the input terminal of the next stage delay circuit.
  • the output terminal of the third NAND gate 6013 in any delay circuit is also connected to the first input terminal of one AND gate in FIG. 6 .
  • any delay circuit among the N delay circuits in the glitch detection circuit includes a first NAND gate, a second NAND gate, a third NAND gate and an inverter, and the first NAND gate
  • Any one of a NAND gate, a second NAND gate, and a third NAND gate includes a first input terminal, a second input terminal, and an output terminal.
  • the input end of the delay circuit is connected to the first input end of the first NAND gate and the second NAND gate.
  • the output end of the delay circuit is connected to the input end of the next stage delay circuit.
  • the control terminal of the delay circuit is connected to the second input terminal of the first NAND gate and the input terminal of the inverter.
  • the output terminal of the inverter is connected to the second input terminal of the second NAND gate.
  • the output terminal of the second NAND gate is connected to the first input terminal of the third NAND gate.
  • the output terminal of the first NAND gate is connected to the second input terminal of the third NAND gate.
  • control signals corresponding to each delay circuit are configured as high-level signals, so that each trigger in the glitch detection circuit shown in FIG. 6 can collect signals, thereby realizing glitches. Signal detection.
  • the glitch detection circuit preconfigured on the chip may include a larger number of delay circuits and AND gates and flip-flops subsequently connected to the delay circuit.
  • the detection range can be determined based on the glitch detection range, by which triggers connected to the serially connected delay circuits are used for detection. For example, 20 delay circuits connected in series are preconfigured in the glitch detection circuit. When it is determined that N is 3, the glitch signal only needs to be detected by the output signal of the trigger connected to the third delay circuit.
  • the glitch detection range of the clock signal it is possible to determine which trigger the upper target trigger is before the chip leaves the factory, and generate the second target circuit indication information, and then trigger the second target. For which flip-flop information is written to the chip.
  • the second target circuit configuration information may also be referred to as target circuit configuration information for the glitch detection circuit.
  • the duty ratio detection circuit 106 is arranged on the chip.
  • the duty cycle of the clock signal on the chip can also be detected.
  • the duty cycle detection circuit can also be configured on the chip in advance.
  • the duty cycle detection circuit is an all-digital circuit, and the advantages of the all-digital circuit are not repeated here.
  • FIG. 9 is a schematic structural diagram of a duty cycle detection circuit provided by an embodiment of the present application.
  • the duty cycle detection circuit includes a first delay adjustment circuit (the first delay adjustment circuit is marked as DLY-FIX in FIG. 9 ), a second delay adjustment circuit (in FIG. 9 the second delay adjustment circuit is marked as DLY-FIX)
  • the delay adjustment circuit is marked as DLE-TRIM-DUTY) and M third delay adjustment circuits (the third delay adjustment circuit is marked as DLY-CLK-DUTY in FIG. 9), frequency divider, inverter, M +2 two-level registers, M+1 XOR gates (the logic gate marked by XOR in Figure 9 indicates XOR gates), M+1 flip-flops.
  • M is a positive integer greater than 1.
  • Each XOR gate includes a first input terminal, a second input terminal and an output terminal.
  • Each two-level register includes a first input terminal, a second input terminal, and an output terminal.
  • the first input terminal of each two-level register is marked as a number "1”
  • the second input terminal of each two-level register is marked as a number "1”.
  • the end is marked with the number "2”.
  • Each flip-flop includes an input terminal, an output terminal and a control terminal.
  • Each XOR gate includes a first input terminal, a second input terminal, and an output terminal.
  • the first input terminal of each XOR gate is marked as a number "1”
  • the second input terminal of each XOR gate is marked as a number "1”.
  • the end is marked with the number "2”.
  • the frequency divider, the inverter, the first delay adjustment circuit, the second delay adjustment circuit and the M third delay adjustment circuits all include an input end and an output end.
  • M third delay adjustment circuits are connected in series, the output end of the frequency divider is connected with the input end of the first delay adjustment circuit, the output end of the first delay adjustment circuit is connected with the input end of the second delay adjustment circuit connection, the output end of the second delay adjustment circuit is connected with the input end of the first third delay adjustment circuit connected in series.
  • the output end of the second delay adjustment circuit and the output end of each third delay adjustment circuit connected in series are connected to the first input end of a two-stage register, and the output end of each two-stage register is connected to an XOR The first input end of the gate is connected.
  • the M two-level registers connected to each XOR gate among the M+1 two-level registers are called two-level registers A.
  • the output terminal of the inverter is connected to the first input terminal of the remaining two-stage register in the M+1 two-stage registers except the M two-stage registers.
  • the two-stage register is marked as two-stage register. stage register B.
  • the output end of the frequency divider is also connected to the second input end of the two-stage register B, and the output end of the two-stage register B is connected to the second input end of each XOR gate.
  • the output terminal of the inverter is also connected to the second input terminal of each two-stage register A. The input terminals of the frequency divider and the inverter are both used for inputting the clock signal to be detected.
  • the above-mentioned two-level register A may also be referred to as a second two-level register, and the two-level register B may also be referred to as a first two-level register.
  • the frequency divider can be obtained by combining a flip-flop and an inverter, that is, the frequency divider includes an input end, an output end and a control end, and the input end and the output end are connected through an inverter.
  • the inverter in the frequency divider may be referred to as the second inverter, and the inverter for inputting the clock signal to be detected may be referred to as the first inverter.
  • the connection relationship of the above duty cycle detection circuit can also be described as follows.
  • the duty cycle detection circuit includes a first delay adjustment circuit, a second delay adjustment circuit, and M cascaded third delay adjustment circuits, a frequency divider, a first inverter, a second inverter, a first Two-level registers, M+1 second two-level registers, M+1 XOR gates, and M+1 flip-flops, where M is a positive integer greater than 1.
  • any one of the first two-level register and the M+1 second two-level registers includes a first input terminal, a second input terminal and an output terminal
  • each XOR gate in the M+1 XOR gates includes a first input terminal, a second input terminal and an output terminal.
  • An input end, a second input end and an output end, each of the M+1 flip-flops includes an input end, an output end and a control end, and the frequency divider includes an input end, an output end and a control end.
  • the control end of the frequency divider is used to input the clock signal, the input end of the frequency divider and the output end of the frequency divider are connected through a second inverter, and the output end of the frequency divider and the input of the first delay adjustment circuit
  • the output end of the first delay adjustment circuit is connected to the input end of the second delay adjustment circuit, and the output end of the second delay adjustment circuit is connected to the first stage of the cascaded M third delay adjustment circuits.
  • the input terminals of the three delay adjustment circuits are connected.
  • the output end of the second delay adjustment circuit and the output end of each third delay adjustment circuit of the cascaded M third delay adjustment circuits are connected to the first one of the M+1 second two-stage registers in a one-to-one correspondence. input.
  • the second input terminals of the M+1 second two-level registers are all connected to the output terminal of the first inverter, and the input terminal of the first inverter is used to input the clock signal.
  • the output terminals are connected with the first input terminals of the M+1 XOR gates in a one-to-one correspondence.
  • the outputs of the M+1 XOR gates are connected to the inputs of the M+1 flip-flops in one-to-one correspondence.
  • the output end of the first inverter is also connected to the first input end of the first two-stage register, the output end of the frequency divider is connected to the second input end of the first two-stage register, and the output end of the first two-stage register is connected to the second input end of the first two-stage register.
  • the second input terminals of the M+1 XOR gates are connected.
  • the output signals of the output terminals of the M+1 flip-flops are used to detect the duty cycle of the clock signal.
  • FIG. 10 is a schematic diagram of a pulse timing sequence of an output signal of each circuit in a duty cycle detection circuit provided by an embodiment of the present application.
  • the clock signal to be detected is marked as clk
  • the output signal of the frequency divider is marked as clk-div2
  • the frequency of clk-div2 is 1/2 of the frequency of clk.
  • the pulse signal of 1/2 original frequency is called a frequency-divided signal
  • the frequency-divided signal is sequentially delayed after being adjusted by the first delay adjustment circuit and the second delay adjustment.
  • the output signal of the first delay adjustment circuit is marked as clk-dly-fix
  • the output signal of the second delay adjustment circuit is marked as clk-dly0.
  • the output signal of the first delay adjustment circuit is delayed relative to the output signal clk-div2 of the frequency divider for a period of time
  • the output signal clk-dly0 of the second delay adjustment circuit is delayed relative to the first delay
  • the output signal clk-dly-fix of the adjustment circuit is delayed for a period of time.
  • the delay duration between the output signal clk-dly-fix of the first delay adjustment circuit and the output signal clk-div2 of the frequency divider is marked as DLY-FIX
  • the output signal of the second delay adjustment circuit is marked as DLY-FIX.
  • the delay duration between clk-dly0 and the output signal clk-dly-fix of the first delay adjustment circuit is marked as DLY-TRIM.
  • the output signal of the second delay adjustment circuit is input to the first third delay adjustment circuit connected in series, and each third delay adjustment circuit delays its own input signal for a period of time. As shown in FIG. 10 , the output signals of each third delay adjustment circuit are sequentially marked as clk-dly1 , clk-dly2 , clk-dly3 , , clk-dlyM.
  • the delay duration of clk-dly1 relative to clk-dly0 is DLY-DUTY
  • the delay duration of clk-dly2 relative to clk-dly2 is DLY-DUTY
  • the delay duration of clk-dlyM relative to clk-dlyM-1 is DLY-DUTY.
  • FIG. 9 and FIG. 10 after the clock signal clk to be detected is input to the inverter, the output signal of the inverter is marked as clk-INV. As shown in Fig. 9, input clk-dly0, clk-dly1, clk-dly2, clk-dly3, ..., clk-dlyM in Fig.
  • the signals processed by the two-level registers are shown as clk-dff2-dly0, clk-dff2-dly1, clk-dff2-dly2, clk-dff2-dly3, ..., clk-dff2-dlyM in Figure 10, respectively .
  • the output signal clk-INV of the inverter and the output signal clk-div2 of the frequency divider are also input to the two-stage register B for synchronization processing, and the obtained signal is marked as clk-no- dly0, the signal clk-no-dly0 can also be called "inverse clock to collect the output signal of the divided-by-two clock", and then clk-no-dly0 and clk-dff2-dly0, clk-dff2-dly1, clk-dff2 -dly2, clk-dff2-dly3, ..., clk-dff2-dlyM input to the corresponding XOR gate.
  • the function of the XOR gate is: if the input levels of the two input terminals are different, the output is a high level; if the input levels of the two input terminals are the same, the output is a low level.
  • the output signals of each XOR gate are sequentially labeled as clk-data-dly0, clk-data-dly1, clk-data-dly2, clk-data-dly3, ..., clk-data-dlyM.
  • the two input signals of any XOR gate are either the same signal or an inverted signal, so each XOR gate outputs a high-level signal or a low-level signal .
  • the output signals of each XOR gate can be collected through flip-flops.
  • the flip-flop includes a control terminal (the control terminal is marked as CP in FIG. 9 ), the input terminal (the input terminal is marked as D in FIG. 9 ), and the output terminal (the output terminal is marked as Q in FIG. 9 ) , the output of each XOR gate is connected to the input of a flip-flop.
  • the control terminal of the flip-flop in FIG. 9 is used to input the output signal clk-INV of the inverter.
  • the output signal of the output terminal of the flip-flop is the same as the input signal of the input terminal of the flip-flop. That is, the flip-flop in FIG.
  • each XOR gate outputs a high-level signal or a low-level signal, so the data collected by the trigger is either 0 or 1.
  • the output signals of each XOR gate can represent the high-level and low-level distributions of the clock signal to be detected on the left and right sides of the falling edge of a clock cycle. Since a high level is usually represented as 1 and a low level is usually represented as 0, the aforementioned distribution of high and low levels on the left and right sides of the falling edge can also be referred to as "output codewords on the left and right sides of the falling edge".
  • a time interval can be set in advance based on the allowable range of the duty cycle, so as to collect the high levels on the left and right sides of the falling edge of a clock cycle of the clock signal to be detected within the time interval and Low level distribution. If the output signal of each XOR gate has both high level and low level in this time interval, it is determined that the duty cycle of the clock signal to be detected is within the allowable duty cycle range. If the output numbers of each XOR gate in this time interval are all high level or all low level (for example, all 0 or all 1), it is determined that the duty cycle of the clock signal to be detected is not on duty than within the allowable range.
  • each third delay adjustment circuit can indicate the above time interval, so each Three delay adjustment circuit delay time.
  • each third delay adjustment circuit may include k delay circuits, k is a positive integer greater than 1, and the structures and connection relationships of the delay circuits included in the third delay adjustment circuit
  • the structure and connection relationship of the delay circuit in the reference clock generating circuit shown in FIG. 2 may be the same.
  • any third delay adjustment circuit in the M third delay adjustment circuits includes k cascaded delay circuits, and each of the k cascaded delay circuits.
  • Each delay circuit includes a control terminal, and the control terminal is used for inputting a control signal to control the corresponding delay circuit to be turned on or off.
  • the first stage delay circuit in the k cascaded delay circuits includes a first input end and a first output end. The first input end of the first stage delay circuit is connected with the input end of the third delay adjustment circuit. The first output end of the first stage delay circuit is connected with the output end of the third delay adjustment circuit.
  • any one of the k delay circuits includes a first NAND gate, a second NAND gate, a third NAND gate and an inverter, the first NAND gate, the second Any of the NAND gate and the third NAND gate includes a first input terminal, a second input terminal, and an output terminal.
  • the first input terminal of the delay circuit is connected to the first input terminals of the first NAND gate and the second NAND gate.
  • the second input terminal of the delay circuit is connected to the second input terminal of the third NAND gate.
  • the first output terminal of the delay circuit is connected to the output terminal of the third NAND gate.
  • the second output terminal of the delay circuit is connected to the output terminal of the first NAND gate.
  • the control terminal of the delay circuit is connected to the second input terminal of the first NAND gate and the input terminal of the inverter.
  • the output terminal of the inverter is connected to the second input terminal of the second NAND gate.
  • the output terminal of the second NAND gate is connected to the first input terminal of the third NAND gate.
  • any delay circuit among the k delay circuits in the third delay adjustment circuit includes a first NAND gate, a second NAND gate, a third NAND gate and an inverter, and the first NAND gate
  • Any one of the gate, the second NAND gate, and the third NAND gate includes a first input terminal, a second input terminal, and an output terminal
  • the inverter includes an input terminal and an output terminal.
  • the first input terminal of the first NAND gate in the first delay circuit connected in series is the input terminal of the corresponding third delay adjustment circuit. After the series connection, other delays except the first delay circuit
  • the first input end of the first NAND gate in the circuit is connected with the output end of the first NAND gate in the upper stage delay circuit connected in series.
  • the second input terminal of the first NAND gate and the input terminal of the inverter in any delay circuit are used to input control signals corresponding to any delay circuit.
  • the output terminal of the inverter in any delay circuit is connected to the second input terminal of the second NAND gate in the same delay circuit, and the first input terminal of the second NAND gate in any delay circuit is connected to the same
  • the input signal of the first input terminal of the first NAND gate in the delay circuit is the same
  • the output terminal of the second NAND gate in any delay circuit is connected to the first input terminal of the third NAND gate in the same delay circuit.
  • the second input terminal of the third NAND gate in the last delay circuit after the series connection is connected to the output terminal of the first NAND gate in the same delay circuit, and other delays except the last delay circuit after the series connection
  • the second input terminal of the third NAND gate in the circuit is connected with the output terminal of the third NAND gate in the next stage delay circuit.
  • the output end of the third NAND gate in the first delay circuit connected in series is the output end of the corresponding third delay adjustment circuit.
  • each delay circuit in the third delay adjustment circuit For the specific connection relationship of each delay circuit in the third delay adjustment circuit, reference may be made to FIG. 2 , which will not be described in detail here.
  • the third delay adjustment can be set based on the inherent delay duration and duty cycle allowable range of a single delay circuit in the trained reference clock generation circuit
  • the number of delay circuits connected in series in the circuit so as to realize setting the delay time of each third delay adjustment circuit. That is, any third delay adjustment circuit is preset with a plurality of delay circuits, and in application, the number of the delay circuits connected in series in the third delay adjustment circuit is set based on the allowable range of the duty cycle.
  • the time interval corresponding to the allowable duty cycle range is 0.1ns.
  • the delay unit that is connected in series among the k delay units included in any third delay adjustment circuit can be determined based on the allowable range of the duty cycle
  • the target circuit configuration information for the duty cycle detection circuit can be generated according to the number of delay units connected in series among the k delay units included in any third delay adjustment circuit, and the target circuit configuration information for the duty cycle detection circuit can be generated.
  • the target circuit configuration information of the duty cycle detection circuit is written into the chip.
  • the delay durations in the first delay adjustment circuit and the second delay adjustment circuit are obtained by training in advance.
  • a clock signal whose duty cycle is an ideal duty cycle is input to the duty cycle detection circuit.
  • the training purpose is achieved at this time.
  • the delay duration of the first delay circuit and the second delay adjustment circuit after the last adjustment is carried in the target circuit configuration information of the duty cycle detection circuit, so that the target circuit configuration information write to the chip.
  • the above target circuit configuration information for the duty cycle detection circuit may also be referred to as third target circuit configuration information.
  • the ratio between the number of flip-flops that output 0 and the number of flip-flops that output 1 in each of the above flip-flops is consistent with the ideal duty cycle, which means that the ratio between the number of flip-flops that output 0 and the number of flip-flops that output 1 in each flip-flop is between the number of flip-flops that output 0 and the number of flip-flops that output 1.
  • the ratio between the high-level width and the low-level width in the ideal duty cycle is the same.
  • the clock signal whose duty cycle meets the ideal duty cycle is input to the duty cycle detection circuit shown in FIG. 9, and then Adjust the delay time length of the first delay adjustment circuit and the second delay adjustment circuit. After each adjustment, determine the ratio between the number of flip-flops that output 0 and the number of flip-flops that output 1 in each flip-flop. Whether the ideal duty cycle is consistent, if so, the delay duration of the first delay adjustment circuit and the second delay adjustment circuit after this adjustment is determined as the target circuit configuration information of the duty cycle detection circuit. If they are inconsistent, continue to adjust the delay time lengths of the first delay adjustment circuit and the second delay adjustment circuit.
  • the ideal duty cycle of the current on-chip clock signal is usually 50%. Therefore, when training the duty cycle detection circuit, a standard clock signal with a duty cycle of 50% can be input to the duty cycle detection circuit, and then the delay time of the first delay adjustment circuit and the second delay adjustment circuit can be adjusted until
  • the number of flip-flops that output 0 is basically the same as the number of flip-flops that output 1, that is, nearly half of the flip-flops in each flip-flop output data as 0, and nearly half of the flip-flops output data as 1. .
  • the first delay adjustment circuit (DLY-FIX) in the duty cycle detection circuit shown in FIG. 9 is used to perform coarse adjustment on the delay of the input signal
  • the second delay adjustment circuit (DLE- TRIM-DUTY) is used to fine-tune the delay of the input signal.
  • only one delay adjustment circuit may be set in the duty ratio detection circuit shown in FIG. 9 , which is not limited in this embodiment of the present application.
  • the configuration signal in FIG. 9 is used to configure the delay size of each delay adjustment circuit. That is, after the delay duration of each delay adjustment circuit is determined, the delay duration of each delay adjustment circuit is set by the configuration signal.
  • the reference clock generation circuit, the glitch detection circuit, and the duty cycle detection circuit can be configured on the chip in advance before the chip leaves the factory, so as to facilitate the realization of the same chip based on these three circuits after the factory leaves the factory.
  • the frequency of the clock signal, the glitch signal and the detection of the duty cycle can be configured on the chip in advance before the chip leaves the factory, so as to facilitate the realization of the same chip based on these three circuits after the factory leaves the factory.
  • an enable switch can be configured for each circuit, so that after the chip leaves the factory, according to the measurement requirements And the enable switch enables a certain circuit and detects the clock signal on the same chip based on the circuit.
  • only one or more of the above three circuits may be configured based on actual measurement requirements. For example, if only the frequency of the clock signal of the chip needs to be detected in an actual application scenario, the above reference clock generation circuit may be configured on the chip before the chip leaves the factory. Or, if only the frequency and glitch signal of the clock signal of the chip need to be detected in the actual application scenario, the above-mentioned reference clock generation circuit and glitch detection circuit can be configured on the chip before the chip leaves the factory. No further examples are given here.
  • the delay circuit included in the glitch detection circuit and the delay circuit included in the reference clock generation circuit are of the same structure, since the delay circuit used in the glitch detection circuit for detecting the glitch signal needs to be It is determined based on the inherent delay duration and glitch detection range of the delay circuit in the reference clock generation circuit after training. In this scenario, even if only the glitch signal in the clock signal of the chip needs to be detected, the reference clock generation circuit and glitch detection are also used.
  • the circuit is also configured on the chip.
  • the delay circuit included in the third delay adjustment circuit in the duty cycle detection circuit and the delay circuit included in the reference clock generation circuit have the same structure
  • the delay circuit in series in the third delay adjustment circuit has the same structure
  • the number of time circuits needs to be determined based on the inherent delay time and duty cycle allowable range of the delay circuit in the reference clock generation circuit after training. In this scenario, even if only the duty cycle of the chip's clock signal needs to be detected, it will be The reference clock generation circuit and the duty cycle detection circuit are configured on the chip at the same time.
  • the above-mentioned training process for the reference clock generation circuit and the training process for the duty cycle detection circuit can be completed before the chip leaves the factory.
  • the target circuit configuration information of the reference clock generation circuit after training and the target circuit configuration information of the duty cycle detection circuit after training are written into the chip. In order to facilitate the subsequent detection of the clock signal to be detected based on the trained target circuit configuration information.
  • the above-mentioned training process for the reference clock generation circuit and the training process for the duty cycle detection circuit can also be completed based on specific requirements after the chip is shipped from the factory.
  • the reference clock generation circuit and the duty cycle detection circuit can be trained based on ideal operating parameters such as ideal operating frequency and ideal duty cycle for specific requirements.
  • the training process can also refer to the above content, and will not be described in detail here.
  • the ideal operating parameters refer to the expected operating parameters of the clock when configuring the clock for the chip.
  • Ideal operating parameters may include ideal operating frequency and/or ideal duty cycle.
  • the ideal operating frequency refers to the frequency of the desired clock signal
  • the ideal duty cycle refers to the desired duty cycle of the clock signal.
  • the ideal operating frequency and the ideal duty cycle can be obtained through the configuration data of the chip when it leaves the factory. For example, the rated operating frequency of the clock configured when the chip is shipped from the factory can be used as the ideal operating frequency, and the rated signal duty cycle of the clock configured when the chip is shipped from the factory can be used as the ideal duty cycle.
  • the rated operating frequency of the clock configured when the chip leaves the factory is usually 24MHz, and the rated signal duty cycle is 50%.
  • the aforementioned ideal operating parameters may include an ideal operating frequency of 24 MHz and/or an ideal duty cycle of 50%.
  • FIG. 11 is a flowchart of a clock detection method provided by an embodiment of the present application. The method is performed by the processor on the chip shown in FIG. 1 . Wherein, the chip further includes a clock for generating a clock signal, and the chip further includes at least one of a reference clock generation circuit, a glitch detection circuit or a duty cycle detection circuit. As shown in Figure 11, the method includes the following steps.
  • Step 1101 The processor detects the clock signal based on at least one of the following.
  • At least one of steps 1101 includes: detecting the frequency of the clock signal based on the reference clock signal generated by the reference clock generating circuit; or, detecting whether the clock signal contains a glitch based on the glitch detection circuit; or, based on the duty cycle
  • the duty cycle detection circuit detects the duty cycle of the clock signal.
  • the frequency of the clock signal on the chip can be detected based on the reference clock generation circuit, thereby avoiding the need to additionally draw a standard reference clock through the analog circuit when detecting the clock signal on the chip. Therefore, chip resources are saved.
  • FIG. 12 is a flowchart of a clock detection method provided by an embodiment of the present application. The method is used to detect the frequency of the clock signal of the chip. For the convenience of subsequent description, the clock signal of the chip to be detected is simply referred to as the clock signal to be detected.
  • the method includes the following steps.
  • Step 1201 The processor determines the second timing duration based on the ideal operating frequency, and controls the control signals corresponding to each delay circuit included in the reference clock generation circuit according to the first target circuit configuration information, so that the reference clock generation circuit outputs the reference clock signal, wherein , the first target circuit configuration information indicates that the control signal corresponding to each delay circuit in the reference clock is a high level or a low level.
  • the reference clock Since the first target circuit configuration information is the circuit configuration information after training the reference clock generation circuit according to the ideal operating frequency, when the processor controls the control signals corresponding to each delay circuit according to the first target circuit configuration information, the reference clock generates The circuit can output a reference clock signal, and the frequency of the reference clock signal is the above-mentioned ideal operating frequency.
  • the above-mentioned second timing duration is a timing duration designed to count the clock signal to be detected.
  • the second timing duration can be configured based on specific requirements after the chip leaves the factory, or can be configured before the chip leaves the factory. It should be noted that the "first” and “second” in the second timing duration and the aforementioned first timing duration have no specific meaning, and the “first” and “second” here are only used to distinguish two different Timing time.
  • Step 1202 The processor counts the number of pulses in the reference clock signal within the second timing period and the number of pulses in the clock signal to be detected within the second timing period to obtain the first count result and the second count result, respectively.
  • the frequency of the standard reference clock is the above-mentioned ideal operating frequency
  • the frequency of the clock signal to be detected can be detected by taking the standard reference clock as a theoretical reference object.
  • a pulse signal with a pulse width equal to the second timing duration can be designed based on the second timing duration, and then the counter is controlled by the pulse signal.
  • the control counter stops counting. Thereby, the counter counts within the second timing period.
  • Step 1203 If the difference between the first count result and the second count result exceeds the second reference difference, output a first frequency prompt signal indicating that the frequency of the clock signal to be detected is unstable.
  • a second frequency prompt signal is output, and the second frequency prompt signal indicates that the frequency of the clock signal to be detected is stable.
  • the above-mentioned second reference difference is a preset threshold, and the threshold may be 5, 10, or the like.
  • first and second in the second reference difference and the aforementioned first reference difference have no specific meaning, and the “first” and “second” here are only used to distinguish two a different reference difference.
  • the frequency of detecting the clock signal to be detected based on the reference clock signal generated by the reference clock generation circuit may specifically be: controlling the reference clock generation circuit to output a reference clock signal whose frequency is an ideal working frequency, and the ideal working frequency The frequency is the ideal operating frequency of the clock signal. If the actual operating frequency of the clock signal to be detected is different from the frequency of the reference clock signal, it is determined that the frequency of the clock signal to be detected is unstable. Correspondingly, if the actual operating frequency of the clock signal to be detected is the same as the frequency of the reference clock signal, it is determined that the frequency of the clock signal to be detected is stable.
  • Whether the actual operating frequency of the above-mentioned clock signal to be detected and the frequency of the reference clock signal are the same can be specifically judged by the two counting results in step 1203. If the difference between the two counting results exceeds the second reference difference, then It indicates that the actual operating frequency of the clock signal to be detected is different from the frequency of the reference clock signal. If the difference between the two counting results does not exceed the second reference difference, it indicates that the actual operating frequency of the clock signal to be detected is the same as the frequency of the reference clock signal.
  • the chip system can also send out an alarm signal to prompt that the frequency of the current clock signal to be detected is unstable.
  • the above-mentioned first frequency prompt signal may be 1, and the second frequency prompt signal may be 0.
  • the processor when the two counting results are not significantly different, indicating that the second counting result is within the theoretical value range, the processor outputs the second frequency prompt signal "0", indicating that the frequency of the clock signal to be detected at this time is within Within a reasonable range, the chip system does not alarm.
  • the processor When the difference between the two count results is large, it indicates that the second count result exceeds the theoretical value range, the processor outputs the first frequency prompt signal "1", and the chip system sends out an alarm signal.
  • FIG. 13 is a schematic diagram of a complete process of training and detecting a clock frequency provided by an embodiment of the present application.
  • the processor on the chip first trains the reference clock generation circuit.
  • the processor takes the pulse signal that meets the ideal operating frequency as the reference object, and trains the reference clock generation circuit.
  • a counter is used to count the difference between the number of pulses in the output signal of the reference clock generation circuit and the number of pulses in the aforementioned pulse signal to determine whether the training purpose is achieved.
  • the purpose of training is to make the reference clock generation circuit also A reference clock signal satisfying the ideal operating frequency is generated, and the configuration information of the control signals corresponding to each delay circuit in the reference clock generation circuit at this time is written into the chip as the first target circuit configuration information.
  • the subsequent processor can detect the frequency of the clock signal to be detected based on the first target circuit configuration information. Specifically, during detection, after the processor configures the control signals of each delay circuit in the reference clock generation circuit according to the first target circuit configuration information, the processor counts the clock signals to be detected by taking the output signal of the reference clock generation circuit as a reference object, By comparing the two count results, it can be judged whether the frequency of the clock signal to be detected is stable, and then a frequency prompt signal is output based on the judgement result. For the specific implementation of the process shown in FIG. 13 , reference may be made to the foregoing embodiments, which will not be repeated here.
  • the processor in FIG. 13 may be configured with a state machine control circuit, and in a specific application, the training and detection processes in FIG. 13 are completed based on the state machine control circuit.
  • the reference clock generation circuit can be expanded on the chip in advance, and then the reference clock generation circuit is trained (trim) based on the ideal operating frequency to obtain the first target circuit of the reference clock generation circuit configuration information.
  • the clock signal on the same chip can be detected based on the configuration information of the first target circuit, thereby avoiding the need to additionally lead out a standard reference clock through the analog circuit when detecting the clock signal on the chip, thus saving chip resources.
  • FIG. 14 is a flowchart of another clock detection method provided by an embodiment of the present application.
  • the method is used to detect the glitch signal in the clock signal on the chip.
  • the clock signal of the chip to be detected is simply referred to as the clock signal to be detected.
  • the method includes the following steps.
  • Step 1401 The processor controls the clock signal to be detected to be input to the glitch detection circuit.
  • the above-mentioned burr detection circuit may specifically be the burr detection circuit shown in FIG. 6 .
  • inputting the to-be-detected clock signal into the glitch detection circuit in step 1401 specifically refers to: inputting the to-be-detected clock signal to the input end of the first delay circuit and each AND gate of the N delay circuits connected in series of the second input.
  • the clock signal is input to the first flip-flop to obtain the first output signal
  • the first flip-flop is one of N+1 flip-flops.
  • the first flip-flop is a flip-flop that is not connected to the AND gate.
  • the clock signal is input to the X+1th flip-flop after passing through the X cascaded delay circuits to obtain the X+1th output signal.
  • X takes each positive integer from 1 to N in sequence
  • the X+1th flip-flop is the flip-flop other than the first flip-flop among the N+1 flip-flops.
  • the X+1 th flip-flop is a flip-flop connected to the N AND gates respectively.
  • Step 1402 The processor obtains the output signal of the target flip-flop among the N+1 flip-flops in the glitch detection circuit and the N flip-flops connected to the AND gate, and the output of the first flip-flop among the N+1 flip-flops Signal.
  • Step 1403 If the output signal of the target flip-flop and the output signal of the first flip-flop are different in the same clock cycle, it is determined that there is a glitch signal in the clock signal to be detected.
  • the output signal of the target flip-flop and the output signal of the first flip-flop are the same in the same clock cycle, it is determined that there is no glitch in the clock signal to be detected.
  • FIG. 15 is a flowchart of a clock detection method provided by an embodiment of the present application. The method is used to detect the duty cycle of the clock signal on the chip. Likewise, for the convenience of subsequent description, the clock signal of the chip to be detected is simply referred to as the clock signal to be detected. Based on the chip shown in FIG. 1 , it can be known that the method provided by the embodiment of the present application is applied to the processor of the chip. Therefore, as shown in Figure 15, the method includes the following steps.
  • Step 1501 The processor controls the clock signal to be detected to be input to the duty cycle detection circuit.
  • inputting the to-be-detected clock signal to the duty cycle detection circuit specifically refers to inputting the to-be-detected clock signal to the frequency divider and the input end of the inverter shown in FIG. 9 . middle.
  • Step 1502 The processor acquires the output signals of the output terminals of the M+1 flip-flops in the duty cycle detection circuit.
  • each trigger is either 0 or 1.
  • the output signal of each XOR gate is either low or high.
  • Step 1503 If the output signals of the output terminals of the M+1 flip-flops have both a low level and a high level, output a first duty cycle prompt signal, which is used to indicate the clock signal to be detected The duty cycle is within the allowable duty cycle range.
  • Step 1504 If the output signals of the output terminals of the M+1 flip-flops are all low levels, output a second duty cycle prompt signal, which indicates the duty cycle of the output signal of the clock to be detected is not within the duty cycle range, and the proportion of the signal at a high level in the to-be-detected clock signal exceeds the duty cycle allowable range.
  • Step 1505 If the output signals of the output terminals of the M+1 flip-flops are all high levels, a third duty cycle prompt signal is output, and the third duty cycle prompt signal indicates that the duty cycle of the clock signal to be detected is not in the duty cycle. Within the duty cycle range, and the proportion of the low level signal in the clock output signal to be detected exceeds the duty cycle allowable range.
  • step 1504 and step 1505 the processor may only output the same duty cycle prompt signal, in this case, the duty cycle prompt signal is only used to indicate that the duty cycle of the clock signal to be detected is not within the allowable duty cycle range within, and no other indicative meaning.
  • FIG. 16 is a detection result of a duty cycle detection circuit provided in an embodiment of the present application in a case where a low level ratio is too large, and a detection result of a duty cycle detection circuit in a case where a high level ratio is too large. If the proportion of the low level in the detected clock signal is too large, it indicates that the duration of the low level in one cycle is too long. As shown in FIG. 16 , the output signals of each third delay adjustment circuit collected at the first rising edge of the output signal clk-INV of the inverter may all be low level (marked as the collected level average in FIG.
  • the output signals of each third delay adjustment circuit collected at the first rising edge of the output signal clk-INV of the inverter may all be high level (the level marked as collected in FIG. 16 is 1).
  • the output signal processed synchronously by each two-level register A may be the same signal as the output signal processed by the two-level register B synchronously, so that the output signal of each XOR gate is all low level.
  • the collected signal may be all 0s.
  • the processor will output a third duty cycle prompt signal, and the third duty cycle prompt signal indicates that the proportion of the high level in the to-be-detected clock signal is relatively large.

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Abstract

一种芯片及时钟检测方法，涉及计算机技术领域。在芯片上配置参考时钟产生电路、毛刺检测电路和占空比检测电路中的至少一项。以便于后续基于参考时钟产生电路对芯片上的时钟信号的频率进行检测，从而避免了在对芯片上的时钟信号检测时需要额外通过模拟电路引出一个标准参考时钟，因此节省了芯片资源。此外，通过该芯片，还可以实现对同一芯片上的时钟信号包含的毛刺以及时钟信号的占空比的检测，提高了检测时钟信号的灵活性。

Description

芯片及时钟检测方法 技术领域
本申请涉及计算机技术领域，特别涉及一种芯片及时钟检测方法。
背景技术
由于芯片是在时钟输出的脉冲信号的控制下按照一定频率工作的，因此，芯片中的时钟的稳定性在一定程度上影响芯片的系统稳定性。为了保证芯片的系统稳定性，通常需要对芯片中的时钟进行检测，以确定芯片中的时钟是否处于稳定工作状态。
相关技术中，为了测试芯片中的时钟，在芯片上配置一个参考时钟，该参考时钟的频率与芯片中的时钟的理论工作频率相同。针对参考时钟配置一个参考时钟计数器，针对芯片中的时钟配置一个被检测时钟计数器。基于两个计数器分别统计两个时钟在相同的计时时长内输出的脉冲信号中的脉冲数量，比较参考时钟计数器的计数结果和被检测时钟计数器的计数结果，如果两个计数结果差距较大，则表明芯片中的时钟的实际工作频率不稳定，也即表明时钟没有处于稳定工作的状态。
上述检测时钟的过程需要在芯片上额外配置一个参考时钟，该参考时钟通常通过模拟方式产生，导致检测过程中芯片的开销比较大，浪费了芯片资源。
发明内容
本申请实施例提供了一种芯片及时钟检测方法，可以降低检测芯片上的时钟时所需的开销，从而节省芯片资源。
第一方面，本申请提供一种芯片，该芯片包括处理器和时钟，时钟用于生成时钟信号，该芯片还包括参考时钟产生电路、毛刺检测电路或占空比检测电路的至少一项。其中，处理器用于基于如下至少一项对时钟信号进行检测：基于参考时钟产生电路生成的参考时钟信号检测时钟信号的频率；或，基于毛刺检测电路检测时钟信号是否包含毛刺；或，基于占空比检测电路检测时钟信号的占空比。
基于本申请实施例提供的芯片，在需要对芯片上的时钟进行检测时，便可基于参考时钟产生电路对芯片上的时钟信号的频率进行检测，从而避免了在对芯片上的时钟信号检测时需要额外通过模拟电路引出一个标准参考时钟，因此节省了芯片资源。此外，通过本申请实施例提供的芯片，还可以实现对同一芯片上的时钟信号包含的毛刺以及时钟信号的占空比的检测，提高了检测时钟信号的灵活性。
基于第一方面提供的芯片，在一种可能的实现方式中，参考时钟产生电路包括P个级联的延时电路，P个级联的延时电路中每个延时电路包括一个控制端，控制端用于输入控制信号以控制对应的延时电路导通或断开，P为大于1的正整数。其中，P个级联的延时电路中第一级延时电路包括第一输入端和第一输出端。第一级延时电路的第一输入端用于输入初始时钟信号，初始时钟信号通过至少一级导通的延时电路后从第一级延时电路的第一输出端输出。 第一级延时电路的第一输出端和参考时钟产生电路的输出端连接，参考时钟产生电路的输出端用于输出参考时钟信号。
在本申请实施例中，通过控制各个延时电路的控制信号来控制串联导通的延时电路的个数，能够实现参考时钟产生电路输出的参考时钟信号的频率不同。因此，可以预先基于芯片上的时钟的理想工作频率对参考时钟产生电路进行训练，直至参考时钟产生电路输出的参考时钟信号满足前述理想工作频率。从而使得本申请实施例提供的参考时钟电路能够适应用于不同芯片上的时钟，提高了本申请实施例提供的芯片的应用灵活性。
基于第一方面提供的芯片，在一种可能的实现方式中，P个级联的延时电路中每个延时电路均包括第一输入端、第二输入端、第一输出端和第二输出端。其中，第一级延时电路的第二输出端连接至第二级延时电路的第一输入端，第一级延时电路的第二输入端连接至第二级延时电路的第一输出端。P个级联的延时电路中最后一级延时电路的第一输入端连接至最后一级延时电路的上一级延时电路的第二输出端；最后一级延时电路的第二输出端连接至最后一级延时电路的第二输入端；最后一级延时电路的第一输出端连接至最后一级延时电路的上一级延时电路的第二输入端。
基于第一方面提供的芯片，在一种可能的实现方式中，P个级联的延时电路中的中间延时电路的第一输入端连接至中间延时电路的上一级延时电路的第二输出端。其中，中间延时电路的第一输出端连接至中间延时电路的上一级延时电路的第二输入端。中间延时电路的第二输出端连接至中间延时电路的下一级延时电路的第一输入端。中间延时电路的第二输入端连接至中间延时电路的下一级延时电路的第一输出端。中间延时电路为P个级联的延时电路中除第一级延时电路和最后一级延时电路之外的任一个延时电路。
上述分别用于说明P个级联的延时电路中第一级延时电路的输入输出情况、最后一级延时电路的输入输出情况、以及P个级联的延时电路中的中间延时电路的输入输出情况。通过上述连接关系，便可实现控制各个延时电路的控制信号来控制串联导通的延时电路的个数，能够实现参考时钟产生电路输出的参考时钟信号的频率不同。从而使得本申请实施例提供的参考时钟电路能够适应用于不同芯片上的时钟，提高了本申请实施例提供的芯片的应用灵活性。
基于第一方面提供的芯片，在一种可能的实现方式中，该芯片上存储有第一目标电路配置信息，第一目标电路配置信息指示参考时钟产生电路中各个延时电路分别对应的控制信号的配置情况。其中，在参考时钟产生电路中各个延时电路对应的控制信号按照第一目标电路配置信息设置后，参考时钟产生电路输出的参考时钟信号的频率为理想工作频率，理想工作频率为时钟信号的理想工作频率。
在本申请实施例中，可以在芯片出厂前完成对参考时钟产生电路的训练过程。这种场景下，将训练后得到的第一目标电路配置信息写入芯片。以便于后续快速基于第一目标电路配置信息对待检测时钟信号的频率进行检测。
基于第一方面提供的芯片，在一种可能的实现方式中，第一目标电路配置信息指示各个延时电路分别对应控制信号为高电平或低电平。其中，P个级联的延时电路中任一延时电路对应的控制信号为高电平时，任一延时电路通往下一级延时电路的通路导通，任一延时电路对应的控制信号为低电平时，任一延时电路通往下一级延时电路的通路断开。
在本申请实施例中，通过高低电平的控制信号便可实现参考时钟产生电路中各个延时电 路的导通和关闭，提高了控制参考时钟产生电路的灵活性。同时在第一目标电路配置信息中仅仅需要指明各个延时电路分别对应控制信号为高电平或低电平即可，降低了第一目标电路配置信息的复杂度，这样便可减少在芯片上写入第一目标电路配置信息所需的资源。
基于第一方面提供的芯片，在一种可能的实现方式中，参考时钟产生电路还包括门控电路，门控电路包括控制端。其中，第一级延时电路的第一输出端通过门控电路和参考时钟产生电路的输出端连接。门控电路的控制端用于输入门控使能信号，门控使能信号用于扣除第一级延时电路的第一输出端输出的时钟信号中的一个或多个脉冲，以得到参考时钟信号。
在本申请实施例中，可能存在无论如何调整各个延时电路的控制信号，参考时钟产生电路产生的时钟信号的频率与理想工作频率上均有一定误差的情况。这种场景下，可以在参考时钟产生电路输出的脉冲信号的频率和理想工作频率在一定误差之内时，通过上述门控电路来微调参考时钟产生电路输出的时钟信号的频率，以使参考时钟产生电路输出的时钟信号的频率和理想工作频率尽量一致。从而提高了后续对时钟信号的频率进行检测的准确性。
基于第一方面提供的芯片，在一种可能的实现方式中，参考时钟产生电路还包括与非门，与非门包括第一输入端、第二输入端以及输出端。其中，与非门的第一输入端用于输入使能信号，使能信号指示开启或关闭参考时钟产生电路。与非门的第二输入端和第一级延时电路的第一输出端连接。与非门的输出端和第一级延时电路的第一输入端连接。
在本申请实施例中，还可以通过与非门上输入的使能信号来控制参考时钟产生电路的开启和关闭，提高了参考时钟产生电路的应用灵活性。
基于第一方面提供的芯片，在一种可能的实现方式中，P个延时电路中任一延时电路包括第一与非门、第二与非门、第三与非门以及反相器，第一与非门、第二与非门、第三与非门中任一者包括第一输入端、第二输入端和输出端。其中，延时电路的第一输入端连接至第一与非门和第二与非门的第一输入端。延时电路的第二输入端连接至第三与非门的第二输入端。延时电路的第一输出端连接至第三与非门的输出端。延时电路的第二输出端连接至第一与非门的输出端。延时电路的控制端连接至第一与非门的第二输入端和反相器的输入端。反相器的输出端连接至第二与非门的第二输入端。第二与非门的输出端连接至第三与非门的第一输入端。
上述是本申请实施例提供的一种参考时钟产生电路中的延时电路的具体结构，通过上述几个简单的逻辑门的组合，便可实现本申请实施例提供的参考时钟产生电路中的延时电路的功能。降低了本申请实施例提供的参考时钟电路的复杂度，从而提高了本申请实施例提供的芯片的生产效率。
基于第一方面提供的芯片，在一种可能的实现方式中，毛刺检测电路包括N个级联的延时电路，N个与门，N+1个触发器，N个与门中每个与门包括第一输入端、第二输入端以及输出端，N+1个触发器中每个触发器包括输入端、输出端以及控制端，N为大于1的正整数。其中，N个级联的延时电路中第一级延时电路的输入端以及N个与门中每个与门的第二输入端用于输入时钟信号。N个级联的延时电路中除最后一级延时电路外其他每个延时电路的输出端连接至下一级延时电路的输入端。N个延时电路中每个延时电路的输出端分别与一个与门的第一输入端连接。N+1个触发器中第一触发器的控制端用于输入时钟信号，N+1个触发器中除第一触发器之外的N个触发器的控制端连接至N个与门的输出端，其中，一个与门对应一个触发器。N+1个触发器中每个触发器的输出端通过反相器连接至同一触发器的输入端。 N+1个触发器的输出端的输出信号用于检测时钟信号中是否包含毛刺。
通过上述全数字的毛刺检测电路，便可检测时钟信号中是否包含毛刺，从而使得本申请实施例提供的芯片能够应用在不同的测试场景中。提高了本申请实施例提供的芯片的应用灵活性。
基于第一方面提供的芯片，在一种可能的实现方式中，该芯片上存储有第二目标电路配置信息。其中，第二目标电路配置信息指示目标触发器为N个触发器中的哪一个。目标触发器的输出信号和第一触发器的输出信号用于检测时钟信号中是否包含毛刺。
在本申请实施例中，可以在芯片出厂前将上述第二目标电路配置信息写入芯片。以便于后续快速基于第二目标电路配置信息检测时钟信号中是否包含毛刺。
基于第一方面提供的芯片，在一种可能的实现方式中，N个延时电路为结构相同的延时电路，目标触发器是基于毛刺检测范围和N个延时电路中单个延时电路的延时时长确定的，毛刺检测范围指示时钟信号包含的毛刺的脉冲宽度。
在本申请实施例中，通过毛刺检测范围便可获知具体通过哪个触发器来检测毛刺。由于毛刺检测电路中包括多个触发器，如此本申请实施例提供的毛刺检测电路便可应用在不同的毛刺检测范围中，提高了本申请实施提供的芯片的应用灵活性。
基于第一方面提供的芯片，在一种可能的实现方式中，N个延时电路中任一延时电路包括第一与非门、第二与非门、第三与非门以及反相器，第一与非门、第二与非门、第三与非门中任一者包括第一输入端、第二输入端和输出端。其中，延时电路的输入端连接至第一与非门和第二与非门的第一输入端。延时电路的输出端连接至下一级延时电路的输入端。延时电路的控制端连接至第一与非门的第二输入端和反相器的输入端。反相器的输出端连接至第二与非门的第二输入端。第二与非门的输出端连接至第三与非门的第一输入端。第一与非门的输出端连接至第三与非门的第二输入端。
上述是本申请实施例提供的一种毛刺检测电路中的延时电路的具体结构，通过上述几个简单的逻辑门的组合，便可实现本申请实施例提供的毛刺检测电路中延时电路的功能。降低了本申请实施例提供的毛刺检测电路的复杂度，从而提高了本申请实施例提供的芯片的生产效率。
基于第一方面提供的芯片，在一种可能的实现方式中，占空比检测电路包括第一延时调整电路、第二延时调整电路以及M个级联的第三延时调整电路、分频器、第一反相器、第二反相器、第一两级寄存器以及M+1个第二两级寄存器、M+1个异或门以及M+1个触发器，M为大于1的正整数。其中，第一两级寄存器以及M+1个第二两级寄存器中任一者包括第一输入端、第二输入端和输出端，M+1个异或门中每个异或门包括第一输入端、第二输入端和输出端，M+1个触发器中每个触发器包括输入端、输出端以及控制端，分频器包括输入端、输出端和控制端。分频器的控制端用于输入时钟信号，分频器的输入端和分频器的输出端之间通过第二反相器连接，分频器的输出端和第一延时调整电路的输入端连接、第一延时调整电路的输出端和第二延时调整电路的输入端连接，第二延时调整电路的输出端和级联的M个第三延时调整电路中第一级第三延时调整电路的输入端连接，级联的M个第三延时调整电路中除最后一级第三延时调整电路外其他每个第三延时调整电路的输出端和下一级第三延时调整电路的输入端连接。第二延时调整电路的输出端以及级联的M个第三延时调整电路的每个第三延时调整电路的输出端一一对应连接至M+1个第二两级寄存器的第一输入端。M+1个 第二两级寄存器的第二输入端均与第一反相器的输出端连接，第一反相器的输入端用于输入时钟信号，M+1个第二两级寄存器的输出端与M+1个异或门的第一输入端一一对应连接。M+1个异或门的输出端和M+1个触发器的输入端一一对应连接。第一反相器的输出端还与第一两级寄存器的第一输入端连接，分频器的输出端与第一两级寄存器的第二输入端连接，第一两级寄存器的输出端与M+1个异或门的第二输入端连接。M+1个触发器的输出端的输出信号用于检测时钟信号的占空比。
通过上述全数字的占空比检测电路，便可检测时钟信号的占空比，从而使得本申请实施例提供的芯片能够应用在不同的测试场景中。提高了本申请实施例提供的芯片的应用灵活性。
基于第一方面提供的芯片，在一种可能的实现方式中，M个第三延时调整电路中任一第三延时调整电路包括k个级联的延时电路，k个级联的延时电路中每个延时电路包括一个控制端，控制端用于输入控制信号以控制对应的延时电路导通或断开，k为大于1的正整数。其中，k个级联的延时电路中第一级延时电路包括第一输入端和第一输出端。第一级延时电路的第一输入端和第三延时调整电路的输入端连接。第一级延时电路的第一输出端和第三延时调整电路的输出端连接。
通过k个级联的延时电路便可实现占空比检测电路中的第三延时调整模块，并且能够基于各个延时电路对应的控制信号，灵活地根据不同需求调整第三延时调整模块的延时时长。不仅降低了芯片上的占空比检测电路的复杂度，还提高了芯片的应用灵活性。
基于第一方面提供的芯片，在一种可能的实现方式中，k个级联的延时电路中每个延时电路均包括第一输入端、第二输入端、第一输出端和第二输出端。第一级延时电路的第二输出端连接至第二级延时电路的第一输入端，第一级延时电路的第二输入端连接至第二级延时电路的第一输出端。k个级联的延时电路中最后一级延时电路的第一输入端连接至最后一级延时电路的上一级延时电路的第二输出端；最后一级延时电路的第二输出端连接至最后一级延时电路的第二输入端；最后一级延时电路的第一输出端连接至最后一级延时电路的上一级延时电路的第二输入端。
基于第一方面提供的芯片，在一种可能的实现方式中，k个级联的延时电路中的中间延时电路的第一输入端连接至中间延时电路的上一级延时电路的第二输出端。中间延时电路的第一输出端连接至中间延时电路的上一级延时电路的第二输入端。中间延时电路的第二输出端连接至中间延时电路的下一级延时电路的第一输入端。中间延时电路的第二输入端连接至中间延时电路的下一级延时电路的第一输出端。中间延时电路为k个级联的延时电路中除第一级延时电路和最后一级延时电路之外的任一个延时电路。
基于第一方面提供的芯片，在一种可能的实现方式中，k个延时电路中任一延时电路包括第一与非门、第二与非门、第三与非门以及反相器，第一与非门、第二与非门、第三与非门中任一者包括第一输入端、第二输入端和输出端。延时电路的第一输入端连接至第一与非门和第二与非门的第一输入端。延时电路的第二输入端连接至第三与非门的第二输入端。延时电路的第一输出端连接至第三与非门的输出端。延时电路的第二输出端连接至第一与非门的输出端。延时电路的控制端连接至第一与非门的第二输入端和反相器的输入端。反相器的输出端连接至第二与非门的第二输入端。第二与非门的输出端连接至第三与非门的第一输入端。
上述k个延时电路之间的连接方式以及延时电路内部的结构均和前述参考时钟产生电路 中的相关内容一致，相应技术效果在此不再赘述。
基于第一方面提供的芯片，在一种可能的实现方式中，该芯片上存储有第三目标电路配置信息，其中，第三目标电路配置信息指示k个延时电路中串联导通的延时电路的数量、以及第一延时调整电路和第二延时调整电路的延时时长。其中，在第一延时调整电路、第二延时调整电路以及第三延时调整电路按照第三目标电路配置信息设置后，如果向占空比检测电路输入占空比为50％的时钟信号，则M+1个触发器的输出端的输出信号中一半为高电平信号、一半为低电平信号。
在本申请实施例中，可以在芯片出厂前将上述第三目标电路配置信息写入芯片。以便于后续快速基于第三目标电路配置信息检测时钟信号的占空比。
基于第一方面提供的芯片，在一种可能的实现方式中，k个延时电路为结构相同的延时电路，k个延时电路中串联导通的延时电路的数量是基于占空比允许范围和k个延时电路中单个延时电路的延时时长确定的，占空比允许范围指示时钟信号的占空比的允许浮动范围。
在本申请实施例中，通过占空比允许范围便可设置k个延时电路中串联导通的延时电路。如此本申请实施例提供的占空比检测电路便可应用在不同的占空比允许范围中，提高了本申请实施提供的芯片的应用灵活性。
第二方面、提供了一种时钟检测方法。该方法用于对上述第一方面提供的芯片上的各个电路的工作过程进行解释说明，从而实现上述各个电路的检测功能。下述第二方面提供的时钟检测方法中各个实现方式的技术效果均可以参考第一方面提供的芯片的相关技术效果，在此不再赘述。
具体地，该方法应用于芯片上的处理器，该芯片还包括时钟，时钟用于生成时钟信号，该芯片还包括参考时钟产生电路、毛刺检测电路或占空比检测电路的至少一项。在该方法中，处理器基于如下至少一项对时钟信号进行检测：基于参考时钟产生电路生成的参考时钟信号检测时钟信号的频率；或，基于毛刺检测电路检测时钟信号是否包含毛刺；或基于占空比检测电路检测时钟信号的占空比。
基于第二方面提供的时钟检测方法，在一种可能的实现方式中，上述基于参考时钟产生电路生成的参考时钟信号检测时钟信号的频率的实现过程可以为：控制参考时钟产生电路输出频率为理想工作频率的参考时钟信号，理想工作频率为时钟信号的理想工作频率；如果时钟信号的实际工作频率和参考时钟信号的频率不同，则确定时钟信号的频率不稳定。
基于第二方面提供的时钟检测方法，在一种可能的实现方式中，如果时钟信号的实际工作频率和参考时钟信号的频率相同，则确定待检测时钟信号的频率稳定。
基于第二方面提供的时钟检测方法，在一种可能的实现方式中，参考时钟产生电路包括P个级联的延时电路，该芯片上存储有第一目标电路配置信息，第一目标电路配置信息指示参考时钟产生电路中各个延时电路分别对应控制信号的配置情况。这种场景下，控制参考时钟产生电路输出频率为理想工作频率的参考时钟信号的实现过程可以为：基于第一目标电路配置信息，控制参考时钟产生电路中各个延时电路对应的控制信号，以使参考时钟产生电路输出频率为理想工作频率的参考时钟信号。
基于第二方面提供的时钟检测方法，在一种可能的实现方式中，毛刺检测电路包括N个级联的延时电路和N+1个触发器。这种场景下，基于毛刺检测电路检测时钟信号是否包含毛 刺的实现过程可以为：将时钟信号输入第一触发器，得到第一输出信号；第一触发器为N+1个触发器中的任一个；将时钟信号通过X个级联的延时电路后输入第X+1触发器，得到第X+1输出信号；其中，X依次取1至N中的每个正整数；获取毛刺检测电路中目标触发器的输出信号以及第一输出信号，目标触发器为N+1个触发器中除第一触发器外的一个触发器；如果目标触发器的输出信号和第一输出信号在同一时钟周期内输出信号不同，则确定时钟信号中包含毛刺。
基于第二方面提供的时钟检测方法，在一种可能的实现方式中，如果目标触发器的输出信号和第一触发器的输出信号在同一时钟周期内输出信号相同，则确定时钟信号中不包含毛刺。
基于第二方面提供的时钟检测方法，在一种可能的实现方式中，该芯片上存储有第二目标电路配置信息，其中，第二目标电路配置信息指示目标触发器为N+1个触发器中哪一个。这种场景下，获取毛刺检测电路中目标触发器的输出信号的实现过程可以为：基于第二目标电路配置信息，获取毛刺检测电路中目标触发器的输出信号。
基于第二方面提供的时钟检测方法，在一种可能的实现方式中，占空比检测电路包括分频器、第一反相器和M+1个触发器。这种场景下，基于占空比检测电路检测时钟信号的占空比的实现过程可以为：将时钟信号输入至分频器和第一反相器的输入端；获取占空比检测电路中的M+1个触发器的输出端的输出信号；如果M+1个触发器的输出端的输出信号中包括高电平信号和低电平信号，则输出第一占空比提示信号，第一占空比提示信号用于指示时钟信号的占空比在允许占空比范围之内。
基于第二方面提供的时钟检测方法，在一种可能的实现方式中，如果M+1个触发器的输出端的输出信号全是高电平信号，则输出第二占空比提示信号，第二占空比提示信号指示时钟信号的占空比没有在允许占空比范围之内，且时钟信号中低电平信号的占比超过占空比允许范围。如果M+1个触发器的输出端的输出信号全是低电平信号，则输出第三占空比提示信号，第三占空比提示信号指示时钟信号的占空比没有在允许占空比范围之内，且时钟信号中高电平信号的占比超过占空比允许范围。
基于第二方面提供的时钟检测方法，在一种可能的实现方式中，该方法应用于前述提供的芯片中，该芯片上存储有第三目标电路配置信息，其中，第三目标电路配置信息指示任一第三延时调整电路包含的k个延时电路中串联导通的延时电路的数量、以及第一延时调整电路和第二延时调整电路的延时时长。这种场景下，前述将时钟信号输入至分频器和第一反相器的输入端之前，还可以先基于第三目标电路配置信息，配置占空比检测电路。
第三方面，提供了一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，当指令在计算机上运行时，使得计算机执行上述第二方面所述的时钟检测方法。
第四方面，提供了一种包含指令的计算机程序产品，当指令在计算机上运行时，使得计算机执行上述第一方面所述的时钟检测方法。
上述第三方面和第四方面所获得的技术效果与第二方面中对应的技术手段获得的技术效果近似，在这里不再赘述。
附图说明
图1是本申请实施例提供的一种芯片的结构示意图；
图2为本申请实施例提供的一种参考时钟产生电路的结构示意图；
图3为本申请实施例提供的另一种参考时钟产生电路的结构示意图；
图4为本申请实施例提供的另一种参考时钟产生电路的结构示意图；
图5是本申请实施例提供的一种训练参考时钟产生电路的流程示意图；
图6是本申请实施例提供的一种毛刺检测电路的结构示意图；
图7是本申请实施例提供的一种毛刺检测电路中脉冲时序示意图；
图8是本申请实施例提供的一种毛刺检测电路中各个延时电路的连接关系示意图；
图9是本申请实施例提供的一种占空比检测电路的结构示意图；
图10是本申请实施例提供的一种占空比检测电路中各个电路的输出信号的脉冲时序示意图；
图11是本申请实施例提供的一种时钟检测方法流程图；
图12是本申请实施例提供的另一种时钟检测方法流程图；
图13是本申请实施例提供的一种训练和检测时钟频率的完整流程示意图；
图14是本申请实施例提供的另一种时钟检测方法流程图；
图15是本申请实施例提供的另一种时钟检测方法流程图；
图16是本申请实施例提供的一种低电平占比过大情况下占空比检测电路的检测结果以及高电平占比过大情况下占空比检测电路的检测结果。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
应当理解的是，本文提及的“多个”是指两个或两个以上。在本申请的描述中，除非另有说明，“/”表示或的意思，例如，A/B可以表示A或B；本文中的“和/或”仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，为了便于清楚描述本申请实施例的技术方案，在本申请的实施例中，采用了“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分。本领域技术人员可以理解“第一”、“第二”等字样并不对数量和执行次序进行限定，并且“第一”、“第二”等字样也并不限定一定不同。
在对本申请实施例进行详细解释说明之前，先对本申请实施例的应用场景进行简单说明。
为了后续便于说明，在本申请实施例中，将芯片上的时钟的输出信号简称为芯片的时钟信号。
随着芯片技术的发展，对于芯片系统的稳定性要求越来越高。而芯片中的时钟信号又是芯片系统中必不可缺的信号，当芯片中的时钟受到攻击时，时钟信号的频率、占空比均可能发生变化，同时，时钟信号有可能引入毛刺信号，而这些情况都有可能导致芯片无法正常工作。在实际芯片应用时，为了提高芯片的安全等级，通常需要对芯片的时钟信号进行检测。
本申请实施例提供的时钟检测方法应用于上述对芯片的时钟信号进行检测的场景中。无 需通过引入外部的标准参考时钟就能对芯片上的时钟信号进行检测，从而避免芯片上的资源浪费。
下面先对芯片的结构进行解释说明。图1是本申请实施例提供的一种芯片的结构示意图。如图1所示，该芯片100包括处理器101、接口电路102、时钟103、参考时钟产生电路104、毛刺检测电路105以及占空比检测电路106。
接口电路102用于接收指令并传输至处理器101，处理器101用于执行指令。时钟103为一个能够输出一定频率的脉冲信号的电路。该时钟103用于向处理器101输入时钟信号，并通过该时钟信号控制处理器101的工作频率。
在本申请实施例中，处理器101还用于执行本申请实施例提供的时钟检测的方法从而完成对同一芯片上的时钟103进行检测。
需要说明的是，图1仅仅是本申请实施例涉及的芯片的一种可选的结构。本申请实施例并不限定芯片的具体结构。任意配置有时钟的芯片均在本申请实施例涉及的芯片的保护范围之内。
为了能够在不引入外部的标准参考时钟的情况下对芯片上的时钟进行检测，在本申请实施例中，预先对芯片上的数字电路进行了改进，以便于后续基于改进后的数字电路对芯片上的时钟信号进行检测。具体的改进包括以下几个方面。
(1)在芯片上配置参考时钟产生电路104。
参考时钟产生电路104用于输出检测芯片的时钟信号所需的参考时钟信号。在本申请实施例中，通过该参考时钟产生电路104模拟一个标准参考时钟。由于参考时钟产生电路是一种全数字电路，而数字电路以二进制作为基础，电源电压的小波动对稳定性基本没有影响，并且温度和工艺偏差对数字电路工作的可靠性影响也比模拟电路小得多，因此数字电路相对于模拟电路具有可靠性高、稳定性好的优势。进一步的，数字电路设计相对于模拟电路，更容易进行工艺移植，当换不同的工艺时，数字电路能够快速完成设计。基于上述数字电路的优势，本申请实施例提供的参考时钟产生电路具有可靠性高、稳定性好等特点。
全数字电路是指电路由多个逻辑门构成，通过多个逻辑门的连接方式来实现参考时钟产生电路的功能。
在一种可能的实现方式中，参考时钟产生电路包括P个级联的延时电路，每个延时电路用于对输入信号进行一定的延时处理，P为大于1的正整数。
其中，P个级联的延时电路中每个延时电路包括一个控制端，控制端用于输入控制信号以控制对应的延时电路导通或断开。P个级联的延时电路中每个延时电路均包括第一输入端、第二输入端、第一输出端和第二输出端。
其中，参考时钟产生电路输出的参考时钟信号和第一级延时电路之间的关系如下：
第一级延时电路的第一输入端用于输入初始时钟信号，初始时钟信号通过至少一级导通的延时电路后从第一级延时电路的第一输出端输出。第一级延时电路的第一输出端和参考时钟产生电路的输出端连接，参考时钟产生电路的输出端用于输出参考时钟信号。
P个级联的延时电路中第一级延时电路的输入输出情况以及最后一级延时电路的输入输出情况如下：
第一级延时电路的第二输出端连接至第二级延时电路的第一输入端，第一级延时电路的 第二输入端连接至第二级延时电路的第一输出端。P个级联的延时电路中最后一级延时电路的第一输入端连接至最后一级延时电路的上一级延时电路的第二输出端。最后一级延时电路的第二输出端连接至最后一级延时电路的第二输入端。最后一级延时电路的第一输出端连接至最后一级延时电路的上一级延时电路的第二输入端。
P个级联的延时电路中的中间延时电路的输入输出情况如下(中间延时电路为P个级联的延时电路中除第一级延时电路和最后一级延时电路之外的任一个延时电路)：
P个级联的延时电路中的中间延时电路的第一输入端连接至中间延时电路的上一级延时电路的第二输出端。中间延时电路的第一输出端连接至中间延时电路的上一级延时电路的第二输入端。中间延时电路的第二输出端连接至中间延时电路的下一级延时电路的第一输入端。中间延时电路的第二输入端连接至中间延时电路的下一级延时电路的第一输出端。
图2是本申请实施例提供的一种参考时钟产生电路200的结构示意图。如图2所示，该参考时钟产生电路200包括P个级联的延时电路。这P个级联的延时电路从左到右依次连接。其中，每个延时电路包括一个控制端，该控制端用于输入控制信号。
如图2所示，从左到右第一级延时电路的第一输入端用于输入初始时钟信号，该初始时钟信号通过图2所示的P个延时电路中至少一级延时电路处理后，从第一级延时电路的第一输入端输出，进而从参考时钟产生电路的输出端输出参考时钟信号。
在图2所示的参考时钟产生电路中，第一级延时电路至最后一级延时电路中各个输入端和输入端的连接关系如图2所示。具体的连接关系已经在上述实施例中详细说明，在此不再赘述。
基于上述内容可知上述P个级联的延时电路中每个延时电路包括一个控制端，控制端用于输入控制信号以控制对应的延时电路导通或断开。由此可知，P个延时电路中各个延时电路的控制端分别用于输入一个控制信号，串联连接后的每个延时电路通往下一级延时电路的通路通过相应的控制信号打开或关闭。
也即是，每个延时电路对应的一个控制信号，且每个延时电路通往下一级延时电路的通路可以通过控制信号打开或关闭。比如，某个延时电路对应的控制信号为高电平时，该延时电路通往下一级延时电路的通路导通。某个延时电路对应的控制信号为低电平时，该延时电路通往下一级延时电路的通路断开。
因此可以通过控制各个延时电路的控制信号来控制串联导通的延时电路的个数，该串联导通的延时电路的个数可以称为串联级数，其中，串联级数不同，参考时钟产生电路输出的参考时钟信号的频率不同。因此，可以预先基于芯片上的时钟的理想工作参数对参考时钟产生电路进行训练，训练的过程包括：不断调整各个延时电路对应的控制信号，直至参考时钟产生电路输出的参考时钟信号满足前述理想工作参数。例如，可以从第一个延时电路开始，依次将延时电路对应的控制信号设置为高电平，直至参考时钟产生电路输出的时钟信号满足理想工作参数。
上述参考时钟产生电路输出的时钟信号满足前述理想工作参数的情况下，与各个延时电路对应的控制信号的配置信息可以称为参考时钟产生电路的目标电路配置信息。该目标电路配置信息还可以称为配置级数或配置码字等等。其中，控制信号的配置信息具体可以指示控制信号为高电平还是低电平或者指示参考时钟产生电路中串联导通的延时电路的数量。此外，针对参考时钟产生电路训练得到的目标电路配置信息还可以称为第一目标电路配置信息。
在一种可能的实现方式中，上述参考时钟产生电路中的任一延时电路可以包括第一与非门、第二与非门、第三与非门以及反相器，第一与非门、第二与非门、第三与非门中任一者包括第一输入端、第二输入端和输出端，反相器包括输入端和输出端。
此时，对于任一延时电路，该延时电路的第一输入端连接至第一与非门和第二与非门的第一输入端。该延时电路的第二输入端连接至第三与非门的第二输入端。该延时电路的第一输出端连接至第三与非门的输出端。该延时电路的第二输出端连接至第一与非门的输出端。该延时电路的控制端连接至第一与非门的第二输入端和反相器的输入端。反相器的输出端连接至第二与非门的第二输入端。第二与非门的输出端连接至第三与非门的第一输入端。
换句话说，参考时钟产生电路中各个延时电路的串联连接方式具体可以表示如下。
其中，串联连接后的第一个延时电路中第一与非门的第一输入端用于输入待调制信号，该待调制信号即为上述初始时钟信号。串联连接后除第一个延时电路外其他延时电路中第一与非门的第一输入端和串联连接的上一级延时电路中第一与非门的输出端连接。任一延时电路中第一与非门的第二输入端以及反相器的输入端均用于输入与任一延时电路相应的控制信号。任一延时电路中的反相器的输出端和同一延时电路中的第二与非门的第二输入端连接，任一延时电路中第二与非门的第一输入端和同一延时电路中第一与非门的第一输入端的输入信号相同，任一延时电路中第二与非门的输出端和同一延时电路中第三与非门的第一输入端连接。串联连接后的最后一个延时电路中第三与非门的第二输入端和同一延时电路中的第一与非门的输出端连接，串联连接后除最后一个延时电路外其他延时电路中第三与非门的第二输入端和下一级延时电路中的第三与非门的输出端连接。串联连接后的第一个延时电路中第三与非门的输出端用于输出将待调制信号的频率调整后的时钟信号，从而得到参考时钟信号。
图3为本申请实施例提供的一种参考时钟产生电路的结构示意图。如图3所示，该参考时钟产生电路200包括P个延时电路201，每个延时电路201包括三个与非门2011-2013和一个反相器2014。每个延时电路对应一个控制信号，图3中将控制信号标记为SEL。
应当理解，与非门有两个输入端和一个输出端。当与非门的输入端的输入信号均为高电平，则输出端输出信号为低电平。当与非门的输入端的输入信号中至少有一个为低电平，则输出端输出信号为高电平。反相器可以将输入端输入的信号的相位反转180度。
以图3中左边的第一个延时电路为例进行说明。如图2所示，与非门2011-2013中任一与非门均包括第一输入端、第二输入端和输出端，图3中采用数字1标记与非门的第一输入端，采用数字2标记与非门的第二输入端。反相器2014包括输入端和输出端。
其中，在图3中左边第一个延时电路中，与非门2011和与非门2012的第一输入端均用于输入信号a，该输入信号a即为初始时钟信号。与非门2011的第二输入端用于输入控制信号SEL，与非门2011的输出端和下一级延时电路中的与非门2011的第一输入端连接。反相器2014的输入端用于输入控制信号SEL。反相器2014的输出端和与非门2012的第二输入端连接。与非门2012的第一输入端和同一延时电路中与非门2011的第一输入端的输入信号相同。与非门2012的输出端和与非门2013的第一输入端连接，与非门2013的第二输入端和下一级延时电路中的与非门2013的输出端连接。
信号a为一定频率的脉冲信号，以第一个延时电路为例说明各个延时电路处理信号的过程。当向第一个延时电路输入信号a时，信号a输入至与非门2011的第一输入端和与非门2012的第一输入端。当SEL信号为高电平时，与非门2011输出的是一个具有一定延迟的脉 冲信号，此时表明通往下一级延时电路的通路被打开。但是由于反相器2014的输出信号是低电平信号，因此与非门2012输出的是高电平信号，与非门2012的输出信号输入至与非门2013的第一输入端，下一级延时电路中的与非门2013的输出信号输入至与非门2013的第二输入端，由于与非门2012输出的是高电平信号，因此，与非门2013输出的是相对于下一级延时电路中的与非门2013的输出信号具有一定延时的输出信号。
相应地，当SEL信号为低电平时，与非门2011输出的是一个高电平信号，表明通往下一级延时电路的通路被关闭，此时下一级延时电路的与非门2013输出的也是高电平信号。此外，当与非门2012输入信号a时，与非门2012输出的是相对于信号a具有一定延时的脉冲信号，与非门2012的输出信号和下一级延时电路中的与非门2013的输出信号输入至本级延时电路的与非门2013。由于下一级延时电路中的与非门2013的输出信号是高电平信号，因此与非门2013输出的是相对于与非门2012的输出信号具有一定延时的脉冲信号。
应当理解，本申请实施例提供的延时电路包括两条通路，一条通路通往下一级延时电路，另一条通路通往本级延时电路的输出端。当延时电路的控制信号为高电平时，通往下一级延时电路的通路导通，信号a输入至下一级延时电路以实现进一步延时；当延时电路的控制信号为低电平时，通过下一级延时电路的通路断开，信号a通过本级延时电路的与非门2012和与非门2013后从本级延时电路的输出端返回前一级延时电路。最后一级延时电路的与非门2011的输出端与最后一级延时电路的与非门2013的第二输入端连接。
图4是本申请实施例提供的另一种参考时钟产生电路的结构示意图。如图4所示，在图3所示的参考时钟产生电路的基础上，该参考时钟产生电路还包括还包括与非门2000，该与非门2000用于将使能信号和参考时钟产生电路中第一级延时电路的第一输出端的输出信号经过与非门2000处理后，得到信号a，并将信号a输入至第一个延时电路，以便于后续通过各个延时电路调整信号a的频率。换句话说，该与非门2000的第一输入端用于输入使能信号，该使能信号指示开启或关闭参考时钟产生电路。该与非门2000的第二输入端和第一级延时电路的第一输出端连接。该与非门2000的输出端和第一级延时电路的第一输入端连接。
具体地，当使能信号为高电平时，表明开启参考时钟产生电路，此时参考时钟产生电路在使能信号的驱动下，第一级延时电路的第一输出端在使能信号输入的初始时刻先输出一定频率的时钟信号，该时钟信号和使能信号通过与非门2000之后输出信号a，然后信号a经过级联的P个延时电路后从第一级延时电路的第一输出端最终输出频率稳定的时钟信号。当使能信号为低电平时，表明关闭参考时钟产生电路，此时第一级延时电路的第一输出端不会输出一定频率的时钟信号。
通过图2至图4任一所示的参考时钟产生电路，对于任一延时电路，如果对应的SEL信号为高电平时，则表明该延时电路通往下一个延时电路的通路被打开，这样可以使得脉冲信号继续通过下一个延时电路被延时。如果对应的SEL信号为低电平时，则表明该延时电路通往下一个延时电路的通路被关闭。
需要说明的是，对于图2至图4任一所示的参考时钟产生电路，当某个延时电路对应的控制信号SEL为低电平时，由于该延时电路通往下一个延时电路的通路被关闭，因此该延时电路后续的各个延时电路也不需要对脉冲信号起延时作用，所以还需将该延时电路后续的各个延时电路对应的控制信号均设置为低电平。
由此可知，调整各个延时电路的SEL信号具体是指：从第一级延时电路开始连续多少个 延时电路的控制信号为高电平。
比如，对于图2至图4任一所示的参考时钟产生电路，图2至图4任一所示的从左到右各个延时电路的控制信号的配置信息依次可以为[1，1，1，0，0，0，0…，0]，“1”表示高电平，“0”表示低电平，此时表明前三个延时电路通往下一级的通路被打开，后续各个延时电路通往下一级延时电路的通路被关闭。
基于图2至图4任一所示的电路，如果调整各个延时电路对应的控制信号SEL，可以实现将输入的脉冲信号a的频率进行调整。因此，可以预先基于芯片上的时钟的理想工作参数对该参考时钟产生电路进行训练，以使参考时钟产生电路输出满足理想工作频率的参考时钟信号。然后将此时参考时钟产生电路的中各个控制信号SEL的配置信息作为目标电路配置信息写入芯片上，以便后续检测时钟时使用。此时的目标电路配置信息具体是指：P个延时电路对应的控制信号为高电平或低电平。比如，高电平为1，低电平为0。
此外，上述对参考时钟产生电路进行训练的过程可以为：调整该参考时钟产生电路中的各个延时电路的控制信号，在调整该参考时钟产生电路的各个延时电路的控制信号后，在第一计时时长内统计该参考时钟产生电路的输出信号中的脉冲数量，如果第一计时时长内统计的脉冲数量和第一理论数值之间的差值在第一参考差值之内，则基于本次调整后的各个延时电路的控制信号确定目标电路配置信息。如果第一计时时长内统计的脉冲数量和第一理论数值之间的差值超过第一参考差值，则继续调整该参考时钟产生电路的各个延时电路的控制信号。其中，第一理论数值指示第一计时时长内频率为理想工作频率的脉冲信号中的脉冲数量。
比如，假设芯片上的时钟的理想工作频率为24兆赫兹(MHz)，对于图2至图4任一所示的参考时钟产生电路，假设目标电路配置信息为[1，1，1，1，0，0，0…，0]，则表明在图2中从左到右前4个延时电路通过下一级的延时电路之间串联的通路依次被打开，其他延时电路通过下一级的延时电路之间的通路关闭的情况下，该参考时钟产生电路输出的参考时钟信号的频率为24MHz。
另外，在每次调整了参考时钟产生电路中的各个延时电路的控制信号后，为了使得参考时钟产生电路产生稳定的时钟信号，可以在调整了各个延时电路的控制信号后，先等待几个循环(cycle)周期，以使参考时钟产生电路输出稳定的时钟信号。其中，参考时钟产生电路中与非门2000和后续各个延时电路形成的环还称为振荡环，此时，等待几个循环周期后，参考时钟产生电路输出稳定的时钟信号也即是振荡环输出稳定的时钟信号。
此外，上述调整该参考时钟产生电路中的各个延时电路的控制信号可以通过二分法来实现，从而加速上述训练过程。也即是，如果本次调整后的参考时钟产生电路输出的时钟信号的频率不满足理想工作频率，则基于上次调整的各个延时电路的控制信号和二分法来获取下次需要调整的各个延时电路的控制信号。
比如，图2至图4任一所示的参考时钟产生电路包括60个延时电路，先假设前30个延时电路对应的控制信号为高电平，后30个延时电路对应的控制信号为低电平，然后确定此时参考时钟产生电路输出的时钟信号的频率。基于该频率和理想工作频率，判断目标数量在30个以内，还是30个以上，其中，目标数量具体是指：参考时钟产生电路输出的时钟信号的频率符合理想工作频率的情况下，参考时钟产生电路中连通的延时电路的数量。如果目标数量在30个以内，继续假设前15个延时电路对应的控制信号为高电平，后45个延时电路对应的控制信号为低电平，然后确定此时参考时钟产生电路输出的时钟信号的频率。重复上述过程， 直至确定出的参考时钟产生电路输出的时钟信号的频率和理想工作频率基本一致。
上述是以参考时钟产生电路包括60个延时电路为例来说明如何调整各个延时电路的控制信号，关于其他数量下的延时电路的二分法的详细过程，本申请实施例不做过多解释。
另外，需要说明的是，可能存在无论如何调整各个延时电路的控制信号，参考时钟产生电路产生的时钟信号的频率与理想工作频率上均有一定误差的情况。这种场景下，可以在参考时钟产生电路输出的脉冲信号的频率和理想工作频率在一定误差之内时，通过扣脉冲的方式来微调参考时钟产生电路输出的时钟信号的频率，以使参考时钟产生电路输出的时钟信号的频率和理想工作频率尽量一致。
其中，扣脉冲的方式具体可以通过门控使能信号来实现。在一种可能的实现方式中，如图4所示，参考时钟产生电路还可以包括门控电路，其中，门控电路和串联连接后的第一个延时电路的第一输出端连接。当向门控电路输入门控使能信号，该门控使能信号用于扣除串联连接后的第一个延时电路的第二输出端输出的时钟信号中的一个或P个脉冲，从而实现扣脉冲。上述门控电路具体可以通过触发器来实现，本申请实施例并不限定门控电路的内部结构。
换句话说，门控电路包括输入端、输出端以及控制端。门控电路的输入端和第一级延时电路的第一输出端连接，门控电路的输出端和参考时钟产生电路的输出端连接，也即是，第一级延时电路的第一输出端通过门控电路和参考时钟产生电路的输出端连接。门控电路的控制端用于输入门控使能信号。图4中为了便于区分，将门控电路的控制端标记为数字“1”，门控电路中的输入端标记为数字“2”，将门控电路的输出端标记为数字“3”。
具体地，当门控使能信号拉低(比如，门控使能信号为低电平0)时，此时参考时钟产生电路输出的时钟信号被门控。当门控使能信号拉高(比如，门控使能信号为高电平1)，参考时钟产生电路输出的时钟信号正常通过，从而实现微调参考时钟产生电路输出的时钟信号的频率。这种场景下，在训练参考时钟产生电路后，目标电路配置信息除了包括各个延时电路对应的控制信号为高电平或低电平，还包括门控使能信号的配置信息。
需要说明的是，图4中输入门控电路的门控使能信号和输入与非门2000的使能信号之间没有任何关联，两者是相互独立的信号。
图5是本申请实施例提供的一种训练参考时钟产生电路的流程示意图。如图5所示，在训练开始之后，先设置参考时钟产生电路的配置级数以及扣脉冲个数，配置级数如前述所讲用于指示各个延时电路对应的控制信号为高电平还是低电平。在等待图2所示的参考时钟产生电路输出的时钟信号循环几个周期后，统计参考时钟产生电路在第一计时时长内的脉冲数量，得到计数结果。然后判断计数结果是否符合第一理论数值，第一理论数值指示第一计时时长内频率为理想工作频率的脉冲信号的脉冲数量。如果计数结果符合第一理论数值，则将此次的配置级数作为最终的配置级数，从而得到目标电路配置信息。如果计数结果不符合第一理论值，则通过二分法改变配置级数，并相应改变扣脉冲个数，返回重新计数的过程，直至得到最终的配置级数。
需要说明的是，图3和图4中的延时电路的具体结构仅仅是本申请实施例提供的一种可选的延时电路的电路结构。任意其他具有相同功能的电路结构也在本申请实施例涉及的延时电路的保护范围之内，在此不再一一举例说明。
(2)在芯片上配置毛刺检测电路105。
在本申请实施例中，为了便于后续还能对芯片的时钟信号中的毛刺信号进行检测。还可以预先在芯片上配置毛刺检测电路。毛刺检测电路和前述参考时钟产生电路一样，均为全数字电路，关于全数字电路的优点在此不再重复说明。此外，本申请实施例中的检测时钟信号中的毛刺信号也可以称为检测时钟信号中的毛刺，也即是，“毛刺信号”和“毛刺”在本申请实施例中用于指示同一概念。
在一种可能的实现方式中，毛刺检测电路包括N个延时电路，N个与门，N+1个触发器。每个延时电路包括输入端、输出端，每个与门包括第一输入端、第二输入端以及输出端，每个触发器包括输入端、输出端以及控制端。N为大于1的正整数。
其中，N个延时电路串联连接，串联连接后除最后一个延时电路外其他每个延时电路的输出端和下一级延时电路的输入端连接，这N个延时电路中每个延时电路的输出端还与一个与门的第一输入端连接。串联连接的第一个延时电路的输入端和每个与门的第二输入端用于输入待检测的芯片的时钟信号。后续将待检测的芯片的时钟信号简称为待检测时钟信号。N+1个触发器中每个触发器的输出端和同一触发器的输入端反相连接，N+1个触发器中有N个触发器的控制端分别一个与门的输出端连接，N+1个触发器中除前述N个触发器外的剩下的触发器的控制端用于输入待检测时钟信号。其中，N+1个触发器中除前述N个触发器外的剩下的触发器还可以称为第一触发器。
由于与门的工作原理是：当所有的输入同时为高电平时，输出才为高电平，否则输出为低电平。因此，基于上述毛刺检测检测电路，每个与门将输出待检测时钟信号和一定延时之后的待检测时钟信号两者之间相与的信号，且输入各个与门的延时之后的待检测时钟信号的延时时长是逐渐增加的。由于待检测时钟信号中毛刺信号的脉冲宽度通常低于正常情况下时钟信号的脉冲宽度，因此，随着待检测时钟信号的延时时长的逐渐增加，如果某个延时电路针对待检测时钟信号的延时时长超过了毛刺信号的脉冲宽度，与该延时电路连接的与门的输出信号便不会有与该毛刺信号对应的脉冲。所以，可以基于毛刺检测范围从与各个与门连接的N个触发器中选择一个目标触发器，然后将目标触发器的输出信号和输入待检测时钟信号的触发器的输出信号进行比较，便可确定待检测时钟信号中是否有毛刺信号。也即是，可以基于N+1个触发器的输出端的输出信号检测待检测时钟信号中的毛刺信号。
也即是，在本申请实施例中，所述毛刺检测电路包括N个级联的延时电路，N个与门，N+1个触发器，所述N个与门中每个与门包括第一输入端、第二输入端以及输出端，所述N+1个触发器中每个触发器包括输入端、输出端以及控制端，所述N为大于1的正整数。
其中，N个级联的延时电路中第一级延时电路的输入端以及N个与门中每个与门的第二输入端用于输入时钟信号。N个级联的延时电路中除最后一级延时电路外其他每个延时电路的输出端连接至下一级延时电路的输入端。N个延时电路中每个延时电路的输出端分别与一个与门的第一输入端连接。N+1个触发器中第一触发器的控制端用于输入时钟信号，N+1个触发器中除第一触发器之外的N个触发器的控制端连接至N个与门的输出端，其中，一个与门对应一个触发器。N+1个触发器中每个触发器的输出端通过反相器连接至同一触发器的输入端。N+1个触发器的输出端的输出信号用于检测时钟信号中是否包含毛刺。
图6是本申请实施例提供的一种毛刺检测电路的结构示意图。如图6所示，N个延时电路串联连接，串联连接之后的前N-1个延时电路中每个延时电路的输出端和下一个延时电路的输入端连接。每个延时电路的输出端还和一个与门的第一输入端连接，图6中将与门的第 一输入端标记为1，将与门的第二输入端标记为数字2。每个与门的第二输入端用于输入待检测时钟信号。
下面以图6为例说明本申请实施例提供的毛刺检测电路的基本工作原理。
如图6所示，将被检测时钟信号输入至串联连接后的第一个延时电路的输入端以及各个与门的第二输入端。图7是本申请实施例提供的一种毛刺检测电路中脉冲时序示意图。如图7所示，将被检测时钟信号标记为clk，clk的脉冲分布如图7所示。将第一个延时电路的输出信号标记为clk-dly1，将第二个延时电路的输出信号标记为clk-dly2，…，将第N个延时电路的输出信号标记为clk-dlyN。其中，clk-dly1、clk-dly2，…，clk-dlyN的脉冲分布如图7所示。如图7所示，相对于待检测时钟信号clk，各个延时电路的输出信号clk-dly1、clk-dly2，…，clk-dlyN相对于待检测时钟信号clk的延时时长是逐渐增加的。
将各个延时电路的输出信号和待检测时钟信号输入至相应与门时，与门输出的是待检测时钟信号和延时之后的待检测时钟信号相与的信号。如图7所示，clk-det1是clk-dly1和clk经过与门之后的输出信号，clk-det2是clk-dly2和clk经过与门之后的输出信号，…，clk-detN是clk-dlyN和clk经过与门之后的输出信号。
基于上述图7所示的脉冲分布可知，在待检测时钟信号clk中有毛刺信号的情况下，如果延时电路针对待检测时钟信号的延时时长小于毛刺信号的脉冲宽度，则与该延时电路连接的与门的输出信号中将存在该毛刺信号对应的脉冲，如果延时电路针对待检测时钟信号的延时时长大于毛刺信号的脉冲宽度，则与该延时电路连接的与门的输出信号中将不存在该毛刺信号对应的脉冲。由于毛刺信号的脉冲宽度通常是低于正常情况下时钟信号的脉冲宽度的，因此，随着串联连接的延时电路个数的增加，前几个与门的输出信号中可能会检测到该毛刺信号对应的脉冲，但是后续的与门的输出信号中将无法检测到该毛刺信号对应的脉冲。比如，图7中，clk-det1对应的脉冲分布中在图7中椭圆框线位置处比clk-detN对应位置的多出一个脉冲。该脉冲即为被检测时钟的输出信号中的毛刺信号对应的脉冲。
此外，图7中各个与门的输出信号中的脉冲分布可以通过触发器来采样确定。如图6所示，每个与门的输出端连接一个触发器。图6中的触发器可以包括控制端(图6中将控制端标记为CP)、输入端(图6中将输入端标记为D)以及输出端(图6中将输出端标记为Q)。如图6所示，图6中的每个与门的输出端与一个触发器的控制端连接。如此，触发器可在与门的输出信号的上升沿来采集数据。此外，图6中触发器的输入端是将触发器的输出端的信号反相后作为输入信号的。因此，图6所示的触发器可以在与门的输出信号的每个上升沿改变输出状态。
比如，在与门的输出信号的第一个上升沿将存储的1变换为0，并存储0，在与门的输出信号第二个上升沿时将存储的0变为1，并存储1。因此，通过触发器记录的1和0，便可确定前述的与门的输出信号中在各个时钟周期上的脉冲分布。
此时，从与各个与门连接的N个触发器中选择一个目标触发器，然后将目标触发器的输出信号和输入待检测时钟信号的触发器的输出信号进行比较，具体地是指：比较每个时钟周期内采集的1和0的分布，便可确定待检测时钟信号中是否有毛刺信号。比如，对于图6所示的从上到下各个触发器，基于毛刺检测范围选择第四个触发器采集的数据来确定待检测时钟信号是否有毛刺信号，且第四个触发器在某个时钟周期内采集的1和0的分布情况为1000，但是最后一个触发器(采集的是待检测时钟信号)在该时钟周期内采集的1和0的分布情况 为1010，此时可表明该时钟周期内待检测时钟信号中有一个毛刺信号。
另外，上述基于毛刺检测范围从与各个与门连接的N个触发器中选择一个目标触发器具体是指：确定各个延时电路的输出信号相对于待检测时钟信号的延时时长，从延时时长超过毛刺检测范围的各个延时时长中选择最小延时时长对应的延时电路，将选择的延时电路所连接的触发器作为目标触发器。
在一种可能的实现方式中，图6所示的各个延时电路的固有延时时长相同，延时电路的固有延时时长是指延时电路的输出信号相对于延时电路自身的输入信号的延时时长。此时，上述基于毛刺检测范围从与各个与门连接的N个触发器中选择一个目标触发器具体是指：将毛刺检测范围和单个延时电路的固有延时时长相除，将相除后的数值取整数，假设取整数为i，则将串联连接的N个延时电路中第i个延时电路所连接的触发器作为目标触发器。
此外，芯片上配置的毛刺检测电路包括的延时电路的内部结构可以和前述参考时钟产生电路包括的延时电路的内部结构为相同结构的延时电路，但是各个延时电路之间的连接关系不同，如此毛刺检测电路中各个延时电路的固有延时时长和参考时钟产生电路中延时电路的固有延时时长相同。以便于在对参考时钟产生电路训练之后，便可基于训练后的参考时钟产生电路中的延时电路的固有延时时长和毛刺检测范围确定上述目标触发器。也即是，在本申请实施例中，毛刺检测电路是不需要预先训练的，仅仅根据训练后的参考时钟产生电路中的单个延时电路的固有延时时长和毛刺检测范围便可确定需要使用毛刺检测电路中哪个触发器作为目标触发器。
具体地，在对参考时钟产生电路进行训练之后，确定训练后的参考时钟产生电路中单个延时电路的固有延时时长，然后确定毛刺检测范围的上限。基于毛刺检测范围的上限和前述固有延时时长，便可配置上述目标触发器。比如，训练后的参考时钟产生电路中单个延时电路的固有延时时长为1ns，将脉冲宽度在3ns以内的脉冲信号称为毛刺信号，则毛刺检测电路中的i配置为3/1＝3。此时，对于图6所示的毛刺检测电路，通过串联连接后的第三个延时电路所连接的触发器的输出信号和图6中最后一个触发器的输出信号之间的比较，便可确定待检测时钟信号中是否有毛刺信号。
需要说明的是，在毛刺检测电路中，单个延时电路的内部结构可以和图2中参考时钟产生电路包括的延时电路的内部结构相同。但是各个延时电路之间的连接关系不同。图8是本申请实施例提供的一种毛刺检测电路中各个延时电路的连接关系示意图。
如图8所示，N个延时电路601中任一延时电路包括第一与非门、第二与非门、第三与非门以及反相器，第一与非门、第二与非门、第三与非门中任一者包括第一输入端、第二输入端和输出端，反相器包括输入端和输出端。图8中将第一与非门标记为6011，第二与非门标记为6012，将第三与非门标记为6013，反相器标记为6014。每个与非门的第一输入端标记为数字“1”，每个与非门的第二输入端标记为数字“2”。
如图8所示，第一与非门6011的第一输入端为延时电路601的输入端，第三与非门6013的输出端为延时电路601的输出端，其中，N个延时电路串联连接具体是指：第一个延时电路601的输出端连接至第二个延时电路601的输入端，第二个延时电路601的输出端连接至第三个延时电路601的输入端，以此类推，直至第N-1个延时电路601的输出端连接至第N个延时电路601的输入端。也即，每一级延时电路的输入端连接至前一级延时电路的输出端，且每一级延时电路的输出端连接至下一级延时电路的输入端。
对于图6所示的毛刺检测电路，任一延时电路中的第三与非门6013的输出端还与图6中的一个与门的第一输入端连接。
也即是，在本申请实施例中，毛刺检测电路中N个延时电路中任一延时电路包括第一与非门、第二与非门、第三与非门以及反相器，第一与非门、第二与非门、第三与非门中任一者包括第一输入端、第二输入端和输出端。
其中，该延时电路的输入端连接至第一与非门和第二与非门的第一输入端。该延时电路的输出端连接至下一级延时电路的输入端。该延时电路的控制端连接至第一与非门的第二输入端和反相器的输入端。反相器的输出端连接至第二与非门的第二输入端。第二与非门的输出端连接至第三与非门的第一输入端。第一与非门的输出端连接至第三与非门的第二输入端。
另外，在图8所示的连接关系中，各个延时电路对应的控制信号均配置为高电平信号，以便图6所示的毛刺检测电路中各个触发器均能采集到信号，从而实现毛刺信号的检测。
需要说明的是，由于毛刺信号的范围可能在发生变化，因此预先在芯片上配置的毛刺检测电路可以包括较多数量的延时电路以及延时电路后续所连接的与门和触发器。后续在实际测量时，可以基于毛刺检测范围，来确定通过串联连接的第几个延时电路所连接的触发器进行检测。比如，预先在毛刺检测电路中配置20个串联连接的延时电路，当确定出N为3时，只需要通过第三个延时电路所连接的触发器的输出信号来检测毛刺信号即可。
此外，在芯片出厂前，如果能够确定时钟信号的毛刺检测范围，则可以在芯片出厂前确定出上目标触发器具体为哪个触发器，并生成第二目标电路指示信息，然后将第二目标触发器为哪个触发器的信息写入芯片。该第二目标电路配置信息还可以称为针对毛刺检测电路的目标电路配置信息。
(3)在芯片上配置占空比检测电路106。
在本申请实施例中，为了便于后续还能对芯片上的时钟信号的占空比进行检测。还可以预先在芯片上配置占空比检测电路。占空比检测电路和前述参考时钟产生电路一样，均为全数字电路，关于全数字电路的优点在此不再重复说明。
在一种可能的实现方式中，图9是本申请实施例提供的一种占空比检测电路的结构示意图。如图9所示，该占空比检测电路包括第一延时调整电路(图9中将第一延时调整电路标记为DLY-FIX)、第二延时调整电路(图9中将第二延时调整电路标记为DLE-TRIM-DUTY)以及M个第三延时调整电路(图9中将第三延时调整电路标记为DLY-CLK-DUTY)、分频器、反相器、M+2个两级寄存器、M+1个异或门(图9中XOR所标记的逻辑门指示异或门)，M+1个触发器。M为大于1的正整数。
每个异或门包括第一输入端、第二输入端和输出端。每个两级寄存器包括第一输入端、第二输入端以及输出端，图9中将每个两级寄存器的第一输入端标记为数字“1”，将每个两级寄存器的第二输入端标记为数字“2”。每个触发器包括输入端、输出端以及控制端。每个异或门包括第一输入端、第二输入端以及输出端，图9中将每个异或门的第一输入端标记为数字“1”，将每个异或门的第二输入端标记为数字“2”。分频器、反相器、第一延时调整电路、第二延时调整电路以及M个第三延时调整电路均包括输入端和输出端。
其中，M个第三延时调整电路串联连接，分频器的输出端和第一延时调整电路的输入端连接、第一延时调整电路的输出端和第二延时调整电路的输入端连接，第二延时调整电路的输出端和串联连接后的第一个第三延时调整电路的输入端连接。第二延时调整电路的输出端 以及串联连接后的每个第三延时调整电路的输出端均与一个两级寄存器的第一输入端连接，每个两级寄存器的输出端与一个异或门的第一输入端连接，图9中将M+1个两级寄存器中与各个异或门连接的M个两级寄存器称为两级寄存器A。
此外，反相器的输出端与M+1个两级寄存器中除前述M个两级寄存器外剩下的一个两级寄存器的第一输入端的连接，图9中将该两级寄存器标记为两级寄存器B。分频器的输出端还与两级寄存器B的第二输入端连接，该两级寄存器B的输出端与每个异或门的第二输入端连接。另外，反相器的输出端还与和各个两级寄存器A的第二输入端连接。前述分频器和反相器的输入端均用于输入待检测时钟信号。
上述两级寄存器A还可以称为第二两级寄存器，两级寄存器B还可以称为第一两级寄存器。分频器具体可以通过一个触发器和一个反相器组合得到，也即是，所述分频器包括输入端、输出端和控制端，输入端和输出端通过一个反相器连接。此外，可以将分频器中的反相器称为第二反相器，将用于输入待检测时钟信号的反相器称为第一反相器。这种场景下，上述占空比检测电路的连接关系还可以描述如下。
占空比检测电路包括第一延时调整电路、第二延时调整电路以及M个级联的第三延时调整电路、分频器、第一反相器、第二反相器、第一两级寄存器以及M+1个第二两级寄存器、M+1个异或门以及M+1个触发器，M为大于1的正整数。
其中，第一两级寄存器以及M+1个第二两级寄存器中任一者包括第一输入端、第二输入端和输出端，M+1个异或门中每个异或门包括第一输入端、第二输入端和输出端，M+1个触发器中每个触发器包括输入端、输出端以及控制端，分频器包括输入端、输出端和控制端。分频器的控制端用于输入时钟信号，分频器的输入端和分频器的输出端之间通过第二反相器连接，分频器的输出端和第一延时调整电路的输入端连接、第一延时调整电路的输出端和第二延时调整电路的输入端连接，第二延时调整电路的输出端和级联的M个第三延时调整电路中第一级第三延时调整电路的输入端连接。
第二延时调整电路的输出端以及级联的M个第三延时调整电路的每个第三延时调整电路的输出端一一对应连接至M+1个第二两级寄存器的第一输入端。M+1个第二两级寄存器的第二输入端均与第一反相器的输出端连接，第一反相器的输入端用于输入时钟信号，M+1个第二两级寄存器的输出端与M+1个异或门的第一输入端一一对应连接。M+1个异或门的输出端和M+1个触发器的输入端一一对应连接。
第一反相器的输出端还与第一两级寄存器的第一输入端连接，分频器的输出端与第一两级寄存器的第二输入端连接，第一两级寄存器的输出端与M+1个异或门的第二输入端连接。M+1个触发器的输出端的输出信号用于检测时钟信号的占空比。
下面以图9为例对本申请实施例提供的占空比检测电路的工作原理进行解释说明。
如图9所示，待检测时钟信号输入至分频器后，分频器将待检测时钟信号转换为1/2原频率的脉冲信号。图10是本申请实施例提供的一种占空比检测电路中各个电路的输出信号的脉冲时序示意图。如图10所示，将待检测时钟信号标记为clk，将分频器的输出信号标记为clk-div2，clk-div2的频率是clk的频率的1/2。
为了后续便于说明，该1/2原频率的脉冲信号称为分频信号，分频信号通过第一延时调整电路和第二延时调整后依次被延时。图10中，将第一延时调整电路的输出信号标记为clk-dly-fix，将第二延时调整电路的输出信号标记为clk-dly0。如图10所示，第一延时调整电路 的输出信号相对于分频器的输出信号clk-div2延时了一段时长，第二延时调整电路的输出信号clk-dly0相对于第一延时调整电路的输出信号clk-dly-fix又延时了一段时长。图10中将第一延时调整电路的输出信号clk-dly-fix和分频器的输出信号clk-div2之间的延时时长标记为DLY-FIX，将第二延时调整电路的输出信号clk-dly0和第一延时调整电路的输出信号clk-dly-fix之间的延时时长标记为DLY-TRIM。
第二延时调整电路的输出信号输入至串联连接后的第一个第三延时调整电路，每个第三延时调整电路均将自身的输入信号延时一段时长。如图10所示，将各个第三延时调整电路的输出信号依次标记为clk-dly1、clk-dly2、clk-dly3、…、clk-dlyM。如图10所示，如果将单个第三延时调整电路的固有延时时长标记为DLY-DUTY，那么如图10所示，clk-dly1相对于clk-dly0的延时时长为DLY-DUTY，clk-dly2相对于clk-dly2的延时时长为DLY-DUTY，…，clk-dlyM相对于clk-dlyM-1的延时时长为DLY-DUTY。
图9和图10中，将待检测时钟信号clk输入至反相器后，反相器的输出信号标记为clk-INV。如图9所示，将图10中clk-dly0、clk-dly1、clk-dly2、clk-dly3、…、clk-dlyM分别和反相器的输出信号clk-INV输入至两级寄存器A进行同步处理，该同步处理过程的作用为：将clk-dly0、clk-dly1、clk-dly2、clk-dly3…、clk-dlyM中各个信号的上升沿或下降沿调整为和clk-INV的上升沿或下降沿对齐。具体地，在反相器的输出信号clk-INV的每个上升沿确定相应的clk-dly信号为高电平或低电平，如果是高电平，则输出高电平，直至下一个上升沿继续判断相应的clk-dly信号为高电平或低电平，如果是低电平，则输出低电平。如此，经过两级寄存器处理后的信号便分别如图10中的clk-dff2-dly0、clk-dff2-dly1、clk-dff2-dly2、clk-dff2-dly3、…、clk-dff2-dlyM所示。
此外，如图9所示，还将反相器的输出信号clk-INV和分频器的输出信号clk-div2也输入至两级寄存器B以进行同步处理，得到的信号标记为clk-no-dly0，该信号clk-no-dly0还可以称为“反时钟采集二分频时钟的输出信号”，然后将clk-no-dly0分别和clk-dff2-dly0、clk-dff2-dly1、clk-dff2-dly2、clk-dff2-dly3、…、clk-dff2-dlyM输入至相应的异或门。其中，异或门的功能为：若两个输入端输入的电平相异，则输出为高电平；若两个输入端输入的电平相同，则输出为低电平。如图9所示，各个异或门的输出信号依次标记为clk-data-dly0、clk-data-dly1、clk-data-dly2、clk-data-dly3、…、clk-data–dlyM。
具体地，如图10所示，任一异或门的两个输入信号要么是相同的信号，要么是反相的信号，因此，各个异或门输出的是高电平信号或低电平信号。
此外，可以通过触发器来采集各个异或门的输出信号。如图9所示，触发器包括控制端(图9中将控制端标记为CP)、输入端(图9中将输入端标记为D)以及输出端(图9中将输出端标记为Q)，每个异或门的输出端和一个触发器的输入端连接。其中，图9中的触发器的控制端用于输入反相器的输出信号clk-INV。触发器的输出端的输出信号和触发器的输入端的输入信号一致。也即，图9中的触发器用于在反相器的输出信号clk-INV的每个上升沿采集异或门的输出信号。基于前述可知，各个异或门输出的是高电平信号或低电平信号，因此，通过触发器采集的数据要么是0要么是1。
基于图10所示的脉冲分布可知，各个异或门的输出信号能够表征待检测时钟信号在一个时钟周期的下降沿左右两侧高电平和低电平分布情况。由于高电平通常表示为1，低电平通常表示为0，因此前述下降沿左右两侧高电平和低电平分布情况还可以称为“下降沿左右两 侧的输出码字”。
基于上述各个异或门的输出信号表征的信息，可以预先基于占空比允许范围设置一个时间区间，以在该时间区间内采集待检测时钟信号在一个时钟周期的下降沿左右两侧高电平和低电平分布情况。如果在该时间区间内各个异或门的输出信号中既有高电平、又有低电平，则确定待检测时钟信号的占空比在占空比允许范围之内。如果在该时间区间内各个异或门的输出的号中均为高电平或者均为低电平(比如全部为0或者全部为1)，则确定待检测时钟信号的占空比不在占空比允许范围之内。
需要说明的是，在图9所示的占空比检测电路中，各个第三延时调整电路的总延时时长便能够指示上述时间区间，因此可以预先基于占空比允许范围来设置各个第三延时调整电路的延时时长。
在一种可能的实现方式中，各个第三延时调整电路可以包括k个延时电路，k为大于1的正整数，且第三延时调整电路中包括的延时电路的结构以及连接关系可以和图2所示的参考时钟产生电路中的延时电路的结构和连接关系相同。
也即是，在一种可能的实现方式中，M个第三延时调整电路中任一第三延时调整电路包括k个级联的延时电路，k个级联的延时电路中每个延时电路包括一个控制端，控制端用于输入控制信号以控制对应的延时电路导通或断开。其中，k个级联的延时电路中第一级延时电路包括第一输入端和第一输出端。第一级延时电路的第一输入端和第三延时调整电路的输入端连接。第一级延时电路的第一输出端和第三延时调整电路的输出端连接。
关于第三延时调整电路中包括中第一级延时电路至最后一级延时电路中各个延时电路的连接关系，均可以参考前述图2的实施例，在此不再赘述。
此外，和图2中一样，k个延时电路中任一延时电路包括第一与非门、第二与非门、第三与非门以及反相器，第一与非门、第二与非门、第三与非门中任一者包括第一输入端、第二输入端和输出端。该延时电路的第一输入端连接至第一与非门和第二与非门的第一输入端。该延时电路的第二输入端连接至第三与非门的第二输入端。该延时电路的第一输出端连接至第三与非门的输出端。该延时电路的第二输出端连接至第一与非门的输出端。该延时电路的控制端连接至第一与非门的第二输入端和反相器的输入端。反相器的输出端连接至第二与非门的第二输入端。第二与非门的输出端连接至第三与非门的第一输入端。
也即是，第三延时调整电路中的k个延时电路中任一延时电路包括第一与非门、第二与非门、第三与非门以及反相器，第一与非门、第二与非门、第三与非门中任一者包括第一输入端、第二输入端和输出端，反相器包括输入端和输出端。
其中，串联连接后的第一个延时电路中第一与非门的第一输入端为相应的第三延时调整电路的输入端，串联连接后除第一个延时电路外其他延时电路中第一与非门的第一输入端和串联连接的上一级延时电路中第一与非门的输出端连接。任一延时电路中第一与非门的第二输入端以及反相器的输入端均用于输入与任一延时电路相应的控制信号。任一延时电路中的反相器的输出端和同一延时电路中的第二与非门的第二输入端连接，任一延时电路中第二与非门的第一输入端和同一延时电路中第一与非门的第一输入端的输入信号相同，任一延时电路中第二与非门的输出端和同一延时电路中第三与非门的第一输入端连接。串联连接后的最后一个延时电路中第三与非门的第二输入端和同一延时电路中的第一与非门的输出端连接，串联连接后除最后一个延时电路外其他延时电路中第三与非门的第二输入端和下一级延时电 路中的第三与非门的输出端连接。串联连接后的第一个延时电路中第三与非门的输出端为相应的第三延时调整电路的输出端。
第三延时调整电路中各个延时电路的具体连接关系可以参考图2，在此不再详细说明。
此时，在训练完图2所示的参考时钟产生电路后，便可基于训练后的参考时钟产生电路中单个延时电路的固有延时时长和占空比允许范围，设置第三延时调整电路中串联导通的延时电路的数量，从而实现设置各个第三延时调整电路的延时时长。也即是，任一第三延时调整电路中预先设置有多个延时电路，在应用时，基于占空比允许范围来设置第三延时调整电路中串联的延时电路的数量。
比如，占空比允许范围为40％～60％，一个时钟周期为1纳秒(ns)，则一个时钟周期内高电平时长为0.4～0.6ns(低电平时长为0.6～0.4ns)，此时占空比允许范围对应的时间区间为0.1ns。假设第三延时调整电路有10级(也即是图9所示的占空比检测电路中N＝10)，则每级第三延时调整电路的延时时长为0.1ns/10＝0.01ns。若训练后的参考时钟产生电路中单个延时电路的固有延时时长为0.005ns，则每个第三延时调整电路中需要设置0.01/0.005＝2个延时电路。此时，确定的延时电路的数量还可以称为针对第三延时调整电路的配置级数。
在芯片出厂前，如果能够确定出时钟信号的占空比允许范围，则可以基于占空比允许范围确定出任一第三延时调整电路包括的k个延时单元中串联导通的延时单元的数量，此时可以根据任一第三延时调整电路包括的k个延时单元中串联导通的延时单元的数量，生成针对占空比检测电路的目标电路配置信息，并将针对占空比检测电路的目标电路配置信息写入芯片。
此外，上述第一延时调整电路和第二延时调整电路中的延时时长是提前训练得到的，训练过程中，向占空比检测电路输入占空比为理想占空比的时钟信号，然后不断调整第一延时调整电路和第二延时调整电路的延时时长，直至各个触发器中输出0的触发器的数量和输出1的触发器数量之间的比值和理想占空比保持一致，此时训练目的达到。在达到训练目的之后，将最后一次调整后的第一延时电路和第二延时调整电路的延时时长携带在上述占空比检测电路的目标电路配置信息中，以便将该目标电路配置信息写入芯片。
上述针对占空比检测电路的目标电路配置信息还可以称为第三目标电路配置信息。
上述各个触发器中输出0的触发器数量和输出1的触发器数量之间的比值和理想占空比一致是指：各个触发器中输出0的触发器数量和输出1的触发器数量之间的比值和理想占空比中高电平宽度与低电平宽度之间比值相同。
具体地，在基于占空比允许范围配置了第三延时调整电路的延时时长后，将占空比满足理想占空比的时钟信号输入至图9所示的占空比检测电路，然后调整第一延时调整电路和第二延时调整电路的延时时长，在每次调整之后，判断各个触发器中输出0的触发器的数量和输出1的触发器的数量之间的比值和理想占空比是否一致，如果一致，则将本次调整后的第一延时调整电路和第二延时调整电路的延时时长确定为占空比检测电路的目标电路配置信息。如果不一致，则继续调整第一延时调整电路和第二延时调整电路的延时时长。
比如，目前芯片上的时钟信号的理想占空比通常为50％。因此，在训练占空比检测电路时，可以向占空比检测电路输入50％占空比的标准时钟信号，然后调整第一延时调整电路和第二延时调整电路的延时时长，直至各个触发器中输出0的触发器的数量和输出1的触发器的数量基本持平，也即是各个触发器中接近一半的触发器输出的数据为0，接近一半的触发 器输出的数据为1。
需要说明的是，图9所示的占空比检测电路中的第一延时调整电路(DLY-FIX)用于实现对输入信号的延时进行粗调，第二延时调整电路(DLE-TRIM-DUTY)用于实现对输入信号的延时进行细调。可选地，图9所示的占空比检测电路中也可以仅仅设置一个延时调整电路，本申请实施例对此不做限定。
此外，图9中的配置信号用于配置各个延时调整电路的延时大小。也即是，在确定了各个延时调整电路的延时时长后，通过配置信号来设置各个延时调整电路的延时时长。
上述内容对芯片上扩展的数字电路进行了详细说明。在本申请实施例中，可以在芯片出厂前，预先在芯片上同时配置上述参考时钟产生电路、毛刺检测电路和占空比检测电路，以便于后续出厂后基于这三个电路实现对同一芯片上的时钟信号的频率、毛刺信号以及占空比的检测。
可选地，在芯片出厂前，还可以在配置完上述参考时钟产生电路、毛刺检测电路和占空比检测电路之后，针对每个电路配置一个使能开关，以便在后续出厂后，根据测量需求和使能开关使能某个电路，并基于该电路对同一芯片上的时钟信号进行检测。
可选地，在芯片出厂前，还可以基于实际的测量需求仅配置上述三个电路中的一个或多个。比如，如果实际应用场景中仅仅需要对芯片的时钟信号的频率进行检测，则在芯片出厂前，在芯片上配置上述参考时钟产生电路即可。或者，如果实际应用场景中，仅仅需要对芯片的时钟信号的频率和毛刺信号进行检测，则在芯片出厂前，在芯片上配置上述参考时钟产生电路和毛刺检测电路即可。在此不再一一举例说明。
需要说明的是，在毛刺检测电路中包括的延时电路和参考时钟产生电路中包括的延时电路为相同结构的情况下，由于毛刺检测电路中用于检测毛刺信号所使用的延时电路需要基于训练后参考时钟产生电路中延时电路的固有延时时长和毛刺检测范围来确定，这种场景下，即使只需要检测芯片的时钟信号中的毛刺信号，也将参考时钟产生电路和毛刺检测电路同时配置在芯片上。
同样地，在占空比检测电路中第三延时调整电路包括的延时电路和参考时钟产生电路中包括的延时电路为相同结构的情况下，由于第三延时调整电路中串联的延时电路的数量需要基于训练后参考时钟产生电路中延时电路的固有延时时长和占空比允许范围来确定，这种场景下，即使只需要检测芯片的时钟信号的占空比，也将参考时钟产生电路和占空比检测电路同时配置在芯片上。
此外，上述对参考时钟产生电路的训练过程以及对占空比检测电路的训练过程可以在芯片出厂前完成。这种场景下，将训练后的参考时钟产生电路的目标电路配置信息、以及训练之后的占空比检测电路的目标电路配置信息均写入芯片。以便于后续基于这些训练后的目标电路配置信息对待检测时钟信号进行检测。
可选地，上述对参考时钟产生电路的训练过程以及对占空比检测电路的训练过程也可以在芯片出厂后基于具体需求来完成。这种场景下，在芯片出厂后，可以基于具体需求的理想工作频率、理想占空比等理想工作参数对参考时钟产生电路和占空比检测电路进行训练。训练过程同样可以参考上述内容，在此不再详细说明。
需要说明的是，在本申请实施例中，理想工作参数是指在为芯片配置时钟时期望的时钟 的工作参数。理想工作参数可以包括理想工作频率和/或理想占空比。其中，理想工作频率是指期望的时钟信号的频率，理想占空比是指期望的时钟信号的占空比。在应用本申请实施例时，理想工作频率和理想占空比可以通过芯片出厂时的配置数据获取。比如，可以将芯片出厂时配置的时钟的额定工作频率作为理想工作频率，将芯片出厂时配置的时钟的额定信号占空比作为理想占空比。
比如，目前市场上通用的芯片，芯片出厂时配置的时钟的额定工作频率通常为24MHz，额定信号占空比为50％。此时，前述理想工作参数便可包括理想工作频率24MHz和/或理想占空比50％。
关于上述参考时钟产生电路、毛刺检测电路以及占空比检测电路的训练过程，前述实施例已经详细解释说明，下面对基于配置的各个电路检测芯片上的时钟信号的过程进行详细说明。
图11是本申请实施例提供的一种时钟检测方法流程图。该方法由图1所示的芯片上的处理器来执行。其中，该芯片还包括时钟，该时钟用于生成时钟信号，该芯片还包括参考时钟产生电路、毛刺检测电路或占空比检测电路的至少一项。如图11所示，该方法包括如下几个步骤。
步骤1101：处理器基于如下至少一项对时钟信号进行检测。
如图11所示，步骤1101中的至少一项包括：基于参考时钟产生电路生成的参考时钟信号检测该时钟信号的频率；或，基于毛刺检测电路检测该时钟信号是否包含毛刺；或，基于占空比检测电路检测该时钟信号的占空比。
基于图11所示的实施例，基于参考时钟产生电路即可对芯片上的时钟信号的频率进行检测，从而避免了在对芯片上的时钟信号检测时需要额外通过模拟电路引出一个标准参考时钟，因此节省了芯片资源。此外，通过图11所示的实施例，还可以实现对同一芯片上的时钟信号包含的毛刺以及时钟信号的占空比的检测，提高了检测时钟信号的灵活性。
关于图11中对时钟信号的频率的检测、时钟信号中的毛刺的检测以及时钟信号的占空比的检测的具体实现方式，将分别通过下述三个实施例详细说明。在此就先不展开阐述。
图12是本申请实施例提供的一种时钟检测方法流程图。该方法用于对芯片的时钟信号的频率进行检测。为了后续便于说明，将需要检测的芯片的时钟信号简称为待检测时钟信号。
基于图1所示的芯片可知，本申请实施例提供的方法应用于芯片的处理器上。因此，如图12所示，该方法包括如下几个步骤。
步骤1201：处理器基于理想工作频率确定第二计时时长，按照第一目标电路配置信息控制参考时钟产生电路包括的各个延时电路对应的控制信号，以使参考时钟产生电路输出参考时钟信号，其中，第一目标电路配置信息指示参考时钟中各个延时电路对应的控制信号为高电平或低电平。
由于第一目标电路配置信息是对参考时钟产生电路按照理想工作频率训练之后的电路配置信息，因此，处理器在按照第一目标电路配置信息控制各个延时电路对应的控制信号时，参考时钟产生电路便可输出参考时钟信号，参考时钟信号的频率即为上述理想工作频率。
上述第二计时时长是为了对待检测时钟信号进行计数所设计的一个计时时长。第二计时 时长可以在芯片出厂后基于具体需求来配置，也可以在芯片出厂前配置。需要说明的是，第二计时时长和前述第一计时时长中的“第一”和“第二”没有特定含义，此处的“第一”和“第二”仅仅用于区分两个不同的计时时长。
步骤1202：处理器统计第二计时时长内参考时钟信号中的脉冲数量，以及第二计时时长内待检测时钟信号中的脉冲数量，分别得到第一计数结果和第二计数结果。
由于标准参考时钟的频率为上述理想工作频率，因此，可以以标准参考时钟为理论参考对象检测待检测时钟信号的频率。
在具体计数时，可以基于第二计时时长设计一个脉宽等于第二计时时长的脉冲信号，然后通过该脉冲信号控制计数器。在计数过程中，如果该脉冲信号为高电平，则无需对计数器执行任何操作，计数器继续计数。如果该脉冲信号为低电平，则控制计数器停止计数。从而实现计数器在第二计时时长内计数。
步骤1203：如果第一计数结果和第二计数结果之间的差值超过第二参考差值，则输出第一频率提示信号，第一频率提示信号指示待检测时钟信号的频率不稳定。
相应地，如果第一计数结果和第二计数结果之间的差值在第二参考差值之内，则输出第二频率提示信号，第二频率提示信号指示待检测时钟信号的频率稳定。
上述第二参考差值为预先设置的阈值，该阈值可以为5、10等等。该预先设置的阈值可以基于理想工作频率的可浮动范围以及第二计时时长来确定。比如，理想工作频率为24MHz，第二计时时长为1秒(s)，理想工作频率的可浮动范围为：在24MHz附近上下浮动100Hz，则上述第二参考差值即为100Hz*1s＝100。
同样需要说明的是，第二参考差值和前述第一参考差值中的“第一”和“第二”没有特定含义，此处的“第一”和“第二”仅仅用于区分两个不同的参考差值。
由此可知，在本申请实施例中，基于参考时钟产生电路生成的参考时钟信号检测待检测时钟信号的频率具体可以为：控制参考时钟产生电路输出频率为理想工作频率的参考时钟信号，理想工作频率为时钟信号的理想工作频率，如果待检测时钟信号的实际工作频率和参考时钟信号的频率不同，则确定待检测时钟信号的频率不稳定。相应地，如果待检测时钟信号的实际工作频率和参考时钟信号的频率相同，则确定待检测时钟信号的频率稳定。
上述待检测时钟信号的实际工作频率和参考时钟信号的频率是否相同具体便可通过步骤1203中的两个计数结果来判断，如果两个计数结果之间的差值超过第二参考差值，则表明待检测时钟信号的实际工作频率和参考时钟信号的频率不同。如果两个计数结果之间的差值没有超过第二参考差值，则表明待检测时钟信号的实际工作频率和参考时钟信号的频率相同。
此外，在处理器输出第一频率提示信号时，芯片系统还可以发出报警信号，以提示当前待检测时钟信号的频率不稳定。
在一种可能的实现方式中，上述第一频率提示信号可以为1，第二频率提示信号可以为0。这种场景下，当两个计数结果相差不大时，表明第二计数结果在理论值范围内时，处理器则输出第二频率提示信号“0”，表示此时待检测时钟信号的频率在合理范围内，芯片系统不报警。当两个计数结果相差较大时，表明第二计数结果超出理论值范围，处理器则输出第一频率提示信号“1”，芯片系统发出报警信号。
图13是本申请实施例提供的一种训练和检测时钟频率的完整流程示意图。如图13所示，芯片上的处理器先对参考时钟产生电路进行训练，在训练时，处理器以满足理想工作频率的 脉冲信号为参考对象，对参考时钟产生电路进行训练。在每次训练时，使用计数器统计参考时钟产生电路的输出信号中的脉冲数量和前述脉冲信号中的脉冲数量之间的差距，以确定是否达到训练目的，训练目的是为了让参考时钟产生电路也产生满足理想工作频率的参考时钟信号，并将此时参考时钟产生电路中各个延时电路对应的控制信号的配置信息作为第一目标电路配置信息写入芯片。
后续处理器便可基于该第一目标电路配置信息对待检测时钟信号的频率进行检测。具体地，在检测时，处理器按照第一目标电路配置信息配置参考时钟产生电路中各个延时电路的控制信号后，以参考时钟产生电路的输出信号为参考对象，对待检测时钟信号进行计数，比较两个计数结果，即可判断待检测时钟信号的频率是否稳定，然后基于判断结果输出频率提示信号。关于图13所示的流程的具体实现方式可以参考前述实施例，在此就不再重复说明了。
此外，图13中的处理器中可以配置有状态机控制电路，在具体应用时，基于该状态机控制电路完成图13中的训练和检测过程。
综上所述，在本申请实施例中，可以预先在芯片上扩展出参考时钟产生电路，然后基于理想工作频率对参考时钟产生电路进行训练(trim)，得到参考时钟产生电路的第一目标电路配置信息。这样后续就可以基于该第一目标电路配置信息对同一芯片上的时钟信号进行检测，从而避免了在对芯片上的时钟信号检测时需要额外通过模拟电路引出一个标准参考时钟，因此节省了芯片资源。
图14是本申请实施例提供的另一种时钟检测方法流程图。该方法用于对芯片上的时钟信号中的毛刺信号进行检测。同样地为了后续便于说明，将需要检测的芯片的时钟信号简称为待检测时钟信号。基于图1所示的芯片可知，本申请实施例提供的方法应用于芯片的处理器上。因此，如图14所示，该方法包括如下几个步骤。
步骤1401：处理器控制待检测时钟信号输入至毛刺检测电路。
上述毛刺检测电路具体可以为图6所示的毛刺检测电路。此时，步骤1401中将待检测时钟信号输入毛刺检测电路具体是指：将待检测时钟信号输入至串联连接的N个延时电路中的第一个延时电路的输入端和每个与门的第二输入端。
换句话说，将时钟信号输入第一触发器，得到第一输出信号，第一触发器为N+1个触发器中的一个。具体地对于图6所示的毛刺检测电路，第一触发器为没有和与门连接的触发器。将时钟信号通过X个级联的延时电路后输入第X+1触发器，得到第X+1输出信号。其中，X依次取1至N中的每个正整数，第X+1触发器为N+1个触发器中除第一触发器外的触发器。具体地对于图6所示的毛刺检测电路，第X+1触发器为和N个与门分别连接的触发器。
步骤1402：处理器获取毛刺检测电路中的N+1个触发器中与与门连接的N个触发器中的目标触发器的输出信号、以及N+1个触发器中第一触发器的输出信号。
关于目标触发器的确定方式在前述毛刺检测电路中已经解释说明，在此不再赘述。
步骤1403：如果目标触发器的输出信号和第一触发器的输出信号在同一时钟周期内输出信号不同，则确定待检测时钟信号中存在毛刺信号。
相应地，如果目标触发器的输出信号和第一触发器的输出信号在同一时钟周期内输出信号相同，则确定待检测时钟信号中不存在毛刺信号。
上述判断目标触发器的输出信号和N+1个触发器除N个触发器外的触发器的输出信号 在同一时钟周期内输出信号是否相同，具体实现方式可以参考图6所示的毛刺检测电路的工作原理，在此不再赘述。
图15是本申请实施例提供的一种时钟检测方法流程图。该方法用于对芯片上的时钟信号的占空比进行检测。同样地为了后续便于说明，将需要检测的芯片的时钟信号简称为待检测时钟信号。基于图1所示的芯片可知，本申请实施例提供的方法应用于芯片的处理器上。因此，如图15所示，该方法包括如下几个步骤。
步骤1501：处理器控制待检测时钟信号输入至占空比检测电路。
针对图9所示的占空比检测电路，将待检测时钟信号输入至占空比检测电路具体是指：将待检测时钟信号输入至图9所示的分频器以及反相器的输入端中。
步骤1502：处理器获取占空比检测电路中的M+1个触发器的输出端的输出信号。
如前述图9所示的占空比检测电路的工作原理可知，各个触发器采集要么是0，要么是1。换句话说明，各个异或门的输出信号要么为低电平要么高电平。
步骤1503：如果M+1个触发器的输出端的输出信号中既有低电平也有高电平，则输出第一占空比提示信号，第一占空比提示信号用于指示待检测时钟信号的占空比在允许占空比范围之内。
步骤1504：如果M+1个触发器的输出端的输出信号中全为低电平，则输出第二占空比提示信号，第二占空比提示信号指示待检测时钟的输出信号的占空比不在占空比范围之内，且待检测时钟信号中位于高电平的信号的占比超过该占空比允许范围。
步骤1505：如果M+1个触发器的输出端的输出信号中全为高电平，则输出第三占空比提示信号，第三占空比提示信号指示待检测时钟信号的占空比不在占空比范围之内，且待检测时钟出信号中位于低电平的信号的占比超过该占空比允许范围。
此外，在步骤1504和步骤1505中，处理器可以仅仅输出同一种占空比提示信号，此时，该占空比提示信号仅仅用于指示待检测时钟信号的占空比不在占空比允许范围之内，并没有其他指示含义。
比如，对于图9所示的占空比检测电路，在基于50％的时钟信号训练之后，如果待检测时钟信号的占空比为50％，则各个触发器的输出信号中一半为高电平，一半为低电平。此时，处理器输出第一占空比提示信号即可。
图16是本申请实施例提供的一种低电平占比过大情况下占空比检测电路的检测结果以及高电平占比过大情况下占空比检测电路的检测结果。如果被检测时钟信号中低电平占比过大，表明一个循环周期内低电平的持续时间过长。如图16所示，在反相器的输出信号clk-INV的第一个上升沿采集的各个第三延时调整电路的输出信号可能均是低电平(图16中标记为采集的电平均是0)，如此通过各个两级寄存器A同步处理后的的输出信号可能和两级寄存器B处理后的输出信号为完全相反的信号，这样各个异或门输出的便全是高电平。此时，在通过图9所示的触发器采集各个异或门的输出信号后，采集的可能全是1。这种场景下，处理器将输出第二占空比提示信号，该第二占空比提示信号指示待检测时钟的输出信号中低电平的占比较大。
相应地，如图16所示，如果被检测时钟信号中高电平占比过大，表明一个循环周期内低电平的持续时间过长。此时，在反相器的输出信号clk-INV的第一个上升沿采集的各个第三 延时调整电路的输出信号可能均是高电平(图16中标记为采集的电平均是1)，如此通过各个两级寄存器A同步处理后的输出信号可能和两级寄存器B同步处理后的输出信号为完全相同的信号，这样各个异或门输出的便全是低电平。在通过图9所示的触发器采集各个异或门的输出信号后，采集的可能全是0。这种场景下，处理器将输出第三占空比提示信号，该第三占空比提示信号指示待检测时钟信号中高电平的占比较大。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成，也可以通过程序来指令相关的硬件完成，所述的程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
以上所述仅为本申请的示例性实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (25)

  1. 一种芯片，其特征在于，所述芯片包括处理器和时钟，所述时钟用于生成时钟信号，所述芯片还包括参考时钟产生电路、毛刺检测电路或占空比检测电路的至少一项；
    所述处理器用于基于如下至少一项对所述时钟信号进行检测：
    基于所述参考时钟产生电路生成的参考时钟信号检测所述时钟信号的频率；或，
    基于所述毛刺检测电路检测所述时钟信号是否包含毛刺；或，
    基于所述占空比检测电路检测所述时钟信号的占空比。
  2. 如权利要求1所述的芯片，其特征在于，所述参考时钟产生电路包括P个级联的延时电路，所述P个级联的延时电路中每个延时电路包括一个控制端，所述控制端用于输入控制信号以控制对应的延时电路导通或断开，所述P为大于1的正整数；
    所述P个级联的延时电路中第一级延时电路包括第一输入端和第一输出端；
    所述第一级延时电路的第一输入端用于输入初始时钟信号，所述初始时钟信号通过至少一级导通的延时电路后从所述第一级延时电路的第一输出端输出；
    所述第一级延时电路的第一输出端和所述参考时钟产生电路的输出端连接，所述参考时钟产生电路的输出端用于输出所述参考时钟信号。
  3. 如权利要求2所述的芯片，其特征在于，所述P个级联的延时电路中每个延时电路均包括第一输入端、第二输入端、第一输出端和第二输出端；
    所述第一级延时电路的第二输出端连接至第二级延时电路的第一输入端，所述第一级延时电路的第二输入端连接至所述第二级延时电路的第一输出端；
    所述P个级联的延时电路中最后一级延时电路的第一输入端连接至所述最后一级延时电路的上一级延时电路的第二输出端；所述最后一级延时电路的第二输出端连接至所述最后一级延时电路的第二输入端；所述最后一级延时电路的第一输出端连接至所述最后一级延时电路的上一级延时电路的第二输入端。
  4. 如权利要求3所述的芯片，其特征在于，
    所述P个级联的延时电路中的中间延时电路的第一输入端连接至所述中间延时电路的上一级延时电路的第二输出端；
    所述中间延时电路的第一输出端连接至所述中间延时电路的上一级延时电路的第二输入端；
    所述中间延时电路的第二输出端连接至所述中间延时电路的下一级延时电路的第一输入端；
    所述中间延时电路的第二输入端连接至所述中间延时电路的下一级延时电路的第一输出端；
    所述中间延时电路为所述P个级联的延时电路中除所述第一级延时电路和所述最后一级延时电路之外的任一个延时电路。
  5. 如权利要求2至4任一所述的芯片，其特征在于，
    所述芯片上存储有第一目标电路配置信息，所述第一目标电路配置信息指示所述参考时钟产生电路中各个延时电路分别对应的控制信号的配置情况；
    在所述参考时钟产生电路中各个延时电路对应的控制信号按照所述第一目标电路配置信息设置后，所述参考时钟产生电路输出的所述参考时钟信号的频率为理想工作频率，所述理想工作频率为所述时钟信号的理想工作频率。
  6. 如权利要求5所述的芯片，其特征在于，所述第一目标电路配置信息指示所述各个延时电路分别对应控制信号为高电平或低电平；
    其中，所述P个级联的延时电路中任一延时电路对应的控制信号为高电平时，所述任一延时电路通往下一级延时电路的通路导通，所述任一延时电路对应的控制信号为低电平时，所述任一延时电路通往下一级延时电路的通路断开。
  7. 如权利要求2所述的芯片，其特征在于，所述参考时钟产生电路还包括门控电路；
    所述第一级延时电路的第一输出端通过所述门控电路和所述参考时钟产生电路的输出端连接；
    所述门控电路包括控制端，所述门控电路的控制端用于输入门控使能信号，所述门控使能信号用于扣除所述第一级延时电路的第一输出端输出的时钟信号中的一个或多个脉冲，以得到所述参考时钟信号。
  8. 如权利要求2所述的芯片，其特征在于，所述参考时钟产生电路还包括与非门，所述与非门包括第一输入端、第二输入端以及输出端；
    所述与非门的第一输入端用于输入使能信号，所述使能信号指示开启或关闭所述参考时钟产生电路；
    所述与非门的第二输入端和所述第一级延时电路的第一输出端连接；
    所述与非门的输出端和所述第一级延时电路的第一输入端连接。
  9. 如权利要求2至8任一所述的芯片，其特征在于，所述P个延时电路中任一延时电路包括第一与非门、第二与非门、第三与非门以及反相器，所述第一与非门、所述第二与非门、所述第三与非门中任一者包括第一输入端、第二输入端和输出端；
    所述延时电路的第一输入端连接至所述第一与非门和所述第二与非门的第一输入端；
    所述延时电路的第二输入端连接至所述第三与非门的第二输入端；
    所述延时电路的第一输出端连接至所述第三与非门的输出端；
    所述延时电路的第二输出端连接至所述第一与非门的输出端；
    所述延时电路的控制端连接至所述第一与非门的第二输入端和所述反相器的输入端；
    所述反相器的输出端连接至所述第二与非门的第二输入端；
    所述第二与非门的输出端连接至所述第三与非门的第一输入端。
  10. 如权利要求1所述的芯片，其特征在于，
    所述毛刺检测电路包括N个级联的延时电路，N个与门，N+1个触发器，所述N个与门中每个与门包括第一输入端、第二输入端以及输出端，所述N+1个触发器中每个触发器包括输入端、输出端以及控制端，所述N为大于1的正整数；
    所述N个级联的延时电路中第一级延时电路的输入端以及所述N个与门中每个与门的第二输入端用于输入所述时钟信号；
    所述N个级联的延时电路中除最后一级延时电路外其他每个延时电路的输出端连接至下一级延时电路的输入端；
    所述N个延时电路中每个延时电路的输出端分别与一个与门的第一输入端连接；
    所述N+1个触发器中第一触发器的控制端用于输入所述时钟信号，所述N+1个触发器中除所述第一触发器之外的N个触发器的控制端连接至所述N个与门的输出端，其中，一个与门对应一个触发器；
    所述N+1个触发器中每个触发器的输出端通过反相器连接至同一触发器的输入端；
    所述N+1个触发器的输出端的输出信号用于检测所述时钟信号中是否包含毛刺。
  11. 如权利要求10所述的芯片，其特征在于，所述芯片上存储有所述第二目标电路配置信息；
    所述第二目标电路配置信息指示目标触发器为所述N个触发器中的哪一个；
    所述目标触发器的输出信号和所述第一触发器的输出信号用于检测所述时钟信号中是否包含毛刺。
  12. 如权利要求11所述的芯片，其特征在于，所述N个延时电路为结构相同的延时电路，所述目标触发器是基于毛刺检测范围和所述N个延时电路中单个延时电路的延时时长确定的，所述毛刺检测范围指示所述时钟信号包含的毛刺的脉冲宽度。
  13. 如权利要求10至12任一所述的芯片，其特征在于，所述N个延时电路中任一延时电路包括第一与非门、第二与非门、第三与非门以及反相器，所述第一与非门、所述第二与非门、所述第三与非门中任一者包括第一输入端、第二输入端和输出端；
    所述延时电路的输入端连接至所述第一与非门和所述第二与非门的第一输入端；
    所述延时电路的输出端连接至下一级延时电路的输入端；
    所述延时电路的控制端连接至所述第一与非门的第二输入端和所述反相器的输入端；
    所述反相器的输出端连接至所述第二与非门的第二输入端；
    所述第二与非门的输出端连接至所述第三与非门的第一输入端；
    所述第一与非门的输出端连接至所述第三与非门的第二输入端。
  14. 如权利要求1所述的芯片，其特征在于，
    所述占空比检测电路包括第一延时调整电路、第二延时调整电路以及M个级联的第三延时调整电路、分频器、第一反相器、第二反相器、第一两级寄存器以及M+1个第二两级寄存器、M+1个异或门以及M+1个触发器，M为大于1的正整数；
    所述第一两级寄存器以及所述M+1个第二两级寄存器中任一者包括第一输入端、第二输入端和输出端，所述M+1个异或门中每个异或门包括第一输入端、第二输入端和输出端，所述M+1个触发器中每个触发器包括输入端、输出端以及控制端，所述分频器包括输入端、输出端和控制端；
    所述分频器的控制端用于输入所述时钟信号，所述分频器的输入端和所述分频器的输出端之间通过所述第二反相器连接，所述分频器的输出端和所述第一延时调整电路的输入端连接、所述第一延时调整电路的输出端和所述第二延时调整电路的输入端连接，所述第二延时调整电路的输出端和所述级联的M个第三延时调整电路中第一级第三延时调整电路的输入端连接，所述级联的M个第三延时调整电路中除最后一级第三延时调整电路外其他每个第三延时调整电路的输出端和下一级第三延时调整电路的输入端连接；
    所述第二延时调整电路的输出端以及所述级联的M个第三延时调整电路的每个第三延时调整电路的输出端一一对应连接至所述M+1个第二两级寄存器的第一输入端；
    所述M+1个第二两级寄存器的第二输入端均与所述第一反相器的输出端连接，所述第一反相器的输入端用于输入所述时钟信号，所述M+1个第二两级寄存器的输出端与所述M+1个异或门的第一输入端一一对应连接；
    所述M+1个异或门的输出端和所述M+1个触发器的输入端一一对应连接；
    所述第一反相器的输出端还与所述第一两级寄存器的第一输入端连接，所述分频器的输出端与所述第一两级寄存器的第二输入端连接，所述第一两级寄存器的输出端与所述M+1个异或门的第二输入端连接；
    所述M+1个触发器的输出端的输出信号用于检测所述时钟信号的占空比。
  15. 如权利要求14所述的芯片，其特征在于，所述M个第三延时调整电路中任一第三延时调整电路包括k个级联的延时电路，所述k个级联的延时电路中每个延时电路包括一个控制端，所述控制端用于输入控制信号以控制对应的延时电路导通或断开，所述k为大于1的正整数；
    所述k个级联的延时电路中第一级延时电路包括第一输入端和第一输出端；
    所述第一级延时电路的第一输入端和所述第三延时调整电路的输入端连接；
    所述第一级延时电路的第一输出端和所述第三延时调整电路的输出端连接。
  16. 如权利要求15所述的芯片，其特征在于，
    所述芯片上存储有第三目标电路配置信息，其中，所述第三目标电路配置信息指示所述k个延时电路中串联导通的延时电路的数量、以及所述第一延时调整电路和所述第二延时调整电路的延时时长；
    在所述第一延时调整电路、所述第二延时调整电路以及所述第三延时调整电路按照所述第三目标电路配置信息设置后，如果向所述占空比检测电路输入占空比为50％的时钟信号，则所述M+1个触发器的输出端的输出信号中一半为高电平信号、一半为低电平信号。
  17. 如权利要求15所述的芯片，其特征在于，所述k个延时电路为结构相同的延时电路，所述k个延时电路中串联导通的延时电路的数量是基于占空比允许范围和所述k个延时 电路中单个延时电路的延时时长确定的，所述占空比允许范围指示所述时钟信号的占空比的允许浮动范围。
  18. 一种时钟检测方法，其特征在于，所述方法应用于芯片上的处理器，所述芯片还包括时钟，所述时钟用于生成时钟信号，所述芯片还包括参考时钟产生电路、毛刺检测电路或占空比检测电路的至少一项；
    所述方法包括：
    所述处理器基于如下至少一项对所述时钟信号进行检测：
    基于所述参考时钟产生电路生成的参考时钟信号检测所述时钟信号的频率；或，
    基于所述毛刺检测电路检测所述时钟信号是否包含毛刺；或，
    基于所述占空比检测电路检测所述时钟信号的占空比。
  19. 如权利要求18所述的方法，其特征在于，所述基于所述参考时钟产生电路生成的参考时钟信号检测所述时钟信号的频率，包括：
    控制所述参考时钟产生电路输出频率为理想工作频率的参考时钟信号，所述理想工作频率为所述时钟信号的理想工作频率；
    如果所述时钟信号的实际工作频率和所述参考时钟信号的频率不同，则确定所述时钟信号的频率不稳定。
  20. 如权利要求19所述的方法，其特征在于，所述参考时钟产生电路包括P个级联的延时电路，所述芯片上存储有第一目标电路配置信息，所述第一目标电路配置信息指示所述参考时钟产生电路中各个延时电路分别对应控制信号的配置情况；
    所述控制所述参考时钟产生电路输出频率为理想工作频率的参考时钟信号，包括：
    基于所述第一目标电路配置信息，控制所述参考时钟产生电路中各个延时电路对应的控制信号，以使所述参考时钟产生电路输出频率为理想工作频率的参考时钟信号。
  21. 如权利要求18所述的方法，其特征在于，所述毛刺检测电路包括N个级联的延时电路和N+1个触发器；
    所述基于所述毛刺检测电路检测所述时钟信号是否包含毛刺，包括：
    将所述时钟信号输入第一触发器，得到第一输出信号；所述第一触发器为所述N+1个触发器中的任一个；
    将所述时钟信号通过X个级联的延时电路后输入第X+1触发器，得到第X+1输出信号；其中，X依次取1至N中的每个正整数，所述第X+1触发器为所述N+1个触发器中除所述第一触发器外的触发器；
    获取所述毛刺检测电路中目标触发器的输出信号以及所述第一输出信号，所述目标触发器为所述N+1个触发器中除所述第一触发器外的一个触发器；
    如果所述目标触发器的输出信号和所述第一输出信号在同一时钟周期内输出信号不同，则确定所述时钟信号中包含毛刺。
  22. 如权利要求21所述的方法，其特征在于，所述芯片上存储有第二目标电路配置信息，其中，所述第二目标电路配置信息指示所述目标触发器为所述N+1个触发器中哪一个；
    所述获取所述毛刺检测电路中目标触发器的输出信号，包括：
    基于所述第二目标电路配置信息，获取所述毛刺检测电路中所述目标触发器的输出信号。
  23. 如权利要求18所述的方法，其特征在于，所述占空比检测电路包括分频器、第一反相器和M+1个触发器；
    所述基于所述占空比检测电路检测所述时钟信号的占空比，包括：
    将所述时钟信号输入至所述分频器和所述第一反相器的输入端；
    获取所述占空比检测电路中的所述M+1个触发器的输出端的输出信号；
    如果所述M+1个触发器的输出端的输出信号中包括高电平信号和低电平信号，则输出第一占空比提示信号，所述第一占空比提示信号用于指示所述时钟信号的占空比在允许占空比范围之内。
  24. 如权利要求23所述的方法，其特征在于，如果所述M+1个触发器的输出端的输出信号全是高电平信号，则输出第二占空比提示信号，所述第二占空比提示信号指示所述时钟信号的占空比没有在允许占空比范围之内，且所述时钟信号中低电平信号的占比超过所述占空比允许范围；
    如果所述M+1个触发器的输出端的输出信号全是低电平信号，则输出第三占空比提示信号，所述第三占空比提示信号指示所述时钟信号的占空比没有在允许占空比范围之内，且所述时钟信号中高电平信号的占比超过所述占空比允许范围。
  25. 如权利要求23所述的方法，其特征在于，所述方法应用于如权利要求16所述的芯片中，所述芯片上存储有第三目标电路配置信息，其中，所述第三目标电路配置信息指示任一第三延时调整电路包含的k个延时电路中串联导通的延时电路的数量、以及所述第一延时调整电路和所述第二延时调整电路的延时时长；
    所述将所述时钟信号输入至所述分频器和所述第一反相器的输入端之前，还包括：
    基于所述第三目标电路配置信息，配置所述占空比检测电路。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115334264A (zh) * 2022-08-17 2022-11-11 中国电子科技集团公司第四十四研究所 Cmos图像传感器片上时钟产生电路、模块及方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030155953A1 (en) * 2002-02-18 2003-08-21 Matsushita Electric Industrial Co., Ltd. Multi-phase clock transmission circuit and method
CN102223143A (zh) * 2010-04-16 2011-10-19 电信科学技术研究院 时钟信号保护的装置、方法及时钟检测补偿电路
CN103728516A (zh) * 2014-01-09 2014-04-16 福州瑞芯微电子有限公司 Soc芯片时钟检测电路
CN104133409A (zh) * 2014-08-07 2014-11-05 电子科技大学 一种对称性可调的三角波合成装置
CN105629772A (zh) * 2014-10-30 2016-06-01 深圳艾科创新微电子有限公司 一种延时控制装置
CN107797442A (zh) * 2017-11-08 2018-03-13 安凯(广州)微电子技术有限公司 时间数字转换装置及数字锁相环

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030155953A1 (en) * 2002-02-18 2003-08-21 Matsushita Electric Industrial Co., Ltd. Multi-phase clock transmission circuit and method
CN102223143A (zh) * 2010-04-16 2011-10-19 电信科学技术研究院 时钟信号保护的装置、方法及时钟检测补偿电路
CN103728516A (zh) * 2014-01-09 2014-04-16 福州瑞芯微电子有限公司 Soc芯片时钟检测电路
CN104133409A (zh) * 2014-08-07 2014-11-05 电子科技大学 一种对称性可调的三角波合成装置
CN105629772A (zh) * 2014-10-30 2016-06-01 深圳艾科创新微电子有限公司 一种延时控制装置
CN107797442A (zh) * 2017-11-08 2018-03-13 安凯(广州)微电子技术有限公司 时间数字转换装置及数字锁相环

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115334264A (zh) * 2022-08-17 2022-11-11 中国电子科技集团公司第四十四研究所 Cmos图像传感器片上时钟产生电路、模块及方法
CN115334264B (zh) * 2022-08-17 2024-04-09 中国电子科技集团公司第四十四研究所 Cmos图像传感器片上时钟产生电路、模块及方法

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