WO2022064317A1 - 撮像装置および電子機器 - Google Patents

撮像装置および電子機器 Download PDF

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Publication number
WO2022064317A1
WO2022064317A1 PCT/IB2021/058290 IB2021058290W WO2022064317A1 WO 2022064317 A1 WO2022064317 A1 WO 2022064317A1 IB 2021058290 W IB2021058290 W IB 2021058290W WO 2022064317 A1 WO2022064317 A1 WO 2022064317A1
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Prior art keywords
layer
transistor
circuit
wiring
potential
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Ceased
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PCT/IB2021/058290
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English (en)
French (fr)
Japanese (ja)
Inventor
根来雄介
宍戸英明
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to CN202180061807.4A priority Critical patent/CN116075943A/zh
Priority to US18/024,084 priority patent/US12212873B2/en
Priority to KR1020237008317A priority patent/KR20230074476A/ko
Priority to JP2022551445A priority patent/JPWO2022064317A1/ja
Publication of WO2022064317A1 publication Critical patent/WO2022064317A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/79—Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/803—Pixels having integrated switching, control, storage or amplification elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors

Definitions

  • One aspect of the present invention relates to an image pickup apparatus.
  • one aspect of the present invention is not limited to the above technical fields.
  • the technical field of one aspect of the invention disclosed in the present specification and the like relates to a product, a method, or a manufacturing method.
  • one aspect of the invention relates to a process, machine, manufacture, or composition (composition of matter). Therefore, more specifically, the technical fields of one aspect of the present invention disclosed in the present specification include semiconductor devices, display devices, liquid crystal display devices, light emitting devices, lighting devices, power storage devices, storage devices, image pickup devices, and the like.
  • the driving method or the manufacturing method thereof can be given as an example.
  • the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics.
  • Transistors and semiconductor circuits are one aspect of semiconductor devices.
  • the storage device, the display device, the image pickup device, and the electronic device may have a semiconductor device.
  • Patent Document 1 discloses an image pickup apparatus having an oxide semiconductor and using a transistor having an extremely low off-current in a pixel circuit.
  • Imaging devices such as CMOS image sensors can easily take high-quality images due to technological developments. In the next generation, it is required to further enhance the functionality of the image pickup device.
  • the image pickup device is incorporated in various devices, there is also a demand for miniaturization. Therefore, it is desired that the sensor chip be miniaturized even when a function is added. Therefore, it is preferable that the elements for adding functions to the image pickup apparatus are arranged in a stacked manner.
  • one of the objects of the present invention is to provide a high-performance image pickup apparatus.
  • one of the purposes is to provide an image pickup apparatus that can be manufactured in a small number of steps.
  • one of the purposes is to provide an imaging device that can be manufactured with a high yield.
  • one of the purposes is to provide a small image pickup device.
  • one of the purposes is to provide an image pickup device capable of high-speed operation.
  • one of the purposes is to provide a highly reliable image pickup apparatus.
  • one of the purposes is to provide a new image pickup device or the like.
  • one of the purposes is to provide a driving method for the image pickup apparatus.
  • one of the purposes is to provide a new semiconductor device or the like.
  • One aspect of the present invention relates to a high-performance image pickup apparatus that can be manufactured in a small number of steps.
  • One aspect of the present invention is a photoelectric conversion device, a pixel circuit, a memory circuit, a readout circuit, a first insulating layer, a second insulating layer, a first conductive layer, and a second conductive layer.
  • the photoelectric conversion device is electrically connected to the pixel circuit
  • the memory circuit is electrically connected to the read circuit
  • the first insulating layer is provided on the memory circuit.
  • the conductive layer has a region embedded in the first insulating layer, the first conductive layer is electrically connected to the pixel circuit, the second insulating layer is provided on the pixel circuit, and the second The conductive layer has a region embedded in the second insulating layer, the second conductive layer is electrically connected to a readout circuit, and the first conductive layer and the second conductive layer are directly connected to each other.
  • the first insulating layer and the second insulating layer are directly bonded to each other, the memory circuit has as many memory cells as the number of bits output by the read circuit, and the memory cell has a strong dielectric layer. It is an image pickup device having a capacitor.
  • the pixel circuit and the memory circuit have a transistor having a metal oxide in the channel forming region, the readout circuit has a transistor having silicon in the channel forming region, and the photoelectric conversion device has a photo having silicon in the photoelectric conversion layer. It can be a diode.
  • the pixel circuit, memory circuit, and readout circuit may have a transistor having silicon in the channel forming region, and the photoelectric conversion device may be a photodiode having silicon in the photoelectric conversion layer.
  • first conductive layer and the second conductive layer are made of the same metal material, and the first insulating layer and the second insulating layer are made of the same insulating material.
  • the metal oxide can have In, Zn, and M (where M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd or Hf).
  • the ferroelectric layer is preferably a metal oxide containing Hf and Zr.
  • a high-performance imaging device can be provided. It is possible to provide an image pickup device that can be manufactured in a small number of steps. Alternatively, it is possible to provide an imaging device that can be manufactured with a high yield. Alternatively, a small imaging device can be provided. Alternatively, it is possible to provide an image pickup device capable of high-speed operation. Alternatively, a highly reliable image pickup device can be provided. Alternatively, a new image pickup device or the like can be provided. Alternatively, it is possible to provide a method for driving the image pickup device. Alternatively, a new semiconductor device or the like can be provided.
  • FIG. 1 is a cross-sectional perspective view illustrating an image pickup apparatus.
  • 2A to 2C are diagrams illustrating a method for producing a laminated body.
  • 3A and 3B are block diagrams illustrating an image pickup apparatus.
  • FIG. 4 is a cross-sectional perspective view illustrating the image pickup apparatus.
  • 5A to 5C are diagrams illustrating a method for producing a laminated body.
  • 6A and 6B are block diagrams illustrating an image pickup apparatus.
  • 7A and 7B are circuit diagrams illustrating a pixel circuit.
  • FIG. 8A is a diagram illustrating the operation of the rolling shutter.
  • FIG. 8B is a diagram illustrating the operation of the global shutter.
  • 9A and 9B are timing charts illustrating the operation of the pixel circuit.
  • FIG. 10A and 10B are circuit diagrams illustrating a pixel circuit.
  • FIG. 11 is a circuit diagram and a block diagram illustrating a readout circuit.
  • FIG. 12A is a diagram illustrating a storage circuit.
  • 12B to 12D are diagrams illustrating memory cells.
  • FIG. 13A is a diagram illustrating a storage circuit. 13B and 13C are diagrams illustrating memory cells.
  • FIG. 14A is a diagram illustrating the hysteresis characteristic of the ferroelectric layer.
  • FIG. 14B is a timing chart illustrating the operation of the memory cell.
  • 17A to 17D are diagrams illustrating an OS transistor.
  • FIG. 18 is a cross-sectional view illustrating the pixels.
  • FIG. 19 is a cross-sectional view illustrating the pixels.
  • FIG. 20 is a cross-sectional view illustrating the pixels.
  • FIG. 21 is a cross-sectional view illustrating the pixels.
  • 22A to 22C are perspective views (cross-sectional views) illustrating pixels.
  • FIG. 23A is a diagram illustrating a package containing an imaging device.
  • FIG. 23B is a diagram illustrating a module containing an image pickup device.
  • 24A to 24F are diagrams illustrating electronic devices.
  • 25A and 25B are diagrams illustrating a moving body.
  • the element may be composed of a plurality of elements if there is no functional inconvenience.
  • a plurality of transistors operating as switches may be connected in series or in parallel.
  • the capacitor may be divided and arranged at a plurality of positions.
  • one conductor may have a plurality of functions such as wiring, electrodes, and terminals, and in the present specification, a plurality of names may be used for the same element. Further, even if the elements are shown to be directly connected on the circuit diagram, the elements may actually be connected via one or a plurality of conductors. , In the present specification, such a configuration is also included in the category of direct connection.
  • One aspect of the present invention is an image pickup apparatus having a plurality of stacked devices.
  • the image pickup apparatus is formed by laminating a first laminated body in which a plurality of devices are laminated and a second laminated body in which a plurality of devices are laminated. Therefore, even in a configuration in which a plurality of circuits having different functions are laminated, the polishing process and the bonding process can be reduced, and the yield can be improved.
  • a pixel circuit, a pixel drive circuit, and the like can be provided in the first laminate, and a pixel circuit read circuit, a memory circuit, a memory circuit drive circuit, and the like can be provided in the second laminate.
  • a small image pickup device can be formed. Further, by stacking each circuit, wiring delay and the like can be suppressed, and high-speed operation can be performed.
  • FIG. 1 is a cross-sectional perspective view illustrating an image pickup apparatus according to an aspect of the present invention.
  • the image pickup apparatus has a layer 201, a layer 202, a layer 203, a layer 204, and a layer 205.
  • the image pickup apparatus is divided into the above five layers for the sake of clarification of the explanation, but the types, quantities, and positions of the elements included in each layer are limited to the description of the present embodiment. Not done.
  • elements such as insulating layers, wirings and plugs near the boundary between layers may belong to a layer different from the description of this embodiment.
  • each layer may contain elements different from the elements described in the present embodiment.
  • Layer 201 has a region 210.
  • a read circuit of a pixel circuit, a drive circuit of a memory circuit, and the like can be provided in the area 210.
  • Layer 202 has a region 220.
  • a memory circuit or the like can be provided in the area 220, for example.
  • Layer 203 has a region 230.
  • the region 230 may be provided with, for example, a pixel circuit (excluding the photoelectric conversion device 240), a drive circuit for the pixel circuit, and the like.
  • Layer 204 has a photoelectric conversion device 240.
  • a photoelectric conversion device 240 for example, a photodiode or the like can be used.
  • the photoelectric conversion device 240 can also be said to be an element of a pixel circuit.
  • the layer 205 has an optical conversion layer 250.
  • the optical conversion layer 250 for example, a color filter or the like can be used.
  • layer 205 can have a microlens array 255.
  • the image pickup apparatus of one aspect of the present invention includes a photoelectric conversion device 240, a pixel circuit and a pixel circuit drive circuit provided in the area 230, a memory circuit provided in the area 220, and a pixel circuit provided in the area 210. It has a read circuit, a drive circuit for a memory circuit, and the like.
  • the photoelectric conversion device 240 has sensitivity to visible light.
  • a Si photodiode that uses silicon for the photoelectric conversion layer can be used for the photoelectric conversion device 240.
  • OS transistor a transistor in which a metal oxide is used in the channel forming region as a component such as a pixel circuit and a drive circuit of the pixel circuit.
  • the OS transistor has an extremely small off current and can suppress unnecessary outflow of data from the pixel circuit. Therefore, it is possible to perform a global shutter operation in which data is acquired all at once by a plurality of pixel circuits and sequentially read out with a simple circuit configuration. Further, the pixel drive circuit can be formed by a process common to the pixel circuit.
  • an OS transistor for the memory circuit as well.
  • an OS transistor for the cell transistor of the memory circuit
  • unnecessary outflow of data can be suppressed and the frequency of refreshing can be suppressed. Therefore, power consumption can be suppressed.
  • a ferroelectric capacitor may be used for the memory cell included in the memory circuit. Since the data held in the ferroelectric capacitor is non-volatile and does not require a refresh operation, power consumption can be suppressed.
  • a transistor having high mobility Since high-speed operation is required for the read circuit of the pixel circuit and the drive circuit of the memory circuit, it is preferable to use a transistor having high mobility.
  • a transistor using silicon for the channel forming region hereinafter referred to as Si transistor.
  • the Si transistor include a transistor having amorphous silicon, a transistor having crystalline silicon (microcrystalline silicon, low temperature polysilicon, single crystal silicon), and the like.
  • the drive circuit of the pixel circuit may be formed of a Si transistor.
  • a polishing step and a bonding step are required a plurality of times. Therefore, there are problems such as a large number of processes, a need for a dedicated device, a low yield, and a high manufacturing cost.
  • the polishing step and the bonding step can be reduced.
  • the OS transistor can be formed on the Si device via an insulating layer without using complicated processes such as bonding and bump bonding.
  • the layer 201 is a layer including a silicon substrate, and a circuit having a Si transistor is formed in the region 210. Then, as shown in FIG. 2A, the layer 202 is formed on the layer 201. A circuit having an OS transistor is formed in the region 220 of the layer 202.
  • the layer 204 is a layer including a silicon substrate, and a Si photodiode is formed on the layer 204 as a photoelectric conversion device 240. Then, as shown in FIG. 2B, the layer 203 is formed on the layer 204. A circuit having an OS transistor is formed in the region 230 of the layer 203.
  • FIG. 1 shows a configuration in which a layer 205 is further provided on the layer 204 of the laminated body shown in FIG. 2C.
  • a polishing step and a laminating step are required at least three times each, but in one aspect of the present invention, the polishing step is laminating once or twice.
  • the matching process can be performed once.
  • FIG. 3A is a simple block diagram illustrating the electrical connection of the elements of layers 201 to 204. Since the photoelectric conversion device 240 included in the layer 204 is included in the pixel circuit 331 (PIX) on the circuit, the electrical connection is not shown here.
  • PIX pixel circuit 331
  • the pixel circuits 331 are arranged side by side in a matrix and are electrically connected to the drive circuit 332 (Driver) via the wiring 351.
  • the drive circuit 332 can control the data acquisition operation and the selection operation of the pixel circuit 331.
  • a shift register or the like can be used for the drive circuit 332, for example, a shift register or the like can be used.
  • the pixel circuit 331 is electrically connected to the readout circuit 311 (RC) via the wiring 352.
  • the readout circuit 311 has a correlated double sampling circuit (CDS circuit) that reduces noise and an A / D converter that converts analog data into digital data.
  • CDS circuit correlated double sampling circuit
  • the read circuit 311 is electrically connected to the memory circuit 321 (MEM) via the wiring 353.
  • the memory circuit 321 can hold the digital data output from the read circuit 311. Alternatively, digital data can be output to the outside from the read circuit 311.
  • the memory circuit 321 is electrically connected to the low driver 312 (RD) via the wiring 354. Further, the memory circuit 321 is electrically connected to the column driver 313 (CD) via the wiring 355.
  • the low driver 312 is a drive circuit of the memory circuit 321 and can control the writing and reading of data.
  • the column driver 313 is a drive circuit of the memory circuit 321 and can control the reading of data.
  • the details of the connection relationship between the pixel circuit 331, the read circuit 311 and the memory circuit 321 will be described with reference to the block diagram of FIG. 3B.
  • the number of read circuits 311 can be the same as that of the pixel circuits 331, and one read circuit 311 is electrically connected to each pixel circuit 331 via the wiring 352. Further, the read circuit 311 is connected to a plurality of wirings 353, and each of the wirings 353 is electrically connected to one memory cell 321a.
  • a data holding circuit may be provided between the read circuit 311 and the memory circuit 321.
  • the A / D converter included in the readout circuit 311 outputs binary data for a predetermined number of bits in parallel. Therefore, the A / D converter is connected to the memory cells 321a for the number of bits. For example, when the output of the A / D converter is 8 bits, it is connected to eight memory cells 321a.
  • a / D conversion of analog data acquired by all pixel circuits 331 can be performed in parallel, and the converted digital data can be directly transferred to the memory circuit 321.
  • the configuration of the image pickup device provided with the layer 202 and the layer 203 having the OS transistor is shown, but as shown in FIG. 4, the image pickup device has the layer 201, the layer 204 and the layer 205, and the layer 202 and the layer 205 are provided.
  • the configuration may be such that the layer 203 is omitted.
  • the layer 201 and the layer 204 are layers including a silicon substrate, as in the description of FIG. 1.
  • the layer 201 is provided with a region 610 and a region 620.
  • a circuit having a Si transistor is provided in the region 610 and the region 620.
  • the layer 204 is provided with a region 630 and a photoelectric conversion device 240.
  • a circuit having a Si transistor is provided in the region 630.
  • the photoelectric conversion device 240 a Si photodiode can be used.
  • FIG. 5C by laminating the layer 201 and the layer 204 on the surface B, a laminated structure in which the layer 201 and the layer 204 overlap can be produced.
  • FIG. 4 shows a configuration in which a layer 205 is further provided on the layer 204 of the laminated body shown in FIG. 5C.
  • the block diagram of the circuit has the configuration shown in FIGS. 6A and 6B.
  • the configuration of the circuit is the same as that of FIGS. 3A and 3B, and the circuit provided in the region 210 shown in FIG. 3A is provided in the region 610. Further, the circuit provided in the area 220 is provided in the area 620. Further, the circuit provided in the area 230 is provided in the area 630.
  • the circuits provided in the regions 620 and 630 are formed by using Si transistors.
  • FIG. 7A is a circuit diagram illustrating an example of the pixel circuit 331.
  • the pixel circuit 331 can include a photoelectric conversion device 240, a transistor 103, a transistor 104, a transistor 105, a transistor 106, and a capacitor 108. It should be noted that the configuration may be such that the capacitor 108 is not provided. In the present specification, among the above elements, the configuration excluding the photoelectric conversion device 240 may be referred to as a pixel circuit.
  • One electrode (cathode) of the photoelectric conversion device 240 is electrically connected to one of the source and drain of the transistor 103.
  • the other of the source or drain of the transistor 103 is electrically connected to one of the source or drain of the transistor 104.
  • One of the source or drain of the transistor 104 is electrically connected to one of the electrodes of the capacitor 108.
  • One electrode of the capacitor 108 is electrically connected to the gate of the transistor 105.
  • One of the source or drain of the transistor 105 is electrically connected to one of the source or drain of the transistor 106.
  • the wiring connecting the source or drain of the transistor 103, one electrode of the capacitor 108, and the gate of the transistor 105 is referred to as a node FD.
  • the node FD can function as a charge detector.
  • the other electrode (anode) of the photoelectric conversion device 240 is electrically connected to the wiring 121.
  • the gate of the transistor 103 is electrically connected to the wiring 127.
  • the other of the source or drain of the transistor 104 is electrically connected to the wiring 122.
  • the other of the source or drain of the transistor 105 is electrically connected to the wiring 123.
  • the gate of the transistor 104 is electrically connected to the wiring 126.
  • the gate of the transistor 106 is electrically connected to the wiring 128.
  • the other electrode of the capacitor 108 is electrically connected to a reference potential line such as a GND wiring.
  • the other of the source or drain of the transistor 106 is electrically connected to the wiring 352.
  • Wiring 127, 126, 128 can have a function as a signal line for controlling the continuity of each transistor.
  • the wiring 352 can have a function as an output line.
  • Wiring 121, 122, 123 can have a function as a power line.
  • the cathode side of the photoelectric conversion device 240 is electrically connected to the transistor 103, and the node FD is reset to a high potential for operation. Therefore, the wiring 122 has a high potential (from the wiring 121). Is also a high potential).
  • FIG. 7A shows a configuration in which the cathode of the photoelectric conversion device 240 is electrically connected to the node FD, but as shown in FIG. 7B, the anode side of the photoelectric conversion device 240 is electrically connected to either the source or the drain of the transistor 103. It may be configured to connect.
  • the wiring 122 since the node FD is reset to a low potential for operation, the wiring 122 has a low potential (potential lower than that of the wiring 121).
  • the transistor 103 has a function of controlling the potential of the node FD.
  • the transistor 104 has a function of resetting the potential of the node FD.
  • the transistor 105 functions as an element of the source follower circuit, and the potential of the node FD can be output to the wiring 352 as image data.
  • the transistor 106 has a function of selecting a pixel for outputting image data.
  • the OS transistor has a characteristic that the off current is extremely low.
  • the period during which the charge can be held in the node FD can be extremely lengthened. Therefore, it is possible to apply the global shutter method in which charge storage operation is performed simultaneously in all pixels without complicating the circuit configuration and operation method.
  • FIG. 8A is a diagram schematically showing the operation method of the rolling shutter system
  • FIG. 8B is a diagram schematically showing the global shutter system.
  • En represents the exposure (accumulation operation) of the nth column (n is a natural number) of the pixel
  • Rn represents the reading operation of the nth column of the pixel.
  • 8A and 8B show the operation from the first row (Line [1]) to the Mth row ((Line [M]), M is a natural number) of the pixel.
  • the rolling shutter method is an operation method in which exposure and data reading are sequentially performed, and is a method in which the reading period of a certain row and the exposure period of another row are overlapped. Since the readout operation is performed immediately after exposure, imaging can be performed even with a circuit configuration having a relatively short data retention period. However, since one frame of the image is composed of data that are not simultaneously imaged, the image is distorted when the moving object is imaged.
  • the global shutter method is an operation method in which all pixels are exposed at the same time, data is held in each pixel, and data is read out row by row. Therefore, it is possible to obtain a distortion-free image even when imaging a moving object.
  • the rolling shutter method is often used because the charge tends to flow out from the charge detection unit.
  • a transistor having a relatively high off-current such as a Si transistor
  • the global shutter method can be easily realized because there is almost no outflow of charge from the charge detection unit.
  • the image pickup apparatus of one aspect of the present invention can also be operated by the rolling shutter method.
  • the pixel circuit 331 may have a configuration in which an OS transistor and a Si transistor are arbitrarily combined. Alternatively, all the transistors may be Si transistors.
  • the transistor 104 becomes non-conducting and the supply of the reset potential is cut off. Further, the potential of the node FD decreases according to the operation of the photoelectric conversion device 240 (accumulation operation).
  • the transistor 103 becomes non-conducting, the potential of the node FD is fixed and held. (Holding operation). At this time, by using an OS transistor having a low off-current for the transistor 103 and the transistor 104 connected to the node FD, it is possible to suppress the outflow of unnecessary charges from the node FD and extend the data retention time. can.
  • the transistor 106 conducts and the potential of the node FD is operated by the source follower operation of the transistor 105. Is read out to the wiring 352 (reading operation).
  • the pixel circuit 331 shown in FIG. 7B can be operated according to the timing chart of FIG. 9B. It is assumed that "H” is always supplied to the wirings 121 and 123, and “L” is always supplied to the wirings 122. The basic operation is the same as the description of the timing chart of FIG. 9A above.
  • the transistor may be provided with a back gate.
  • FIG. 10A shows a configuration in which the back gate is electrically connected to the front gate, and has the effect of increasing the on-current.
  • FIG. 10B shows a configuration in which the back gate is electrically connected to a wiring capable of supplying a constant potential, and the threshold voltage of the transistor can be controlled.
  • the transistor configurations shown in FIGS. 10A and 10B may be combined so that each transistor can perform an appropriate operation.
  • the pixel circuit 331 may have a transistor without a back gate.
  • FIG. 11 is a diagram illustrating an example of a readout circuit 311 connected to the pixel circuit 331, and shows a circuit diagram of the CDS circuit 400 and a block diagram of the A / D converter 410 electrically connected to the CDS circuit 400. ing.
  • the CDS circuit and A / D converter shown in FIG. 11 are examples, and may have other configurations.
  • the CDS circuit 400 includes a resistance 401 for voltage conversion, a capacitor 402 for capacitive coupling, a transistor 403 for supplying a potential V 0 , a transistor 404 for holding a potential to be supplied to an A / D converter 410, and a capacitor 405 for holding the potential. It can be configured to have.
  • the input is electrically connected to the pixel circuit 331 and the output is electrically connected to the comparator circuit (COMP) of the A / D converter 410.
  • COMP comparator circuit
  • the potential of the wiring 352 is V res (the pixel circuit 331 is in the reset state)
  • the potential of the node N (the connection point of the transistors 403 and 404 and the capacitor 402) is set to V 0 .
  • the potential of the wiring 352 becomes V data (the pixel circuit 331 outputs the image data) with the node N floating
  • the potential of the node N becomes V 0 + V data ⁇ V res . Therefore, in the CDS circuit 400, the potential in the reset state can be subtracted from the potential of the imaging data output by the pixel circuit 331, and the noise component can be reduced.
  • the analog-to-digital converter 410 can be configured to include a comparator circuit (COMP) and a counter circuit (COUNTER).
  • COMP comparator circuit
  • COUNTER counter circuit
  • the signal potential input from the CDS circuit 400 to the comparator circuit (COMP) and the sweeped reference potential (RAMP) are compared.
  • the counter circuit (COUNTER) operates according to the output of the comparator circuit (COMP), and the digital signal is output to the plurality of wirings 353.
  • FIG. 12A is a diagram showing the connection relationship between the memory cell 321a, the low driver 312, and the column driver 313 included in the memory circuit 321.
  • the plurality of memory cells 321a are provided in the area 220 or the area 620 as the memory circuit 321.
  • the low driver 312 and the column driver 313 are drive circuits of the memory cell 321a and can be provided in the area 210 or the area 610.
  • a sense amplifier or the like may be used for reading the data.
  • the memory circuit 321 has m (m is an integer of 1 or more) in one column, n (n is an integer of 1 or more) in one row, and a total of m ⁇ n memory cells 321a, and the memory cells 321a have a matrix shape. Is located in.
  • 12B to 12D are diagrams illustrating memory cells 321b to memory cells 321d that can be applied to memory cells 321a.
  • the bit wires can be connected to the column driver 313.
  • the word wire can be connected to the low driver 312.
  • a decoder or a shift register can be used for the low driver 312 and the column driver 313, for example.
  • a plurality of low drivers 312 and column drivers 313 may be provided.
  • FIG. 12B shows a circuit configuration example of the DRAM type memory cell 321b.
  • the memory cell 321b has a transistor 271 and a capacitor 274.
  • One of the source or drain of the transistor 271 is connected to one electrode of the capacitor 274, the other of the source or drain of the transistor 271 is connected to the wiring BIL, the gate of the transistor 271 is connected to the wiring WL, and the transistor 271 The back gate of is connected to the wiring BGL.
  • the other electrode of the capacitor 274 is connected to the wiring GNDL.
  • the wiring GNDL is a wiring that gives a low level potential (reference potential).
  • the wiring BIL functions as a bit line.
  • the wiring WL functions as a word line.
  • the wiring BGL functions as wiring for applying a potential to the back gate of the transistor 271.
  • the threshold voltage of the transistor 271 can be increased or decreased by applying an appropriate potential to the wiring BGL.
  • the wiring BGL may be electrically connected to the wiring WL. By applying the same potential as the wiring WL to the wiring BGL, the current characteristics of the transistor 271 can be enhanced.
  • Data writing and reading is performed by applying a high level potential to the wiring WL, making the transistor 271 conductive, and electrically connecting one electrode of the wiring BIL and the capacitor 274.
  • a sense amplifier is electrically connected to the wiring BIL, and the potential of the wiring BIL can be amplified and read by the sense amplifier.
  • An OS transistor or a Si transistor can be used as the transistor 271.
  • a DRAM using an OS transistor is referred to as a DOSRAM (Dynamic Oxide Semiconductor Memory Random Access Memory).
  • An OS transistor to which an oxide semiconductor containing indium, gallium, and zinc is applied has a characteristic that the off-current is extremely small.
  • the leakage current of the transistor 271 can be made very low. That is, since the written data can be held for a long time by the transistor 271, the frequency of refreshing the memory cell can be reduced. Alternatively, the memory cell refresh operation can be eliminated.
  • FIG. 12C shows a circuit configuration example of a gain cell type (also referred to as “2Tr1C type”) memory cell 321c having two transistors and one capacitor.
  • the memory cell 321c has a transistor 273, a transistor 272, and a capacitor 275.
  • One of the source or drain of the transistor 273 is connected to one electrode of the capacitor 275, the other of the source or drain of the transistor 273 is connected to the wiring WBL, the gate of the transistor 273 is connected to the wiring WL, and the transistor 273.
  • the back gate of is connected to the wiring BGL.
  • the other electrode of the capacitor 275 is connected to the wiring RL.
  • One of the source or drain of the transistor 272 is connected to the wiring RBL, the other of the source or drain of the transistor 272 is connected to the wiring SL, and the gate of the transistor 272 is connected to one electrode of the capacitor 275.
  • the wiring WBL functions as a write bit line.
  • the wiring RBL functions as a read bit line.
  • the wiring WL functions as a word line.
  • the wiring RL functions as wiring for applying a predetermined potential to the other electrode of the capacitor 275. It is preferable to apply a reference potential to the wiring RL during data writing and data retention.
  • the wiring BGL functions as wiring for applying a potential to the back gate of the transistor 273.
  • the threshold voltage of the transistor 273 can be increased or decreased by applying an appropriate potential to the wiring BGL.
  • the wiring BGL may be electrically connected to the wiring WL. By applying the same potential as the wiring WL to the wiring BGL, the current characteristics of the transistor 273 can be enhanced.
  • Data writing is performed by applying a high level potential to the wiring WL, making the transistor 273 conductive, and electrically connecting one electrode of the wiring WBL and the capacitor 275. Specifically, when the transistor 273 is in a conductive state, a potential corresponding to the information recorded in the wiring WBL is applied, and the potential is written to one electrode of the capacitor 275 and the gate of the transistor 272. After that, a low level potential is applied to the wiring WL to make the transistor 273 non-conducting, thereby holding the potential of one electrode of the capacitor 275 and the potential of the gate of the transistor 272.
  • Data is read out by applying a predetermined potential to the wiring RL and the wiring SL.
  • the source of transistor 272 and the potential of one of the source or drain of transistor 273 are determined by the potential of the gate of transistor 272 and the potential of the other of the source or drain of transistor 273, so that the current flowing between the source and drain of transistor 272 and the potential of one of the source or drain of transistor 273 are the source of transistor 272.
  • the potential held by one electrode of the capacitor 275 (or the gate of the transistor 272) can be read out. That is, the information written in this memory cell can be read out from the potential held in one of the electrodes of the capacitor 275 (or the gate of the transistor 272).
  • the wiring WBL and the wiring RBL may be combined into one wiring BIL.
  • the wiring WBL and the wiring RBL of the memory cell 321c are used as one wiring BIL, and the other of the source or drain of the transistor 273 and one of the source or drain of the transistor 272 are connected to the wiring BIL. It has become a configuration. That is, the memory cell 321d has a configuration in which the write bit line and the read bit line operate as one wiring BIL.
  • an OS transistor for the transistor 273 A storage device using an OS transistor for the transistor 273 and using a 2Tr1C type memory cell such as a memory cell 321c and a memory cell 321d is called a NOSRAM (Non-volatile Oxide Semiconductor Random Access Memory).
  • NOSRAM Non-volatile Oxide Semiconductor Random Access Memory
  • the memory circuit 321 may have the configuration shown in FIG. 13A.
  • the memory circuit 321 having the configuration shown in FIG. 13A the memory cell 321e shown in FIG. 13B can be used.
  • the memory cell 321e has a transistor 276 and a capacitor 277.
  • One of the source or drain of the transistor 276 is connected to one electrode of the capacitor 277, the other of the source or drain of the transistor 276 is connected to the wiring BIL, and the gate of the transistor 276 is connected to the wiring WL. Further, the other electrode of the capacitor 277 is connected to the wiring PL.
  • the wiring BIL functions as a bit line.
  • the wiring WL functions as a word line.
  • the wiring PL is wiring that gives the capacitor 277 a plate potential required for writing data or reading data.
  • the circuit 314 shown in FIG. 13A is a circuit for supplying a plate potential, and can be provided in the region 210 or the region 610 in the same manner as the low driver 312 and the column driver 313. Further, a sense amplifier may be electrically connected to the wiring BIL. With the sense amplifier, the potential of the wiring BIL can be amplified and read out.
  • an OS transistor, a Si transistor, or the like can be used as the transistor 276, an OS transistor, a Si transistor, or the like.
  • an OS transistor is used for the transistor 276, it is preferable to provide a back gate that is electrically connected to the wiring BGL as shown in FIG. 13C.
  • the threshold voltage of the transistor 271 can be increased or decreased by applying an appropriate potential to the wiring BGL.
  • the wiring BGL may be electrically connected to the wiring WL. By applying the same potential as the wiring WL to the wiring BGL, the current characteristics of the transistor 271 can be enhanced.
  • the OS transistor has a characteristic of having a high withstand voltage. Therefore, by using the OS transistor for the transistor 276, a high voltage can be applied to the transistor 276 even if the transistor 276 is miniaturized. By miniaturizing the transistor 276, the occupied area of the memory cell 321e can be reduced.
  • Capacitor 277 has a material between the two electrodes that can have ferroelectricity as a dielectric layer.
  • the dielectric layer of the capacitor 277 is referred to as a ferroelectric layer.
  • a capacitor having a ferroelectric layer can be called a ferroelectric capacitor.
  • a configuration in which a switch such as a transistor and a ferroelectric capacitor are combined can be referred to as a ferroelectric memory.
  • Materials that can have strong dielectric properties include hafnium oxide, zirconium oxide, HfZrOX ( X is a real number larger than 0), hafnium oxide and element J1 (here, element J1 is zirconium (Zr), silicon. (Si), aluminum (Al), gadrinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) added to the material, zirconium oxide with element J2 (element J2 here is Examples thereof include materials to which hafnium (Hf), silicon (Si), aluminum (Al), gadrinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) are added.
  • PT lead titanate
  • BST barium titanate strontium
  • PZT lead zirconate titanate
  • SBT strontium bismuthate tantanate
  • a piezoelectric ceramic having a perovskite structure such as ferrite (BFO) or barium titanate
  • the material capable of having ferroelectricity for example, a mixture or a compound containing a plurality of materials selected from the materials listed above can be used.
  • the ferroelectric layer may have a laminated structure composed of a plurality of materials selected from the materials listed above.
  • hafnium oxide or a material having hafnium oxide and zirconium oxide as a material capable of having ferroelectricity, can have ferroelectricity even when processed into a thin film of several nm. Since the ferroelectric layer can be made thin, the consistency with the transistor miniaturization process can be improved.
  • HfZrOX When used as a material capable of having ferroelectricity, it is preferable to form a film by using an atomic layer deposition (ALD) method, particularly a thermal ALD method. Further, when a material capable of having ferroelectricity is formed by using the thermal ALD method, it is preferable to use a material containing no hydrocarbon (also referred to as Hydro Carbon, HC) as a precursor. When one or both of hydrogen and carbon are contained in the material which may have a ferroelectricity, the crystallization of the material which may have a ferroelectricity may be hindered.
  • ALD atomic layer deposition
  • HC Hydro Carbon
  • a precursor containing no hydrocarbon a chlorine-based material can be mentioned.
  • HfZrO x hafnium oxide and zirconium oxide
  • HfCl 4 and / or ZrCl 4 may be used as the precursor.
  • high-purity intrinsicity is achieved by thoroughly eliminating at least one of impurities, here hydrogen, hydrocarbon, and carbon in the film. It is possible to form a film having a strong ferroelectricity. It should be noted that the film having high-purity intrinsic ferroelectricity and the high-purity intrinsic oxide semiconductor shown in the embodiment described later have very high consistency in the manufacturing process. Therefore, it is possible to provide a method for manufacturing a semiconductor device having high productivity.
  • HfZrOX is used as a material capable of having ferroelectricity
  • the oxidizing agent of the thermal ALD method is not limited to this.
  • the oxidizing agent in the thermal ALD method may contain one or more selected from O 2 , O 3 , N 2 O, NO 2 , H 2 O, and H 2 O 2 .
  • the crystal structure of the material capable of having ferroelectricity is not particularly limited.
  • the crystal structure of the material that may have strong dielectric property may be one or more selected from cubic, tetragonal, orthorhombic, and monoclinic.
  • a material capable of having ferroelectricity it is preferable to have an orthorhombic crystal structure because ferroelectricity is exhibited.
  • a composite structure having an amorphous structure and a crystal structure may be used as a material capable of having ferroelectricity.
  • FIG. 14A is a graph showing an example of the hysteresis characteristics of the ferroelectric layer.
  • the horizontal axis shows the voltage applied to the ferroelectric layer.
  • the voltage can be, for example, the difference between the potential of one electrode of the capacitor 277 and the potential of the other electrode of the capacitor 277.
  • the vertical axis indicates the amount of polarization of the ferroelectric layer.
  • the hysteresis characteristics of the ferroelectric layer can be represented by curves 71 and 72.
  • VSP and ⁇ VSP can be referred to as saturated polarization voltages.
  • VSP may be referred to as a first saturated polarization voltage
  • ⁇ VSP may be referred to as a second saturation polarization voltage.
  • the absolute value of the first saturated polarization voltage and the absolute value of the second saturated polarization voltage are equal to each other, but they may be different.
  • the voltage (countervoltage) at which the polarization amount of the ferroelectric layer becomes 0 when the polarization amount of the ferroelectric layer changes according to the curve 71 is defined as Vc.
  • the voltage (countervoltage) at which the polarization amount of the ferroelectric layer becomes 0 is defined as ⁇ Vc.
  • the value of Vc and the value of -Vc are values between -VSP and VSS.
  • Vc may be referred to as a first coercive voltage
  • ⁇ Vc may be referred to as a second coercive voltage.
  • FIG. 14A shows an example in which the absolute value of the first coercive voltage and the absolute value of the second coercive voltage are equal, they may be different.
  • the voltage applied to the ferroelectric layer of the capacitor 277 can be expressed by the difference between the potential of one electrode of the capacitor 277 and the potential of the other electrode of the capacitor 277.
  • the other electrode of the capacitor 277 is electrically connected to the wiring PL. Therefore, by controlling the potential of the wiring PL, the voltage applied to the ferroelectric layer of the capacitor 277 can be controlled.
  • the voltage applied to the ferroelectric layer of the capacitor 277 is the difference between the potential of one electrode of the capacitor 277 and the potential of the other electrode (wiring PL) of the capacitor 277.
  • the transistor 276 is an n-channel type transistor.
  • FIG. 14B is a timing chart showing an example of the driving method of the memory cell 321e shown in FIG. 13B.
  • FIG. 14B shows an example of writing and reading binary digital data to the memory cell 321e.
  • a sense amplifier is electrically connected to the wiring BIL, and Vref is supplied to the sense amplifier as a reference potential. For example, when the potential of the wiring BIL is higher than Vref, the data “1” can be read out. Further, when the potential of the wiring BIL is lower than Vref, the data "0" can be read out.
  • the transistor 276 When the potential of the wiring WL is set to the high potential H at the time T01 to the time T02, the transistor 276 is turned on. Further, the potential of the wiring BIL is Vw. Since the transistor 276 is in the ON state, the potential of one electrode of the capacitor 277 is Vw. Further, the potential of the wiring PL is set to GND. By this operation, the voltage applied to the ferroelectric layer of the capacitor 277 becomes "Vw-GND". Therefore, the data “1” can be written to the memory cell 321e.
  • Vw is preferably VSP or higher, and can be equal to, for example, VSP.
  • the GND can be, for example, a ground potential or 0V, but may be another potential.
  • the voltage applied to the ferroelectric layer of the capacitor 277 becomes 0V.
  • the voltage "Vw-GND" applied to the ferroelectric layer of the capacitor 277 is VSP or higher at time T01 to time T02
  • the amount of polarization of the ferroelectric layer of the capacitor 277 is set at time T02 to time T03. It changes to the position of 0V according to the curve 72 shown in FIG. 14A. Therefore, the direction of polarization is maintained in the ferroelectric layer of the capacitor 277.
  • the transistor 276 When the potential of the wiring WL is set to the high potential H at the time T03 to the time T04, the transistor 276 is turned on. Further, the potential of the wiring PL is Vw. By setting the potential of the wiring PL to Vw, the voltage applied to the ferroelectric layer of the capacitor 277 becomes “GND-Vw”.
  • the voltage applied to the ferroelectric layer of the capacitor 277 is inverted from "Vw-GND” to "GND-Vw", so that the polarization inversion occurs in the ferroelectric layer of the capacitor 277. Since a current flows through the wiring BIL during the polarization reversal, the potential of the wiring BIL is higher than Vref. Therefore, the data “1” held in the memory cell 321e can be read out by the operation of the sense amplifier. Although the case where Vref is higher than GND and lower than Vw is illustrated, it may be higher than Vw, for example.
  • the read operation is a destructive read that reverses the direction of polarization, the data "1" held in the memory cell 321e is lost. Therefore, at time T04 to time T05, the potential of the wiring BIL is set to Vw, the potential of the wiring PL is set to GND, and the data "1" is rewritten to the memory cell 321e.
  • the potential of the wiring BIL and the potential of the wiring PL are set to GND.
  • the potential of the wiring WL is set to the low potential L.
  • the rewrite operation is completed, and the data "1" is held in the memory cell 321e.
  • the potential of the wiring WL is set to the high potential H, and the potential of the wiring PL is set to Vw. Since the data "1" is held in the memory cell 321e, the potential of the wiring BIL becomes higher than Vref, and the data "1" held in the memory cell 321e is read out.
  • the potential of the wiring BIL is set to GND. Since the transistor 276 is in the ON state, the potential of one electrode of the capacitor 277 is GND. Further, the potential of the wiring PL is Vw. From the above, the voltage applied to the ferroelectric layer of the capacitor 277 is "GND-Vw". Therefore, the data “0” can be written to the memory cell 321e.
  • the voltage applied to the ferroelectric layer of the capacitor 277 becomes 0V.
  • the voltage "GND-Vw" applied to the ferroelectric layer of the capacitor 277 at time T12 to time T13 is -VSP or less
  • the amount of polarization of the ferroelectric layer of the capacitor 277 at time T13 to time T14 is shown in the figure. It changes to the position of 0V according to the curve 71 shown in 14A. Therefore, the direction of polarization is maintained in the ferroelectric layer of the capacitor 277.
  • the transistor 276 When the potential of the wiring WL is set to the high potential H at the time T14 to the time T15, the transistor 276 is turned on. Further, the potential of the wiring PL is Vw. By setting the potential of the wiring PL to Vw, the voltage applied to the ferroelectric layer of the capacitor 277 becomes “GND-Vw”.
  • the polarization inversion does not occur in the ferroelectric layer of the capacitor 277. Therefore, the amount of current flowing through the wiring BIL is smaller than when the polarization inversion occurs in the ferroelectric layer of the capacitor 277. Therefore, the increase width of the potential of the wiring BIL is also small. Specifically, the potential of the wiring BIL becomes Vref or less, and the data “0” held in the memory cell 321e can be read out by the operation of the sense amplifier.
  • the potential of the wiring BIL is GND, and the potential of the wiring PL is Vw.
  • the data "0" is rewritten to the memory cell 321e.
  • the potential of the wiring BIL and the potential of the wiring PL are defined as GND.
  • the potential of the wiring WL is set to the low potential L.
  • the rewrite operation is completed, and the data "0" is held in the memory cell 321e.
  • the potential of the wiring WL is set to the high potential H, and the potential of the wiring PL is set to Vw. Since the data "0" is held in the memory cell 321e, the potential of the wiring BIL becomes lower than Vref, and the data "0" held in the memory cell 321e is read out.
  • the potential of the wiring BIL is Vw. Since the transistor 276 is in the ON state, the potential of one electrode of the capacitor 277 is Vw. Further, the potential of the wiring PL is set to GND. As a result, the voltage applied to the ferroelectric layer of the capacitor 277 becomes "Vw-GND". Therefore, the data “1” can be written to the memory cell 321e.
  • the potential of the wiring BIL and the potential of the wiring PL are set to GND.
  • the potential of the wiring WL is set to the low potential L.
  • the writing operation is completed, and the data "1" is held in the memory cell 321e.
  • FIG. 15 is an example of a cross-sectional view of a laminated body having layers 201 to 205 and having a bonded surface between layers 202 and 203.
  • FIG. 15 corresponds to the laminate shown in FIG.
  • the layer 201 has a read circuit 311 provided on the silicon substrate 211, a low driver 312, and a column driver 313.
  • the capacitor 402 and the transistor 403 included in the CDS circuit of the readout circuit 311, the transistor 115 included in the A / D converter of the readout circuit 311 and the transistor 116 included in the low driver 312 are shown.
  • One electrode of the capacitor 402 and one of the source or drain of the transistor 403 are electrically connected.
  • the layer 201 is provided with insulating layers 212, 213, 214, 215, 216, 217, and 218.
  • the insulating layer 212 has a function as a protective film.
  • the insulating layers 213, 214, 215, and 217 have a function as an interlayer insulating film and a flattening film.
  • the insulating layer 216 has a function as a dielectric layer of the capacitor 402.
  • the insulating layer 218 has a function as a blocking film.
  • a silicon nitride film, a silicon oxide film, an aluminum oxide film, or the like can be used as the protective film.
  • an inorganic insulating film such as a silicon oxide film or an organic insulating film such as an acrylic resin or a polyimide resin can be used.
  • a silicon nitride film, a silicon oxide film, an aluminum oxide film, or the like can be used as the blocking film.
  • the blocking film it is preferable to use a film having a function of preventing the diffusion of hydrogen.
  • the blocking film for example, aluminum oxide, aluminum nitride, gallium oxide, gallium oxide, yttrium oxide, yttrium oxide, hafnium oxide, hafnium oxide, yttria-stabilized zirconia (YSZ) and the like can be used.
  • aluminum oxide, aluminum nitride, gallium oxide, gallium oxide, yttrium oxide, yttrium oxide, hafnium oxide, hafnium oxide, yttria-stabilized zirconia (YSZ) and the like can be used.
  • the Si transistor shown in FIG. 15 is a fin type having a channel forming region on the silicon substrate 211, and a cross section in the channel width direction (cross section of A1-A2 shown in FIG. 15) is shown in FIG. 16A.
  • the Si transistor may be a planar type as shown in FIG. 16B.
  • the transistor may have a semiconductor layer 545 of a silicon thin film.
  • the semiconductor layer 545 can be, for example, single crystal silicon (SOI (Silicon on Insulator)) formed on the insulating layer 546 on the silicon substrate 211.
  • SOI Silicon on Insulator
  • Conductors that can be used as wiring, electrodes, and plugs for electrical connections between devices include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, and hafnium. , Vanadium, Niob, Manganese, Magnesium, Zirconium, Berylium, Indium, Luthenium, Iridium, Strontium, Lantern, etc., or alloys containing the above-mentioned metal elements as components, or alloys containing the above-mentioned metal elements. Etc. may be appropriately selected and used.
  • the conductor is not limited to a single layer, and may be a plurality of layers made of different materials.
  • the layer 202 is formed on the layer 201.
  • the layer 202 has a memory circuit 321 having an OS transistor.
  • the transistor 276 and the capacitor 277 included in the memory cell 321e shown in FIGS. 13B and 13C are shown as a part of the memory circuit 321.
  • the capacitor 277 is a ferroelectric capacitor having a ferroelectric layer 226.
  • the memory cell 321e may be replaced with the memory cell 321b shown in FIG. 12B, the memory cell 321c shown in FIG. 12C, or the memory cell 321d shown in FIG. 12D.
  • the layer 202 is provided with insulating layers 221, 222, 223, 224, 225, 227, 228, and 229. Further, the conductive layer 131 is provided.
  • the insulating layers 221 and 224, 225, 227, and 228 have functions as an interlayer insulating film and a flattening film.
  • the insulating layer 222 has a function as a gate insulating film.
  • the insulating layer 223 has a function as a protective film.
  • the insulating layer 229 and the conductive layer 131 have a function as a bonded layer.
  • the gate insulating film a silicon oxide film or the like can be used.
  • the bonding layer will be described later.
  • the conductive layer 131 is electrically connected to the other electrode of the capacitor 402 of the layer 201.
  • One of the source or drain of transistor 276 is electrically connected to one of the source or drain of transistor 115 of layer 201.
  • the gate of transistor 276 is electrically connected to either the source or drain of transistor 116 in layer 201.
  • the other of the source or drain of the transistor 276 is electrically connected to one of the electrodes of the capacitor 277.
  • FIG. 17A shows the details of the OS transistor.
  • the OS transistor shown in FIG. 17A is a self-aligned type in which an insulating layer is provided on a laminate of an oxide semiconductor layer and a conductive layer, and an opening reaching the oxide semiconductor layer is provided to form a source electrode 705 and a drain electrode 706. It is the composition of.
  • the OS transistor may have a channel forming region, a source region 703, and a drain region 704 formed in the oxide semiconductor layer, as well as a gate electrode 701 and a gate insulating film 702. At least the gate insulating film 702 and the gate electrode 701 are provided in the opening.
  • the groove may be further provided with an oxide semiconductor layer 707.
  • the OS transistor may have a self-aligned configuration in which the source region 703 and the drain region 704 are formed in the semiconductor layer using the gate electrode 701 as a mask.
  • FIG. 17C it may be a non-self-aligned top gate type transistor having a region where the source electrode 705 or the drain electrode 706 and the gate electrode 701 overlap.
  • the OS transistor shows a structure having a back gate 535, it may have a structure without a back gate.
  • the back gate 535 may be electrically connected to the front gate of the transistor provided opposite to each other as shown in the cross-sectional view in the channel width direction of the transistor shown in FIG. 17D.
  • FIG. 17D shows the cross section of B1-B2 shown in FIG. 17A as an example, the same applies to transistors having other structures.
  • the back gate 535 may be configured to be able to supply a fixed potential different from that of the front gate.
  • a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used.
  • a typical example is an oxide semiconductor containing indium, and for example, CAAC-OS or CAC-OS, which will be described later, can be used.
  • CAAC-OS is suitable for transistors and the like in which the atoms constituting the crystal are stable and reliability is important. Further, since the CAC-OS exhibits high mobility characteristics, it is suitable for a transistor or the like that is driven at high speed.
  • the OS transistor Since the OS transistor has a large energy gap in the semiconductor layer, it exhibits an extremely low off-current characteristic of several yA / ⁇ m (current value per 1 ⁇ m of channel width). Further, the OS transistor has features different from those of the Si transistor such as impact ionization, avalanche breakdown, and short channel effect, and can form a circuit having high withstand voltage and high reliability. In addition, variations in electrical characteristics due to crystallinity non-uniformity, which is a problem with Si transistors, are unlikely to occur with OS transistors.
  • the semiconductor layer of the OS transistor is In-M containing, for example, indium, zinc and M (one or more of metals such as aluminum, titanium, gallium, germanium, ittrium, zirconium, lanthanum, cerium, tin, neodymium or hafnium). It can be a film represented by ⁇ Zn-based oxide.
  • the In-M-Zn-based oxide can be typically formed by a sputtering method. Alternatively, it may be formed by using an ALD (Atomic layer deposition) method.
  • the atomic number ratio of the metal element of the sputtering target used for forming the In—M—Zn-based oxide by the sputtering method preferably satisfies In ⁇ M and Zn ⁇ M.
  • the atomic number ratio of the semiconductor layer to be formed includes a variation of plus or minus 40% of the atomic number ratio of the metal element contained in the sputtering target.
  • the semiconductor layer an oxide semiconductor having a low carrier density is used.
  • the semiconductor layer has a carrier density of 1 ⁇ 10 17 / cm 3 or less, preferably 1 ⁇ 10 15 / cm 3 or less, more preferably 1 ⁇ 10 13 / cm 3 or less, and more preferably 1 ⁇ 10 11 / cm.
  • Oxide semiconductors of 3 or less, more preferably less than 1 ⁇ 10 10 / cm 3 and 1 ⁇ 10 -9 / cm 3 or more can be used.
  • Such oxide semiconductors are referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. It can be said that the oxide semiconductor is an oxide semiconductor having a low defect level density and stable characteristics.
  • a transistor having an appropriate composition may be used according to the required semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the transistor. Further, in order to obtain the required semiconductor characteristics of the transistor, it is preferable that the carrier density and impurity concentration of the semiconductor layer, the defect density, the atomic number ratio between the metal element and oxygen, the interatomic distance, the density and the like are appropriate. ..
  • the concentration of silicon or carbon in the semiconductor layer is 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less.
  • the concentration of the alkali metal or alkaline earth metal in the semiconductor layer is 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less.
  • the nitrogen concentration in the semiconductor layer is preferably 5 ⁇ 10 18 atoms / cm 3 or less.
  • the oxide semiconductor constituting the semiconductor layer when the oxide semiconductor constituting the semiconductor layer contains hydrogen, it reacts with oxygen bonded to a metal atom to become water, which may form an oxygen deficiency in the oxide semiconductor. If the channel formation region in the oxide semiconductor contains oxygen deficiency, the transistor may have normally-on characteristics. In addition, a defect containing hydrogen in an oxygen deficiency may function as a donor and generate electrons as carriers. In addition, a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have normally-on characteristics.
  • Defects containing hydrogen in oxygen deficiencies can function as donors for oxide semiconductors. However, it is difficult to quantitatively evaluate the defect. Therefore, in oxide semiconductors, the carrier concentration may be used for evaluation instead of the donor concentration. Therefore, in the present specification and the like, as a parameter of the oxide semiconductor, a carrier concentration assuming a state in which an electric field is not applied may be used instead of the donor concentration. That is, the "carrier concentration" described in the present specification and the like may be paraphrased as a "donor concentration".
  • the hydrogen concentration obtained by secondary ion mass spectrometry is less than 1 ⁇ 10 20 atoms / cm 3 , preferably 1 ⁇ 10 19 atoms / cm. It is less than 3 , more preferably less than 5 ⁇ 10 18 atoms / cm 3 , and even more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • the semiconductor layer may have, for example, a non-single crystal structure.
  • the non-single crystal structure includes, for example, a CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) having crystals oriented on the c-axis, a polycrystalline structure, a microcrystalline structure, or an amorphous structure.
  • CAAC-OS C-Axis Aligned Crystalline Oxide Semiconductor
  • the amorphous structure has the highest defect level density
  • CAAC-OS has the lowest defect level density.
  • the oxide semiconductor film having an amorphous structure has, for example, a disordered atomic arrangement and has no crystal component.
  • the oxide semiconductor film having an amorphous structure has, for example, a completely amorphous structure and does not have a crystal portion.
  • the semiconductor layer is a mixed film having two or more of an amorphous structure region, a microcrystal structure region, a polycrystal structure region, a CAAC-OS region, and a single crystal structure region.
  • the mixed film may have, for example, a single-layer structure or a laminated structure including any two or more of the above-mentioned regions.
  • CAC Cloud-Aligned Complex
  • the CAC-OS is, for example, a composition of a material in which the elements constituting the oxide semiconductor are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof.
  • the oxide semiconductor one or more metal elements are unevenly distributed, and the region having the metal elements is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or a size in the vicinity thereof.
  • the state of being mixed in is also called a mosaic shape or a patch shape.
  • the oxide semiconductor preferably contains at least indium. In particular, it preferably contains indium and zinc. Also, in addition to them, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lantern, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc. One or more selected from the above may be included.
  • CAC-OS in In-Ga-Zn oxide is an indium oxide (hereinafter, InO).
  • InO indium oxide
  • X1 X1 is a real number larger than 0
  • In X2 Zn Y2 O Z2 X2, Y2, and Z2 are real numbers larger than 0
  • gallium With an oxide (hereinafter, GaO X3 (X3 is a real number larger than 0)) or gallium zinc oxide (hereinafter, Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 are real numbers larger than 0)).
  • Ga X4 Zn Y4 O Z4 X4, Y4, and Z4 are real numbers larger than 0
  • the CAC-OS is a composite oxide semiconductor having a structure in which a region containing GaO X3 as a main component and a region containing In X2 Zn Y2 O Z2 or InO X1 as a main component are mixed.
  • the atomic number ratio of In to the element M in the first region is larger than the atomic number ratio of In to the element M in the second region. It is assumed that the concentration of In is higher than that in the region 2.
  • IGZO is a common name and may refer to one compound consisting of In, Ga, Zn, and O. As a typical example, it is represented by InGaO 3 (ZnO) m1 (m1 is a natural number) or In (1 + x0) Ga (1-x0) O 3 (ZnO) m0 (-1 ⁇ x0 ⁇ 1, m0 is an arbitrary number). Crystalline compounds can be mentioned.
  • the crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure.
  • the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have a c-axis orientation and are connected without orientation on the ab plane.
  • CAC-OS relates to the material composition of oxide semiconductors.
  • CAC-OS is a region that is observed in the form of nanoparticles mainly composed of Ga in a material structure containing In, Ga, Zn, and O, and nanoparticles mainly composed of In. The regions observed in the shape are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element.
  • the CAC-OS does not include a laminated structure of two or more types of films having different compositions. For example, it does not include a structure consisting of two layers, a film containing In as a main component and a film containing Ga as a main component.
  • CAC-OS has a region observed in the form of nanoparticles mainly composed of the metal element and a nano portion containing In as a main component.
  • the regions observed in the form of particles refer to a configuration in which the regions are randomly dispersed in a mosaic pattern.
  • the CAC-OS can be formed by a sputtering method, for example, under the condition that the substrate is not intentionally heated.
  • a sputtering method one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas may be used as the film forming gas. good.
  • the lower the flow rate ratio of the oxygen gas to the total flow rate of the film-forming gas at the time of film formation is preferable, and for example, the flow rate ratio of the oxygen gas is preferably 0% or more and less than 30%, preferably 0% or more and 10% or less. ..
  • CAC-OS is characterized by the fact that no clear peak is observed when measured using the ⁇ / 2 ⁇ scan by the Out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. Have. That is, from the X-ray diffraction measurement, it can be seen that the orientation of the measurement region in the ab plane direction and the c axis direction is not observed.
  • XRD X-ray diffraction
  • the CAC-OS has a ring-shaped region with high brightness (ring region) and the ring in the electron diffraction pattern obtained by irradiating an electron beam having a probe diameter of 1 nm (also referred to as a nanobeam electron beam). Multiple bright spots are observed in the area. Therefore, from the electron diffraction pattern, it can be seen that the crystal structure of CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and the cross-sectional direction.
  • nc nano-crystal
  • GaO X3 is the main component by EDX mapping obtained by using energy dispersive X-ray spectroscopy (EDX). It can be confirmed that the region and the region containing In X2 Zn Y2 O Z2 or InO X1 as a main component have a structure in which they are unevenly distributed and mixed.
  • EDX energy dispersive X-ray spectroscopy
  • CAC-OS has a structure different from that of the IGZO compound in which metal elements are uniformly distributed, and has properties different from those of the IGZO compound. That is, the CAC-OS is phase-separated into a region containing GaO X3 or the like as a main component and a region containing In X2 Zn Y2 O Z2 or InO X1 as a main component, and a region containing each element as a main component. Has a mosaic-like structure.
  • the region in which In X2 Zn Y2 O Z2 or InO X1 is the main component is a region having higher conductivity than the region in which GaO X3 or the like is the main component. That is, the conductivity as an oxide semiconductor is exhibited by the carrier flowing through the region where In X2 Zn Y2 O Z2 or InO X1 is the main component. Therefore, a high field effect mobility ( ⁇ ) can be realized by distributing the region containing In X2 Zn Y2 O Z2 or InO X1 as a main component in the oxide semiconductor in a cloud shape.
  • the region in which GaO X3 or the like is the main component is a region having higher insulating properties than the region in which In X2 Zn Y2 O Z2 or InO X1 is the main component. That is, since the region containing GaO X3 or the like as the main component is distributed in the oxide semiconductor, leakage current can be suppressed and good switching operation can be realized.
  • CAC-OS when CAC-OS is used for a semiconductor element, the insulating property caused by GaO X3 and the like and the conductivity caused by In X2 Zn Y2 O Z2 or InO X1 act in a complementary manner, so that the insulation is high. On current (Ion) and high field effect mobility ( ⁇ ) can be achieved.
  • CAC-OS is suitable as a constituent material of various semiconductor devices.
  • the layer 203 is formed on the layer 202.
  • the layer 203 has a pixel circuit 331 having an OS transistor.
  • the transistor 103 and the transistor 104 are shown as a part of the pixel circuit 331.
  • the layer 203 is provided with insulating layers 231, 232, 233, 234, 235, 236, and 237. Further, the conductive layer 132 is provided.
  • the insulating layer 231 and the conductive layer 132 have a function as a bonded layer.
  • the insulating layer 232, 233, 234, and 237 have a function as an interlayer insulating film and a flattening film.
  • the insulating layer 235 has a function as a protective film.
  • the insulating layer 236 has a function as a gate insulating film.
  • the conductive layer 132 is electrically connected to the wiring 352 that functions as an output line of the pixel circuit 331.
  • the layer 204 has a photoelectric conversion device 240 and insulating layers 241 and 242, 245.
  • the photoelectric conversion device 240 is a pn junction type photodiode formed on a silicon substrate and has a p-type region 243 and an n-type region 244.
  • the photoelectric conversion device 240 is an embedded photodiode, and a thin p-type region 243 provided on the surface side (current extraction side) of the n-type region 244 can suppress dark current and reduce noise.
  • the insulating layer 241 has a function as a blocking layer.
  • the insulating layer 242 has a function as an element separation layer.
  • the insulating layer 245 has a function of suppressing the outflow of carriers.
  • the silicon substrate is provided with a groove for separating pixels, and the insulating layer 245 is provided on the upper surface of the silicon substrate and the groove.
  • the insulating layer 245 By providing the insulating layer 245, it is possible to prevent the carriers generated in the photoelectric conversion device 240 from flowing out to the adjacent pixels.
  • the insulating layer 245 also has a function of suppressing the intrusion of stray light. Therefore, the insulating layer 245 can suppress color mixing.
  • An antireflection film may be provided between the upper surface of the silicon substrate and the insulating layer 245.
  • the element separation layer can be formed by using a LOCOS (LOCOExidation of Silicon) method, an STI (Shallow Trench Isolation) method, or the like.
  • LOCOS LOCOS
  • STI Shallow Trench Isolation
  • the insulating layer 245 for example, an inorganic insulating film such as silicon oxide or silicon nitride, or an organic insulating film such as a polyimide resin or an acrylic resin can be used.
  • the insulating layer 245 may have a multi-layer structure.
  • the n-type region 244 (corresponding to the cathode) of the photoelectric conversion device 240 is electrically connected to either the source or the drain of the transistor 103 of the layer 203.
  • the p-type region 243 (anode) is electrically connected to the wiring 121 of the layer 203 that functions as a power supply line.
  • Layer 205 is formed on layer 204.
  • the layer 205 has a light-shielding layer 251, an optical conversion layer 250, and a microlens array 255.
  • the light-shielding layer 251 can suppress the inflow of light to adjacent pixels.
  • a metal layer such as aluminum or tungsten can be used for the light-shielding layer 251. Further, the metal layer and a dielectric film having a function as an antireflection film may be laminated.
  • a color filter can be used for the optical conversion layer 250.
  • a color image can be obtained by assigning color filters of colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) for each pixel.
  • color filters of colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) for each pixel.
  • the color filter 250R (red), the color filter 250G (green), and the color filter 250B (blue) can be assigned to different pixels.
  • an image pickup device capable of obtaining images in various wavelength regions can be obtained.
  • an infrared filter that blocks light having a wavelength of visible light or less is used for the optical conversion layer 250.
  • an infrared image pickup device can be obtained.
  • a filter that blocks light having a wavelength of near infrared rays or less is used for the optical conversion layer 250, a far infrared ray imaging device can be obtained.
  • the optical conversion layer 250 uses an ultraviolet filter that blocks light having a wavelength equal to or higher than that of visible light, the optical conversion layer 250 can be used as an ultraviolet image pickup device.
  • a plurality of different optical conversion layers may be arranged in one image pickup apparatus.
  • the color filter 250R red
  • the color filter 250G green
  • the color filter 250B blue
  • the infrared filter 250IR can be assigned to different pixels.
  • a visible light image and an infrared light image can be acquired at the same time.
  • the color filter 250R red
  • the color filter 250G green
  • the color filter 250B blue
  • the ultraviolet filter 250UV can be assigned to different pixels.
  • a visible light image and an ultraviolet light image can be acquired at the same time.
  • a scintillator is used for the optical conversion layer 250, it is possible to obtain an image that visualizes the intensity of radiation used in an X-ray image pickup device or the like.
  • radiation such as X-rays transmitted through a subject
  • a scintillator it is converted into light (fluorescence) such as visible light or ultraviolet light by a photoluminescence phenomenon.
  • the image data is acquired by detecting the light with the photoelectric conversion device 240.
  • an image pickup device having the above configuration may be used for a radiation detector or the like.
  • a scintillator contains a substance that absorbs its energy and emits visible or ultraviolet light when irradiated with radiation such as X-rays or gamma rays.
  • Gd 2 O 2 S Tb
  • Gd 2 O 2 S Pr
  • Gd 2 O 2 S Eu
  • BaFCl Eu
  • NaI, CsI, CaF 2 , BaF 2 , CeF 3 LiF, LiI, ZnO and the like.
  • Those dispersed in resin or ceramics can be used.
  • imaging with infrared light or ultraviolet light it is possible to impart an inspection function, a security function, a sensor function, and the like to the imaging device. For example, by performing imaging with infrared light, non-destructive inspection of products, selection of agricultural products (sugar content meter function, etc.), vein authentication, medical inspection, etc. can be performed. Further, by performing imaging with ultraviolet light, it is possible to detect ultraviolet light emitted from a light source or a flame, and it is possible to manage a light source, a heat source, a production apparatus, and the like.
  • a microlens array 255 is provided on the optical conversion layer 250.
  • the light passing through the individual lenses of the microlens array 255 passes through the optical conversion layer 250 directly below and irradiates the photoelectric conversion device 240.
  • the microlens array 255 is preferably formed of a resin or glass having high translucency with respect to light of a target wavelength.
  • the layer 202 is provided with an insulating layer 229 and a conductive layer 131.
  • the conductive layer 131 has a region embedded in the insulating layer 229. Further, the surfaces of the insulating layer 229 and the conductive layer 131 are flattened so that their heights match.
  • the layer 203 is provided with an insulating layer 231 and a conductive layer 132.
  • the conductive layer 132 has a region embedded in the insulating layer 232. Further, the surfaces of the insulating layer 231 and the conductive layer 132 are flattened so that their heights match.
  • the conductive layer 131 and the conductive layer 132 are metal elements having the same main components. Further, it is preferable that the insulating layer 229 and the insulating layer 231 are composed of the same components.
  • Cu, Al, Sn, Zn, W, Ag, Pt, Au, or the like can be used for the conductive layers 131 and 132.
  • Cu, Al, W, or Au is preferably used because of the ease of joining.
  • silicon oxide, silicon nitride nitride, silicon nitride oxide, silicon nitride, titanium nitride and the like can be used for the insulating layer 229 and 231.
  • the conductive layer 131 and the conductive layer 132 may have a multi-layer structure of a plurality of layers, in which case the surface layer (bonding surface) may be the same metal material. Further, the insulating layer 229 and the insulating layer 231 may also have a multi-layered structure of a plurality of layers, in which case the insulating materials having the same surface layer (bonding surface) may be used.
  • a surface-activated bonding method in which the oxide film on the surface and the adsorption layer of impurities are removed by sputtering, etc., and the cleaned and activated surfaces are brought into contact with each other for bonding.
  • a diffusion bonding method or the like in which surfaces are bonded to each other by using both temperature and pressure can be used. In both cases, bonds occur at the atomic level, so excellent bonding can be obtained not only electrically but also mechanically.
  • the surfaces treated with hydrophilicity such as oxygen plasma are brought into contact with each other for temporary bonding, and then main bonding is performed by dehydration by heat treatment.
  • a sex joining method or the like can be used. Since the hydrophilic bonding method also causes bonding at the atomic level, it is possible to obtain mechanically excellent bonding.
  • an insulating layer and a metal layer coexist on the respective bonding surfaces. Therefore, for example, a surface activation bonding method and a hydrophilic bonding method may be combined.
  • a method can be used in which the surface is cleaned after polishing, the surface of the metal layer is subjected to an antioxidant treatment, and then a hydrophilic treatment is performed to join the metal layer.
  • the surface of the metal layer may be made of a refractory metal such as Au and subjected to hydrophilic treatment.
  • a joining method other than the above-mentioned method may be used.
  • the pixel circuit 331 of the layer 203 and the readout circuit 311 of the layer 201 can be electrically connected.
  • FIG. 18 shows a modified example in which the configurations of the layer 203 and the layer 204 are different from those of the laminated structure 1 shown in FIG.
  • the modification shown in FIG. 18 is a configuration in which the transistor 102 included in the pixel circuit 331 is provided on the layer 204.
  • the transistor 103 is formed of a Si transistor.
  • One of the source or drain of the transistor 103 is directly connected to the photoelectric conversion device 240, and the other of the source or drain acts as a node FD.
  • the layer 203 is provided with a transistor excluding the transistor 103 among the transistors constituting the pixel circuit 331.
  • FIG. 18 illustrates the transistor 104 and the transistor 105.
  • ⁇ Laminate structure 2> In the laminated structure 1 and its modification, the configuration in which the layer 202 and the layer 203 are bonded to each other is shown, but the layer 202 and the layer 203 may be bonded to each other.
  • the laminated structure 2 shown in FIG. 19 has a structure having a bonded surface between the layer 203 and the layer 204.
  • the layer 203 is provided with a conductive layer 135 that is electrically connected to either the source or the drain of the transistor 103. Further, a conductive layer 136 that is electrically connected to the wiring 121 is provided.
  • the conductive layers 135 and 136 have a region embedded in the insulating layer 231. Further, the surfaces of the insulating layer 231 and the conductive layers 135 and 136 are flattened so that their heights match.
  • the layer 204 is provided with a conductive layer 133 that is electrically connected to the n-type region 244 (corresponding to the cathode) of the photoelectric conversion device 240. Further, a conductive layer 134 electrically connected to the p-type region 243 (anode) is provided. Further, an insulating layer 249 is provided on the insulating layer 246. The conductive layers 133 and 134 have a region embedded in the insulating layer 249. Further, the surfaces of the insulating layer 249 and the conductive layers 133 and 134 are flattened so that their heights match.
  • the conductive layers 133, 134, 135, 136 are the same bonded layers as the above-mentioned conductive layers 131, 132.
  • the insulating layer 249 is the same bonded layer as the above-mentioned insulating layers 229 and 231.
  • the conductive layer 133 and the conductive layer 135 one of the source or drain of the transistor 103 can be electrically connected to the n-type region 244 (corresponding to the cathode) of the photoelectric conversion device 240. Further, by laminating the conductive layer 134 and the conductive layer 136, the p-type region 243 (corresponding to the anode) of the photoelectric conversion device 240 and the wiring 121 can be electrically connected. Further, by laminating the insulating layer 231 and the insulating layer 249, the layer 203 and the layer 204 can be electrically and mechanically bonded.
  • the laminated structure 3 shown in FIG. 20 has a structure having a bonded surface between the layer 201 and the layer 202.
  • the layer 201 is provided with a conductive layer 141 that is electrically connected to the other electrode of the capacitor 402. Further, a conductive layer 142 electrically connected to one of the source and drain of the transistor 115 is provided. Further, the conductive layer 143 which is electrically connected to one of the source and the drain of the transistor 116 is electrically connected. Further, an insulating layer 219 is provided on the insulating layer 218. The conductive layers 141, 142, and 143 have regions embedded in the insulating layer 219. Further, the surfaces of the insulating layer 219 and the conductive layers 141, 142, and 143 are flattened so that their heights match.
  • the layer 202 is provided with a conductive layer 137 that is electrically connected to the wiring 352 of the layer 203. Further, a conductive layer 138 is provided which is electrically connected to one of the source and drain of the transistor 276 of the layer 202. Further, a conductive layer 139 is provided which is electrically connected to the gate of the transistor 276.
  • the conductive layers 137, 138, and 139 have a region embedded in the insulating layer 229. Further, the surfaces of the insulating layer 229 and the conductive layer 137, 138, 139 are flattened so that their heights match.
  • the conductive layers 137, 138, 139, 141, 142, and 143 are the same bonded layers as the above-mentioned conductive layers 131 and 132.
  • the insulating layer 219 is the same bonded layer as the above-mentioned insulating layers 229 and 231.
  • the readout circuit 311 and the pixel circuit 331 can be electrically connected. Further, by laminating the conductive layer 138 and the conductive layer 142, the column driver 313 and the memory circuit 321 can be electrically connected. Further, by laminating the conductive layer 139 and the conductive layer 143, the low driver 312 and the memory circuit 321 can be electrically connected.
  • the configuration in which the pixel circuit readout circuit and the memory circuit drive circuit are provided in the layer 201 and the memory circuit is provided in the layer 202 has been described, but the present invention is not limited to this.
  • a pixel circuit drive circuit, a neural network, a communication circuit, a CPU, and the like may be provided on the layer 201 or the layer 202.
  • a normally-off CPU (also referred to as "Noff-CPU") can be realized by using an OS transistor and a Si transistor.
  • the Nonf-CPU is an integrated circuit including a normally-off type transistor that is in a non-conducting state (also referred to as an off state) even when the gate voltage is 0V.
  • the Noff-CPU can stop the power supply to the unnecessary circuit in the Noff-CPU and put the circuit in the standby state. No power is consumed in the circuit where the power supply is stopped and the circuit is in the standby state. Therefore, the Nonf-CPU can minimize the amount of power used. Further, the Nonf-CPU can retain information necessary for operation such as setting conditions for a long period of time even if the power supply is stopped. To return from the standby state, it is only necessary to restart the power supply to the circuit, and it is not necessary to rewrite the setting conditions and the like. That is, high-speed recovery from the standby state is possible. In this way, the Nonf-CPU can reduce the power consumption without significantly reducing the operating speed.
  • FIG. 21 is an example of a cross-sectional view of a laminate having layers 201 and 204 and having a laminating surface between layers 201 and 204.
  • FIG. 21 corresponds to the laminate shown in FIG.
  • the layer 201 is provided with transistors 115, 276, 403, capacitors 277, and capacitors 402, which are Si transistors
  • the layer 204 is provided with transistors 103, 104, 105, 106, which are Si transistors, and a photoelectric conversion device 240.
  • the configuration is illustrated. The description of the elements common to the elements of the laminated structure described above will be omitted as appropriate.
  • the capacitor 402 and the transistor 403 included in the layer 201 are elements included in the CDS circuit of the readout circuit 311.
  • the capacitor 277 and the transistor 276 are elements of the memory cell 321e.
  • the capacitor 277 is a ferroelectric capacitor.
  • the transistors 103, 104, 105 and 106 included in the layer 204 are elements included in the pixel circuit 331.
  • the layer 201 is provided with a conductive layer 145 that is electrically connected to the other electrode of the capacitor 402. Further, a conductive layer 146 that is electrically connected to the other electrode of the capacitor 277 is provided. Further, the layer 201 has an insulating layer 261 and the conductive layers 145 and 146 have a region embedded in the insulating layer 261. The surfaces of the insulating layer 261 and the conductive layers 145 and 146 are flattened so that their heights match.
  • the layer 204 is provided with a conductive layer 148 that is electrically connected to the other of the source or drain of the transistor 106. Further, a conductive layer 147 that is electrically connected to the wiring 129 is provided. Further, the layer 204 has an insulating layer 262, and the conductive layers 147 and 148 have a region embedded in the insulating layer 262. The surfaces of the insulating layer 262 and the conductive layer 147 and 148 are flattened so as to have the same height.
  • the conductive layers 145, 146, 147, and 148 are the same bonded layers as the above-mentioned conductive layers 131 and 132.
  • the insulating layers 261 and 262 are the same bonded layers as the above-mentioned insulating layers 229 and 231.
  • the wiring 129 corresponds to the wiring PL shown in FIGS. 13B and 13C.
  • the readout circuit 311 and the pixel circuit 331 can be electrically connected. Further, by laminating the conductive layer 146 and the conductive layer 147, the other electrode of the capacitor 277 and the wiring 129 can be electrically connected.
  • the wiring 129 can also be provided on the layer 201.
  • Embodiment 2 In this embodiment, an example of a package containing an image sensor chip and a camera module will be described.
  • the image sensor chip the configuration of the image pickup apparatus according to one aspect of the present invention can be used.
  • FIG. 23A is an external perspective view of the package containing the image sensor chip.
  • the package is a CSP (Chip Size Package) and has a bare chip 850 of an image sensor, a cover glass 840, an adhesive 830 for adhering both, and the like.
  • CSP Chip Size Package
  • the electrode pad 825 provided on the outside of the pixel array 855 is electrically connected to the back surface electrode 815 via the through electrode 820.
  • the electrode pad 825 is electrically connected to the circuit constituting the image sensor by wiring or wire.
  • the bare chip 850 may be a laminated chip laminated with a circuit having various functions.
  • FIG. 23A exemplifies a BGA (Ball Grid Array) having a configuration in which a bump 810 is formed by a solder ball on the back surface electrode 815.
  • BGA Bit Grid Array
  • it is not limited to BGA, and may be LGA (Land Grid Array) or PGA (Pin Grid Array).
  • a package in which the bare chip 850 is mounted on a QFN (Quad Flat No-lead package) or a QFP (Quad Flat Package) may be used.
  • FIG. 23B is an external perspective view of the upper surface side of the camera module in which the image sensor chip and the lens are combined.
  • the camera module has a lens cover 860, a plurality of lenses 870, and the like on the configuration of FIG. 23A.
  • an optical filter 880 that absorbs light having a specific wavelength is provided between the lens 870 and the cover glass 840, if necessary.
  • the optical filter 880 for example, in the case of an image sensor that mainly captures visible light, an infrared cut filter or the like can be used.
  • the image sensor chip By housing the image sensor chip in a package having the above-mentioned form, it can be easily mounted on a printed circuit board or the like, and the image sensor chip can be incorporated into various semiconductor devices and electronic devices.
  • a display device As electronic devices that can use the image pickup device according to one aspect of the present invention, a display device, a personal computer, an image storage device or image reproduction device provided with a recording medium, a mobile phone, a game machine including a portable type, and a portable data terminal.
  • Electronic book terminals video cameras, cameras such as digital still cameras, goggle type displays (head mount displays), navigation systems, sound reproduction devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, multifunction printers , Automatic cash deposit / payment machine (ATM), vending machine, etc. Specific examples of these electronic devices are shown in FIGS. 24A to 24F.
  • FIG. 24A is an example of a mobile phone, which includes a housing 981, a display unit 982, an operation button 983, an external connection port 984, a speaker 985, a microphone 986, a camera 987, and the like.
  • the mobile phone includes a touch sensor on the display unit 982. All operations such as making a phone call or inputting characters can be performed by touching the display unit 982 with a finger or a stylus.
  • the image pickup apparatus of one aspect of the present invention can be applied to the mobile phone.
  • FIG. 24B is a portable data terminal, which includes a housing 911, a display unit 912, a speaker 913, a camera 919, and the like.
  • Information can be input / output by the touch panel function of the display unit 912.
  • characters and the like can be recognized from the image acquired by the camera 919, and the characters can be output as voice by the speaker 913.
  • the image pickup apparatus of one aspect of the present invention can be applied to the portable data terminal.
  • FIG. 24C is a surveillance camera, which has a support base 951, a camera unit 952, a protective cover 953, and the like.
  • the camera unit 952 is provided with a rotation mechanism or the like, and by installing it on the ceiling, it is possible to take an image of the entire surroundings.
  • An image pickup device can be applied to an element for image acquisition in the camera unit.
  • the term "surveillance camera” is an idiomatic name and does not limit its use.
  • a device having a function as a surveillance camera is also called a camera or a video camera.
  • FIG. 24D is a drive recorder, which includes a frame 941, a camera 942, an operation button 943, a mounting component 944, and the like. By installing it on the front window of an automobile or the like via the mounting component 944, it is possible to record the scenery in front of the vehicle while driving. A display panel for displaying the recorded image is provided on the back surface (not shown).
  • the image pickup apparatus of one aspect of the present invention can be applied to the camera 942.
  • FIG. 24E is a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, a light emitting unit 967, a lens 965, and the like.
  • the image pickup apparatus of one aspect of the present invention can be applied to the digital camera.
  • FIG. 24F is a wristwatch-type information terminal, which has a display unit 932, a housing / wristband 933, a camera 939, and the like.
  • the display unit 932 includes a touch panel for operating the information terminal.
  • the display unit 932 and the housing / wristband 933 have flexibility and are excellent in wearability to the body.
  • the image pickup apparatus of one aspect of the present invention can be applied to the information terminal.
  • FIG. 25A is a drone which is an example of a moving body, has a frame 921, an arm 922, a rotor 923, a blade 924, a camera 925, a battery 926, and the like, and has a function of autonomously flying, a function of resting in the air, and the like.
  • the image pickup apparatus of one aspect of the present invention can be applied to the camera 925.
  • FIG. 25B illustrates an external view of an automobile as an example of a moving body.
  • the automobile 890 has a plurality of cameras 891 and the like, and can acquire information on the front, rear, left, right, and above of the automobile 890.
  • the image pickup apparatus of one aspect of the present invention can be applied to the camera 891.
  • the automobile 890 is equipped with various sensors (not shown) such as an infrared radar, a millimeter wave radar, and a laser radar.
  • the automobile 890 can analyze the image acquired by the camera 891 for a plurality of imaging directions 892, determine the surrounding traffic conditions such as the presence or absence of a guardrail or a pedestrian, and perform automatic driving. It can also be used in systems for road guidance, danger prediction, and the like.
  • the obtained image data is subjected to arithmetic processing such as a neural network to increase the resolution of the image, reduce image noise, face recognition (for security purposes, etc.), and object recognition. It can perform processing such as (purpose of automatic operation, etc.), image compression, image correction (wide dynamic range), image restoration of lensless image sensor, positioning, character recognition, and reduction of reflection reflection.
  • arithmetic processing such as a neural network to increase the resolution of the image, reduce image noise, face recognition (for security purposes, etc.), and object recognition. It can perform processing such as (purpose of automatic operation, etc.), image compression, image correction (wide dynamic range), image restoration of lensless image sensor, positioning, character recognition, and reduction of reflection reflection.
  • the automobile may be an automobile having an internal combustion engine, an electric vehicle, a hydrogen vehicle, or the like.
  • the moving body is not limited to the automobile.
  • examples of moving objects include trains, monorails, ships, flying objects (helicopters, unmanned aerial vehicles, airplanes, rockets), etc., and artificial intelligence is applied to these moving objects by applying a computer of one aspect of the present invention. It is possible to add a system that utilizes intelligence.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Thin Film Transistor (AREA)
PCT/IB2021/058290 2020-09-25 2021-09-13 撮像装置および電子機器 Ceased WO2022064317A1 (ja)

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US18/024,084 US12212873B2 (en) 2020-09-25 2021-09-13 Imaging device and electronic device
KR1020237008317A KR20230074476A (ko) 2020-09-25 2021-09-13 촬상 장치 및 전자 기기
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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7834102B2 (ja) * 2021-06-17 2026-03-23 株式会社半導体エネルギー研究所 撮像装置および電子機器

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006129762A1 (ja) * 2005-06-02 2006-12-07 Sony Corporation 半導体イメージセンサ・モジュール及びその製造方法
WO2014050694A1 (ja) * 2012-09-28 2014-04-03 ソニー株式会社 半導体装置および電子機器
JP2018037441A (ja) * 2016-08-29 2018-03-08 富士通セミコンダクター株式会社 ３次元積層チェーン型メモリ装置及びその製造方法
JP2018117102A (ja) * 2017-01-20 2018-07-26 ソニーセミコンダクタソリューションズ株式会社 半導体装置
JP2020123612A (ja) * 2019-01-29 2020-08-13 株式会社半導体エネルギー研究所 半導体装置の製造方法、半導体装置の製造装置

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100610481B1 (ko) * 2004-12-30 2006-08-08 매그나칩 반도체 유한회사 수광영역을 넓힌 이미지센서 및 그 제조 방법
US8049293B2 (en) 2005-03-07 2011-11-01 Sony Corporation Solid-state image pickup device, electronic apparatus using such solid-state image pickup device and method of manufacturing solid-state image pickup device
CN101228631A (zh) 2005-06-02 2008-07-23 索尼株式会社 半导体图像传感器模块及其制造方法
CN104393007A (zh) 2009-11-06 2015-03-04 株式会社半导体能源研究所 半导体装置
JP5791571B2 (ja) * 2011-08-02 2015-10-07 キヤノン株式会社 撮像素子及び撮像装置
US9607971B2 (en) * 2012-06-04 2017-03-28 Sony Corporation Semiconductor device and sensing system
WO2014141663A1 (ja) * 2013-03-14 2014-09-18 株式会社ニコン 撮像ユニット、撮像装置および撮像制御プログラム
JP2015041677A (ja) * 2013-08-21 2015-03-02 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
KR102450562B1 (ko) * 2014-03-13 2022-10-07 가부시키가이샤 한도오따이 에네루기 켄큐쇼 촬상 장치
KR102380829B1 (ko) * 2014-04-23 2022-03-31 가부시키가이샤 한도오따이 에네루기 켄큐쇼 촬상 장치
WO2016046685A1 (en) * 2014-09-26 2016-03-31 Semiconductor Energy Laboratory Co., Ltd. Imaging device
JP6499006B2 (ja) * 2015-05-07 2019-04-10 株式会社半導体エネルギー研究所 撮像装置
US9876946B2 (en) * 2015-08-03 2018-01-23 Semiconductor Energy Laboratory Co., Ltd. Imaging device and electronic device
KR102653044B1 (ko) * 2015-09-01 2024-04-01 소니그룹주식회사 적층체
WO2018186197A1 (ja) * 2017-04-04 2018-10-11 ソニーセミコンダクタソリューションズ株式会社 固体撮像装置、及び電子機器
US12119359B2 (en) * 2018-12-20 2024-10-15 Sony Semiconductor Solutions Corporation Imaging device
KR102661820B1 (ko) * 2019-02-11 2024-05-02 삼성전자주식회사 이미지 센서 및 그것의 구동 방법
US12376410B2 (en) * 2019-07-04 2025-07-29 Semiconductor Energy Laboratory Co., Ltd. Imaging device with embedded conductive layers
US11302736B2 (en) * 2019-08-08 2022-04-12 Semiconductor Energy Laboratory Co., Ltd. Imaging device and electronic device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006129762A1 (ja) * 2005-06-02 2006-12-07 Sony Corporation 半導体イメージセンサ・モジュール及びその製造方法
WO2014050694A1 (ja) * 2012-09-28 2014-04-03 ソニー株式会社 半導体装置および電子機器
JP2018037441A (ja) * 2016-08-29 2018-03-08 富士通セミコンダクター株式会社 ３次元積層チェーン型メモリ装置及びその製造方法
JP2018117102A (ja) * 2017-01-20 2018-07-26 ソニーセミコンダクタソリューションズ株式会社 半導体装置
JP2020123612A (ja) * 2019-01-29 2020-08-13 株式会社半導体エネルギー研究所 半導体装置の製造方法、半導体装置の製造装置

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US12212873B2 (en) 2025-01-28
JPWO2022064317A1 (https=) 2022-03-31
TW202220227A (zh) 2022-05-16

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