WO2022062644A1 - 半导体结构及其制备方法、存储装置 - Google Patents

半导体结构及其制备方法、存储装置 Download PDF

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Publication number
WO2022062644A1
WO2022062644A1 PCT/CN2021/109059 CN2021109059W WO2022062644A1 WO 2022062644 A1 WO2022062644 A1 WO 2022062644A1 CN 2021109059 W CN2021109059 W CN 2021109059W WO 2022062644 A1 WO2022062644 A1 WO 2022062644A1
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Prior art keywords
bit line
dielectric
region
material layer
layer
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PCT/CN2021/109059
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English (en)
French (fr)
Inventor
金星
孙正庆
程明
李冉
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长鑫存储技术有限公司
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Priority to US17/649,187 priority Critical patent/US20220157827A1/en
Publication of WO2022062644A1 publication Critical patent/WO2022062644A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

Definitions

  • the present disclosure relates to the technical field of semiconductors, and in particular, to a semiconductor structure, a method for preparing the same, and a storage device.
  • the dynamic random access memory may include a recessed transistor array layer, a wiring layer and a capacitor layer arranged in layers.
  • the wiring layer includes a bit line structure, a conductive plug and a contact pad.
  • the bit line structure is electrically connected to the source of the recessed transistor; a capacitor contact hole separated by a dielectric barrier wall is arranged between two adjacent bit line structures, and a conductive plug is filled in the capacitor contact hole to connect with the drain of the recessed transistor, and the contact
  • the pad is connected to the side of the conductive plug away from the recessed transistor array layer for electrical connection with the capacitor.
  • the DRAM is prone to the failure of the conductive plug and the open circuit.
  • the purpose of the present disclosure is to provide a semiconductor structure, a method for fabricating the same, and a storage device, so as to improve the yield of the semiconductor structure.
  • a method for fabricating a semiconductor structure comprising:
  • bit line structures forming a plurality of bit line structures on the semiconductor substrate, any of the bit line structures passing through the first region and the second region;
  • any one of the electrode structures includes conductive plugs and contact pads that are electrically connected to each other, the conductive plugs are located in the first region and between two adjacent bit line structures and are connected with the Semiconductor substrate connection.
  • a semiconductor structure comprising:
  • a semiconductor substrate comprising a plurality of alternately arranged first regions and second regions;
  • any one of the bit line structures penetrates the first region and the second region; in the first region, sidewalls on both sides of the bit line structure are stepped;
  • any one of the electrode structures includes conductive plugs and contact pads that are electrically connected to each other, the conductive plugs are located in the first region and between two adjacent bit line structures and are connected to the semiconductor Substrate connection.
  • a memory device including the above-mentioned semiconductor structure.
  • the sidewalls of the bit line structure on both sides of the capacitor contact hole are stepped, so that the pressure of the bit line structure on the capacitor contact hole can be reduced and the conductive plug can be improved.
  • the contact area with the contact pads thereby avoiding disconnection between the conductive plugs and the contact pads, and improving the yield of the semiconductor structure.
  • FIG. 1 is a cross-sectional electron microscope view of a wiring layer in the related art.
  • FIG. 2 is a top-view electron microscope view of a wiring layer in the related art.
  • FIG. 3 is a schematic diagram of a manufacturing process of a semiconductor structure according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic top-view structural diagram of a semiconductor substrate according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic cross-sectional structural diagram of a semiconductor substrate according to an embodiment of the present disclosure, and the cutting direction is the extending direction of the active region.
  • FIG. 6 is a schematic structural diagram of forming a bit line contact trench according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of forming a conductive material layer and a dielectric material layer according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of forming a bit line lead according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic top-view structural diagram of forming a bit line lead according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of forming a dielectric sidewall according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of forming a sacrificial dielectric layer according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic three-dimensional structural diagram of forming a dielectric barrier wall according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic three-dimensional structure diagram of the first region after the first etching of the bit line structure according to an embodiment of the present disclosure.
  • FIG. 14 is a schematic three-dimensional structure diagram of the second etching of the bit line structure in the first region according to an embodiment of the present disclosure.
  • 15 is a schematic three-dimensional structural diagram of forming a plug material layer according to an embodiment of the present disclosure.
  • FIG. 16 is a schematic cross-sectional structural diagram of forming a plug material layer according to an embodiment of the present disclosure, and the cutting direction is parallel to the word line direction.
  • FIG. 17 is a schematic top-view structural diagram of a plug-forming material layer according to an embodiment of the present disclosure.
  • FIG. 18 is a schematic three-dimensional structure diagram of forming a contact pad material layer according to an embodiment of the present disclosure.
  • FIG. 19 is a schematic cross-sectional structural diagram of forming a contact pad material layer according to an embodiment of the present disclosure.
  • FIG. 20 is a schematic cross-sectional structural diagram of forming a second mask structure according to an embodiment of the present disclosure.
  • FIG. 21 is a schematic cross-sectional structural diagram of forming an electrode structure according to an embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided in order to give a thorough understanding of the embodiments of the present disclosure.
  • the height of a structure refers to the dimension between the end of the structure away from the semiconductor substrate and the semiconductor substrate.
  • the top surface/top of a structure refers to the surface/end of the structure that is remote from the semiconductor substrate.
  • FIG. 1 is a cross-sectional electron microscope view of a wiring layer in the related art
  • FIG. 2 is a top electron microscope view of a metal wiring layer in the related art. It can be seen from FIG. 1 and FIG. 2 that the conductive plug 310 is used for electrical connection with the contact pad 320 . However, in FIGS. 1 and 2, it can also be seen that there is a poor open circuit between the contact pad 320a and the conductive plug 310a.
  • the inventor believes that the defect is caused by the bit line structure pressing the capacitor contact hole, which reduces the contact area between the conductive plug in the capacitor contact hole and the contact pad.
  • the defect is caused by the bit line structure pressing the capacitor contact hole, which reduces the contact area between the conductive plug in the capacitor contact hole and the contact pad.
  • it is difficult to improve the yield of DRAM by reducing the size of the bit line structure; this is because reducing the size of the bit line structure will result in an excessively high aspect ratio of the bit line structure. Large and prone to collapse.
  • the preparation method of the semiconductor structure includes:
  • step S110 referring to FIG. 4 and FIG. 5, a semiconductor substrate 100 is provided, and the semiconductor substrate 100 includes a plurality of alternately arranged first regions A and second regions B;
  • Step S120 referring to FIG. 9 and FIG. 10, forming a plurality of bit line structures 200 on the semiconductor substrate 100, any of the bit line structures 200 passing through the first region A and the second region B;
  • Step S130 referring to FIG. 14 , the bit line structure 200 is etched in the first region A, so that both sidewalls of the bit line structure 200 are stepped;
  • Step S140 referring to FIG. 21, forming a plurality of electrode structures 300, any one of the electrode structures 300 includes a conductive plug 310 and a contact pad 320 that are electrically connected to each other, and the conductive plug 310 is located in the first region A and is located in two adjacent bit line structures 200 between and connected to the semiconductor substrate 100 .
  • a capacitor contact hole 330 for forming the conductive plug 310 can be prepared, and the capacitor contact hole 330 is located in the first area A and between two adjacent ones. between the bit line structures 200 . Since the sidewall of the bit line structure 200 is stepped in the first area A, the capacitor contact hole 330 has the characteristics of a small bottom and a large top, which can increase the size of the top of the capacitor contact hole 330 and prevent the bit line structure from being squeezed The top of the capacitor contact hole 330 causes the conductive plug 310 to be pinched off.
  • step S140 referring to FIG.
  • the size of the top of the conductive plug 310 can be made larger, the process window for preparing the conductive plug 310 can be increased, and the conductive plug 310 can be prevented from being damaged during the preparation process.
  • the circuit is etched and disconnected to ensure that the contact pads 320 can be electrically connected to the semiconductor substrate 100 through the conductive plugs 310 . In this way, the preparation method of the semiconductor structure of the present disclosure can improve the preparation yield of the semiconductor structure, increase the process window of the semiconductor structure, and reduce the preparation cost of the semiconductor structure.
  • the prepared semiconductor structure may include a semiconductor substrate 100 , a plurality of bit line structures 200 and a plurality of electrode structures 300 ; wherein, referring to FIG. 4 , the semiconductor substrate 100 It includes a plurality of alternately arranged first regions A and second regions B. Any bit line structure 200 runs through the first region A and the second region B; in the first region A, the sidewalls on both sides of the bit line structure 200 are stepped; a plurality of electrode structures 300, any one of the electrode structures 300 includes mutual The conductive plug 310 and the contact pad 320 are electrically connected.
  • the conductive plug 310 is located in the first region A and between two adjacent bit line structures 200 and is connected to the semiconductor substrate 100 .
  • the semiconductor structure can be prepared by using the above-mentioned preparation method of the semiconductor structure, and thus has the same or similar technical effects, which will not be repeated in the present disclosure.
  • a semiconductor substrate 100 may be provided, referring to FIG. 4 and FIG. 5, the semiconductor substrate 100 is filled with recessed transistors and word lines 140, wherein the word lines 140 may be connected to the gates of the recessed transistors or partially Multiplexed as the gate of the recessed transistor.
  • the material of the semiconductor substrate 100 can be selected from Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, and also includes multilayer structures composed of these semiconductors, or silicon-on-insulator ( SOI), silicon on insulator (SSOI), silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), etc.
  • the semiconductor substrate 100 can also be doped, for example, it can be lightly doped locally to form the channel of the recessed transistor, and locally heavily doped so that the source and drain of the recessed transistor can be connected with the bit line structure 200 and the electrode structure 300 . electrical connection.
  • the semiconductor substrate 100 is provided with isolation shallow trenches so that the semiconductor substrate 100 is formed with a plurality of independent active regions 110; the isolation shallow trenches may be filled with a dielectric to form the shallow trench isolation structures 120, such as silicon oxide and the like. Dielectric.
  • each active region 110 is arranged into a plurality of active region columns extending along the first direction C and parallel to each other, any one active region column may include a plurality of active regions 110 and extend along the active region 110 The direction is the first direction C.
  • the semiconductor substrate 100 is further provided with word line trenches along the second direction D, and the included angle between the second direction D and the first direction C is less than 90°.
  • the word line trenches pass through the shallow trench isolation structure 120 and the active region 110 in sequence along the second direction D, and expose the semiconductor substrate 100 in the active region 110 .
  • the amount of dopant on the surface of the semiconductor substrate 100 exposed by the word line trench can also be adjusted, for example, by ion implantation and other methods to increase the amount of dopant at the bottom of the word line trench or implant ions of opposite types and so on, thereby adjusting the threshold voltage of the recessed transistor.
  • the word line trench there may be a gate dielectric layer 130 covering the sidewalls of the word line trench, and a word line 140 inside the gate dielectric layer 130 .
  • the gate dielectric layer 130 may serve as the gate insulating layer of the recessed transistor in the active region 110, and the word line 140 may be partially multiplexed as the gate of the recessed transistor. It can be understood that the gate dielectric layer 130 may be a layer of insulating material, or may be a composite of multiple layers of insulating materials, and may also cover air gaps in the multiple layers of insulating materials, which is not limited in the present disclosure.
  • the portion of the semiconductor substrate 100 corresponding to the word line 140 may be the channel of the recessed transistor, and the portion of the semiconductor substrate 100 connected to the channel may be the source and drain of the recessed transistor.
  • the trenches of the word lines 140 may also be filled with insulating material to form a dielectric cap 150 ; the dielectric cap 150 covers the word lines 140 so that the word lines 140 are buried in the semiconductor substrate 100 .
  • an insulating material may also be provided on the surface of the semiconductor substrate 100 to form a protective layer, and the protective layer covers the semiconductor substrate 100 and protects the active region 110 .
  • the material of the protective layer may be silicon nitride.
  • the surface of the semiconductor substrate 100 may be heavily doped to ensure that the source and drain of the recessed transistor have good conductivity, thereby ensuring that the bit line structure 200 and the conductive plug 310 can be connected to the source of the recessed transistor. is electrically connected to the drain.
  • every three columns of active region columns are periodically arranged in a period; along a plane perpendicular to the second direction D and within the semiconductor substrate 100
  • the rows of active regions are periodically arranged.
  • the sum of the length of the active region 110 and the distance between two adjacent active regions 110 in the same active region column is the set size; in two adjacent active region columns , after translating the pattern of one active area row to an adjacent active area row along the second direction D, the pattern of the shifted active area row can be translated along a specific direction in the first direction C by 1/3
  • a set size is coincident with the pattern of the active area 110 of the adjacent active area row.
  • the pattern of the shifted active area column is the same as the pattern of the adjacent active area column.
  • the active regions 110 of the active region columns are patterned coincident.
  • two word line trenches pass through any one active region 110 , so that two word lines 140 pass through the active region 110 .
  • the active region 110 is divided into a first contact region and a second contact region by the two word lines 140 ; wherein the second contact region is located between the two word lines 140 running through the active region 110 ,
  • the number of the first contact areas is two and they are located on two sides of the second contact area, respectively.
  • the provided semiconductor substrate 100 may include a plurality of alternately arranged first regions A and second regions B, wherein the extension directions of the first regions A and the second regions B are both in the second direction D. In other words, the extension directions of the first region A and the second region B are both consistent with the extension direction of the word lines 140 .
  • the first region A may include at least a partial region of any active region 110
  • the second region B may include at least a partial region of any active region 110 .
  • the second regions B are used to form the dielectric barrier walls 420 for isolating the first regions A
  • the first regions A are used to form the dielectric barrier walls 420 isolated by the bit line structure 200 and the first regions A.
  • the capacitive contact holes 330 are filled with conductive material and patterned into conductive plugs 310 in step S140 .
  • the second regions B are arranged in a one-to-one correspondence with the word lines 140, and any word line 140 is located in the corresponding second region B; the first region A is located between two adjacent word lines 140.
  • the semiconductor substrate 100 can be prepared by the following method:
  • step S210 a semiconductor substrate is provided, and the semiconductor substrate 100 may be a P-type lightly doped single crystal silicon substrate or a P-type lightly doped single crystal silicon substrate.
  • Step S220 forming an isolation shallow trench on the semiconductor substrate 100 to isolate a plurality of independent active regions 110 from the surface of the semiconductor substrate 100 . Any one of the active regions 110 extends along the first direction C.
  • a dielectric is filled in the isolation shallow trench to form the shallow trench isolation structure 120, and the dielectric may be silicon oxide.
  • step S240 word line trenches extending along the second direction D are formed by etching on the semiconductor substrate 100 , and the word line trenches pass through the shallow trench isolation structure 120 and the active region 110 in sequence.
  • Step S250 forming a gate dielectric layer 130 covering the sidewalls of the word line trenches, and filling conductive structures inside the gate dielectric layer 130 to form word lines 140 .
  • Step S260 filling the word line trenches with a dielectric to form a dielectric cap 150 covering the word lines 140 .
  • the word line 140 may be partially multiplexed as the gate of the recessed transistor, the gate dielectric layer 130 may be partially multiplexed as the gate insulating layer of the recessed transistor, and the semiconductor substrate adjacent to the word line 140 may be partially multiplexed as the gate insulating layer of the recessed transistor.
  • the portion 100 can act as the channel of the recessed transistor. Recessed transistors and word lines 140 are buried in the semiconductor substrate 100 .
  • bit line structures 200 are formed on the semiconductor substrate 100 , and any of the bit line structures 200 penetrates through the first region A and the second region B.
  • the bit line structure 200 is a straight line and runs through each of the first regions A and the second regions B in sequence.
  • the bit line structure 200 extends along the third direction E, and the third direction E is perpendicular to the second direction D. As shown in FIG.
  • bit line structure 200 may be formed through the following steps S310 to S330.
  • Step S310 etch the bit line contact groove 230 on the semiconductor substrate 100 , and the bit line contact groove 230 sequentially penetrates each of the first regions A and the second region B; wherein, the bit line contact groove 230 penetrates each Active region 110 . Further, the bit line contact trench 230 exposes the source electrode or the drain electrode of the recessed transistor in the active region 110, so that the bit line structure 200 is connected to the source electrode or the drain electrode of the recessed transistor.
  • a conductive material may be sequentially deposited on the semiconductor substrate 100 to form a conductive material layer 201, and a dielectric material may be deposited to form a dielectric material layer 202; referring to FIG.
  • the patterning operation is performed to form the bit line lead 210 ; wherein the orthographic projection of the bit line lead 210 on the semiconductor substrate 100 is located in the bit line contact groove 230 , and the bit line lead 210 protrudes from the bit line contact groove 230 .
  • Step S330 referring to FIG. 10 , at least one layer of dielectric sidewalls 220 is formed on both sides of the bit line lead 210 respectively.
  • the bit line structure 200 of the present disclosure includes the bit line lead 210 and the dielectric sidewalls 220 on both sides of the bit line lead.
  • step S310 part of the active region 110 and part of the shallow trench isolation structure 120 may be removed by etching through a photolithography process to form the bit line contact trench 230 .
  • step S310 the bit line contact trench 230 passes through the second contact region of the active region 110 .
  • the bit line lead 210 passes through the second contact region of the active region 110 .
  • the conductive material layer 201 may include one or more layers of conductive materials, which may be selected from polysilicon, metals, alloys, conductive metal oxides, conductive metal nitrides, conductive metal silicides or other conductive materials.
  • the conductive material layer 201 can be formed by a deposition method, such as chemical vapor deposition, physical vapor deposition, atomic layer vapor deposition, etc.
  • the conductive material layer 201 is formed on the surface of the semiconductor substrate 100 to cover the bit line contact Slot 230.
  • the conductive material layer 201 includes a first conductive material layer 2011 , a second conductive material layer 2012 and a third conductive material layer 2013 sequentially stacked on the semiconductor substrate 100 .
  • the material of the first conductive material layer 2011 may be a polysilicon material, especially a doped polysilicon material.
  • the material of the second conductive material layer 2012 can be conductive metal nitride or conductive metal silicide, for example, titanium nitride or tungsten silicide.
  • the material of the third conductive material layer 2013 may be a metal material, such as tungsten.
  • the dielectric material layer 202 may include one or more layers of dielectric materials, and these dielectric materials may be selected from silicon oxide, silicon nitride, silicon oxynitride or other inorganic insulating materials.
  • the dielectric material layer 202 includes a first dielectric material layer 2021 and a second dielectric material layer 2022 sequentially stacked on the conductive material layer 201, wherein the first dielectric material layer 2021 and the second dielectric material layer 2021 The material of the material layer 2022 is different.
  • the material of the first dielectric material layer 2021 is silicon nitride.
  • the material of the second dielectric material layer 2022 is silicon oxide.
  • a patterning operation may be performed on the conductive material layer 201 and the dielectric material layer 202 through a photolithography process, so that the conductive material layer 201 is patterned into the conductive leads 211 and the dielectric material layer 202 is patterned to be located on the conductive Dielectric protection layer 212 on lead 211 .
  • the bit line lead 210 includes a conductive lead 211 and a dielectric protection layer 212 on the conductive lead 211 .
  • the conductive lead 211 includes a first conductive lead layer 2111 patterned from the first conductive material layer 2011 , and a second conductive lead layer patterned from the second conductive material layer 2012 . 2112 and a third conductive lead layer 2113 formed by patterning the third conductive material layer 2013;
  • the dielectric protective layer 212 includes a first dielectric protective layer 2121 formed by patterning the first dielectric material layer 2021 and a second dielectric material The second dielectric protective layer 2122 is formed by patterning the layer 2022.
  • a dielectric sidewall material layer 203 covering the surface of the conductive lead 211 and the surface of the semiconductor substrate 100 may be formed.
  • the layer of dielectric sidewall material 203 may include a first portion covering the surface of the semiconductor substrate 100 , a portion of the dielectric sidewall 220 covering the sides of the bitline leads 210 , and a second portion covering the top surface of the bitline leads 210 .
  • the first part and the second part may be removed by a photolithography process, or may be retained in step S330 and removed in a subsequent process.
  • step S330 the patterning operation of the dielectric sidewall material layer 203 is not performed, that is, the first part and the second part of the dielectric sidewall material layer 203 are retained in step S330.
  • step S330 since the bit line structure 200 includes at least one layer of dielectric sidewalls 220, in step S130, the bitline leads 210 and the dielectric sidewalls 220 may be etched in the first region A, so that the dielectric sidewalls 220 The top of the bit line lead 210 is located between the top of the bit line lead 210 and the semiconductor substrate 100 .
  • step S330 by etching the bit line leads 210 and the dielectric sidewalls 220 in the first region A, the capacitor contact holes located between two adjacent bit line structures 200 in the first region A can be made 330 has a shape with a small bottom end and a large top end.
  • one layer of dielectric sidewalls 220 may be formed, or multiple layers of dielectric sidewalls 220 may be formed.
  • the materials of the different dielectric sidewalls 220 may be different; thus, in step S140, the difference in the etching rates of the different materials may be used to make the sidewalls on both sides of the bit line structure 200 to be in the same shape. stepped.
  • step S330 at least two layers of dielectric sidewalls 220 are formed on both sides of the bit line lead 210, respectively.
  • step S130 the bit line lead 210 and the dielectric sidewalls 220 of each layer are etched in the first region A, so that the height of the dielectric sidewall 220 close to the bit line lead 210 in the adjacent two layers of the dielectric sidewalls 220 is bigger.
  • the capacitor contact holes 330 located between two adjacent bit line structures 200 in the first region A can exhibit a shape with a gradient increasing from bottom to top, further reducing the squeeze of the bit line structures on the capacitor contact holes 330 pressure.
  • a first dielectric sidewall 221 and a second dielectric sidewall 222 may be formed in sequence, wherein the first dielectric sidewall 221 is located between the second dielectric sidewall 222 and the bit line leads between 210.
  • the bit line structure 200 includes the bit line lead 210 , and the first dielectric sidewalls 221 and the second dielectric sidewalls 222 flanking the bit line lead 210 .
  • the material of the first dielectric sidewall 221 is silicon nitride.
  • the material of the second dielectric sidewall 222 is silicon oxynitride.
  • a first dielectric sidewall material layer 2031 may be formed covering the surface of the conductive lead 211 and the surface of the semiconductor substrate 100 , and a second dielectric sidewall material layer 2032 may be formed on the surface of the first dielectric sidewall material layer 2031 .
  • the bit line structure 200 includes the first dielectric sidewall 221 and the second dielectric sidewall 222 on the side of the bit line lead 210 ; the top surface of the bit line structure 200 is sequentially provided with the second portion of the first dielectric sidewall material layer 2031 and a second portion of the second dielectric sidewall material layer 2032.
  • the method for fabricating a semiconductor structure provided by the present disclosure may further include the following steps: before step S130 , referring to FIG. 11 , filling a sacrificial dielectric material between each bit line structure 200 to form a sacrificial dielectric layer 410 .
  • the sacrificial dielectric material may be silicon oxide.
  • a sacrificial dielectric material may be filled between the respective bit line structures 200 by deposition. Further, a sacrificial dielectric material may fill the gaps between the bit line structures 200 , and then the deposited sacrificial dielectric material may be planarized by a CMP (Chemical Mechanical Polishing) process to form the filled gaps between the bit line structures 200 The sacrificial dielectric layer 410.
  • CMP Chemical Mechanical Polishing
  • the capacitive contact hole 330 for accommodating the conductive plug 310 can be prepared in the first region A, and the dielectric barrier wall 420 can be prepared in the second region B .
  • the capacitive contact hole 330 or the conductive plug 310 may be formed first, and then the dielectric barrier wall 420 may be formed.
  • the dielectric barrier wall 420 may be formed first, and then the capacitive contact hole 330 and the conductive plug 310 may be formed.
  • the method for forming the dielectric barrier wall 420 will be described by taking the formation of the dielectric barrier wall 420 as an example.
  • the dielectric barrier wall 420 can be formed according to the methods of steps S410 to S440:
  • a first mask structure 430 is formed on the side of the sacrificial dielectric layer 410 away from the semiconductor substrate 100 .
  • the first mask structure 430 can cover the first region A and expose the sacrificial dielectric layer 410 in the second region B.
  • the mask structure can also expose the bit line structure 200 in the second region B. As shown in FIG.
  • step S420 the second region B is etched to remove the exposed sacrificial dielectric material; thus, a dielectric trench is formed in the second region B.
  • step S430 the first mask structure 430 is removed.
  • step S440 referring to FIG. 12 , the dielectric material is filled in the dielectric trench to form the dielectric barrier wall 420 .
  • the first mask structure 430 may include one layer of mask layers, or may include multiple layers of mask layers, as long as the second area B can be effectively exposed and the first area A can be protected.
  • the second region B may be etched by using the first mask structure 430 as a mask to remove the exposed sacrificial dielectric material.
  • the bit line structure 200 may also be partially etched, for example, the dielectric sidewall 220 and the dielectric protection layer 212 in the bit line structure 200 may be partially etched etching. Not only that, if the top surface of the bit line structure 200 is provided with the second portion of the dielectric sidewall material layer 203, the second portion of the dielectric sidewall material layer 203 may also be etched.
  • the bit line structure 200 in the second region B, before the dielectric trench is formed, includes a bit line lead 210 and a first dielectric sidewall 221 flanking the bit line lead 210 and the second dielectric sidewall 222, the bit line structure 200 includes a first conductive wiring layer 2111, a second conductive wiring layer 2112, a third conductive wiring layer 2113, a first dielectric protection layer 2121 and a second dielectric protection layer 2122 stacked in sequence .
  • a second portion of the first dielectric sidewall material layer 2031 and a second portion of the second dielectric sidewall material layer 2032 are also disposed on the top surface of the bit line structure 200 in sequence.
  • the second portion of the first dielectric sidewall material layer 2031 and the second portion of the second dielectric sidewall material layer 2032 are removed,
  • the second dielectric protective layer 2122 is removed, the first dielectric protective layer 2121 is partially removed, and the upper portions of the first dielectric sidewalls 221 and the second dielectric sidewalls 222 are both partially removed.
  • a dielectric material may be filled in the dielectric trench by a deposition method, and the dielectric material filled in the dielectric trench and the bit line structure 200 of the second region B are fitted with each other, so that two adjacent first The regions A are isolated by dielectric barrier walls 420 .
  • the dielectric material filled in the dielectric trench may be silicon nitride, so as to improve the isolation performance of the dielectric barrier wall 420 and reduce the parasitic capacitance between two adjacent conductive plugs 310 .
  • the excess dielectric material may also be removed by a CMP process.
  • the entire substrate may also be thinned to expose the sacrificial dielectric layer 410 in the first region A, as well as to expose the bit line leads 210 .
  • bit line structure 200 is etched in the first region A, so that both sidewalls of the bit line structure 200 are stepped.
  • the bit line structure 200 includes a bit line lead 210 and a dielectric sidewall 220 on the side of the bit line lead 210; the bit line lead 210 and the dielectric sidewall 220 are etched in the first region A; after the etching, The top ends of the dielectric sidewalls 220 are positioned between the top surfaces of the bit line leads 210 and the semiconductor substrate 100 .
  • different etching conditions may be selected to perform selective etching according to the materials of the bit line leads 210 and the dielectric sidewalls 220 , so that the heights of the bitline leads 210 and the dielectric sidewalls 220 are different.
  • the bit line structure 200 before step S130 , in the first region A, includes the bit line lead 210 and the first dielectric sidewalls 221 and the first dielectric sidewalls 221 on the side of the bit line lead 210 .
  • the bit line lead 210 includes a stacked conductive lead 211 and a first dielectric protective layer 2121 and a second dielectric protective layer 2122 .
  • a sacrificial dielectric material is filled between two adjacent bit line structures 200, that is, a sacrificial dielectric layer 410 has been formed; the sacrificial dielectric material is the same as the material of the second dielectric protection layer 2122, that is, the same The material of the dielectric material layer 2022 is the same.
  • the sacrificial dielectric layer 410 and the second dielectric protection layer 2122 may be exposed, that is, the sacrificial dielectric layer 410 and the second dielectric protection layer in the first area A may be exposed by etching, CMP or other methods before step S130 2122.
  • step S130 the following two selective etchings may be used to etch the first region A:
  • the first etching firstly use the first etching conditions to etch the first region A, so that the etching rate of the second dielectric material layer 2022 ⁇ the etching rate of the second dielectric sidewalls 222 ⁇ the first dielectric sidewalls 221 etching rate;
  • the first region A is etched by using the second etching conditions, so that the etching rate of the sacrificial dielectric layer 410 > the etching rate of the second dielectric sidewall 222 > the etching rate of the first dielectric sidewall 221 etch rate to completely remove the sacrificial dielectric layer 410 located in the first region A.
  • the second dielectric protective layer 2122 can protect the first dielectric protective layer 2121 and avoid the first
  • the dielectric protection layer 2121 is etched in the first etching; correspondingly, the sacrificial dielectric layer 410 located in the first region A is also retained due to the slow etching rate.
  • the etch rate of the second dielectric sidewalls 222 is lower than the etch rate of the first dielectric sidewalls 221, so that the tops of the second dielectric sidewalls 222 are higher than the first dielectric sidewalls 221.
  • the etching depth of each structure can be adjusted by controlling the etching time.
  • the height of the top surface of the first dielectric sidewall 221 can be made lower than the height of the top surface of the second dielectric protection layer 2122, so as to ensure that the first dielectric side after the second etching
  • the height of the top surface of the wall 221 is lower than the height of the top surface of the second dielectric protection layer 2122 .
  • the second dielectric protective layer 2122 can be completely removed.
  • the sacrificial dielectric layer 410 located in the first region A is also completely removed due to the high etching rate.
  • the etch rate of the second dielectric sidewalls 222 is greater than the etch rate of the first dielectric sidewalls 221 such that the tops of the second dielectric sidewalls 222 are lower than the first dielectric sidewalls 221 . Due to the protection of the second dielectric protection layer 2122 at the initial stage, it can be ensured that the height of the top surface of the first dielectric sidewall 221 is lower than that of the first dielectric protection layer 2121 .
  • the material of the second dielectric material layer 2022 and the sacrificial dielectric material are both silicon oxide; the material of the first dielectric sidewall 221 is silicon nitride; the material of the second dielectric sidewall 222 is silicon oxynitride.
  • the greater the oxygen content in the dielectric material the lower the etching rate of the dielectric material under the first etching condition, and the greater the etching rate under the second etching condition; the smaller the oxygen content in the dielectric material, Then, the higher the etching rate of the dielectric material under the first etching condition, the smaller the etching rate under the second etching condition.
  • step S130 when the first region A is etched, the second region B may not need to be protected. In other words, even if the etching process of step S130 thins the dielectric of the second region B, the performance of the second region B will not be changed.
  • the second region B is formed with a dielectric barrier 420, and the first region A and the second region B may be etched simultaneously in step S130, so that the height of the dielectric barrier 420 in the second region B is reduced.
  • step S130 when the first region A is etched, after removing the sacrificial dielectric layer 410, the etching may be continued, so as to remove the first part of the dielectric sidewall material layer 203 and expose the semiconductor substrate 100 , especially the source or drain of the active region 110 is exposed.
  • steps S120 and S130 can be implemented as follows:
  • step S120 the conductive material layer 201 , the first dielectric material layer 2021 and the second dielectric material layer 2022 are sequentially deposited on the semiconductor substrate 100 , and then the conductive material layer 201 , the first dielectric material layer 2021 and the second dielectric material layer 2021 The material layer 2022 is patterned to form the bit line lead 210; the bit line lead 210 runs through the first region A and the second region B; wherein, the material of the second dielectric material layer 2022 is silicon oxide;
  • a first dielectric sidewall 221 and a second dielectric sidewall 222 are sequentially formed on both sides of the bit line lead 210 ; wherein the material of the first dielectric sidewall 221 is silicon nitride, and the material of the second dielectric sidewall 222 is oxynitride silicon;
  • the preparation method of the semiconductor structure further includes:
  • a sacrificial dielectric material is filled between the bit line structures 200 to form a sacrificial dielectric layer 410; the sacrificial dielectric material is the same as the material of the second dielectric material layer 2022;
  • the sacrificial dielectric layer 410 is removed and filled with silicon nitride
  • step S130
  • the first region A is etched by using the first etching conditions, so that the etching rate of silicon oxide ⁇ the etching rate of silicon oxynitride ⁇ the etching rate of silicon nitride;
  • the first area A is etched by using the second etching condition, so that the etching rate of silicon oxide>the etching rate of silicon oxynitride>the etching rate of silicon nitride, so as to completely remove the sacrificial parts located in the first area A Dielectric layer 410 .
  • a plurality of electrode structures 300 may be formed, any one of the electrode structures 300 includes a conductive plug 310 and a contact pad 320 that are electrically connected to each other, and the conductive plug 310 is located in the second region B and between two adjacent bit line structures 200 and connected to the semiconductor substrate 100 .
  • the electrode structure 300 may be formed by the methods shown in steps S510 to S530.
  • Step S510 referring to FIGS. 15 to 17 , filling conductive material between two adjacent bit line structures 200 in the first region A to form a plug material layer 311 ;
  • Step S520 referring to FIG. 18 and FIG. 19, forming a contact pad material layer 321 covering the plug material layer 311;
  • Step S530 referring to FIG. 21, performing a patterning operation on the plug material layer 311 and the contact pad material layer 321, so that the contact pad material layer 321 is patterned into a plurality of contact pads 320, and the plug material layer 311 is patterned into a plurality of contact pads 320.
  • a conductive plug 310 performing a patterning operation on the plug material layer 311 and the contact pad material layer 321, so that the contact pad material layer 321 is patterned into a plurality of contact pads 320, and the plug material layer 311 is patterned into a plurality of contact pads 320.
  • step S510 polysilicon and a metal material may be sequentially filled between two adjacent bit line structures 200 in the first region A, and the metal material may be tungsten. Then, planarization can be performed by a CMP process to obtain a plug material layer 311; the plug material layer 311 includes a stacked polysilicon layer 3111 and a metal layer 3112, and is filled in the capacitive contact defined by the bit line structure 200 and the dielectric barrier wall 420 in hole 330.
  • a dielectric barrier wall 420 is formed in the first area A.
  • the surface of the entire substrate can be made flush, especially the dielectric barrier 420 and the second region B can be made flush.
  • a planarized surface may be provided for the contact pad material layer 321 .
  • a metal material may be deposited on the entire substrate to form a contact pad material layer 321 covering the plug material layer 311 .
  • the material of the contact pad material layer 321 may be the same as the material of the top of the plug material layer 311, for example, both may be tungsten.
  • the material of the contact pad material layer 321 may also cover the second region B where the dielectric barrier wall 420 has been formed.
  • the plug material layer 311 and the contact pad material layer 321 may be etched to form isolation grooves 350; the isolation grooves 350 penetrate through the contact pad material layer 321 so that the contact pad material layer 321 is patterned
  • the bottom surface of the isolation groove 350 is located on the plug material layer 311 and is not lower than the top surface of the sidewall of the bit line structure 200 .
  • the portion of the plug material layer 311 above the top surface of the sidewall of the bit line structure 200 has the largest size; when the portion is etched to form the isolation groove 350, it is more difficult to make this portion
  • the contact pad 320 cannot be electrically connected to the active region 110 due to being completely etched.
  • the present disclosure increases the size of the upper end of the plug material layer 311 and etches only the enlarged upper end portion, so as to avoid the contact pad 320 caused by the etching of the plug material layer 311 during the etching process. Disconnecting from the active region 110 can improve the yield of the semiconductor structure.
  • a second mask structure 340 may be formed on the side of the contact pad material layer 321 away from the backplane, the second mask structure 340 covers the area where the contact pad 320 is to be formed and exposes other areas, Then, etching is performed to form contact pads 320 , and the etching is continued to etch the plug material layer 311 to form isolation grooves 350 for isolating the respective contact pads 320 .
  • the contact pad 320 when the contact pad material layer 321 is patterned, can be formed into a diamond shape with chamfered corners.
  • the contact pads 320 may also have other shapes, for example, the contact pads 320 may be circular.
  • a patterning operation may be performed on the contact pad material layer 321 to form a plurality of contact pads 320 densely distributed in regular hexagons.
  • the line connecting the centers of the three contact pads 320 adjacent to each other may be an equilateral triangle;
  • the lines connecting the centers of the contact pads 320 are regular hexagons.
  • the semiconductor structure includes a semiconductor substrate 100 , a plurality of bit line structures 200 and a plurality of electrode structures 300 .
  • the semiconductor substrate 100 includes a plurality of alternately arranged first regions A and second regions B; referring to FIGS. 14 and 9 , any bit line structure 200 penetrates the first region A and the second region B; In the first region A, both sidewalls of the bit line structure 200 are stepped; referring to FIG. 21 , any electrode structure 300 includes a conductive plug 310 and a contact pad 320 that are electrically connected to each other, and the conductive plug 310 is located in the second region B and located between two adjacent bit line structures 200 and connected to the semiconductor substrate 100 .
  • the semiconductor structure provided by the present disclosure can be prepared by the above-mentioned embodiments of the preparation method of the semiconductor structure, and therefore has the same or similar technical features, such as higher production yield, etc., which will not be described in detail in the present disclosure.
  • Other details and features of the semiconductor structure provided by the present disclosure have been described in the above-mentioned embodiments of the method for fabricating the semiconductor structure, or can be reasonably deduced from the contents described in the above-mentioned embodiments of the method for fabricating the semiconductor structure. This will not be repeated here.
  • the bit line structure 200 includes a bit line lead 210 and at least one layer of dielectric sidewalls 220 on both sides of the bit line lead 210; in the first region A, The top ends of the dielectric sidewalls 220 are located between the top ends of the bit line leads 210 and the semiconductor substrate 100 .
  • the bit line structure 200 includes a bit line lead 210 and at least two layers of dielectric sidewalls 220 on both sides of the bit line lead 210; in the first region A, The height of the dielectric sidewall 220 close to the bit line lead 210 in the adjacent two layers of the dielectric sidewall 220 is larger.
  • an isolation groove 350 is provided between two adjacent electrode structures 300 , and the bottom surface of the isolation groove 350 is not lower than the sidewall of the bit line structure 200 . top.
  • each of the contact pads 320 is densely distributed in a regular hexagon.
  • Embodiments of the present disclosure further provide a storage device, where the storage device includes any of the storage devices described in the semiconductor structure embodiments above.
  • the storage device may be a DRAM (Dynamic Random Access Memory) or other type of storage device. Since the memory device has any of the semiconductor structures described in the above-mentioned semiconductor structure embodiments, it has the same beneficial effects, and details are not described herein again in this disclosure.

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Abstract

本公开提供了一种半导体结构及其制备方法、存储装置，属于半导体技术领域。该半导体结构的制备方法包括：提供半导体衬底，所述半导体衬底包括多个交替设置的第一区域和第二区域；在所述半导体衬底上形成多个位线结构，任一所述位线结构贯穿所述第一区域和所述第二区域；在所述第一区域对所述位线结构进行刻蚀，使得所述位线结构的两侧侧壁均呈台阶状；形成多个电极结构，任意一个所述电极结构包括相互电连接的导电栓塞和接触垫，所述导电栓塞位于所述第一区域且位于相邻两个所述位线结构之间并与所述半导体衬底连接。半导体结构的制备方法能够提高半导体结构的良率。 (图21)

Description

半导体结构及其制备方法、存储装置
交叉引用
本公开要求于2020年9月27日提交的申请号为202011034963.5、名称均为“半导体结构及其制备方法、存储装置”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体技术领域，尤其涉及一种半导体结构及其制备方法、存储装置。
背景技术
动态随机存储器可以包括层叠设置的凹陷晶体管阵列层、布线层和电容层。其中，布线层包括位线结构、导电栓塞和接触垫。位线结构与凹陷晶体管的源极电连接；相邻两个位线结构之间具有被电介质挡墙隔离的电容接触孔，导电栓塞填充于电容接触孔中以与凹陷晶体管的漏极连接，接触垫连接于导电栓塞远离凹陷晶体管阵列层的一侧，以便与电容电连接。
然而，随着制程尺寸的不断缩小，动态随机存储器容易出现导电栓塞断路的不良。
所述背景技术部分公开的上述信息仅用于加强对本公开的背景的理解，因此它可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
本公开的目的在于提供一种半导体结构及其制备方法、存储装置，提高半导体结构的良率。
为实现上述发明目的，本公开采用如下技术方案：
根据本公开的第一个方面，提供一种半导体结构的制备方法，包括：
提供半导体衬底，所述半导体衬底包括多个交替设置的第一区域和第二区域；
在所述半导体衬底上形成多个位线结构，任一所述位线结构贯穿所述第一区域和所述第二区域；
在所述第一区域对所述位线结构进行刻蚀，使得所述位线结构的两侧侧壁均呈台阶状；
形成多个电极结构，任意一个所述电极结构包括相互电连接的导电栓塞和接触垫，所述导电栓塞位于所述第一区域且位于相邻两个所述位线结构之间并与所述半导体衬底连接。
根据本公开的第二个方面，提供一种半导体结构，包括：
半导体衬底，包括多个交替设置的第一区域和第二区域；
多个位线结构，任一所述位线结构贯穿所述第一区域和所述第二区域；在所述第一区域，所述位线结构的两侧侧壁均呈台阶状；
多个电极结构，任意一个所述电极结构包括相互电连接的导电栓塞和接触垫，所述导电栓塞位于所述第一区域且位于相邻两个所述位线结构之间并与所述半导体衬底连接。
根据本公开的第三个方面，提供一种存储装置，包括上述的半导体结构。
根据本公开提供的半导体结构及其制备方法、存储装置中，电容接触孔两侧的位线结构的侧壁呈台阶状，因此可以减小位线结构对电容接触孔的挤压并提高导电栓塞与接触垫的接触面积，进而避免导电栓塞与接触垫断路，提高半导体结构的良率。
附图说明
通过参照附图详细描述其示例实施方式，本公开的上述和其它特征及优点将变得更加明显。
图1是相关技术中布线层的剖切电镜图。
图2是相关技术中布线层的俯视电镜图。
图3是本公开一种实施方式的半导体结构的制备流程示意图。
图4是本公开一种实施方式的半导体衬底的俯视结构示意图。
图5是本公开一种实施方式的半导体衬底的剖视结构示意图，剖切方向为有源区的延伸方向。
图6是本公开一种实施方式的形成位线接触槽的结构示意图。
图7是本公开一种实施方式的形成导电材料层和电介质材料层的结构示意图。
图8是本公开一种实施方式的形成位线引线的结构示意图。
图9是本公开一种实施方式的形成位线引线的俯视结构示意图。
图10是本公开一种实施方式的形成电介质侧壁的结构示意图。
图11是本公开一种实施方式的形成牺牲电介质层的结构示意图。
图12是本公开一种实施方式的形成电介质挡墙的立体结构示意图。
图13是本公开一种实施方式的在第一区域对位线结构进行第一次刻蚀后的立体结构示意图。
图14是本公开一种实施方式的在第一区域对位线结构进行第二次刻蚀后的立体结构示意图。
图15是本公开一种实施方式的形成栓塞材料层的立体结构示意图。
图16是本公开一种实施方式的形成栓塞材料层的剖视结构示意图，剖切方向为平行于字线方向。
图17是本公开一种实施方式的形成栓塞材料层俯视结构示意图。
图18是本公开一种实施方式的形成接触垫材料层立体结构示意图。
图19是本公开一种实施方式的形成接触垫材料层剖视结构示意图。
图20是本公开一种实施方式的形成第二掩膜结构的剖视结构示意图。
图21是本公开一种实施方式的形成电极结构的剖视结构示意图。
图中主要元件附图标记说明如下：
100、半导体衬底；110、有源区；120、浅槽隔离结构；130、栅极电介质层；140、字线；150、电介质顶盖；200、位线结构；201、导电材料层；2011、第一导电材料层；2012、第二导电材料层；2013、第三导电材料层；202、电介质材料层；2021、第一电介质材料层；2022、第二电介质材料层；203、电介质侧壁材料层；2031、第一电介质侧壁材料层；2032、第二电介质侧壁材料层；210、位线引线；211、导电引线；2111、第一导电引线层；2112、第二导电引线层；2113、第三导电引线层；212、电介质保护层；2121、第一电介质保护层；2122、第二电介质保护层；220、电介质侧壁；221、第一电介质侧壁；222、第二电介质侧壁；230、位线接触槽；300、电极结构；310、导电栓塞；311、栓塞材料层；3111、多晶硅层；3112、金属层；320、接触垫；321、接触垫材料层；330、电容接触孔；340、第二掩膜结构；350、隔离凹槽；410、牺牲电介质层；420、电介质挡墙；430、第一掩膜结构；A、第一区域；B、第二区域。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。
在图中，为了清晰，可能夸大了区域和层的厚度。在图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而没有所述特定细节中的一个或更多，或者可以采用其它的方法、组元、材料等。在其它情况下，不详细示出或描述公知结构、材料或者操作以避免模糊本公开的主要技术创意。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。用语“第一”和“第二”等仅作为标记使用，不是对其对象的数量限制。
在本公开中，当描述一个结构的高度时，指的是该结构远离半导体衬底的一端与 半导体衬底之间的尺寸。当描述一个结构的顶面/顶端时，指的是该结构远离半导体衬底的表面/端部。
在相关技术中，在制备布线层时，容易出现导电栓塞断路不良。图1为相关技术中一种布线层的剖视的电镜图，图2为相关技术中一种金属布线层的俯视的电镜图。根据图1和图2可以看出，导电栓塞310用于与接触垫320电连接。然而，在图1和图2中，还可以看到，接触垫320a与导电栓塞310a之间出现了断路不良。
发明人通过对该不良进行大量研究和分析，认为该不良是位线结构挤压电容接触孔，导致电容接触孔中的导电栓塞与接触垫的接触面积减小产生的。然而，随着制程尺寸的不断减小，难以通过减小位线结构的尺寸来提高动态随机存储器的良率；这是由于，减小位线结构的尺寸会导致位线结构的深宽比过大而容易倒塌。
本公开提供一种半导体结构的制备方法，参见图3，该半导体结构的制备方法包括：
步骤S110，参见图4和图5，提供半导体衬底100，半导体衬底100包括多个交替设置的第一区域A和第二区域B；
步骤S120，参见图9和图10，在半导体衬底100上形成多个位线结构200，任一位线结构200贯穿第一区域A和第二区域B；
步骤S130，参见图14，在第一区域A对位线结构200进行刻蚀，使得位线结构200的两侧侧壁均呈台阶状；
步骤S140，参见图21，形成多个电极结构300，任意一个电极结构300包括相互电连接的导电栓塞310和接触垫320，导电栓塞310位于第一区域A且位于相邻两个位线结构200之间并与半导体衬底100连接。
根据本公开提供的半导体结构的制备方法，在步骤S130中，参见图14，可以制备出用于形成导电栓塞310的电容接触孔330，该电容接触孔330位于第一区域A且位于相邻两个位线结构200之间。由于位线结构200的侧壁在第一区域A呈现出台阶状，因此电容接触孔330呈现出底部小、顶部大的特点，能够增大电容接触孔330顶部的尺寸，避免位线结构挤压电容接触孔330的顶部而导致导电栓塞310被夹断。相应的，在步骤S140中，参见图21，在形成导电栓塞310时，能够使得导电栓塞310的顶部的尺寸更大，增大导电栓塞310制备的工艺窗口并避免导电栓塞310在制备过程中被刻蚀断路，保证接触垫320能够通过导电栓塞310与半导体衬底100电连接。如此，本公开的半导体结构的制备方法，能够提高半导体结构的制备良率并增大半导体结构的工艺窗口，降低半导体结构的制备成本。
根据本公开提供的半导体结构的制备方法，参见图21，所制备的半导体结构可以包括半导体衬底100、多个位线结构200和多个电极结构300；其中，参见图4，半导体衬底100包括多个交替设置的第一区域A和第二区域B。任一位线结构200贯穿第一区域A和第二区域B；在第一区域A，位线结构200的两侧侧壁均呈台阶状；多个 电极结构300，任意一个电极结构300包括相互电连接的导电栓塞310和接触垫320，导电栓塞310位于第一区域A且位于相邻两个位线结构200之间并与半导体衬底100连接。该半导体结构可以采用上述的半导体结构的制备方法进行制备，因此具有相同或者类似的技术效果，本公开在此不再赘述。
下面，结合附图对本公开提供的半导体结构的制备方法的原理、细节和效果做进一步地解释和说明。
在步骤S110中，可以提供一半导体衬底100，参见图4和图5，该半导体衬底100填埋有凹陷晶体管和字线140，其中，字线140可以与凹陷晶体管的栅极连接或者局部复用为凹陷晶体管的栅极。
其中，半导体衬底100的材料可以选自Si、Ge、SiGe、SiC、SiGeC、InAs、GaAs、InP或者其它III/V化合物半导体，还包括这些半导体构成的多层结构等或者为绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。半导体衬底100还可以进行掺杂，例如可以局部进行轻掺杂以形成凹陷晶体管的沟道，局部进行重掺杂以使得凹陷晶体管的源极和漏极能够与位线结构200和电极结构300电连接。
半导体衬底100设置有隔离浅沟槽以使得半导体衬底100形成有多个独立的有源区110；隔离浅槽内可以填充有电介质以形成浅槽隔离结构120，例如可以填充有氧化硅等电介质。参见图4，各个有源区110排列成多个沿第一方向C延伸且相互平行的有源区列，任意一个有源区列沿可以包括多个有源区110且有源区110的延伸方向为第一方向C。
半导体衬底100还设置有沿第二方向D的字线沟槽，第二方向D与第一方向C的夹角小于90°。其中，字线沟槽沿第二方向D依次贯穿浅槽隔离结构120和有源区110，并在有源区110暴露半导体衬底100。在一些实施方式中，还可以对字线沟槽所暴露的半导体衬底100表面的掺杂剂量进行调节，例如通过离子注入等方法增大字线沟槽底部的掺杂剂量或者注入类型相反的离子等，进而调节凹陷晶体管的阈值电压。在字线沟槽内，可以具有覆盖字线沟槽的侧壁的栅极电介质层130，以及在栅极电介质层130内侧的字线140。栅极电介质层130在有源区110可以作为凹陷晶体管的栅极绝缘层，且字线140可以局部复用为凹陷晶体管的栅极。可以理解的是，该栅极电介质层130可以为一层绝缘材料，也可以为多层绝缘材料的复合，还可以在多层绝缘材料中包覆气隙，本公开对此不做限定。在有源区110，与字线140对应的半导体衬底100部分可以为凹陷晶体管的沟道，半导体衬底100与沟道连接的部分可以作为凹陷晶体管的源极和漏极。字线140沟槽内还可以填充有绝缘材料以形成电介质顶盖150； 该电介质顶盖150覆盖字线140，使得字线140填埋于半导体衬底100中。可选地，半导体衬底100表面还可以设置有绝缘材料以形成保护层，保护层覆盖半导体衬底100并保护有源区110。在本公开的一种实施方式中，该保护层的材料可以为氮化硅。
可选地，半导体衬底100的表面还可以进行重掺杂，以保证凹陷晶体管的源极和漏极具有良好的导电性，进而保证位线结构200和导电栓塞310能够与凹陷晶体管的源极和漏极电连接。
在本公开的一种实施方式中，沿第二方向D，每三列有源区列为一个周期进行周期性排布；沿与第二方向D垂直且在半导体衬底100内的平面内的第三方向E，有源区列周期性排布。换言之，在同一有源区列中，有源区110的长度与同一有源区列中相邻两个有源区110的间距的和为设定尺寸；在相邻两个有源区列中，将一个有源区列的图案沿第二方向D平移至相邻的有源区列后，该平移后的有源区列的图案可以沿第一方向C中的一个具体方向平移1/3个设定尺寸，而与该相邻的有源区列的有源区110图案重合。在相邻两个有源区列中，将一个有源区列的图案沿第三方向E平移至相邻的有源区列后，该平移后的有源区列的图案与该相邻的有源区列的有源区110图案重合。
可选的，任意一个有源区110穿过有两个字线沟槽，使得两根字线140穿过有源区110。如此，从俯视角度，有源区110被两个字线140分割为第一接触区和第二接触区；其中，第二接触区位于贯穿该有源区110的两根字线140之间，第一接触区数量为两个且分别位于第二接触区的两侧。
在所提供的半导体衬底100中，可以包括多个交替设置的第一区域A和第二区域B，其中，第一区域A和第二区域B的延伸方向均为第二方向D。换言之，第一区域A和第二区域B的延伸方向均与字线140的延伸方向一致。其中，第一区域A可以包括有任意一个有源区110的至少部分区域，且第二区域B可以包括任意一个有源区110的至少部分区域。在本公开提供的半导体衬底100中，第二区域B用于形成隔离各个第一区域A的电介质挡墙420，第一区域A用于形成被位线结构200和电介质挡墙420所隔离出的电容接触孔330，这些电容接触孔330用于在步骤S140中填充导电材料并被图案化为导电栓塞310。
可选地，第二区域B与字线140一一对应设置，且任意一个字线140在对应的第 二区域B内；第一区域A位于相邻两个字线140之间。
可选地，可以通过如下方法制备半导体衬底100：
步骤S210，提供一种半导体衬底，半导体衬底100可以为P型轻掺杂的单晶硅衬底或者P型轻掺杂的单晶硅衬底。
步骤S220，在半导体衬底100上形成隔离浅沟槽，以将半导体衬底100的表面隔离出多个独立的有源区110。任意一个有源区110沿第一方向C延伸。
步骤S230，在隔离浅沟槽内填充电介质以形成浅槽隔离结构120，该电介质可以为氧化硅。
步骤S240，在半导体衬底100上刻蚀形成沿第二方向D延伸的字线沟槽，字线沟槽依次贯穿浅槽隔离结构120和有源区110。
步骤S250，形成覆盖字线沟槽的侧壁的栅极电介质层130，并在栅极电介质层130内侧填充导电结构以形成字线140。
步骤S260，在字线沟槽内填充电介质，以形成覆盖字线140的电介质顶盖150。
如此，在有源区110，字线140可以局部复用为凹陷晶体管的栅极，栅极电介质层130可以局部复用为凹陷晶体管的栅极绝缘层，与字线140相邻的半导体衬底100部分可以作为凹陷晶体管的沟道。凹陷晶体管和字线140填埋于半导体衬底100中。
在步骤S120中，在半导体衬底100上形成多个位线结构200，任一位线结构200贯穿第一区域A和第二区域B。可选地，位线结构200为直线并依次贯穿各个第一区域A和第二区域B。更进一步地，位线结构200沿第三方向E延伸，第三方向E垂直于第二方向D。
可选地，可以通过如下步骤S310～步骤S330形成位线结构200。
步骤S310，参见图6，在半导体衬底100上刻蚀出位线接触槽230，位线接触槽230依次贯穿各个第一区域A和第二区域B；其中，位线接触槽230穿过各个有源区110。进一步地，位线接触槽230在有源区110暴露凹陷晶体管的源极或者漏极，以便位线结构200与凹陷晶体管的源极或者漏极连接。
步骤S320，参见图7，可以在半导体衬底100上依次沉积导电材料以形成导电材料层201、沉积电介质材料以形成电介质材料层202；参见图8，对导电材料层201和电介质材料层202进行图案化操作以形成位线引线210；其中，位线引线210在半导体衬底100上的正投影位于位线接触槽230内，位线引线210凸出于位线接触槽230。
步骤S330，参见图10，在位线引线210的两侧面分别形成至少一层电介质侧壁220。如此，本公开的位线结构200包括位线引线210和位线引两侧面的电介质侧壁220。
可选地，在步骤S310中，可以通过光刻工艺，刻蚀去除部分有源区110及部分浅槽隔离结构120以形成位线接触槽230。
在本公开的一种实施方式中，在步骤S310中，位线接触槽230穿过有源区110的第二接触区。相应的，参见图9，位线引线210穿过有源区110的第二接触区。
在步骤S320中，导电材料层201可以包括一层或者多层导电材料，这些导电材料可以选自多晶硅、金属、合金、导电金属氧化物、导电金属氮化物、导电金属硅化物或者其他导电材料。可以通过沉积的方法形成导电材料层201，例如通过化学气相沉积、物理气相沉积、原子层气相沉积等方法形成导电材料层201，导电材料层201形成于半导体衬底100的表面以覆盖位线接触槽230。
示例性地，在本公开的一种实施方式中，导电材料层201包括依次层叠于半导体衬底100上的第一导电材料层2011、第二导电材料层2012和第三导电材料层2013。其中，第一导电材料层2011的材料可以为多晶硅材料，尤其是可以为掺杂的多晶硅材料。第二导电材料层2012的材料可以为导电金属氮化物、导电金属硅化物，例如可以为氮化钛或者硅化钨。第三导电材料层2013的材料可以为金属材料，例如可以为钨。
在步骤S320中，电介质材料层202可以包括一层或者多层电介质材料，这些电介质材料可以选自氧化硅、氮化硅、氮氧化硅或者其他无机绝缘材料。在本公开的一种实施方式中，电介质材料层202包括依次层叠于导电材料层201上的第一电介质材料层2021和第二电介质材料层2022，其中，第一电介质材料层2021和第二电介质材料层2022的材料不同。
在本公开的一种实施方式中，第一电介质材料层2021的材料为氮化硅。
在本公开的一种实施方式中，第二电介质材料层2022的材料为氧化硅。
在步骤S320中，可以通过光刻工艺对导电材料层201和电介质材料层202进行图案化操作，以使得导电材料层201被图案化为导电引线211且使得电介质材料层202被图案化为位于导电引线211上的电介质保护层212。如此，该位线引线210包括导电引线211和位于导电引线211上的电介质保护层212。
在本公开的一种实施方式中，导电引线211包括由第一导电材料层2011图案化而形成的第一导电引线层2111、由第二导电材料层2012图案化而形成的第二导电引线层2112和由第三导电材料层2013图案化而形成的第三导电引线层2113；电介质保护层212包括由第一电介质材料层2021图案化而形成的第一电介质保护层2121和由第二电介质材料层2022图案化而形成的第二电介质保护层2122。
可选地，在步骤S330中，可以形成覆盖导电引线211的表面和半导体衬底100表面的电介质侧壁材料层203。该电介质侧壁材料层203可以包括覆盖半导体衬底100 表面的第一部分、覆盖位线引线210侧面的电介质侧壁220部分和覆盖位线引线210顶面的第二部分。其中，第一部分和第二部分既可以通过光刻工艺去除，也可以在步骤S330中保留并在后续工序中去除。
优选地，步骤S330中，不对电介质侧壁材料层203进行图案化操作，即在步骤S330中保留电介质侧壁材料层203的第一部分和第二部分。
在步骤S330中，由于位线结构200包括至少一层电介质侧壁220，因此在步骤S130中，可以在第一区域A对位线引线210和电介质侧壁220进行刻蚀，使得电介质侧壁220的顶端位于位线引线210的顶端与半导体衬底100之间。换言之，在步骤S330中，通过在第一区域A对位线引线210和电介质侧壁220进行刻蚀，可以使得位于第一区域A中的相邻两个位线结构200之间的电容接触孔330呈现下端小、顶端大的形状。
在步骤S330中，可以形成一层电介质侧壁220，也可以形成多层电介质侧壁220。当形成多层电介质侧壁220时，可以使得不同电介质侧壁220的材料不相同；如此，在步骤S140中，可以利用不同材料的刻蚀速率的差异使得位线结构200的两侧侧壁呈台阶状。
优选地，在步骤S330中，在位线引线210的两侧面分别形成至少两层电介质侧壁220。如此，在步骤S130中，在第一区域A对位线引线210和各层电介质侧壁220进行刻蚀，使得相邻两层电介质侧壁220中靠近位线引线210的电介质侧壁220的高度更大。如此，可以使得位于第一区域A中的相邻两个位线结构200之间的电容接触孔330呈现出从下向上梯度增大的形状，进一步减小位线结构对电容接触孔330的挤压。
在本公开的一种实施方式中，参见图10，可以依次形成第一电介质侧壁221和第二电介质侧壁222，其中，第一电介质侧壁221位于第二电介质侧壁222和位线引线210之间。如此，位线结构200包括位线引线210，以及位于位线引线210侧面的第一电介质侧壁221和第二电介质侧壁222。可选地，第一电介质侧壁221的材料为氮化硅。可选地，第二电介质侧壁222的材料为氮氧化硅。
示例性地，可以形成覆盖导电引线211的表面和半导体衬底100表面的第一电介质侧壁材料层2031，并在第一电介质侧壁材料层2031的表面形成第二电介质侧壁材料层2032。如此，位线结构200包括位于位线引线210侧面的第一电介质侧壁221和第二电介质侧壁222；位线结构200的顶面依次设置有第一电介质侧壁材料层2031的第二部分和第二电介质侧壁材料层2032的第二部分。
可选地，本公开提供的半导体结构的制备方法还可以包括如下步骤：在步骤S130之前，参见图11，在各个位线结构200之间填充牺牲电介质材料，以形成牺牲电介质层410。
可选地，牺牲电介质材料可以为氧化硅。
可选地，可以通过沉积的方法形成在各个位线结构200之间填充牺牲电介质材料。 进一步地，牺牲电介质材料可以填充满位线结构200之间的间隙，然后通过CMP(化学机械抛光)工艺对沉积的牺牲电介质材料进行平坦化，以形成填充满了位线结构200之间的间隙的牺牲电介质层410。
根据本公开提供的半导体结构的制备方法，在形成牺牲电介质层410后，可以在第一区域A制备用于容置导电栓塞310的电容接触孔330，以及在第二区域B制备电介质挡墙420。在一些实施方式中，可以先形成电容接触孔330或者先形成导电栓塞310，然后再形成电介质挡墙420。在另外一些实施方式中，可以先形成电介质挡墙420，然后再形成电容接触孔330和导电栓塞310。
下面，以先形成电介质挡墙420为例，对形成电介质挡墙420的方法进行介绍。
在该示例中，可以按照步骤S410～步骤S440的方法形成电介质挡墙420：
步骤S410，在牺牲电介质层410远离半导体衬底100的一侧形成第一掩膜结构430，该第一掩膜结构430可以覆盖第一区域A并在第二区域B暴露牺牲电介质层410。在一些实施方式中，该掩膜结构在第二区域B还可以暴露位线结构200。
步骤S420，对第二区域B进行刻蚀，以便去除暴露的牺牲电介质材料；如此，在第二区域B形成有电介质沟槽。
步骤S430，去除第一掩膜结构430。
步骤S440，参见图12，在电介质沟槽内填充电介质材料，以形成电介质挡墙420。
在步骤S410中，第一掩膜结构430可以包括一层掩膜层，也可以包括多层掩膜层，以能够有效暴露第二区域B并保护第一区域A为准。
在步骤S420中，可以以第一掩膜结构430为掩膜，对第二区域B进行刻蚀，以去除暴露的牺牲电介质材料。
进一步地，在第二区域B，在刻蚀去除牺牲电介质材料时，位线结构200也可能被部分刻蚀，例如位线结构200中的电介质侧壁220、电介质保护层212等可能会发生部分刻蚀。不仅如此，如果位线结构200的顶面设置有电介质侧壁材料层203的第二部分，该电介质侧壁材料层203的第二部分也可以被刻蚀。
举例而言，在本公开的一种实施方式中，在第二区域B，在形成电介质沟槽之前，位线结构200包括位线引线210和位于位线引线210侧面的第一电介质侧壁221和第二电介质侧壁222，位线结构200包括依次层叠的第一导电引线层2111、第二导电引线层2112、第三导电引线层2113、第一电介质保护层2121和第二电介质保护层2122。在位线结构200的顶面上还依次设置有第一电介质侧壁材料层2031的第二部分和第二电介质侧壁材料层2032的第二部分。在对第二区域B进行刻蚀以形成电介质沟槽之后，在第二区域B，第一电介质侧壁材料层2031的第二部分和第二电介质侧壁材料层2032的第二部分被去除，第二电介质保护层2122被去除，第一电介质保护层2121被部分去除，第一电介质侧壁221和第二电介质侧壁222的上部均被部分去除。
在步骤S440中，可以通过沉积的方法在电介质沟槽内填充电介质材料，填充于电 介质沟槽内的电介质材料与第二区域B的位线结构200相互嵌合，进而使得相邻两个第一区域A之间通过电介质挡墙420隔离。
可选地，填充于电介质沟槽内的电介质材料，可以为氮化硅，以提高电介质挡墙420的隔离性能，并减小相邻两个导电栓塞310之间的寄生电容。
可选地，在电介质沟槽内填充电介质材料后，还可以通过CMP工艺去除多余的电介质材料。优选地，在该CMP工艺中，还可以对整个衬底进行减薄，以便在第一区域A暴露牺牲电介质层410，以及暴露位线引线210。
可以理解的是，上述示例仅仅为形成电介质挡墙420的一种方法示例；在本公开的实施方式中，还可以采用其他方法形成电介质挡墙420，本公开对此不做详述。
在步骤S130中，在第一区域A对位线结构200进行刻蚀，使得位线结构200的两侧侧壁均呈台阶状。可选地，位线结构200包括位线引线210，以及位于位线引线210侧面电介质侧壁220；在第一区域A对位线引线210和电介质侧壁220进行刻蚀；在刻蚀后，使得电介质侧壁220的顶端位于位线引线210的顶面与半导体衬底100之间。
可选地，可以根据位线引线210和电介质侧壁220的材料，选择不同的刻蚀条件进行选择性刻蚀，进而使得位线引线210的高度与电介质侧壁220的高度不同。
示例性地，在本公开的一种实施方式中，在步骤S130之前，在第一区域A，位线结构200包括位线引线210以及位于位线引线210侧面的第一电介质侧壁221和第二电介质侧壁222。位线引线210包括层叠的导电引线211和第一电介质保护层2121和第二电介质保护层2122。在第一区域A中，相邻两个位线结构200之间填充有牺牲电介质材料，即已经形成有牺牲电介质层410；牺牲电介质材料与第二电介质保护层2122的材料相同，即与第二电介质材料层2022的材料相同。在第一区域A，可以暴露牺牲电介质层410和第二电介质保护层2122，即在步骤S130之前可以通过刻蚀、CMP或者其他方法暴露第一区域A的牺牲电介质层410和第二电介质保护层2122。
在步骤S130中，可以采用如下两次选择性刻蚀对第一区域A进行刻蚀：
第一次刻蚀：先采用第一刻蚀条件对第一区域A进行刻蚀，使得第二电介质材料层2022的刻蚀速率＜第二电介质侧壁222的刻蚀速率＜第一电介质侧壁221的刻蚀速率；
第二次刻蚀：采用第二刻蚀条件对第一区域A进行刻蚀，使得牺牲电介质层410的刻蚀速率＞第二电介质侧壁222的刻蚀速率＞第一电介质侧壁221的刻蚀速率，以完全去除位于第一区域A的牺牲电介质层410。
在第一次刻蚀中，参见图13，由于第一刻蚀条件对第二电介质材料层2022的刻蚀速率最低，因此第二电介质保护层2122可以保护第一电介质保护层2121，避免第一电介质保护层2121在第一次刻蚀中被刻蚀；相应的，位于第一区域A中的牺牲电介质层410也因刻蚀速率慢而被保留。第二电介质侧壁222的刻蚀速率小于第一电介 质侧壁221的刻蚀速率，使得第二电介质侧壁222的顶部高于第一电介质侧壁221。
在第一次刻蚀中，可以通过控制刻蚀时间进而调整各个结构的刻蚀深度。优选地，在第一次刻蚀后，可以使得第一电介质侧壁221顶面的高度低于第二电介质保护层2122的顶面的高度，进而保证在第二次刻蚀后第一电介质侧壁221顶面的高度低于第二电介质保护层2122的顶面的高度。
在第二次刻蚀中，参见图14，由于第二刻蚀条件对第二电介质材料层2022的刻蚀速率最大，因此第二电介质保护层2122可以被完全去除。相应的，位于第一区域A中的牺牲电介质层410也因刻蚀速率大而被完全去除。第二电介质侧壁222的刻蚀速率大于第一电介质侧壁221的刻蚀速率，使得第二电介质侧壁222的顶部低于第一电介质侧壁221。由于第二电介质保护层2122在开始阶段的保护，可以保证第一电介质侧壁221的顶面高度低于第一电介质保护层2121的高度。
优选地，第二电介质材料层2022的材料和牺牲电介质材料均为氧化硅；第一电介质侧壁221的材料为氮化硅；第二电介质侧壁222的材料为氮氧化硅。电介质材料中氧的含量越大，则该电介质材料在第一刻蚀条件下的刻蚀速率越小，在第二刻蚀条件下的刻蚀速率越大；电介质材料中氧的含量越小，则该电介质材料在第一刻蚀条件下的刻蚀速率越大，在第二刻蚀条件下的刻蚀速率越小。
可选地，在步骤S130中，在对第一区域A进行刻蚀时，可以无需对第二区域B进行保护。换言之，即便步骤S130的刻蚀过程减薄了第二区域B的电介质，也不会导致第二区域B的性能改变。示例性地，第二区域B形成有电介质挡墙420，在步骤S130中可以同时对第一区域A和第二区域B进行刻蚀，使得第二区域B中的电介质挡墙420的高度降低。
可选地，在步骤S130中，在对第一区域A进行刻蚀时，在去除牺牲电介质层410后，还可以继续刻蚀，以便去除电介质侧壁材料层203的第一部分，暴露半导体衬底100，尤其是暴露有源区110的源极或者漏极。
作为一种具体示例，可以按照如下方法实现步骤S120和步骤S130：
在步骤S120中，在半导体衬底100上依次沉积形成导电材料层201、第一电介质材料层2021和第二电介质材料层2022，然后对导电材料层201、第一电介质材料层2021和第二电介质材料层2022进行图案化操作以形成位线引线210；位线引线210贯穿第一区域A和第二区域B；其中，第二电介质材料层2022的材料为氧化硅；
在位线引线210的两侧依次形成第一电介质侧壁221和第二电介质侧壁222；其中，第一电介质侧壁221的材料为氮化硅，第二电介质侧壁222的材料为氮氧化硅；
在步骤S130之前，半导体结构的制备方法还包括：
在形成多个位线结构200后，在位线结构200之间填充牺牲电介质材料以形成牺牲电介质层410；牺牲电介质材料与第二电介质材料层2022的材料相同；
在第二区域B，移除牺牲电介质层410并填充氮化硅；
在步骤S130中：
采用第一刻蚀条件对第一区域A进行刻蚀，使得氧化硅的刻蚀速率＜氮氧化硅的刻蚀速率＜氮化硅的刻蚀速率；
采用第二刻蚀条件对第一区域A进行刻蚀，使得氧化硅的刻蚀速率＞氮氧化硅的刻蚀速率＞氮化硅的刻蚀速率，以完全移除位于第一区域A的牺牲电介质层410。
在步骤S140中，可以形成多个电极结构300，任意一个电极结构300包括相互电连接的导电栓塞310和接触垫320，导电栓塞310位于第二区域B且位于相邻两个位线结构200之间并与半导体衬底100连接。
可选地，可以通过步骤S510～步骤S530所示的方法形成电极结构300。
步骤S510，参见图15～图17，在第一区域A的相邻两个位线结构200之间填充导电材料，以形成栓塞材料层311；
步骤S520，参见图18和图19，形成覆盖栓塞材料层311的接触垫材料层321；
步骤S530，参见图21，对栓塞材料层311和接触垫材料层321进行图案化操作，使得接触垫材料层321被图案化为多个接触垫320，且使得栓塞材料层311被图案化为多个导电栓塞310。
在步骤S510中，可以依次向第一区域A的相邻两个位线结构200之间依次填充多晶硅和金属材料，金属材料可以为钨。然后，可以通过CMP工艺进行平坦化，获得栓塞材料层311；该栓塞材料层311包括层叠的多晶硅层3111和金属层3112，且填充于位线结构200和电介质挡墙420所界定出的电容接触孔330中。
优选地，参见图14和15，在步骤S510之前，在第一区域A形成电介质挡墙420。在步骤S510中，在CMP工艺中，可以使得整个衬底的表面齐平，尤其是使得电介质挡墙420和第二区域B齐平。如此，可以为接触垫材料层321提供平坦化表面。
在步骤S520中，可以在整个衬底上沉积金属材料，以形成覆盖栓塞材料层311的接触垫材料层321。可选地，接触垫材料层321的材料可以与栓塞材料层311顶部的材料相同，例如可以都为钨。
可以理解的是，在步骤S520中，接触垫材料层321的材料还可以覆盖已经形成了电介质挡墙420的第二区域B。
在步骤S530中，参见图21，可以对栓塞材料层311和接触垫材料层321进行刻蚀以形成隔离凹槽350；隔离凹槽350贯穿接触垫材料层321以使得接触垫材料层321被图案化为多个分离的接触垫320；隔离凹槽350的底面位于栓塞材料层311且不低于位线结构200的侧壁的顶面。
在该实施方式中，栓塞材料层311在位线结构200的侧壁的顶面以上的部分具有最大的尺寸；在该部分进行刻蚀以形成隔离凹槽350时，更不容易在使得该部分被完全刻蚀而导致接触垫320无法与有源区110电连接。相对于现有技术，本公开增大了栓塞材料层311上端的尺寸并仅对该增大了的上端部分进行刻蚀，避免刻蚀过程中导 致栓塞材料层311刻蚀断路而导致接触垫320与有源区110断路，能够提高半导体结构的良率。
在一些实施方式中，参见图20，可以在接触垫材料层321远离背板的一侧形成第二掩膜结构340，第二掩膜结构340覆盖待形成接触垫320的区域并暴露其他区域，然后进行刻蚀以形成接触垫320，并继续刻蚀以对栓塞材料层311进行刻蚀，形成隔离各个接触垫320的隔离凹槽350。
在本公开的一种实施方式中，在对接触垫材料层321进行图案化操作时，可以使得接触垫320呈具有倒角的菱形。当然的，在其他实施方式中，也可以使得接触垫320具有其他形状，例如使得接触垫320呈圆形。
在本公开的一种实施方式中，在步骤S530中，可以对接触垫材料层321进行图案化操作，以形成呈正六方密布的多个接触垫320。换言之，彼此相邻的三个接触垫320的中心的连线可以为等边三角形；在非边缘位置，一个接触垫320与六个接触垫320相邻，且与该接触垫320相邻的六个接触垫320的中心的连线呈正六边形。
需要说明的是，尽管在附图中以特定顺序描述了本公开中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等，均应视为本公开的一部分。
本公开还提供一种半导体结构，参见图21，该半导体结构包括半导体衬底100、多个位线结构200和多个电极结构300。其中，参见图4，半导体衬底100包括多个交替设置的第一区域A和第二区域B；参见图14和图9，任一位线结构200贯穿第一区域A和第二区域B；在第一区域A，位线结构200的两侧侧壁均呈台阶状；参见图21，任意一个电极结构300包括相互电连接的导电栓塞310和接触垫320，导电栓塞310位于第二区域B且位于相邻两个位线结构200之间并与半导体衬底100连接。
本公开提供的半导体结构可以通过上述半导体结构的制备方法实施方式进行制备，因此具有相同或者类似的技术特征，例如具有更高的制备良率等，本公开对此不再赘述。本公开提供的半导体结构的其他细节和特征，已经记载于上述半导体结构的制备方法实施方式中，或者可以根据上述半导体结构的制备方法实施方式所记载的内容而可以合理的推导出来，本公开在此不再赘述。
示例性地，在本公开的一种实施方式中，参见图14，位线结构200包括位线引线210和位于位线引线210两侧的至少一层电介质侧壁220；在第一区域A，电介质侧壁220的顶端位于位线引线210的顶端与半导体衬底100之间。
示例性地，在本公开的一种实施方式中，参见图14，位线结构200包括位线引线210和位于位线引线210两侧的至少两层电介质侧壁220；在第一区域A，相邻两层电介质侧壁220中靠近位线引线210的电介质侧壁220的高度更大。
示例性地，在本公开的一种实施方式中，参见图21，相邻两个电极结构300之间具有隔离凹槽350，隔离凹槽350的底面不低于位线结构200的侧壁的顶部。
示例性地，在本公开的一种实施方式中，各个接触垫320呈正六方密布。
本公开实施方式还提供一种存储装置，该存储装置包括上述半导体结构实施方式所描述的任意一种存储装置。该存储装置可以为DRAM(动态随机存取存储器)或者其他类型的存储装置。由于该存储装置具有上述半导体结构实施方式所描述的任意一种半导体结构，因此具有相同的有益效果，本公开在此不再赘述。
应可理解的是，本公开不将其应用限制到本说明书提出的部件的详细结构和布置方式。本公开能够具有其他实施方式，并且能够以多种方式实现并且执行。前述变形形式和修改形式落在本公开的范围内。应可理解的是，本说明书公开和限定的本公开延伸到文中和/或附图中提到或明显的两个或两个以上单独特征的所有可替代组合。所有这些不同的组合构成本公开的多个可替代方面。本说明书的实施方式说明了已知用于实现本公开的最佳方式，并且将使本领域技术人员能够利用本公开。

Claims (15)

  1. 一种半导体结构的制备方法，包括：
    提供半导体衬底，所述半导体衬底包括多个交替设置的第一区域和第二区域；
    在所述半导体衬底上形成多个位线结构，任一所述位线结构贯穿所述第一区域和所述第二区域；
    在所述第一区域对所述位线结构进行刻蚀，使得所述位线结构的两侧侧壁均呈台阶状；
    形成多个电极结构，任意一个所述电极结构包括相互电连接的导电栓塞和接触垫，所述导电栓塞位于所述第一区域且位于相邻两个所述位线结构之间并与所述半导体衬底连接。
  2. 根据权利要求1所述的半导体结构的制备方法，其中，在所述半导体衬底上形成多个位线结构包括：
    在所述半导体衬底上形成多个位线引线，任一所述位线引线贯穿所述第一区域和所述第二区域；
    在所述位线引线的两侧面分别形成至少一层电介质侧壁；
    在所述第一区域对所述位线结构进行刻蚀包括：
    在所述第一区域对所述位线引线和所述电介质侧壁进行刻蚀，使得所述电介质侧壁的顶端位于所述位线引线的顶端与所述半导体衬底之间。
  3. 根据权利要求2所述的半导体结构的制备方法，其中，在所述位线引线的两侧面分别形成至少一层电介质侧壁包括：
    在所述位线引线的两侧面分别形成至少两层电介质侧壁；
    在所述第一区域对所述位线结构进行刻蚀包括：
    在所述第一区域对所述位线引线和各层所述电介质侧壁进行刻蚀，使得相邻两层所述电介质侧壁中靠近所述位线引线的电介质侧壁的高度更大。
  4. 根据权利要求1所述的半导体结构的制备方法，其中，在所述半导体衬底上形成多个位线结构包括：
    在所述半导体衬底上依次沉积形成导电材料层、第一电介质材料层和第二电介质材料层，然后对所述导电材料层、所述第一电介质材料层和所述第二电介质材料层进行图案化操作以形成位线引线；
    在所述位线引线的两侧面依次形成第一电介质侧壁和第二电介质侧壁；
    所述半导体结构的制备方法还包括：
    在各个所述位线结构之间填充牺牲电介质材料以形成牺牲电介质层；所述牺牲电介质材料与所述第二电介质材料层的材料相同；
    在所述第一区域对所述位线结构进行刻蚀包括：
    采用第一刻蚀条件对所述第一区域进行刻蚀，使得所述第二电介质材料层的刻蚀 速率＜所述第二电介质侧壁的刻蚀速率＜所述第一电介质侧壁的刻蚀速率；
    采用第二刻蚀条件对所述第一区域进行刻蚀，使得所述牺牲电介质层的刻蚀速率＞所述第二电介质侧壁的刻蚀速率＞所述第一电介质侧壁的刻蚀速率，以完全去除位于所述第一区域的所述牺牲电介质层。
  5. 根据权利要求4所述的半导体结构的制备方法，其中，所述第二电介质材料层的材料和所述牺牲电介质材料均为氧化硅；所述第一电介质侧壁的材料为氮化硅；所述第二电介质侧壁的材料为氮氧化硅。
  6. 根据权利要求1所述的半导体结构的制备方法，其中，形成多个电极结构包括：
    在所述第一区域的相邻两个所述位线结构之间填充导电材料，以形成栓塞材料层；
    形成覆盖所述栓塞材料层的接触垫材料层；
    对所述栓塞材料层和所述接触垫材料层进行图案化操作，使得所述接触垫材料层被图案化为多个所述接触垫，且使得所述栓塞材料层被图案化为多个所述导电栓塞。
  7. 根据权利要求6所述的半导体结构的制备方法，其中，对所述栓塞材料层和所述接触垫材料层进行图案化操作包括：
    对所述栓塞材料层和所述接触垫材料层进行刻蚀以形成隔离凹槽；所述隔离凹槽贯穿所述接触垫材料层以使得接触垫材料层被图案化为多个分离的接触垫；所述隔离凹槽的底面位于所述栓塞材料层且不低于所述位线结构的侧壁的顶面。
  8. 根据权利要求1所述的半导体结构的制备方法，其中，对所述栓塞材料层和所述接触垫材料层进行图案化操作包括：
    对所述接触垫材料层进行图案化操作，以形成呈正六方密布的多个所述接触垫。
  9. 根据权利要求1所述的半导体结构的制备方法，其中，
    在所述半导体衬底上形成多个位线结构包括：
    在所述半导体衬底上依次沉积形成导电材料层、第一电介质材料层和第二电介质材料层，然后对所述导电材料层、所述第一电介质材料层和所述第二电介质材料层进行图案化操作以形成位线引线；所述位线引线贯穿所述第一区域和所述第二区域；其中，所述第二电介质材料层的材料为氧化硅；
    在所述位线引线的两侧依次形成第一电介质侧壁和第二电介质侧壁；其中，所述第一电介质侧壁的材料为氮化硅，所述第二电介质侧壁的材料为氮氧化硅；
    所述半导体结构的制备方法还包括：
    在形成多个所述位线结构后，在所述位线结构之间填充牺牲电介质材料以形成牺牲电介质层；所述牺牲电介质材料与所述第二电介质材料层的材料相同；
    在所述第二区域，移除所述牺牲电介质层并填充氮化硅；
    在所述第一区域对所述位线结构进行刻蚀包括：
    采用第一刻蚀条件对所述第一区域进行刻蚀，使得氧化硅的刻蚀速率＜氮氧化硅的刻蚀速率＜氮化硅的刻蚀速率；
    采用第二刻蚀条件对所述第一区域进行刻蚀，使得所述氧化硅的刻蚀速率＞氮氧化硅的刻蚀速率＞氮化硅的刻蚀速率，以完全移除位于所述第一区域的所述牺牲电介质层。
  10. 一种半导体结构，包括：
    半导体衬底，包括多个交替设置的第一区域和第二区域；
    多个位线结构，任一所述位线结构贯穿所述第一区域和所述第二区域；在所述第一区域，所述位线结构的两侧侧壁均呈台阶状；
    多个电极结构，任意一个所述电极结构包括相互电连接的导电栓塞和接触垫，所述导电栓塞位于所述第一区域且位于相邻两个所述位线结构之间并与所述半导体衬底连接。
  11. 根据权利要求10所述的半导体结构，其中，所述位线结构包括位线引线和位于所述位线引线两侧的至少一层电介质侧壁；在所述第一区域，所述电介质侧壁的顶端位于所述位线引线的顶端与所述半导体衬底之间。
  12. 根据权利要求11所述的半导体结构，其中，所述位线结构包括位线引线和位于所述位线引线两侧的至少两层电介质侧壁；在所述第一区域，相邻两层所述电介质侧壁中靠近所述位线引线的电介质侧壁的高度更大。
  13. 根据权利要求10所述的半导体结构，其中，相邻两个所述电极结构之间具有隔离凹槽，所述隔离凹槽的底面不低于所述位线结构的侧壁的顶部。
  14. 根据权利要求10所述的半导体结构，其中，各个所述接触垫呈正六方密布。
  15. 一种存储装置，包括权利要求10～14任意一项所述的半导体结构。
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