GB2276980A - Semiconductor device stacked capacitor and method of manufacture - Google Patents

Description

2276980 1 SEMICONDUCTOR DEVICE CAPACITOR AND METHOD FOR MANUFACTURING THE

SAME The present invention relates to a capacitor of a semiconductor device capacitor and a method for manufacturing the same, and more particularly to a stacked capacitor of a semiconductor device having an increased cell capacitance and a method for manufacturing the same.

In a dynamic random access memory (DRAM) cell which consists of one transistor and one capacitor, an increase in cell capacitance causes an improvement in reading ability of the memory cell and a reduction of soft error ratio, thereby to improve memory characteristics of the cell. DRAM integration increases by 4 times approximately every 3 years, whereas the chip area increases only by 1.4 times. Relatively, unit memory cell area decreases by 1/3 while the cell capacitance required by the unit memory cell is regular. Accordingly, cell capacitance decreases and an electrical characteristic of a memory device is lowered. Therefore, the cell capacitance in a unit memory cell needs to be increased in a limited area.

It is hard to ensure the sufficient and large cell capacitance in the limited area in the conventional capacitor structure. Therefore, a lot of methods for forming the capacitor structure three-dimensionally so as to increase cell capacitance are proposed. There are representative structures of the threedimensional capacitors such as a trench capacitor, stacked capacitor and a stack-trench capacitor. The trench capacitor is advantageous in ensuring the large capacitance, however, device 2 characteristics are decreased by the complicated parasitic transistor effect such as MOS parasitic transistor effect which exists in the surf ace of the trench or the leakage current between the trenches. Moreover, the manufacturing process is very strict. By contrast, the stacked capacitor has less parasitic transistor ef f ect compared with the trench capacitor, and is simple in manufacturing process. However, in the stacked capacitor, the capacitance is not sufficient, which gives disadvantage in a high integration. Accordingly, a new capacitor having a simple process for manufacturing the device and which can ensure the large cell capacitance is needed.

T. Ema et al. proposed a new capacitor structure, i.e., a f in-structured capacitor, in order to realize the above demands (see 13-dimensional stacked capacitor cell for 16M and 64M DRAM' by T. Ema et al., IEDM, 1988, pp. 592-595).

The f in-structured capacitor is a kind of stacked capacitor, and has a storage electrode comprising multiconductive layers and spacers for separating the conductive layers. Therefore, the side and bottom surfaces as well as the upper surface of the conductive layer can be used as an effective area, and the conductive layer can be formed by a single layer or by the multi-layers. For this reason, the fin-structured capacitor is an advantageous structure since the cell capacitance can be easily controlled.

A semiconductor memory device having the f in-structured capacitor comprises a storage electrode where four first conductive layers are formed in symmetry on all sides, centered around the source region of a transistor, and four spacers for 3 separating four first conductive layers are formed, and a cylindrical column of the f irst conductive layer is f ormed by connecting the edges of the f our conductive layers, a dielectric f ilm. coated all over the storage electrode and a plate electrode formed all over the dielectric film.

Referring to FIGs. 1 to 3 of the accompanying drawings, a method for manufacturing the fin structured capacitor of the conventional semiconductor device as disclosed by T. Ema et al will be explained.

Referring to FIG. 1, a switching transistor comprising a source region 14, drain region 16 and a gate electrode IS is f ormed in an active region of a semiconductor substrate 10 which is def ined into an active region and an isolation region by a f ield oxide layer 12. At this time, a word- line 18 1 elongated from a gate electrode of the adjacent transistor is formed on f ield oxide f ilm 12. Then, a f irst etch blocking f ilm 31 is f ormed all over semiconductor substrate 10 by depositing nitride silicon S'3N4 so as to hinder an etching process and to insulate gate electrode 18 and word-line IS I. Then, first insulating layer 32 and f irst conductive layer 34, f or example, a f irst insulating layer having four layers and a f irst conductive layer having three layers in a 4 f in structure, are serially deposited all over first etch resist film 31, and a photolithography process for forming a contact hole is performed on source region 14, to thereby form a contact hole 36 for exposing source region 14. At this time, an insulating material, for example, silicon dioxide (S'02), is used as material that constitutes f irst insulating layer 32, while a conductive material, for example, impurity- 4 doped polycrystalline silicon, is used constitutes first conductive layer 34.

Referring to FIG. 2, conductive material same as the material that constitutes f irst conductive layer 34 is deposited to a predetermined thickness all over the resultant structure, thereby to f orm second conductive layer 35. Second conductive layer 35 is coupled with source region 14 of semiconductor substrate 10 via contact hole 36 and electrically coupled with first conductive layer 34 via the sidewall of contact hole 36.

Referring to FIG. 3, the deposited first insulating layer 32, and first and second conductive layers 34 and 35 are patterned by performing a photolithography process by applying a mask pattern (not shown) for forming a storage electrode, thereby forming a storage electrode pattern. Then, the insulating material remaining between first and second conductive layers 34 and 35 is removed by wet-etching process, thereby to form a storage electrode 100. At this time, first etching blocking film 31 prevents the previously formed transistor from being damaged by etchant when the wet-etching process is performed. Then, a dielectric film 110 is formed all over a storage electrode 100 and a conductive material is deposited all over the resultant structure, thereby forming a plate electrode 120. Then, a contact hole which exposes a drain region 16 is formed on drain region 16 by a photolithography process. A second etching blocking film 42 and a second insulating f ilm 44 are formed all over the resultant structure and part of drain region 16 is then exposed. Then, a conductive material is deposited all over the resultant structure so as to f orm a third conductive layer,, and a as material that photolithography process is performed by applying a mask pattern (not shown), thereby to form a bit line 50.

In a semiconductor memory device comprising a f instructure capacitor manufactured by the conventional method, multi conductive layers and insulating layers are alternately deposited on a semiconductor substrate and the insulating layer is etched. Thus, the upper, side and bottom surf aces of the conductive layers are used as an effective area of a capacitor. As a result, a capacitor having a large capacitance can be f ormed in the small area of semiconductor substrate in accordance with high integration.

However, a process f or etching the multi-conductive layers and insulating layers which have largely different etching selectivity rate is necessary in order to form the f in-structure capacitor. The conductive layer and insulating layer cannot be removed by a one-time etching process. Thus, an etching process suitable f or each layer is necessary, which causes a complicated processing and an extended processing time. As a result, throughput is lowered. In general, an etching process which divides the storage electrode into each cell unit is a dryetching process. However, the dry-etching process has to be conducted by varying the etching source in accordance with an etching selectivity ratio if the object of the etching process is changed. In addition, the conductive layer is deposited by 2 times or more so as to increase the cell capacitance. Therefore, connecting each conductive layer results in the generation of a contact surface, and the native oxide f ilm is f ormed on the contact surface, thereby to lower the electrical characteristics 6 of a memory device. Moreover, the height of from the substrate surface to the uppermost portion of a capacitor is increased as the number of f ins is increased so as to increase the cell capacitance. Thus, problems are caused by the high step coverage when the metalization processing is performed. As a result, memory device reliability is lowered.

Meanwhile, U.S. Patent No. 5,,142,639 discloses an improved finstructured capacitor. FIG. 4 of the accompanying drawings is a sectional view of a capacitor shown in the above U.S. Patent. Referring to FIG. 4, those reference numerals which are the same as those of FIG. 1 to FIG. 3 denote the same member. The semiconductor memory device having the abovedescribed finstructured capacitor comprises a first insulating film 20, a second insulating film 21, a storage electrode 25, a dielectric film 26 and a plate electrode 27 on an insulating film 19 which insulates gate electrode 18 and word-line 181 and also comprises a hierarchical structure where dielectric film 26 and storage electrode 25 are piled on one another.

Since the fin-structure forms a storage electrode by a single conductive layer differently from the conventional method described with reference to FIGs. I to 3, a leakage current caused by an intermediate material like a natural oxide material can be prevented. However, the side surface of the storage electrode cannot be used as an effective capacitor region, thereby limiting the increase of the cell capacitance.

In addition, improved fin-structure capacitors are disclosed in U.S. Patents No. 4,974,040 (Taguchi et al.), 5,071,781 (Seo et al.), 5,053,351 and in U.S. Patent No.

7 5,164,337 (Ogawa et al.). However, since capacitors having the improved structure form a storage electrode by forming a plurality of conductive layers, characteristics are degraded by a native oxide film and the process becomes complicated.

Accordingly, it is an object of the present invention to provide a capacitor of a semiconductor device f ormed of a single conductive layer and which makes it possible to improve the reliability and the capacitance.

it is another object of the present invention to provide a method suitable for manufacturing the capacitor of a semiconductor device formed of a single conductive layer by using insulating materials having different etching rates.

According to one aspect of the present invention there is provided a capacitor of a semiconductor device comprising a storage electrode f ormed of a single conductive layer and having a lower portion connected to a predetermined portion of a semiconductor substrate and with a body elongated upward from the lower portion, and which has at least one convex portion in a middle portion of the body so as to increase a capacitance thereof; a dielectric f ilm formed inside and outside of the storage electrode; and a plate electrode f ormed in the dielectric film. It is desirable for a capacitor of the present invention to comprise a horizontally elongated fin-structured portion in the uppermost portion of the body.

According to an embodiment of the present invention, the outside bottom surf ace of the convex Portion and the outside surf ace of the lower body under the convex portion are f ormed being in contact to the structure formed on the semiconductor 8 substrate.

According to another embodiment of the present invention, the elongated dielectric film and plate electrode are formed on the bottom surface of the outside of the convex portion.

According to another aspect of the present invention, there is provided a method for manufacturing a capacitor of a semiconductor device, the method comprising the steps of:

serially depositing a f irst material and a second material whose etching rates are different with respect to a first isotropic etching process all over the semiconductor substrate where an insulating layer for insulating a transistor which consists of a source region, a drain region and a gate electrode is formed, to form a first material layer and a second material layer; partially etching the f irst material layer and the second material layer which are formed on the source region and the insulating layer, to form a contact hole f or partially exposing the source region; partially and isotropically etching the side of the first material layer exposed by the contact hole via the first isotropic etching process, to form a convex space portion; forming a first conductive layer all over the structure including the contact hole and the convex space portion; defining the first conductive layer into each cell unit to form a storage electrode pattern; removing the first and second material layers to expose the storage electrode pattern; and z 9 forming a dielectric film and a plate electrode on the storage electrode pattern.

The step of removing the f irst and second material layers is preferably performed by a second isotropic etching process by using an etchant having a similar etching rate for the first and second material layers.

An embodiment of the present invention, further comprises the step of: forming a third material layer on the insulating film by depositing a third material prior to the formation of the first material layer. Material whose etching rate is different from that of the first material and second material with respect to an arbitrary isotropic etching process, is used as a third material. The elements formed in the lower portion can be protected during an arbitrary isotropic etching process by forming a third material layer.

It is preferable to have the first material whose etching rate is the same as that of second material with respect to a predetermined anisotropic etching process and whose etching rate is different from that of second material with respect to a first isotropic etching process. Accordingly, the contact hole can be easily formed, and the first material layer is isotropically etched, thereby forming the convex space portion easily.

In addition, it is desirable to have the thickness of the first and second material layers to be greater than double the thickness of the conductive layer. Thus, the convex portion of the storage electrode can be easily f ormed by considering the thickness.

According to another embodiment of the present invention, the second material is deposited prior to the step of serially depositing the first and second material layers, to thereby form a lower second material layer. Then, the lower second material layer is also removed when the first and second material layers are removed, thereby to expose the lower portion of the convex portion of the storage electrode pattern.

According to an embodiment of the present invention, the step of serially forming the first material layer and the second material layer has to be repeated at least twice. Thus, a multitude of convex portions are provided to a storage electrode pattern, which increases the cell capacitance.

According to an embodiment of the present invention, the convex portion is extended by repeating the first isotropic etching process at least twice. The convex portion can be extended to the degree that it does not affect the adjacent peripheral structure.

The contact hole can be formed by an anisotropic etching process, and also can be formed by performing an isotropic etching first and an anisotropic etching secondly.

Since the storage electrode is formed of a single conductive layer, a degradation of electrode characteristics caused by the formation of a native oxide film can be prevented. Further, the upper, side and bottom surfaces of a storage electrode can be used as an effective capacitor area, thereby easily increasing the cell capacitance. As a result, a reliable capacitor having a high capacitance can be obtained.

Embodiments of the present invention will now be 11 described by way of example with reference to the attached drawings in which:

FIGs. 1 to 3 are sectional views showing a method for manufacturing a finstructured capacitor of a semiconductor device according to a conventional method; FIG. 4 is a sectional view showing an embodiment of a conventional modif ied f in-structured capacitor of a semiconductor device; FIG. 5 is a sectional view showing an embodiment of a capacitor of a semiconductor device according to the present invention; FIGs. 6 to 10 are sectional views illustrating an embodiment of a method for manufacturing a capacitor of a semiconductor device according to the present invention; FIGs. 11 and 12 are sectional views illustrating another embodiment of a method for manufacturing a capacitor of a semiconductor device according to the present invention; and FIGs. 13 and 14 are sectional views illustrating a further embodiment of a method for manufacturing a capacitor of a semiconductor device according to the present invention.

FIG. 5 is a sectional view showing an embodiment of a capacitor of a semiconductor device of the present invention. The same reference numerals are employed in FIG. 5 as in FIGs. 1 to 4 to denote the same members. A storage electrode 105 of the semiconductor memory device comprises a lower portion connected to a predetermined portion (source region of a transistor) of the semiconductor substrate where the lower structure (for example, a transistor) is f ormed and a body extends upwards f rom the lower 12 portion. The middle portion of the body comprises a convex portion, and therefore, has a vase shape whereby the surface area of the storage electrode is increased. A horizontally elongated fin structure is formed in the uppermost portion of the body. A plate electrode 125 is formed on the entire exposed surface, i.e., on the internal and external surfaces, of storage electrode 105 with a dielectric film interposed therebetween. Referring to storage electrode 105 shown in FIG. 5, the bottom surface of the lower portion of the convex portion and part of the lower body of the convex portion are connected to insulating film 30 and etching blocking film 31 which are formed on semiconductor substrate 10. As shown in FIG. 5, dielectric film 115 is formed on the inside and outer surface and on the upper portion of the body above the convex portion, which are used as an effective area of a capacitor.

A method for manufacturing a capacitor of a semiconductor device according to the present invention will be explained in more detail by the following embodiments.

Embodiment I FIGs. 6 to 10 are sectional views illustrating a first embodiment of a method for manufacturing a capacitor of a semiconductor device according to the present invention.

FIG. 6 shows the step of forming a transistor on a semiconductor substrate 10. In more detail, a field oxide film 12 for defining an active region and an isolation region is formed on semiconductor substrate 10. Then, an oxide film is formed all over the resultant structure so as to form a gate

13 oxide f ilm. Then, a conductive material is deposited on the oxide f ilm f or f orming a gate electrode. Then, the oxide f ilm and conductive layer are patterned by a photolithography process. thereby to form a gate electrode 18. At this time, word-line is' connected to a gate electrode of the adjacent transistor is f ormed on f ield oxide f ilm. 12. Then, f or example, an N-type impurity ion, is doped all over the resultant structure using gate electrode 10 as a mask when the semiconductor substrate is doped with P-type impurities, thereby forming source region 14 and drain region 16. Thus, a transistor comprising source region 14, drain region 16 and gate electrode 18 is f ormed. Then, insulating material, for example, high temperature oxide (HTO), is deposited all over semiconductor substrate 10 where a transistor is f ormed, so as to insulate the transistor, to thereby form an insulating layer 30.

FIG. 7 shows the step of sequentially forming a first material layer 33 and a second material layer 37 all over semiconductor substrate 10. A silicon nitride layer is deposited to a thickness of approximately 200A to 500A all over the resultant structure where the transistor is formed, thereby to form etching blocking film 31. A first material and a second material whose etching rate are dif f erent with respect to a first isotropic etching process and whose etching rate are similar with respect to a second isotropic etching process, are serially deposited to a thickness of approximately 1, 0001 to 10, OOOA, thereby to form first material layer 33 and second material layer 37. When a boron phosphorous silicate glass (BPSG) is used as a first material, a high temperature oxide (HTO) can be used as a 14 second material. When BPSG is used as first material layer 33, the successive process can be smoothly performed by a planarization process, i.e., WSG reflow process, which is desirable. in addition, it is desirable to form the thickness of first material layer 33 to be thicker, for example, by 2 times or more, than that of a first conductive layer (reference numeral 41 of FIG. 9) f or f orming a f irst electrode of the capacitor. Materials (say "All and "B") having the same etching rate with respect to a predetermined anisotropic etching and different etching rates (it is desirable that the etching rate of "B" is 8 or higher when the etching rate of "All is 1) with respect to a predetermined first isotropic etching process, have to be used for constituting first material layer 33 and second material layer 37. When an isotropic etching process is performed by a wet-etching method where an etchant such as standard cleaning 1 (SC1: etchant where NH40H, H202 and H20 are mixed in a ratio of 1:4:20), which shows an etching rate of first material layer 33 which is much higher with respect to the predetermined isotropic etching process as compared with second material layer 37, is used. it is desirable to use BP5G film as first material layer 33 and HTO film as second material layer 37 (here, the etching rate of HTO film with respect to SC1 is approximately 4.4A/min, and an etching rate of BPSG film is approximately 35.2A/rain). When an isotropic etching is performed by a wet-etching method using hydrofluoric acid (HF), it is desirable to use spin-onglass (SOG) film as first material layer 33 and HTO film as second material layer 37 (here, the etching rate of SOG film to HF is approximately 5, 000Almin to 9, 000Almin and that of HTO f ilm is is approximately 901/min). As for a material that constitutes etching blocking film 31, it is desirable to use a material whose etching rate is different from that of the material constituting the first material layer, with respect to the predetermined isotropic etching aiming partially to remove the first material layer, such as a nitride which is mentioned above. Moreover, a cell capacitance can be controlled by varying the times of depositing first and second layers. When a capacitor is formed after a bit line is formed, the thickness of first and second layers 33 and 37 can be increased, thereby to increase a cell capacitance.

FIG. 8 shows a step of forming a contact hole 39 and a space portion 38. Layers formed on source region 14 of a transistor are partially removed using a mask pattern (not shown) for forming a contact hole which aims to make a storage electrode contact to source region 14 of a transistor, thereby to form contact hole 39. When materials that constitute first and second material layers 33 and 37 have the same etching rate with respect to an anisotropic etching process for forming contact hole 39, an etching gas doesn't need to be changed according to the change of the etching object, as it did in the conventional method, which simplifies the process. After an isotropic etching is performed by wet-etching method, an anisotropic etching is performed by a dry-etching method. to thereby form contact hole 39. Thus, an aperture of the upper portion of contact hole 39 is formed large, to thereby remove a void which may occur in the succeeding process.

Then, first isotropic etching process having first 16 material layer 33 as an etching objective, using wet-etching method is performed all over the resultant structure, to thereby form space portion 38. The side portion of first material layer 33 exposed by contact hole 39 in the first isotropic etching process is partially etched and removed. Here, space portion 38 means a portion where the exposed side portion of first material layer 33 is removed. In the present embodiment, a wet- etching process using standard cleaning (SC1) is performed for twenty to fifty minutes, to thereby form space portion 38.

FIG. 9 shows a step of forming a storage electrode. After the step of FIG. 8 is performed, a conductive material, for example, an impurity-doped polycrystalline silicon, is deposited thereby to form a first conductive layer 41 having a thickness of approximately half of the thickness of the f irst material layer, for example, approximately 5001 to 5,0001, all over the resultant structure. Then, a photoresist pattern 43 is formed by applying a mask pattern (not shown) for forming the storage electrode. First conductive layer 41 is defined into each cell unit by using the photoresist pattern as an etching mask, thereby completing a storage electrode (reference numeral 105 of FIG. 10). In order to form the storage electrode, multiple conductive layers and insulating layers having large different eching rates from each other have to be etched by the etching process appropriate for each layer in the conventional method. Therefore, the process is complicated and the process time is elongated. However, in the present embodiment, the process is much more simplified and process time is considerably reduced since only first conductive layer 41 is necessary to be etched.

17 FIG. 10 shows the step of forming a dielectric f ilm 115 and a plate electrode 125. All the remaining f irst and second material layers 33 and 37 are removed by performing a second isotropic etching by a wet-etching method all over the resultant structure where storage electrode 105 is formed, thereby exposing the side surface of storage electrode 105. At this time, the wetetching process is performed for approximately five to fifty minutes by using a wet-etching etchant where first and second material layers have similar etching rate, for example, LAL500, buffered oxide etchant (BOE; mixture of NH4F and HF) or surf actant buffered oxide etchant (SBOE; NH4F and HF mixture with a surfactant added). Then, an insulating material, for example, nitride/oxide (NO), oxidelnitride/oxide (ONO) or tantalum pentaoxide (Ta20.) is deposited all over storage electrode 105, thereby forming dielectric film 115. Then, a conductive material such as an impurity-doped polycrystalline silicon is deposited all over the resultant structure, thereby forming a second conductive layer. Then, a photolithography process adapting a mask pattern (not shown) for forming a plate electrode is performed, to thereby form plate electrode 125. In the present embodiment, all the remaining first and second material layers 33 and 37 are removed by the second wet-etching process. Therefore, all the inner and outer surfaces of storage electrode 105 which contact the first and second material layers are exposed, to thereby increase the area of an effective capacitor.

Embodiment 2 FIGs. 11 and 12 are sectional views illustrating a is second embodiment of a method for manufacturing a capacitor of a semiconductor device according to the present invention. In the present embodiment, all processes are similar with that of embodiment 1, except that an additional second material layer is formed before the first material layer is formed in embodiment 1.

FIG. 11 shows a step of forming contact hole 39 and space portion 38. According to a method described with reference to FIG. 6, insulating layer 30 and etching blocking film 31 are serially formed on semiconductor substrate 10 where a transistor is formed. Then, a first second materiallayer 37a is firstly formed all over the resultant structure, and f irst material layer 33 and a second second material layer 37b are serially formed on first second material layer 37a. At this time, as for the first material layer and first and second second material layers 37a and 37b, materials the same as that explained with reference to FIG. 6 is used. That is, it is preferable to use BPSG for example for first material layer 33 and HTO for first and second second material layers 37a and 37b.

Then, in the same manner as explained with reference to FIG. 8, contact hole 39 is formed by removing the material deposited on source region 14 of the transistor. Then, a first wet-etching process where first material layer 33 is an etchingobjective is performed all over the resultant structure, thereby forming space portion 38.

FIG. 12 shows a step of completing the formation of a capacitor. After the step described with reference to FIG. 11 is performed, storage electrode 105 is formed in the same manner as 19 explained in FIGs. 9 and 10. Then, all the remaining first material layer 3 3 _ and f irst and second second material layers 3 7 a and 37b are removed by a second wet-etching method. Then, dielectric film 115 and plate electrode 125 are formed all over storage electrode 105, thereby completing formation of a capacitor.

According to the present embodiment, the area of an effective capacitor can be increased by exposing the lower portion of the convex portion of storage electrode 105 f ormed in embodiment 1, i.e., the portion which contacts to a predetermined surface of etching blocking film 31.

Embodiment 3 FIGs. 13 and 14 are sectional views illustrating a third embodiment of a method for manufacturing a capacitor of a semiconductor device according to the present invention. In the present embodiment. the processes are the same with those of embodiment 1 except that the space portion for forming a storage electrode is further extended by repeating the first wet-etching process in embodiment 1.

FIG. 13 shows the step of f orming a space portion. First wet-etching process having first material layer 31 as an etching-objective is performed all over the resultant structure having contact hole 39 obtained according to the method explained with reference to FIGs. 6 to 9, to thereby form the space portion as shown in FIG. 8 (reference numeral 38 of FIG. 8 denotes the portion which corresponds to reference numeral Bl of FIG. 13). Then, a space portion B2 where portion B1 is further extended, is formed by performing the first wet-etching process again. At this time, space portion B2 can be extended up to the size which may not disturb the formation of the peripheral structure (for example, the bit line when a bit line is formed after a capacitor is formed) by repeating the first wet-etching process.

FIG. 14 shows the step of completing the formation of a capacitor. After space portion B2 is formed, storage electrode 105, dielectric film 115 and plate electrode 125 are formed in same manner as explained with reference to FIG. 10, thereby completing formation of a capacitor.

According to the present embodiment, the area of the effective capacitor can be increased due to the enlargement of space portion B2. Since the area of the effective capacitor is increased mainly in the horizontal direction, an increase of cell capacitance can be achieved even without largely increasing the step coverage in the vertical direction. The present embodiment can be applied together with embodiment 2.

According to a method for manufacturing a capacitor of semiconductor device of the present invention, first and second materials whose etching rates are the same with respect to a predetermined anisotropic etching process and whose etching rates are different from each other with respect to a predetermined isotropic etching process, are deposited all over the semiconductor substrate where a lower structure (for example, when a bit line is formed before a transistor and capacitor are formed, the bit line included) is formed, thereby sequentially to form a first material layer and a second material layer. Then, a contact hole exposing a portion of the source region of a 21 transistor is f ormed. Thereafter, a convex space portion is f ormed by partially removing one material layer of the two material layers exposed by the contact hole using a first isotropic etching method. Then, a conductive material is deposited so as to f orm a storage electrode and then all the first and second material layers are removed by a second isotropic etching process. The outer sidewall of the storage electrode which contacts to the two material layers is exposed, thereby to easily increase the cell capacitance. Thus, the outside surface of the storage electrode can be utilized as an effective capacitor area, thereby to increase the cell capacitance. Further, in the conventional method, a dryetching process (an etching gas has to be changed in accordance with the change of the etching-objective in the conventional method) for an anisotropic etching has to be performed several times; however, the dry- etching process is reduced to one time in the present invention, which simplifies the process. Moreover, since the storage electrode is formed of a single conductive layer, the leakage current caused by the intermediate material like a native oxide film can be prevented and the surface area of the storage electrode can be increased in the horizontal direction. Thus, step coverage in the vertical direction is not much increased. which enables the subsequent metalization process to be achieved reliably. As a result, a high integrated semiconductor memory device having a high reliability can be manufactured.

It will be understood by those skilled in the art that the foregoing and other changes in form and details can be made therein without departing from the scope of the invention.

22

Claims (17)

1. A semiconductor device comprising a capacitor, which capacitor comprises:

a storage electrode which consists of a single conductive layer and is constituted by a first portion connected to a region on a semiconductor substrate and a second portion which extends from said first portion in a direction substantially perpendicular thereto and defines a body having internal and external surfaces, a middle portion of which body having at least one convex portion; a dielectric film on internal and external surfaces of said storage electrode, and a plate electrode on said dielectric film.

2. A semiconductor device according to claim 1, wherein said second portion comprises an elongate fin structure at that end of said body remote from said first portion, which fin structure extends substantially parallel to said first portion of the storage electrode.

3. A semiconductor device according to claim 1 or 2, wherein an external surface portion of said convex portion and an external surface of said body between the convex portion and said first portion of the storage electrode are in contact with a structure on the semiconductor substrate.

4.

1 A semiconductor device according to claim 1 or 2 1 23 wherein said dielectric film and said plate electrode extend over the entire external surface of said convex portion.

5. A semiconductor device comprising a capacitor substantially as herein described with reference to any of Figures 5, 10, 12 and 14 of the accompanying drawings.

6. A method for manufacturing a capacitor of a semiconductor device comprising the steps of: sequentially depositing f irst and second materials which have a dif f erent etching rate with respect to a f irst isotropic etching process all over the semiconductor substrate where an insulating layer is formed so as to insulate a transistor constituted by a source region, drain region and a gate electrode, to form first and second material layers; partially etching the first and second material layers and said insulating layer which are formed on said source region, to f orm a contact hole for partially exposing said source region; partially and isotropically etching on the side portion of the first material layer exposed by said contact hole via said first isotropic etching process to form a convex space portion; forming a first conductive layer all over the resultant structure including said contact hole and convex space portion; defining said first conductive layer into each cell unit, to form a storage.electrode pattern; removing said f irst and second material layers to expose said storage electrode pattern, and forming a dielectric film and a plate electrode on said 24 storage electrode pattern.

7. A method. for manufacturing a capacitor of a semiconductor device according to claim 6, wherein said step of removing f irst and second material layers is performed by a second isotropic etching using an etchant which shows similar etching rates for said first and second material layers.

8. A method for manufacturing a capacitor of a semiconductor device capacitor according to claims 6 or 7, further comprising the step of depositing a third material on said insulating layer to form a third material layer before said first material layer is formed.

g. A method f or manufacturing a capacitor of a semiconductor device capacitor according to claim 8, wherein a material having the etching rate different from those of said f irst and second materials with respect to an arbitrary wet etching method is used as said third material.

10. A method for manufacturing a capacitor of a semiconductor device according to any of claims 6 to 9, wherein said first material has an etching rate the same as that of said second material with respect to a predetermined anisotropic etching process and has an etching rate different from that of said second material with respect to said f irst isotropic etching process.

11. A method for manufacturing a capacitor of a semiconductor device according to any of claims 6 to 10, wherein the thickness of first and second material layers is thicker than double the thickness of said first conductive layer.

12. A method for manufacturing a capacitor of a semiconductor device according to any of claims 6 to 11, further comprising a step of forming a lower second material layer by depositing said second material prior to the step of sequentially depositing the first and second material layers.

13. A method for manufacturing a capacitor of a semiconductor device according to any of claims 6 to 12, wherein the step of sequentially forming the first and second material layers is repeated at least twice.

14. A method for manufacturing a capacitor of a semiconductor device according to any of claims 6 to 13, wherein said first isotropic etching process is repeated at least twice so as to extend said convex space portion.

15. A method for manufacturing a capacitor of a semiconductor device according to any of claims 6 to 14, wherein said contact hole is formed by an anisotropic etching process.

16. A method for manufacturing a capacitor of a semiconductor device according to any of claims 6 to 15, wherein said contact hole is formed by performing an isotropic etching 1 26 firstly and an anisotropic etching secondly.

17. A method f or manuf acturing a capacitor of a semiconductor device substantially as hereinbef ore described with ref erence to the Figures 6 to 10 with or without reference to any of Figures 11 to 14 of accompanying drawings.