WO2022062497A1 - 数据通路接口电路、存储器和存储系统 - Google Patents

数据通路接口电路、存储器和存储系统 Download PDF

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Publication number
WO2022062497A1
WO2022062497A1 PCT/CN2021/100794 CN2021100794W WO2022062497A1 WO 2022062497 A1 WO2022062497 A1 WO 2022062497A1 CN 2021100794 W CN2021100794 W CN 2021100794W WO 2022062497 A1 WO2022062497 A1 WO 2022062497A1
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Prior art keywords
delay
module
data
memory
control
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PCT/CN2021/100794
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English (en)
French (fr)
Inventor
冀康灵
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长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to JP2022548061A priority Critical patent/JP7376728B2/ja
Priority to EP21859353.1A priority patent/EP4009326B1/en
Priority to KR1020227027597A priority patent/KR102686157B1/ko
Priority to US17/446,571 priority patent/US11847073B2/en
Publication of WO2022062497A1 publication Critical patent/WO2022062497A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0611—Improving I/O performance in relation to response time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the embodiments of the present application relate to the field of integrated circuits, and in particular, to a data path interface circuit, a memory, and a storage system.
  • DRAM Dynamic Random Access Memory
  • Multiple storage blocks are usually set in the memory to achieve larger storage space.
  • the data transmission speed of different storage blocks is different, which leads to inconsistent timing of different storage blocks and storage data. Transmission synchronization is poor.
  • One aspect of the present application provides a data path interface circuit, comprising:
  • a write access module which is connected to the internal port and the external port respectively, and is used for transmitting and storing data from the external port to the internal port;
  • a read access module connected to the internal port and the external port respectively, for transmitting the stored data from the internal port to the external port;
  • the first delay module is connected to the external port and the internal port respectively, and is used for acquiring the stored data from the external port or the internal port, performing delay processing on the stored data, and storing the processed data.
  • the stored data is transmitted to the write access module and/or the read access module;
  • a delay control module connected to the first delay module, is configured to receive an externally input signal instruction, and control the delay time for the first delay module to perform the delay processing according to the signal instruction.
  • a memory comprising:
  • a data processing module connected to the external port of the data path interface circuit, for processing the stored data
  • a storage block connected to the internal port of the data path interface circuit, is used for storing the storage data.
  • Another aspect of the present application provides a storage system, including:
  • a processing module controller is connected to the memory and the electronic device respectively, and is used for enabling a corresponding number of the data processing modules in the memory according to the system information of the electronic device.
  • FIG. 1 is a schematic structural diagram of a data path interface circuit of the first embodiment
  • FIG. 2 is a schematic structural diagram of a data path interface circuit of the second embodiment
  • FIG. 3 is a schematic structural diagram of a data path interface circuit according to a third embodiment
  • FIG. 4 is a schematic structural diagram of a data path interface circuit according to a fourth embodiment
  • FIG. 5 is a schematic structural diagram of a data path interface circuit according to a fifth embodiment
  • FIG. 6 is a schematic structural diagram of a memory according to an embodiment
  • FIG. 7 is a schematic diagram of an effective working mode of two data processing modules according to an embodiment
  • FIG. 8 is a schematic diagram of an effective working mode of a single data processing module of the first embodiment
  • FIG. 9 is a schematic diagram of an effective working mode of a single data processing module of the second embodiment.
  • FIG. 10 is a schematic diagram of an effective working mode of a single data processing module of the third embodiment
  • FIG. 11 is a schematic diagram of an effective working mode of a single data processing module of the fourth embodiment.
  • FIG. 12 is a schematic structural diagram of a memory according to another embodiment.
  • the data path interface circuit 10 includes a write path module 100 , a read path module 200 , a first delay module 300 and a delay Control module 400 .
  • the data path interface circuit 10 is configured with an internal port 11 and an external port 12, and the internal port 11 is used to connect the storage block 30 inside the memory to transmit the storage data to be written to the storage block 30, or read the storage data from the storage block 30.
  • the external port 12 is used for receiving the storage data to be written sent from the external electronic device, or sending the storage data read from the storage block 30 to the external electronic device.
  • the write access module 100 is connected to the internal port 11 and the external port 12 respectively, and is used for transmitting stored data from the external port 12 to the internal port 11 .
  • the input terminal of the write access module 100 is indirectly connected to the external port 12 , specifically, the input terminal of the write access module 100 is indirectly connected to the external port 12 through the first delay module 300 , and the output terminal of the write access module 100 is connected to the internal port 11 direct connection. That is, the storage data to be written is input by an external electronic device, and is connected to the storage block 30 via the external port 12, the first delay module 300, the write access module 100 and the internal port 11 of the interface circuit, thereby realizing the writing of the stored data enter.
  • the read channel module 200 is connected to the internal port 11 and the external port 12 respectively, and is used for transmitting the stored data from the internal port 11 to the external port 12 .
  • the input terminal of the read access module 200 is indirectly connected to the internal port 11, specifically, the input terminal of the read access module 200 is indirectly connected to the internal port 11 through the first delay module 300, and the output terminal of the read access module 200 is connected to the external port 12. direct connection. That is, the stored data is read from the storage block 30 and connected to the external electronic device via the internal port 11, the first delay module 300, the read access module 200 and the external port 12 of the data path interface circuit, thereby realizing the reading of the stored data .
  • the data path interface circuit 10 only performs one of the write operation and the read operation at the same time. Therefore, the write path module 100 and the read path module 200 output the stored data in a time-sharing manner.
  • the first delay module 300 is connected to the external port 12 and the internal port 11 respectively, and is used for acquiring the stored data from the external port 12 or the internal port 11, and performing delay processing on the stored data, and transmit the processed stored data to the write channel module 100 and/or the read channel module 200 .
  • the first delay module 300 obtains the stored data from the external port 11 , delays the data and sends it to the write path module 100 .
  • the stored data to be written is written from the data pins of the memory, each data pin is connected to a plurality of storage blocks 30 , and the stored data is sent to the connected multiple storage blocks 30 . It can be understood that the lengths of the transmission paths between the external port 12 and the data pins of each data path interface circuit 10 are not the same.
  • the stored data cannot reach each storage block 30 at the same time, which leads to the phenomenon that the transmission of the stored data described in the background art is asynchronous.
  • the data path interface circuit 10 reads the stored data, there is also a phenomenon that the transmission of the stored data is out of synchronization, and the cause is similar to the aforementioned reason for the out of synchronization of the written data, which will not be repeated here.
  • the first delay module 300 can perform delay processing on the received stored data for an appropriate delay time, so that the stored data reaches the internal port 11 at a preset target time, so that each data path interface circuit 10 The time when the stored data arrives at the internal port 11 is the same, or the time error is within the error range that the data path interface circuit 10 can bear, thereby solving the phenomenon that the transmission of the stored data is asynchronous.
  • the functions of the write channel module 100 and the read channel module 200 for outputting the stored data in a time-sharing manner may be implemented through various hardware structures.
  • the first delay module 300 is configured with one output terminal, and the output terminal is connected to the write channel module 100 and the read channel module 200 respectively, and the first delay module 300 outputs the delay at the same time.
  • the processed storage data is sent to the write access module 100 and the read access module 200, and one of the write access module 100 and the read access module 200 can be controlled to be turned on, so that one of the two outputs storage data.
  • the first delay module 300 may also be configured with two output terminals, and the two output terminals are connected to the write channel module 100 and the read channel module 200 in a one-to-one correspondence, and can control the output of the first delay module 300 One of the two output terminals outputs the storage data, so that only one of the write-path module 100 and the read-path module 200 can receive the storage data, so that one of the two outputs the storage data.
  • the delay control module 400 connected to the first delay module 300, is configured to receive an externally input signal instruction, and control the delay time for the first delay module 300 to perform the delay processing according to the signal instruction.
  • the signal instruction refers to an instruction used to instruct the data path interface circuit 10 to perform a corresponding operation, such as one or more of a write instruction, a read instruction, and a mode selection encoding instruction.
  • the datapath interface circuit 10 is instructed to perform a corresponding write operation.
  • the delay control module 400 may be configured with one or more input terminals, and generate a control signal of the first delay module 300 according to the signal instructions input from the input terminals. For example, if the delay control module 400 is configured with an input, the control signal may be generated in response to one of a write command, a read command, and a mode select encoding command. If the delay control module 400 is configured with two input terminals, the control signal can be generated in response to two of a write command, a read command, and a mode selection encoding command.
  • the data path interface circuit 10 includes: a write path module 100, which is connected to the internal port 11 and the external port 12, respectively, for transmitting stored data from the external port 12 to the internal port 11; a read path module 200, respectively connected to the internal port 11 and the external port 12, for transmitting the stored data from the internal port 11 to the external port 12; a first delay module 300, respectively connected to the external port 12 connected to the internal port 11, for obtaining the stored data from the external port 12 or the internal port 11, delaying processing the stored data, and transmitting the processed stored data to the
  • the write path module 100 and/or the read path module 200; the delay control module 400, connected to the first delay module 300, is used to receive an externally input signal instruction, and control the first delay according to the signal instruction The delay time for which the module 300 performs the delay processing.
  • the first delay module 300 can perform delay processing on the received stored data with an appropriate delay time, so that the stored data reaches the internal port 11 or the external port 12 at the target time, so that each The transmission time of the data stored in each data path interface circuit 10 between the internal port 11 and the external port 12 is the same, or the error of the transmission time is within the tolerance range of the data path interface circuit 10, thereby realizing the transmission of the stored data.
  • Datapath interface circuit 10 with better synchronization.
  • FIG. 2 is a schematic structural diagram of the data path interface circuit 10 according to the second embodiment.
  • the first delay module 300 includes a selection unit 310 and a temporary storage unit 320 .
  • the setting methods of the write channel module 100 , the read channel module 200 , and the delay control module 400 are the same as those of the embodiment in FIG. 1 , which will not be repeated here.
  • the selection unit 310, the input terminal of the selection unit 310 is connected to the external port 12 and the internal port 11 respectively, and the control terminal of the selection unit 310 is used for receiving the signal instruction.
  • the selection unit 310 is configured with two input terminals, and the two input terminals of the selection unit 310 are respectively connected to the internal port 11 and the external port 12 in a one-to-one correspondence, so as to obtain storage data from the two ports respectively, and the selection unit 310 is also configured with There is a control terminal, and the control terminal of the selection unit 310 is used for receiving a signal instruction, so as to select and output one of the received two stored data according to the signal instruction.
  • the signal instruction may be a write instruction
  • the selection unit 310 selects and outputs the stored data from the external port 12, thereby realizing data writing.
  • the selection unit 310 is a two-to-one multiplexer. In other embodiments, the selection unit 310 may also be a three-to-one multiplexer, that is, by configuring three inputs
  • the terminal implements more complex selection and transfer functions.
  • the data input terminal of the temporary storage unit 320 is connected to the output terminal of the selection unit 310
  • the control terminal of the temporary storage unit 320 is connected to the output terminal of the delay control module 400 .
  • the temporary storage unit 320 includes one or more of latches, flip-flops, and registers
  • the control terminal of the temporary storage unit 320 includes one of a clock drive terminal, a set terminal, and a reset terminal or variety.
  • the temporary storage unit 320 may include a flip-flop, the flip-flop is a D flip-flop, the input end of the D flip-flop is connected to the output end of the selection unit 310, and the D flip-flop
  • the clock drive terminal is connected to the output terminal of the delay control module 400 , and the output terminal of the D flip-flop is connected to the write channel module 100 and the read channel module 200 respectively.
  • the D flip-flop samples the signal input from the input terminal in response to the control signal input from the clock drive terminal. Therefore, the sampling time of the D flip-flop can be controlled by adjusting the delay time of the control signal, so that the stored data can pass through the write channel module 100.
  • the temporary storage unit 320 may also be other devices with a signal temporary storage function, such as a JK flip-flop, an RS flip-flop, and the like.
  • control signal includes one or more of a pulse signal, a rising edge of a signal, and a falling edge of a signal.
  • the temporary storage unit 320 is a latch, it can be controlled by a pulse signal.
  • the temporary storage unit 320 is a trigger, it can be triggered by the rising edge of the signal or the falling edge of the signal. It can be understood that the edge triggering can provide a larger timing margin, thereby improving the sampling timing accuracy of the temporary storage unit 320 , thereby improving the reliability of the data path interface circuit 10 .
  • the write path module 100 includes a write buffer unit 110
  • the read path module 200 includes a read buffer unit 210 .
  • the setting methods of the selection unit 310 , the temporary storage unit 320 and the delay control module 400 are the same as those of the embodiment in FIG. 2 , and details are not repeated here.
  • the write buffer unit 110 the input end of the write buffer unit 110 is connected to the output end of the temporary storage unit 320, the output end of the write buffer unit 110 is connected to the internal port 11, the write buffer unit 110
  • the control terminal is used for receiving the signal instruction.
  • the write buffer unit 110 in response to the signal instruction received by the control terminal, buffers and outputs the delayed-processed stored data input from the input terminal, so as to further adjust the timing, so as to provide a timing accuracy when the storage data is written. Better write path module 100 and data path interface circuit 10.
  • the read buffer unit 210 the input end of the read buffer unit 210 is connected to the output end of the temporary storage unit 320, the output end of the read buffer unit 210 is connected to the external port 12, the read buffer unit 210
  • the control terminal is used for receiving the signal instruction. Similar to the write buffer unit 110 , by setting the read buffer unit 210 , a read path module 200 and a data path interface circuit 10 with better timing accuracy when the stored data is read can be provided.
  • FIG. 4 is a schematic structural diagram of the data path interface circuit 10 according to the fourth embodiment.
  • the delay control module 400 includes a delay chain 410 and a control signal generating circuit 420.
  • the setting methods of the selection unit 310 , the temporary storage unit 320 , the write buffer unit 110 and the read buffer unit 210 are the same as those of the embodiment in FIG. 3 , and will not be repeated here.
  • a delay chain 410 the input end of the delay chain 410 is used for receiving the signal instruction, delaying and outputting the signal instruction.
  • the delay chain 410 may be a fixed delay chain 410 .
  • the fixed delay chain 410 may include a plurality of transmission gates connected in series, and each transmission gate is configured with a fixed delay time. Therefore, a corresponding number of transmission gates may be set according to the preset delay time required to be generated by the delay chain 410, This results in a preset delay time for the target.
  • the fixed delay chain 410 may also include an even number of inverters connected in series. By setting the even number of inverters, it can be ensured that the output delay signal corresponds to the level state of the input signal command, and only exists. The difference in timing is similar to the fixed delay chain 410 formed by the aforementioned transmission gates. A corresponding number of inverters can be set according to the preset delay time required by the delay chain 410 to generate the target preset delay time.
  • the delay chain 410 is a programmable delay chain 410 . It can be understood that the characteristics such as the signal transmission speed in the data path interface circuit 10 will change with the changes of conditions such as the temperature of the use environment. Therefore, if the conditions of the use environment change, there is a risk of abnormal timing or even an error in the transmitted signal.
  • the delay chain 410 composed of the programmable delay chain 410 and setting up a corresponding detection structure, through the detection structure, the condition change of the use environment of the data path interface circuit 10 can be detected, and The delay time of the programmable delay chain 410 is adjusted according to the detection result, thereby avoiding timing errors, thereby providing a data path interface circuit 10 with higher reliability.
  • the detection structure may be a sensor for detecting the use environment, so as to adjust the delay time accordingly with the change of the environment; the detection structure may also be a feedback circuit, that is, according to the time sequence of the signal output by the data path interface circuit 10 Feedback on the input improves timing accuracy through closed-loop regulation.
  • the programmable delay chain 410 may include a plurality of delay units, each delay unit is used to generate a delay of a set step size, and the adjustment of the delay time is realized by the coding group.
  • the encoding group includes a plurality of control encoding bits, and the encoding bits are in one-to-one correspondence with the delay units.
  • the programmable delay chain 410 includes 8 delay units, and the code group includes 8 control code bits.
  • the programmable delay chain 410 can be controlled by changing the value of the code group. It should be noted that the above examples are only used for illustration, and are not used to specifically limit the programmable delay chain 410 and the encoding group.
  • a control signal generation circuit 420 the input end of the control signal generation circuit 420 is connected with the output end of the delay chain 410, the output end of the control signal generation circuit 420 is connected with the control end of the temporary storage unit 320, so the The control signal generating circuit 420 is used for generating a control signal according to the signal output by the delay chain 410 .
  • the control signal output by the control signal generating circuit 420 is a pulse signal, a signal rising edge or a signal falling edge
  • the control signal can implement a relatively reliable timing control function for the temporary storage unit 320.
  • the signal command and the delayed-processed signal command are not necessarily in the form of the above-mentioned desired control signal. Therefore, by providing the control signal generating circuit 420, it is possible to generate a target signal that matches the timing of the delayed-processed signal command. form control signal, so as to achieve accurate control of the temporary storage unit 320 .
  • the first delay module 300 and the delay control module 400 are configured with two working modes, the two working modes include a delay mode and a fast mode, when in the delay mode, all the Both the first delay module 300 and the delay control module 400 are valid; when in the fast mode, the delay control module 400 is invalid, and the transmission delay of the first delay module 300 to the stored data is zero.
  • the fact that both the first delay module 300 and the delay control module 400 are valid means that the delay function of the first delay module 300 is enabled, and the delay control module 400 generates a control signal according to a signal instruction to perform corresponding processing on the stored data. Delay.
  • Both the first delay module 300 and the delay control module 400 are invalid means that the first delay module 300 only enables the transmission function of the stored data, but does not enable the delay function, so that the stored data can pass through quickly, thereby improving the data path interface.
  • the operating speed of the circuit 10 It should be noted that the aforementioned "transmission delay is zero" means that the first delay module 300 does not set an additional delay time for the stored data, but the wires and other structures in the first delay module 300 have a certain inherent delay, but the inherent delay The delay time is minimal, ie, the inherent delay is negligible.
  • FIG. 5 is a schematic structural diagram of the data path interface circuit 10 according to the fifth embodiment.
  • the data path interface circuit 10 further includes a mode selection module 500 .
  • the mode selection module 500 is connected to the first delay module 300 and the delay control module 400 respectively, and is used for receiving the signal instruction and controlling the first delay module 300 and the delay control according to the signal instruction The working mode of the module 400. It can be understood that, for different working modes and positions of the storage blocks 30, each storage block 30 has different path lengths for receiving and storing data.
  • the data path interface circuit 10 corresponding to the storage block 30 with the longest data transmission path can be set as: Fast mode, so that the stored data passes through at the fastest speed, and the data path interface circuits 10 of other storage blocks 30 are delay modules, and the data path interface circuits 10 corresponding to each storage block 30 are controlled to generate corresponding delays, so as to
  • the sum of the transmission time and the delay time consumed by the stored data on the transmission path is a set value, so that the data transmission time corresponding to each storage block 30 is the same.
  • the set value may be the transmission time corresponding to the longest data transmission path.
  • FIG. 6 is a schematic structural diagram of a memory according to an embodiment.
  • the memory includes a data path interface circuit 10 , a data processing module 20 and a storage block 30 .
  • the interface circuit is respectively connected with the data processing module 20 and the storage block 30, so as to realize the sequential processing of the transmitted stored data.
  • the data processing module 20 is connected to the external port 12 of the data path interface circuit 10, and is used for processing the stored data.
  • the processing of the stored data by the data processing module 20 may be serial-to-parallel conversion of storage data transmission. It can be understood that the data processing module 20 may also perform other types of processing on the stored data, so as to improve the transmission of the stored data. speed etc.
  • the storage block 30 is connected to the internal port 11 of the data path interface circuit 10 and is used for storing the storage data.
  • the storage block 30 may include at least two storage sub-blocks 31 , and the storage sub-blocks 31 are connected to the same storage block 30 control circuit.
  • the control circuit includes one or more of a row decoding circuit, a column decoding circuit, and a redundant circuit. By sharing the control circuit, the number of wirings in the memory can be reduced, thereby improving the overall integration of the memory. It is understandable that Yes, sharing the control circuit will also increase the complexity of the control. Therefore, an appropriate circuit can be selected for sharing according to the actual wiring requirements, so as to achieve a balance between the integration degree and the control difficulty.
  • FIG. 6 shows a plurality of bidirectional drivers 40, and the bidirectional drivers 40 are arranged on the transmission path for storing data.
  • the bidirectional driver 40 in FIG. 6 is only used to illustrate the length of the data transmission path. and data transmission speed, specifically, the data transmission path provided with the bidirectional drive 40 is longer, and the data transmission speed is relatively slow.
  • the bidirectional drivers 40 shown in FIG. 6 are not used to limit the specific structure of the data transmission path of the embodiment of the present application, and the bidirectional drivers 40 on each transmission path are not limited to the number and arrangement positions shown in FIG. 6 .
  • the memory includes a plurality of the data path interface circuits 10 and a plurality of storage blocks 30, and the data path interface circuits 10 and the storage blocks 30 are set in a one-to-one correspondence;
  • the external port 12 of the data path interface circuit 10 is connected to the same data processing module 20
  • the internal port 11 of the data path interface circuit 10 is connected to a plurality of the storage sub-blocks 31 .
  • the read stored data can reach the data processing module 20 from the storage sub-block 31 via the internal port 11 and the external port 12 of the interface circuit, thereby realizing data reading.
  • the written storage data can reach the storage sub-block 31 from the data processing module 20 via the external port 12 and the internal port 11 of the interface circuit, thereby realizing data writing.
  • the transmission time of the stored data from the output end of the data processing module 20 to any of the storage sub-blocks 31 matches, and/or the stored data arrives from any of the storage sub-blocks 31 to the storage sub-block 31.
  • the transmission times of the data processing modules 20 are matched. It should be noted that the matching of transmission times includes that the data transmission times corresponding to each storage sub-block 31 are completely the same, and also includes that the errors between the data transmission times corresponding to different storage sub-blocks 31 are within an acceptable range, that is, no affect the accuracy of stored data.
  • two data processing modules 20 are configured to adapt to electronic devices with different configurations.
  • the data processing modules 20 are respectively connected with the plurality of data path interface circuits 10; wherein, when the memory is in the valid mode of the single data processing module 20, one of the data processing modules 20 is controlled to be turned on to transmit data ; When the memory is in the active mode of the multiple data processing modules 20, control a set number of the data processing modules 20 to be turned on, so as to transmit data to the different storage blocks 30 synchronously.
  • the computing speed and addressing capability of the computer are relatively strong, so two data processing modules 20 can be turned on at the same time to achieve faster data transmission speed; In the case of a computer with a 32-bit system, only one data processing module 20 can be turned on, thereby ensuring stable and reliable transmission of the stored data.
  • a corresponding number of data processing modules 20 can be selected and turned on according to an external electronic device, thereby improving the application flexibility and extensiveness of the memory.
  • FIG. 7 is a schematic diagram of a working mode in which both data processing modules 20 are valid according to an embodiment.
  • the embodiment of FIG. 7 takes accessing the storage sub-block B0L and the storage sub-block B0H as an example.
  • the storage sub-block B0H connected to the second data processing module 20H (High Byte) on the right side in FIG. 7 the data transmission path 202 is longer, and the stored data needs to pass through the data path interface at the fastest speed.
  • the circuit 10 is connected to the remote second data processing module 20H through a bidirectional driver 40 between the two data processing module 20 circuits.
  • the data transmission path 201 is short, and the stored data is delayed in the data path interface circuit 10 for a time, and then according to the read and write operations direction, and output the stored data to the corresponding drive.
  • the delay time of the interface circuit is used to match the length of the intermediate bidirectional driver 40 and the corresponding transmission path.
  • the data timing sequence corresponding to the two storage sub-blocks 31 (the storage sub-block B0L and the storage sub-block B0H) can be kept consistent.
  • the adjustment method of the delay time of the other storage blocks 30 is the same as the adjustment method of the storage sub-block B0L and the storage sub-block B0H, which will not be repeated here.
  • Figures 8 to 11 show schematic diagrams of the effective working modes of a single data processing module 20 of the four embodiments, with reference to Figures 8 to 11, the working modes effective for a single data processing module 20 to access the storage sub-block B0L,
  • the storage sub-block B0H, the storage sub-block B3L, and the storage sub-block B3H are exemplified.
  • the longest transmission path is the data transmission path 203 from the first data processing module 20L to the storage sub-block B3H (implemented in bold in black), therefore, accessing other
  • the data transmission path of the location needs to match the data transmission path 203 accessing the storage sub-block B3H.
  • the data transmission path 203 can be called the timing reference path, and the timing reference path includes the wiring and the data path interface circuit 10 .
  • the data passes through the bidirectional driver 40 twice, one is the bidirectional driver 401 between the two data processing modules 20, and the other is the bidirectional driver 402 under the same data processing module 20H.
  • the delay time control that is, work in the fast mode, and the data is transmitted at the fastest speed.
  • the delay time circuit in the data path interface circuit 10 when accessing the storage sub-block B0L and the storage sub-block B0H, if it is a read operation, because the delay time circuit in the data path interface circuit 10 can generate a limited delay time, it is necessary to first store the sub-block.
  • the signal instructions of B0L and storage sub-block B0H are delayed for a time, and then sent to storage sub-block B0L and storage sub-block B0H.
  • the delay time can pass through the middle bidirectional on the data transmission path of storage sub-block B3L and storage sub-block B3H.
  • the delay time introduced by the driver 40 is matched.
  • the transmission path from the data processing module 20L to the storage sub-block B0H is shown as 205 in FIG. 10 (black bold solid line).
  • the transmission path from the data processing module 20L to the storage sub-block B0L is shown as 201 in FIG. 11 (black bold solid line).
  • FIG. 12 is a schematic structural diagram of a memory according to another embodiment, and FIG. 12 is a simplified drawing, only showing the storage sub-block B0L and the storage sub-block B0H.
  • the memory further includes a second delay module 50, and the second delay module 50 can generate the above-mentioned delay of the storage block control signal for the storage sub-block B0L and the storage sub-block B0H, so that the The delay time is further matched.
  • the second delay module 50 is connected to the storage block 30, and is configured to receive the signal instruction, and generate a control signal of the storage block 30 according to the signal instruction, and the control signal of the storage block 30 is used to control the storage block 30.
  • the delay time generated by the second delay module 50 for the control signal of the storage block 30 matches the delay time generated by the data path interface circuit 10 for the stored data.
  • the first delay module 300 and the second delay module 50 function at the same time, which can further improve the synchronization of the transmission of stored data among the plurality of storage sub-blocks 31 .
  • T1 denote the delay time of the timing reference path 203 (see FIG. 8 ) as T1
  • T2A denote the delay time on the lines of the transmission path 204 (see FIG. 9 ) as T2B
  • T3A denote the delay time on the line of the transmission path 205 (see FIG. 10 ) as T3A
  • T3A denote the delay time on the transmission path 205 (see FIG. 10 ) as T3A
  • the delay time on the data path interface circuit 10 is T3B, the delay time on the trace of the transmission path 201 (see FIG.
  • T4A the delay time on the data path interface circuit 10 of the transmission path 201 (see FIG. 11 ) is denoted
  • the delay time is T4B
  • T4C the delay time between the signal command and the second delay module 50 to generate the memory block control signal
  • An embodiment of the present application also provides a storage system, including: the above-mentioned memory; an electronic device; a corresponding number of the data processing modules in the memory.
  • a storage system including: the above-mentioned memory; an electronic device; a corresponding number of the data processing modules in the memory.

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Abstract

一种数据通路接口电路、存储器和存储系统，数据通路接口电路包括：写通路模块（100），分别与内部端口（12）和外部端口（11）连接，用于从外部端口（11）向内部端口（12）传输存储数据；读通路模块（200），分别与内部端口（12）和外部端口（11）连接，用于从内部端口（12）向外部端口（11）传输存储数据；第一延迟模块（300），分别与外部端口（11）和内部端口（12）连接，用于从外部端口（11）或内部端口（12）获取存储数据，对存储数据进行延迟处理，并将处理后的存储数据传输至写通路模块（100）和/或读通路模块（200）；延迟控制模块（400），与第一延迟模块（300）连接，用于接收外部输入的信号指令，并根据信号指令控制第一延迟模块（300）执行延迟处理的延迟时间。

Description

数据通路接口电路、存储器和存储系统
本申请要求于2020年9月23日提交的申请号为202011006722.X、名称为“数据通路接口电路、存储器和存储系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及集成电路领域，特别是涉及一种数据通路接口电路、存储器和存储系统。
背景技术
半导体存储器是一种利用半导体电路进行存取的存储器，其中，动态随机存取存储器(Dynamic Random Access Memory，DRAM)以其快速的存储速度和高集成度被广泛应用于各个领域。存储器中通常会设置多个存储块，以实现更大的存储空间，但是，目前的存储器在运行时，不同的存储块的数据传输速度不同，从而导致不同的存储块的时序不一致，存储数据的传输同步性不佳。
发明内容
本申请一方面提供一种数据通路接口电路，包括：
写通路模块，分别与内部端口和外部端口连接，用于从所述外部端口向所述内部端口传输存储数据；
读通路模块，分别与所述内部端口和所述外部端口连接，用于从所述内部端口向所述外部端口传输所述存储数据；
第一延迟模块，分别与所述外部端口和所述内部端口连接，用于从所述外部端口或所述内部端口获取所述存储数据，对所述存储数据进行延迟处理，并将处理后的所述存储数据传输至所述写通路模块和/或所述读通路模块；
延迟控制模块，与所述第一延迟模块连接，用于接收外部输入的信号指令，并根据所述信号指令控制所述第一延迟模块执行所述延迟处理的延迟时间。
本申请另一方面提供一种存储器，包括：
如上述的数据通路接口电路；
数据处理模块，与所述数据通路接口电路的外部端口连接，用于处理所述存储数据；
存储块，与所述数据通路接口电路的内部端口连接，用于存储所述存储数据。
本申请再一方面提供一种存储系统，包括：
如上述的存储器；
电子设备；
处理模块控制器，分别与所述存储器和所述电子设备连接，用于根据所述电子设备的系统信息开启所述存储器中对应数量的所述数据处理模块。
本发明的各个实施例的细节将在下面的附图和描述中进行说明。根据说明书、附图以及权利要求书的记载，本领域技术人员将容易理解本发明的其它特征、解决的问题以及有益效果。
附图说明
为了更好地描述和说明本申请的实施例，可参考一幅或多幅附图，但用于描述附图的附加细节或示例不应当被认为是对本申请的发明创造、目前所描述的实施例或优选方式中任何一者的范围的限制。
图1为第一实施例的数据通路接口电路的结构示意图；
图2为第二实施例的数据通路接口电路的结构示意图；
图3为第三实施例的数据通路接口电路的结构示意图；
图4为第四实施例的数据通路接口电路的结构示意图；
图5为第五实施例的数据通路接口电路的结构示意图；
图6为一实施例的存储器的结构示意图；
图7为一实施例的两个数据处理模块均有效的工作模式的示意图；
图8为第一实施例的单个数据处理模块有效的工作模式的示意图；
图9为第二实施例的单个数据处理模块有效的工作模式的示意图；
图10为第三实施例的单个数据处理模块有效的工作模式的示意图；
图11为第四实施例的单个数据处理模块有效的工作模式的示意图；
图12为另一实施例的存储器的结构示意图。
具体实施方式
为了便于理解本申请实施例，下面将参照相关附图对本申请实施例进行更全面的描述。附图中给出了本申请实施例的首选实施例。但是，本申请实施例可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请实施例的 公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请实施例的技术领域的技术人员通常理解的含义相同。本文中在本申请实施例的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请实施例。本文所使用的术语“和/或”包括一个或多个相关的所列项目的任意的和所有的组合。
在本申请实施例的描述中，需要理解的是，可能存在的术语“上”、“下”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方法或位置关系，仅是为了便于描述本申请实施例和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请实施例的限制。
图1为第一实施例的数据通路接口电路10的结构示意图，参考图1，在本实施例中，数据通路接口电路10包括写通路模块100、读通路模块200、第一延迟模块300和延迟控制模块400。数据通路接口电路10配置有内部端口11和外部端口12，内部端口11用于连接存储器内部的存储块30，以向存储块30传输待写入的存储数据、或从存储块30读取存储数据，外部端口12用于接收来自外部的电子设备发送的待写入的存储数据、或将从存储块30中读取到的存储数据发送至外部的电子设备。
写通路模块100，分别与内部端口11和外部端口12连接，用于从所述外部端口12向所述内部端口11传输存储数据。其中，写通路模块100的输入端与外部端口12间接连接，具体地，写通路模块100的输入端通过第一延迟模块300间接连接至外部端口12，写通路模块100的输出端与内部端口11直接连接。即，待写入的存储数据由外部的电子设备输入，并接经由口电路的外部端口12、第一延迟模块300、写通路模块100和内部端口11到达存储块30，从而实现存储数据的写入。
读通路模块200，分别与所述内部端口11和所述外部端口12连接，用于从所述内部端口11向所述外部端口12传输所述存储数据。其中，读通路模块200的输入端与内部端口11间接连接，具体地，读通路模块200的输入端通过第一延迟模块300间接连接至内部端口11，读通路模块200的输出端与外部端口12直接连接。即，从存储块30读取存储数据，并接经由数据通路接口电路的内部端口11、第一延迟模块300、读通路模块200和外部端口12到达外部的电子设备，从而实现存储数据的读取。可以理解的是，数据通路接口电路10在同一时间只执行写操作和读操作中的一种，因此，写通路模块100和读通路模块200分时进行存储数据的输出。
第一延迟模块300，分别与所述外部端口12和所述内部端口11连接，用于从所述外部端口12或所述内部端口11获取所述存储数据，对所述存储数据进行延迟处理，并将处理后 的所述存储数据传输至所述写通路模块100和/或所述读通路模块200。
具体地，当数据通路接口电路10进行存储数据的写入时，第一延迟模块300从外部端口11获取存储数据，并对数据进行延迟处理后发送给写通路模块100。其中，待写入的存储数据从存储器的数据引脚写入，每个数据引脚连接至多个存储块30，并将存储数据发送至相连接的多个存储块30中。可以理解的是，每个数据通路接口电路10的外部端口12与数据引脚之间的传输路径的长度并不相同，因此，即使数据同时到达数据引脚，但基于相近的数据传输速度和不同的传输路径长度，存储数据不能同时到达每个存储块30，从而导致了背景技术中记载的存储数据的传输不同步的现象。数据通路接口电路10进行存储数据的读取时，也存在存储数据的传输不同步的现象，引发原因与前述的写入数据不同步的原因相似，此处不再进行赘述。在本实施例中，第一延迟模块300可以对接收到的存储数据进行恰当延迟时间的延迟处理，以使存储数据在预设的目标时间到达内部端口11，从而使每个数据通路接口电路10中存储数据到达内部端口11的时间相同，或使时间误差在数据通路接口电路10可以承受的误差范围内，从而解决了存储数据的传输不同步的现象。
可选地，可以通过多种硬件结构实现写通路模块100和读通路模块200分时进行存储数据的输出的功能。示例性地，在图1所示的实施例中，第一延迟模块300配置有一个输出端，且该输出端分别连接至写通路模块100和读通路模块200，第一延迟模块300同时输出延迟处理后的存储数据至写通路模块100和读通路模块200，并可以通过控制写通路模块100和读通路模块200中的一个开启，从而使二者中的一个输出存储数据。在其他实施例中，也可以是第一延迟模块300配置有两个输出端，且两个输出端一一对应连接至写通路模块100和读通路模块200，并可以控制第一延迟模块300的两个输出端中的一个输出存储数据，以使写通路模块100和读通路模块200中只有一个能接收到存储数据，从而使二者中的一个输出存储数据。
延迟控制模块400，与所述第一延迟模块300连接，用于接收外部输入的信号指令，并根据所述信号指令控制所述第一延迟模块300执行所述延迟处理的延迟时间。其中，信号指令是指用于指示数据通路接口电路10执行相应操作的指令，例如可以为写指令、读指令、模式选择编码指令中的一种或多种，示例性地，写指令即用于指示数据通路接口电路10执行相应的写操作。
具体地，延迟控制模块400可以配置有一个或多个输入端，并根据输入端输入的信号指令生成第一延迟模块300的控制信号。例如，若延迟控制模块400配置有一个输入端，则可以响应于写指令、读指令、模式选择编码指令中的一种生成控制信号。若延迟控制模块400配置有两个输入端，则可以响应于写指令、读指令、模式选择编码指令中的两种生成控制信号。 可以理解的是，延迟控制模块400所需相应的信号指令的种类越多，生成控制信号的逻辑越复杂，但相应地也会具有更加可靠、全面的控制功能，从而提高数据通路接口电路10的可靠性和全面性，即更大程度上的改善存储数据的传输同步性。
在本实施例中，数据通路接口电路10包括：写通路模块100，分别与内部端口11和外部端口12连接，用于从所述外部端口12向所述内部端口11传输存储数据；读通路模块200，分别与所述内部端口11和所述外部端口12连接，用于从所述内部端口11向所述外部端口12传输所述存储数据；第一延迟模块300，分别与所述外部端口12和所述内部端口11连接，用于从所述外部端口12或所述内部端口11获取所述存储数据，对所述存储数据进行延迟处理，并将处理后的所述存储数据传输至所述写通路模块100和/或所述读通路模块200；延迟控制模块400，与所述第一延迟模块300连接，用于接收外部输入的信号指令，并根据所述信号指令控制所述第一延迟模块300执行所述延迟处理的延迟时间。通过延迟控制模块400输出的控制信号，可以使第一延迟模块300对接收到的存储数据进行恰当延迟时间的延迟处理，以使存储数据在目标时间到达内部端口11或外部端口12，从而使每个数据通路接口电路10中存储数据在内部端口11和外部端口12之间的传输时间相同，或使传输时间的误差在数据通路接口电路10可以承受的误差范围内，从而实现了存储数据的传输同步性更好的数据通路接口电路10。
图2为第二实施例的数据通路接口电路10的结构示意图，参考图2，在本实施例中，所述第一延迟模块300包括选择单元310和暂存单元320。在本实施例中，写通路模块100、读通路模块200和延迟控制模块400的设置方式和图1实施例的设置方式相同，此处不再进行赘述。
选择单元310，所述选择单元310的输入端分别与所述外部端口12和所述内部端口11连接，所述选择单元310的控制端用于接收所述信号指令。
具体地，选择单元310配置有两个输入端，选择单元310的两个输入端分别一一对应连接至内部端口11和外部端口12，以分别从两个端口获取存储数据，选择单元310还配置有控制端，选择单元310的控制端用于接收信号指令，以根据信号指令选择输出接收到的两个存储数据中的一个。示例性地，信号指令可以为写指令，则选择单元310选择输出来自外部端口12的存储数据，从而实现数据的写入。在图2所示的实施例中，选择单元310为二选一多路选择器，在其他实施例中，选择单元310也可以为三选一多路选择器等，即，通过配置三个输入端实现更加复杂的选择和传输功能。
暂存单元320，所述暂存单元320的数据输入端与所述选择单元310的输出端连接，所述暂存单元320的控制端与所述延迟控制模块400的输出端连接。其中，所述暂存单元320 包括锁存器、触发器、寄存器中的一种或多种，所述暂存单元320的控制端包括时钟驱动端、置位端、复位端中的一种或多种。
具体地，在图2所示的实施例中，暂存单元320可以包括一个触发器，该触发器为D触发器，D触发器的输入端与选择单元310的输出端连接，D触发器的时钟驱动端与延迟控制模块400的输出端连接，D触发器的输出端分别与写通路模块100和读通路模块200连接。D触发器的响应于时钟驱动端输入的控制信号对输入端输入的信号进行采样，因此，可以通过调节控制信号的延迟时间，控制D触发器的采样时间，以使存储数据通过写通路模块100或读通路模块200，并在目标时间到达内部端口11或外部端口12，从而实现时序同步性更好的数据通路接口电路10。可选地，通过为暂存单元320配置置位端和/或复位端，并在暂存单元320未执行信号采样时，向置位端和/或复位端输出预设的使能信号，可以确保暂存单元320的稳定输出，从而提高数据通路接口电路10的输出信号的可靠性。在其他实施例中，暂存单元320也可以为JK触发器、RS触发器等具有信号的暂存功能的其他器件。
进一步地，所述控制信号包括脉冲信号、信号上升沿、信号下降沿中的一种或多种。其中，若暂存单元320为锁存器，则可以选择通过脉冲信号进行控制。若暂存单元320为触发器，则可以选择通过信号上升沿或信号下降沿进行触发，可以理解的是，边沿触发可以提供更大的时序裕度，从而提高暂存单元320的采样时序准确性，进而提高数据通路接口电路10的可靠性。
图3为第三实施例的数据通路接口电路10的结构示意图，参考图3，在本实施例中，所述写通路模块100包括写缓冲单元110，读通路模块200包括读缓冲单元210。在本实施例中，选择单元310、暂存单元320和延迟控制模块400的设置方式和图2实施例的设置方式相同，此处不再进行赘述。
写缓冲单元110，所述写缓冲单元110的输入端与所述暂存单元320的输出端连接，所述写缓冲单元110的输出端与所述内部端口11连接，所述写缓冲单元110的控制端用于接收所述信号指令。写缓冲单元110响应于控制端接收到的信号指令，对输入端输入的延迟处理后的存储数据进行缓冲输出，从而实现对时序的进一步调节，以提供一种存储数据写入时的时序准确性更好的写通路模块100和数据通路接口电路10。读缓冲单元210，所述读缓冲单元210的输入端与所述暂存单元320的输出端连接，所述读缓冲单元210的输出端与所述外部端口12连接，所述读缓冲单元210的控制端用于接收所述信号指令。与写缓冲单元110相似地，通过设置读缓冲单元210，可以提供一种存储数据读取时的时序准确性更好的读通路模块200和数据通路接口电路10。
图4为第四实施例的数据通路接口电路10的结构示意图，参考图4，在本实施例中，所 述延迟控制模块400包括延迟链410和控制信号产生电路420。在本实施例中，选择单元310、暂存单元320、写缓冲单元110和读缓冲单元210的设置方式和图3实施例的设置方式相同，此处不再进行赘述。
延迟链410，所述延迟链410的输入端用于接收所述信号指令，并对所述信号指令进行延迟并输出。
在其中一个实施例中，延迟链410可以为固定延迟链410。示例性地，固定延迟链410可以包括多个串联的传输门，每个传输门配置有固定的延迟时间，因此，可以根据延迟链410所需产生的预设延迟时间设置相应数量的传输门，从而产生目标的预设延迟时间。另一示例性地，固定延迟链410也可以包括偶数个串联的反相器，通过设置偶数个反相器，可以确保输出的延迟信号与输入的信号指令的电平状态相对应，且只存在时序上的差异，与前述传输门构成的固定延迟链410相似地，可以根据延迟链410所需产生的预设延迟时间设置相应数量的反相器，从而产生目标的预设延迟时间。
在其中另一个实施例中，所述延迟链410为可编程延迟链410。可以理解的是，数据通路接口电路10中的信号传输速度等特性，都会随着使用环境的温度等条件的变化而发生改变。因此，若使用环境的条件变化，会存在时序异常甚至传输的信号发生错误的风险。在本实施例中，通过设置由可编程延迟链410构成的延迟链410，并设置一相应的检测结构，通过检测结构，可以对数据通路接口电路10的使用环境的条件变化情况进行检测，并根据检测结果调节可编程延迟链410的延迟时间，从而避免了时序发生错误，从而提供了一种可靠性更高的数据通路接口电路10。其中，检测结构可以是一个对使用环境进行检测的传感器，从而跟随环境的变化对延迟时间进行相应的调节；检测结构也可以是一个反馈电路，即，根据数据通路接口电路10输出的信号的时序对输入进行反馈，从而通过闭环调节的方式改善时序的准确性。
进一步地，可编程延迟链410可以包括多个延迟单元，每个延迟单元用于产生设定步长的延迟，并通过编码组实现对延迟时间的调节。具体地，编码组包括多个控制编码位，且编码位与延迟单元一一对应。示例性地，可编程延迟链410包括8个延迟单元，编码组包括8个控制编码位，当编码组的数值为10000000时，即控制第一个延迟单元开启，而其他延迟单元关闭，以产生一个设定步长的延迟；当编码组的数值为10000001时，即控制第一个延迟单元和第八个延迟单元开启，而其他延迟单元关闭，以产生两个设定步长的延迟。因此，通过改变编码组的数值，即可实现对可编程延迟链410的控制。需要说明的是，上述示例仅用于说明，而不用于具体限定可编程延迟链410和编码组。
控制信号产生电路420，所述控制信号产生电路420的输入端与所述延迟链410的输出 端连接，所述控制信号产生电路420的输出端与所述暂存单元320的控制端连接，所述控制信号产生电路420用于根据所述延迟链410输出的信号产生一控制信号。具体地，根据前述说明，当控制信号产生电路420输出的控制信号为脉冲信号、信号上升沿或信号下降沿时，控制信号可以实现对暂存单元320的较为可靠的时序控制功能，可以理解的是，信号指令和延迟处理后的信号指令不一定为上述期望的控制信号的形式，因此，通过设置控制信号产生电路420，可以生成与延迟处理后的信号指令的时序相匹配的、且为目标形式的控制信号，从而实现对暂存单元320的准确控制。
在其中一个实施例中，所述第一延迟模块300和所述延迟控制模块400配置有两个工作模式，所述两个工作模式包括延迟模式和快速模式，当处于所述延迟模式时，所述第一延迟模块300和所述延迟控制模块400均有效；当处于所述快速模式时，所述延迟控制模块400无效，所述第一延迟模块300对所述存储数据的传输延迟为零。其中，所述第一延迟模块300和所述延迟控制模块400均有效是指，第一延迟模块300的延迟功能开启，且延迟控制模块400根据信号指令生成控制信号，以对存储数据进行相应的延迟。所述第一延迟模块300和所述延迟控制模块400均无效是指，第一延迟模块300只开启存储数据的传输功能，而不开启延迟功能，以使存储数据快速通过，从而提高数据通路接口电路10的运行速度。需要说明的是，前述“传输延迟为零”是指第一延迟模块300不对存储数据设置额外的延迟时间，但是第一延迟模块300中的导线等结构存在一定的固有延迟，只是该固有延迟的延迟时间极小，即，该固有延迟可以忽略不计。
图5为第五实施例的数据通路接口电路10的结构示意图，参考图5，在本实施例中，所述数据通路接口电路10还包括模式选择模块500。
模式选择模块500，分别与所述第一延迟模块300和所述延迟控制模块400连接，用于接收所述信号指令，并根据所述信号指令控制所述第一延迟模块300和所述延迟控制模块400的工作模式。可以理解的是，针对不同的工作模式和存储块30位置，每个存储块30接收存储数据的路径长度不同，因此，可以设置数据传输路径最长的存储块30对应的数据通路接口电路10为快速模式，从而使存储数据以最快的速度通过，并使其他存储块30的数据通路接口电路10为延迟模块，并控制每个存储块30对应的数据通路接口电路10产生相应的延迟，以使存储数据在传输路径上消耗的传输时间与延迟时间之和均为一设定值，从而使每个存储块30对应的数据传输时间相同。其中，该设定值可以为最长的数据传输路径所对应的传输时间。
图6为一实施例的存储器的结构示意图，参考图6，在本实施例中，存储器包括数据通路接口电路10、数据处理模块20和存储块30。
如上述的数据通路接口电路10，接口电路分别与数据处理模块20和存储块30连接，从而实现对传输的存储数据的时序处理。
数据处理模块20，与所述数据通路接口电路10的外部端口12连接，用于处理所述存储数据。示例性地，数据处理模块20对存储数据的处理可以为存储数据传输的串并行转换，可以理解的是，数据处理模块20也可以对存储数据进行其他类型的处理，以实现提高存储数据的传输速度等目的。
存储块30，与所述数据通路接口电路10的内部端口11连接，用于存储所述存储数据。其中，所述存储块30可以包括至少两个存储子块31，所述存储子块31连接至同一存储块30控制电路。其中，控制电路包括行译码电路、列译码电路、冗余电路中的一种或多种，通过共用控制电路，可以减少存储器中的布线数量，从而提高存储器的整体集成度，可以理解的是，共用控制电路也会同时提高控制的复杂度，因此，可以根据实际的布线需求选择恰当的电路进行共用，从而实现集成度和控制难度之间的平衡。
需要说明的是，图6实施例中示出了多个双向驱动器40，双向驱动器40设置于存储数据的传输路径上，图6中的双向驱动器40仅用于示例性地说明数据传输路径的长度和数据的传输速度，具体是指设置有双向驱动器40的数据传输路径较长，数据的传输速度较慢。但是，图6中示出的双向驱动器40不用于限定本申请实施例的数据传输路径的具体结构，每个传输路径上的双向驱动器40也不局限于图6中示出的数量和设置位置。
进一步地，继续参考图6，所述存储器包括多个所述数据通路接口电路10和多个存储块30，所述数据通路接口电路10和所述存储块30一一对应设置；所述多个数据通路接口电路10的外部端口12与同一所述数据处理模块20连接，所述数据通路接口电路10的内部端口11与多个所述存储子块31连接。读取的存储数据即可从存储子块31经由接口电路的内部端口11、外部端口12到达数据处理模块20，从而实现数据的读取。写入的存储数据即可从数据处理模块20经由接口电路的外部端口12、内部端口11到达存储子块31，从而实现数据的写入。其中，所述存储数据从所述数据处理模块20的输出端到达任一所述存储子块31的传输时间相匹配，和/或所述存储数据从任一所述存储子块31到达所述数据处理模块20的传输时间相匹配。需要说明的是，传输时间相匹配包括每个存储子块31对应的数据传输时间完全相同，还包括不同存储子块31对应的数据传输时间之间的误差在可接受的范围内，即不会对存储数据的准确性造成影响。
进一步地，在图6所示的实施例中，配置有两个数据处理模块20，以适配不同配置的电子设备。具体地，所述数据处理模块20分别与所述多个数据通路接口电路10连接；其中，当所述存储器处于单数据处理模块20有效模式时，控制一个所述数据处理模块20开启以传 输数据；当所述存储器处于多数据处理模块20有效模式时，控制设定数量的所述数据处理模块20开启，以同步传输数据至不同的所述存储块30。示例性地，当存储器应用于64位系统的电脑时，电脑的运算速度和寻址能力较强，因此可以同时开启两个数据处理模块20，以实现更快的数据传输速度；当存储器应用于32位系统的电脑时，则可以只开启一个数据处理模块20，从而确保存储数据的稳定、可靠传输。本实施例的存储器可以根据外部的电子设备，选择开启相应数量的数据处理模块20，从而提高了存储器的应用灵活性和广泛性。
具体地，图7为一实施例的两个数据处理模块20均有效的工作模式的示意图，图7实施例以访问存储子块B0L和存储子块B0H为例。参考图7，对于连接到位于图7中右侧的第二数据处理模块20H(High Byte)的存储子块B0H，数据传输路径202较长，存储数据需要以最快的速度穿过数据通路接口电路10，并且通过两个数据处理模块20电路之间的双向驱动器40，连接到远端的第二数据处理模块20H。对于连接到位于图7中左侧的第一数据处理模块20L(Low Byte)的存储子块B0L，数据传输路径201较短，存储数据在数据通路接口电路10被延迟时间，然后根据读写操作的方向，将存储数据输出给对应的驱动器。而接口电路的延迟时间，用于匹配中间的双向驱动器40和对应的传输路径的长度。在本实施例中，通过调整接口电路的延迟时间，可以使两个存储子块31(存储子块B0L和存储子块B0H)对应的数据时序保持一致。其他存储块30的延迟时间的调节方式与存储子块B0L和存储子块B0H的调节方式相同，此处不再进行赘述。
图8至图11示出了四个实施例的单个数据处理模块20有效的工作模式的示意图，参考8图至图11，对于单个数据处理模块20有效的工作模式，以访问存储子块B0L，存储子块B0H，存储子块B3L，存储子块B3H举例说明。
如图8所示，对于单个数据处理模块20L有效的工作模式，最长的传输路径是第一数据处理模块20L到存储子块B3H的数据传输路径203(黑色加粗实现)，因此，访问其他位置的数据传输路径都需要和访问存储子块B3H的数据传输路径203匹配，这里可以将数据传输路径203称为时序基准路径，该时序基准路径包括了走线和数据通路接口电路10。访问存储子块B3H时，数据通过两次双向驱动器40，一次是两个数据处理模块20之间的双向驱动器401，另一次是同一个数据处理模块20H下方的双向驱动器402，对于数据通路接口电路10，则跳过延迟时间控制，即工作在快速模式，数据以最快的速度传输。
参考图9，访问存储子块B3L时，与存储子块B3H相比，数据传输路径上减少一个双向驱动器40和部分走线，该传输路径如图9中204所示(黑色加粗实线)，因此，存储子块B3L的数据通路接口电路10中的延迟时间电路是工作的，延迟时间被设置为与存储子块B3H的多出来的双向驱动器40及相关走线匹配。
参考图10和图11，访问存储子块B0L和存储子块B0H时，如果是读操作，由于数据通路接口电路10中的延迟时间电路能产生的延迟时间有限，因此，需要先将存储子块B0L和存储子块B0H的信号指令进行延迟时间，再发送至存储子块B0L和存储子块B0H，而且，该延迟时间可以与存储子块B3L和存储子块B3H的数据传输路径上经过中间双向驱动器40引入的延迟时间相匹配。数据处理模块20L到存储子块B0H的传输路径如图10中205所示(黑色加粗实线)。数据处理模块20L到存储子块B0L的传输路径如图11中201所示(黑色加粗实线)。
因此，图12为另一实施例的存储器的结构示意图，图12为简化附图，仅示出了存储子块B0L和存储子块B0H。参考图12，在本实施例中，存储器还包括第二延迟模块50，第二延迟模块50可以产生上述对存储子块B0L和存储子块B0H的存储块控制信号延迟，以使传输路径上的延迟时间进一步匹配。具体地，第二延迟模块50与所述存储块30连接，用于接收所述信号指令，并根据所述信号指令生成存储块30控制信号，所述存储块30控制信号用于控制所述存储数据进入所述存储块30的时间。基于上述结构，所述第二延迟模块50对存储块30控制信号产生的延迟时间与所述数据通路接口电路10对所述存储数据产生的延迟时间相匹配。在本实施例中，第一延迟模块300和第二延迟模块50同时作用，可以进一步提高多个存储子块31之间的存储数据的传输的同步性。
继续参考图8、图9、图10、图11和图12，记时序基准路径203(见图8)的延迟时间为T1，记传输路径204(见图9)的走线上的延迟时间为T2A，记传输路径204(见图9)的数据通路接口电路10上的延迟时间为T2B，记传输路径205(见图10)的走线上的延迟时间为T3A，记传输路径205(见图10)的数据通路接口电路10上的延迟时间为T3B，记传输路径201(见图11)的走线上的延迟时间为T4A，记传输路径201(见图11)的数据通路接口电路10上的延迟时间为T4B，记从信号指令经过第二延迟模块50产生存储块控制信号之间的延迟时间为T4C，则T2A加T2B之和、T3A加T3B之和、T4A加T4B再加T4C之和均应与T1相匹配，这里的匹配是指相等或基本相等或误差在一可接受范围内。
本申请实施例还提供了一种存储系统，包括：如上述的存储器；电子设备；处理模块控制器，分别与所述存储器和所述电子设备连接，用于根据所述电子设备的系统信息开启所述存储器中对应数量的所述数据处理模块。在本实施例中，通过设置上述结构，实现了一种存储数据传输同步性更高的存储系统，其中，存储器的具体的设置方式可参考前述说明，此处不再进行赘述。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾， 都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请实施例的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请实施例构思的前提下，还可以做出若干变形和改进，这些都属于本申请实施例的保护范围。因此，本申请实施例专利的保护范围应以所附权利要求为准。

Claims (19)

  1. 一种数据通路接口电路，包括：
    写通路模块，分别与内部端口和外部端口连接，用于从所述外部端口向所述内部端口传输存储数据；
    读通路模块，分别与所述内部端口和所述外部端口连接，用于从所述内部端口向所述外部端口传输所述存储数据；
    第一延迟模块，分别与所述外部端口和所述内部端口连接，用于从所述外部端口或所述内部端口获取所述存储数据，对所述存储数据进行延迟处理，并将处理后的所述存储数据传输至所述写通路模块和/或所述读通路模块；
    延迟控制模块，与所述第一延迟模块连接，用于接收外部输入的信号指令，并根据所述信号指令控制所述第一延迟模块执行所述延迟处理的延迟时间。
  2. 根据权利要求1所述的数据通路接口电路，其中，所述第一延迟模块包括：
    选择单元，所述选择单元的输入端分别与所述外部端口和所述内部端口连接，所述选择单元的控制端用于接收所述信号指令；
    暂存单元，所述暂存单元的数据输入端与所述选择单元的输出端连接，所述暂存单元的控制端与所述延迟控制模块的输出端连接。
  3. 根据权利要求2所述的数据通路接口电路，其中，所述暂存单元包括锁存器、触发器、寄存器中的一种或多种，所述暂存单元的控制端包括时钟驱动端、置位端、复位端中的一种或多种。
  4. 根据权利要求2所述的数据通路接口电路，其中，所述写通路模块包括：
    写缓冲单元，所述写缓冲单元的输入端与所述暂存单元的输出端连接，所述写缓冲单元的输出端与所述内部端口连接，所述写缓冲单元的控制端用于接收所述信号指令；
    所述读通路模块包括：
    读缓冲单元，所述读缓冲单元的输入端与所述暂存单元的输出端连接，所述读缓冲单元的输出端与所述外部端口连接，所述读缓冲单元的控制端用于接收所述信号指令。
  5. 根据权利要求2所述的数据通路接口电路，其中，所述延迟控制模块包括：
    延迟链，所述延迟链的输入端用于接收所述信号指令，并对所述信号指令进行延迟并输出；
    控制信号产生电路，所述控制信号产生电路的输入端与所述延迟链的输出端连接，所述控制信号产生电路的输出端与所述暂存单元的控制端连接，所述控制信号产生电路用于根据所述延迟链输出的信号产生一控制信号。
  6. 根据权利要求5所述的数据通路接口电路，其中，所述延迟链为可编程延迟链。
  7. 根据权利要求5所述的数据通路接口电路，其中，所述控制信号包括脉冲信号、信号上升沿、信号下降沿中的一种或多种。
  8. 根据权利要求1所述的数据通路接口电路，其中，所述第一延迟模块和所述延迟控制模块配置有两个工作模式，所述两个工作模式包括延迟模式和快速模式，当处于所述延迟模式时，所述第一延迟模块和所述延迟控制模块均有效；当处于所述快速模式时，所述延迟控制模块无效，所述第一延迟模块对所述存储数据的传输延迟为零，所述数据通路接口电路还包括：
    模式选择模块，分别与所述第一延迟模块和所述延迟控制模块连接，用于接收所述信号指令，并根据所述信号指令控制所述第一延迟模块和所述延迟控制模块的工作模式。
  9. 根据权利要求8所述的数据通路接口电路，其中，所述信号指令包括写指令、读指令、模式选择编码指令中的一种或多种。
  10. 一种存储器，包括：
    如权利要求1至9中任一项所述的数据通路接口电路；
    数据处理模块，与所述数据通路接口电路的外部端口连接，用于处理所述存储数据；
    存储块，与所述数据通路接口电路的内部端口连接，用于存储所述存储数据。
  11. 根据权利要求10所述的存储器，其中，还包括：
    第二延迟模块，与所述存储块连接，用于接收所述信号指令，并根据所述信号指令生成存储块控制信号，所述存储块控制信号用于控制所述存储数据进入所述存储块的时间。
  12. 根据权利要求11所述的存储器，其中，所述第二延迟模块对存储块控制信号产生的延迟时间与所述数据通路接口电路对所述存储数据产生的延迟时间相匹配。
  13. 根据权利要求10所述的存储器，其中，所述存储块包括至少两个存储子块，所述存储子块连接至同一存储块控制电路。
  14. 根据权利要求13所述的存储器，其中，所述存储块控制电路包括行译码电路、列译码电路、冗余电路中的一种或多种。
  15. 根据权利要求13所述的存储器，其中，所述存储器包括多个所述数据通路接口电路和多个存储块，所述数据通路接口电路和所述存储块一一对应设置；
    所述多个数据通路接口电路的外部端口与同一所述数据处理模块连接，所述数据通路接口电路的内部端口与多个所述存储子块连接。
  16. 根据权利要求15所述的存储器，其中，所述存储数据从所述数据处理模块的输出端到达任一所述存储子块的传输时间相匹配。
  17. 根据权利要求15所述的存储器，其中，所述存储数据从任一所述存储子块到达所述数据处理模块的传输时间相匹配。
  18. 根据权利要求15所述的存储器，其中，所述存储器包括两个所述数据处理模块，所述数据处理模块分别与所述多个数据通路接口电路连接；
    其中，当所述存储器处于单数据处理模块有效模式时，控制一个所述数据处理模块开启以传输数据；当所述存储器处于多数据处理模块有效模式时，控制设定数量的所述数据处理模块开启，以同步传输数据至不同的所述存储块。
  19. 一种存储系统，包括：
    如权利要求10至18任一项所述的存储器；
    电子设备；
    处理模块控制器，分别与所述存储器和所述电子设备连接，用于根据所述电子设备的系统信息开启所述存储器中对应数量的所述数据处理模块。
PCT/CN2021/100794 2020-09-23 2021-06-18 数据通路接口电路、存储器和存储系统 WO2022062497A1 (zh)

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