WO2022052242A1 - Substrat de réseau et écran d'affichage - Google Patents

Substrat de réseau et écran d'affichage Download PDF

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Publication number
WO2022052242A1
WO2022052242A1 PCT/CN2020/124691 CN2020124691W WO2022052242A1 WO 2022052242 A1 WO2022052242 A1 WO 2022052242A1 CN 2020124691 W CN2020124691 W CN 2020124691W WO 2022052242 A1 WO2022052242 A1 WO 2022052242A1
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WIPO (PCT)
Prior art keywords
sub
via hole
electrode
thin film
array substrate
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PCT/CN2020/124691
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English (en)
Chinese (zh)
Inventor
奚苏萍
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2022052242A1 publication Critical patent/WO2022052242A1/fr

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate and a display panel.
  • the backlight As the size of the panel becomes larger and larger, the backlight also becomes larger, which means that the heating of the backlight will increase.
  • the brightness of the backlight can be reduced by increasing the penetration rate of the panel, thereby effectively avoiding the heating phenomenon, that is, increasing the pixel (pixel) ), it is particularly necessary to increase the penetration rate of the panel accordingly.
  • Large size and high resolution means that the size of the pixel is getting smaller and smaller, and the opening area is also getting smaller. And people's requirements for color shift are getting higher and higher.
  • 8-domain display is usually used, that is, the so-called 3T or 3T plus structure is usually used, which means that it will take up more space and sacrifice accordingly. Partially open area.
  • Large-size backlights generate serious heat, and it is necessary to effectively avoid this phenomenon by increasing the transmittance. However, for high-resolution, large-size, and high-specification products, it becomes difficult to increase the transmittance.
  • the present application provides an array substrate and a display panel, which can improve the pixel aperture ratio of high-resolution large-size products, thereby improving the transmittance to solve the problem of serious heat generation of large-size backlights.
  • the present application provides an array substrate, including sub-pixels distributed in an array, each of the sub-pixels includes a main area thin film transistor, a sub area thin film transistor and a shared thin film transistor;
  • the sub-pixel includes a main area and a sub-area, a main pixel electrode is disposed corresponding to the main area, and a sub-pixel electrode is disposed corresponding to the sub-area, and the sub-pixel further includes the main pixel electrode and the sub-pixel.
  • the main area thin film transistor is electrically connected to the main pixel electrode through a first via hole
  • the sub area thin film transistor is electrically connected to the sub pixel electrode through a second via hole
  • the shared thin film transistor is electrically connected through a third via hole electrically connected to the common electrode
  • the diameter of the third via hole is smaller than the diameter of the first via hole and the diameter of the second via hole.
  • the array substrate includes:
  • a gate disposed on the substrate
  • a gate insulating layer disposed on the gate
  • an active layer disposed on the gate insulating layer corresponding to the gate
  • source/drain disposed at both ends of the active layer and in contact with the ion-doped regions of the active layer;
  • a pixel electrode layer disposed on the organic protective layer, including the main pixel electrode and the sub-pixel electrode;
  • the common electrode and the gate electrode are disposed in the same layer, the first via hole and the second via hole penetrate through the organic protective layer, and the third via hole penetrates through the gate insulating layer.
  • one of the sub-pixels is provided with a first source electrode, a second source electrode, a first drain electrode and a second drain electrode, wherein the main area thin film transistor and the sub area thin film The transistors share the first source electrode, and the sub-region thin film transistor and the shared thin film transistor share the second drain electrode.
  • a non-display area is included between the main area and the sub area of the same sub-pixel, and the main area thin film transistor, the sub area thin film transistor and the shared thin film transistor correspond to In the non-display area, at least a part of the first via hole is located in the main area, and at least a part of the second via hole is located in the sub area.
  • the projection range of the main pixel electrode on the array substrate at least partially covers the projection range of the first via hole on the array substrate, and the sub-pixel electrode is on the array substrate.
  • the projection range on the substrate at least partially covers the projection range of the second via hole on the array substrate.
  • both the main pixel electrode and the sub-pixel electrode include a trunk electrode and a branch electrode, and the first via hole and the second via hole are located at the trunk electrode correspondingly.
  • the first via hole and the second via hole are symmetrically arranged along the center line of the non-display area.
  • At least a part of the third via hole is located in the sub-region.
  • the projection range of the main pixel electrode and the sub-pixel electrode on the array substrate at least partially covers the projection range of the common electrode on the array substrate.
  • the common electrode is a transparent material.
  • the present application further provides a display panel including an array substrate, the array substrate includes sub-pixels distributed in an array, and each of the sub-pixels includes a main area thin film transistor, a sub area thin film transistor and a shared thin film transistor;
  • the sub-pixel includes a main area and a sub-area, a main pixel electrode is disposed corresponding to the main area, and a sub-pixel electrode is disposed corresponding to the sub-area, and the sub-pixel further includes the main pixel electrode and the sub-pixel.
  • the main area thin film transistor is electrically connected to the main pixel electrode through a first via hole
  • the sub area thin film transistor is electrically connected to the sub pixel electrode through a second via hole
  • the shared thin film transistor is electrically connected through a third via hole electrically connected to the common electrode
  • the diameter of the third via hole is smaller than the diameter of the first via hole and the diameter of the second via hole.
  • the array substrate includes:
  • a gate disposed on the substrate
  • a gate insulating layer disposed on the gate
  • an active layer disposed on the gate insulating layer corresponding to the gate
  • source/drain disposed at both ends of the active layer and in contact with the ion-doped regions of the active layer;
  • a pixel electrode layer disposed on the organic protective layer, including the main pixel electrode and the sub-pixel electrode;
  • the common electrode and the gate electrode are disposed in the same layer, the first via hole and the second via hole penetrate through the organic protective layer, and the third via hole penetrates through the gate insulating layer.
  • one of the sub-pixels is provided with a first source electrode, a second source electrode, a first drain electrode and a second drain electrode, wherein the main area thin film transistor and the sub area thin film The transistors share the first source electrode, and the sub-region thin film transistor and the shared thin film transistor share the second drain electrode.
  • a non-display area is included between the main area and the sub area of the same sub-pixel, and the main area thin film transistor, the sub area thin film transistor and the shared thin film transistor correspond to In the non-display area, at least a part of the first via hole is located in the main area, and at least a part of the second via hole is located in the sub area.
  • the projection range of the main pixel electrode on the array substrate at least partially covers the projection range of the first via hole on the array substrate, and the sub pixel electrode is on the array substrate.
  • the projection range on the substrate at least partially covers the projection range of the second via hole on the array substrate.
  • both the main pixel electrode and the sub-pixel electrode include a main electrode and a branch electrode, and the first via hole and the second via hole are located at the main electrode correspondingly.
  • the first via hole and the second via hole are symmetrically arranged along the center line of the non-display area.
  • At least a part of the third via hole is located in the sub-region.
  • the projection range of the main pixel electrode and the sub-pixel electrode on the array substrate at least partially covers the projection range of the common electrode on the array substrate.
  • the common electrode is a transparent material.
  • each sub-pixel includes a main area thin film transistor, a sub area thin film transistor and a shared thin film transistor, and the main area thin film transistor is electrically connected to the main pixel electrode through the first via hole.
  • the sub-region thin film transistor is electrically connected to the sub-pixel electrode through the second via hole
  • the shared thin film transistor is electrically connected to the common electrode through the third via hole.
  • the aperture of the third via hole is reduced by changing the third via hole that originally penetrated through the organic protective layer to the gate insulating layer, thereby increasing the aperture ratio and transmittance of the pixel, thus solving the problem of backlight heat generation. big technical problem.
  • FIG. 1 is a schematic structural diagram of a sub-pixel on a conventional array substrate
  • FIG. 2 is a schematic structural diagram of a sub-pixel on an array substrate provided in Embodiment 1 of the present application;
  • FIG. 3 is a schematic cross-sectional view of the array substrate provided in Embodiment 1 of the present application along the first/second via hole;
  • FIG. 4 is a schematic cross-sectional view of the array substrate according to Embodiment 1 of the present application along a third via hole;
  • FIG. 5 is a schematic structural diagram of a sub-pixel on an array substrate according to Embodiment 2 of the present application.
  • FIG. 6 is a schematic structural diagram of a sub-pixel on an array substrate provided in Embodiment 3 of the present application.
  • FIG. 7 is a schematic structural diagram of a display panel provided by the present application.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, features defined as “first”, “second” may expressly or implicitly include one or more of said features.
  • pluralit means two or more, unless otherwise expressly and specifically defined. In this application, “/” means “or”.
  • the array substrate of the present application includes sub-pixels distributed in an array. It should be noted that, for the convenience of description, only one sub-pixel is illustrated in FIG. 2 for description.
  • Each of the sub-pixels includes a main area thin film transistor T1, a sub area thin film transistor T2 and a shared thin film transistor T3.
  • Each of the sub-pixels includes a main area 10 and a sub-area 20, a non-display area is included between the main area 10 and the sub-area 20 of the same sub-pixel, the main area thin film transistor T1, the sub-area 20
  • the area thin film transistor T2 and the shared thin film transistor T3 are correspondingly located in the non-display area.
  • a gate line 30 is arranged corresponding to each row of the sub-pixels, the gate line 30 is located between the main region 10 and the sub-region 20, and a data line 40 is arranged corresponding to each column of the sub-pixels, adjacent to each other.
  • the two data lines 40 define pixel boundaries.
  • the sub-pixel is provided with a main pixel electrode 601 corresponding to the main area 10 and a sub-pixel electrode 602 corresponding to the sub-area 20.
  • the sub-pixel further includes the main pixel electrode 601 and the sub-pixel electrode 602. Common electrodes 50 arranged in different layers.
  • the array substrate includes: a base 101; a gate 102, disposed on the base 101; a gate insulating layer 103, disposed on the gate 102; an active layer 104, Corresponding to the gate 102 is disposed on the gate insulating layer 103; the source/drain 105 is disposed on both ends of the active layer 104, and is in contact with the ion-doped region of the active layer 104;
  • the organic protective layer 106 is disposed on the source/drain electrodes 105 ; the pixel electrode layers ( 601 , 602 ) are disposed on the organic protective layer 106 and include the main pixel electrode and the sub-pixel electrode.
  • the structure disposed on the same layer as the gate 102 further includes the gate line 30 , the common electrode 50 and other conventional structures.
  • the gate 102 , the gate line 30 and the common electrode 50 may be formed simultaneously from the same material and through the same mask process.
  • the structure disposed on the same layer as the source/drain 105 also includes the data line 40 and other conventional structures, etc.
  • the source/drain 105 and the data line 40 can be formed of the same material at the same time through the same mask process of.
  • an array substrate with a bottom gate structure is used as an example, but in other embodiments, the array substrate may also be a top gate structure, which is not limited here.
  • the thin film transistor T1 in the main area is electrically connected to the main pixel electrode 601 through the first via hole 100
  • the thin film transistor T2 in the sub area is connected to the sub pixel through the second via hole 200
  • the electrode 602 is electrically connected
  • the shared thin film transistor T3 is electrically connected to the common electrode 50 through the third via hole 300 .
  • the first via hole 100 and the second via hole 200 penetrate through the organic protective layer 101
  • the third via hole 300 penetrates through the gate insulating layer 102
  • the diameter of the third via hole 300 is smaller than that of the third via hole 300 .
  • a via hole 100 and the diameter of the second via hole 200 are examples of the second via hole 200 .
  • the first via hole 100 and the second via hole 200 penetrate through the organic protective layer 106 , and the third via hole 300 penetrates through the gate insulating layer 103 .
  • the defects such as uneven display brightness caused by the poor uniformity of the cell thickness of the liquid crystal cell will become more obvious. Therefore, it is usually necessary to cover the array (thin film transistor) substrate with a transparent organic protective layer (ie, the organic film on the array substrate side (Polymer Film on Array, PFA)) to change the flatness of the surface of the underlying film and prevent the electric field from interfering with each other. Therefore, the display unevenness of the liquid crystal display device caused by the terrain factor can be effectively improved, the parasitic capacitance can be reduced, the display abnormality such as flicker caused by excessive electrical load can be reduced, and the quality of the display device can be improved.
  • a transparent organic protective layer ie, the organic film on the array substrate side (Polymer Film on Array, PFA)
  • the common electrode 50 ′ and the pixel electrodes are in the same layer and are arranged around the pixel electrodes, so the main area thin film transistor T1 is connected to the main pixel electrode 601 ′
  • the first via hole 100', the second via hole 200' connecting the sub-region thin film transistor T2 and the sub-pixel electrode 602', and the third via hole 300' connecting the shared thin film transistor T3 and the common electrode are all through the organic protective layer.
  • the via holes formed through the organic protective layer are usually relatively large, so they will occupy more space in the non-display area, making the display area (ie the main area and the secondary area) The space is compressed, resulting in a reduction in the aperture ratio of the pixel.
  • the third via hole 300 originally passing through the organic protective layer 106 is changed to pass through the gate insulating layer 103.
  • the size of the via hole in the gate insulating layer 103 can be made much smaller than the size of the via hole penetrating the organic protective layer 106.
  • the size ratio of the via hole penetrating the organic protective layer 106 to the via hole penetrating the gate insulating layer 103 can be 1.5:1 to 4:1.
  • the diameter of the via hole passing through the organic protective layer 106 is 9 mm, and the diameter of the via hole passing through the gate insulating layer 103 is 4 mm. Therefore, the present application can reduce the aperture of the third via hole 300 , thereby reducing the space ratio of the non-display area between the main area 10 and the sub area 20 , thereby improving the aperture ratio and transmittance of the pixel, thus reducing the Reduce the brightness of the backlight and reduce the power, so as to effectively solve the technical problem of large backlight heat.
  • the sub-region thin film transistor T2 and the shared thin film transistor T3 are combined and designed, that is, one of the sub-pixels is correspondingly provided with a first source electrode 1051, a second source electrode 1052, a first drain electrode 1053 and a second drain electrode 1054, wherein the main area thin film transistor T1 and the sub area thin film transistor T2 share the first source electrode 1051, and the sub area thin film transistor T2 shares the first source electrode 1051.
  • the thin film transistor T2 and the shared thin film transistor T3 share the second drain electrode 1054 .
  • the sub-pixel electrode 602' leads out two lines through the second via hole 200' to form the drain D1 of the sub-region thin film transistor T2 and the drain D2 of the shared thin film transistor T3, respectively.
  • a line is drawn from the sub-pixel electrode 602 through the second via hole 200 to form the second drain electrode 1054 , and the second drain electrode 1054 is used as the drain of the sub-region thin film transistor T2
  • the pole is also used as the drain of the shared thin film transistor T3.
  • the present application can reduce the wiring in the non-display area between the main area 10 and the sub area 20, because the sub area thin film transistor T2 and the shared thin film transistor T3 are combined and designed, so that The space ratio of the non-display area is reduced, thereby further increasing the aperture ratio and transmittance of the pixels, and further reducing the brightness and power of the backlight.
  • the common electrode line 50 is made of a transparent material, and the projection range of the main pixel electrode 601 and the sub-pixel electrode 602 on the array substrate at least partially covers the common electrode 50 on the Projection range on the array substrate. Understandably, this projection is an orthographic projection.
  • the projection range of the pixel electrode layers ( 601 , 602 ) on the array substrate at least covers the projection range of the portion of the common electrode 50 corresponding to the data line 40 on the array substrate. Since the common electrode line 50 is made of transparent material, the pixel electrode layers ( 601 , 602 ) can cover the top of the common electrode 50 .
  • the pixel electrode layer ( 601 , 602 ) covers the part of the common electrode 50 corresponding to the direction of the data line 40 , since the pixel electrode layer ( 601 , 602 ) increases in width in the direction along the gate line 30 , Therefore, the aperture ratio of the pixel is increased, thereby improving the transmittance of the pixel, so that the brightness of the backlight matched with the array substrate is appropriately reduced, thereby reducing the heat generation of the backlight.
  • the projection range of the pixel electrode layers (601, 602) on the array substrate completely covers the projection range of the common electrode 50 on the array substrate. Since the pixel electrode layer (601, 602) increases the length in the direction of the data line 40, that is, the pixel electrode layer (601, 602) also covers the part of the common electrode 50 corresponding to the direction of the gate line 30, Therefore, the aperture ratio and transmittance of the pixel can be further improved.
  • FIG. 5 it is a schematic structural diagram of a sub-pixel on the array substrate provided in the second embodiment of the present application.
  • the structure of the array substrate of this embodiment is the same/similar to the array substrate of the above-mentioned first embodiment, the difference is that in this embodiment, the first via hole 100 and the second via hole 200 are close to the side of the pixel opening area, That is, at least a part of the first via hole 100 is located in the main area 10 , and at least a part of the second via hole 200 is located in the sub area 20 , thereby reducing the size of the main area 10 and the sub area 20 The area of the non-display area in between, thereby increasing the aperture ratio of the pixel.
  • the projection range of the main pixel electrode 601 on the array substrate at least partially covers the projection range of the first via hole 100 on the array substrate, and the sub-pixel electrode 602 is on the array substrate The projection range of at least partially covers the projection range of the second via hole 200 on the array substrate.
  • half of the first via hole 100 is located in the main area 10
  • half of the second via hole 200 is located in the secondary area 20 , which may be determined according to actual conditions.
  • the first via hole 100 is completely disposed in the main area 10
  • the second via hole 200 is completely disposed in the sub area 20 , so that all the The space ratio of the non-display area between the main area 10 and the secondary area 20 is reduced.
  • the main pixel electrode 601 and the sub-pixel electrode 602 both include a main electrode 60a and a branch electrode 60b, and the main electrode 60a can be in the shape of a "cross", or a shape of a "field", or other The shape is not limited here.
  • the first via hole 100 and the second via hole 200 are located at the main electrode 60a correspondingly, therefore, the arrangement of the first via hole 100 and the second via hole 200 will not affect the deflection of the liquid crystal, It will not affect the display effect.
  • first via hole 100 and the second via hole 200 are located within the coverage area of the trunk electrode 60a, so the aperture ratio of the pixel and the display effect can be improved.
  • first via hole 100 and the second via hole 200 may be symmetrically arranged along the center line of the non-display area.
  • the first via hole 100 and the second via hole 200 are respectively disposed in the main area 10 and the sub area 20 , so it is possible to The space of the non-display area is further saved, thereby further improving the aperture ratio and transmittance of the pixel, and can effectively solve the technical problem of large backlight heat.
  • FIG. 6 it is a schematic structural diagram of a sub-pixel on the array substrate provided in the third embodiment of the present application.
  • the structure of the array substrate of this embodiment is the same/similar to the array substrate of the above-mentioned second embodiment, the difference is that at least a part of the third via hole 300 of this embodiment is located in the sub-region 20, thereby further increasing the pixel density opening rate.
  • the projection range of the sub-pixel electrode 602 on the array substrate at least partially covers the projection range of the third via hole 300 on the array substrate.
  • the third via hole 300 is completely disposed in the sub-region 20, and the third via hole 300 is correspondingly located at the main electrode 60a. Therefore, the The setting of the third via hole 300 will not affect the deflection of the liquid crystal, and thus will not affect the display effect.
  • the third via hole 300 is located within the coverage area of the trunk electrode 60a, so the aperture ratio of the pixel and the display effect can be improved.
  • this embodiment can further save the space of the non-display area because the third via hole 300 is disposed in the sub-region 20, thereby further increasing the opening of the pixel. It can effectively solve the technical problem of large backlight heat.
  • the main area 10 further includes a main storage electrode (not shown), the main storage electrode and the common electrode corresponding to the main area 10 50 is insulated by a dielectric layer and forms a main storage capacitor;
  • the sub-region 20 further includes a sub-storage electrode (not shown), and the sub-storage electrode and the common electrode 50 corresponding to the sub-region 20 pass through the dielectric layer.
  • the electrical layer insulates and forms a secondary storage capacitor.
  • the projections of the main storage electrodes and the secondary storage electrodes on the array substrate are both located within the projection range of the pixel electrode layers (601, 602) on the array substrate.
  • the main storage electrode and the secondary storage electrode are both transparent electrodes, so the light transmittance and display effect of the sub-pixels will not be affected. Therefore, the area of the non-display area is further reduced, the aperture ratio of the pixel is increased, and the transmittance of the sub-pixel is further improved.
  • the present application also provides a display panel including the above-mentioned array substrate.
  • the display panel is a liquid crystal display panel.
  • the display panel includes an array substrate 1 , a color filter substrate 2 and a liquid crystal layer between the array substrate 1 and the color filter substrate 2 . 3.
  • the display panel of the present application has high pixel aperture ratio and transmittance, so the technical problem of large backlight heat can be solved.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Liquid Crystal (AREA)
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  • Electroluminescent Light Sources (AREA)

Abstract

La présente invention concerne un substrat de réseau et un écran d'affichage. Un sous-pixel du substrat de réseau comprend un transistor en couches minces de région principale, un transistor en couches minces de sous-région, et un transistor en couches minces partagé. Le sous-pixel comprend en outre une électrode de pixel principal et une électrode de sous-pixel, ainsi qu'une électrode commune. Le transistor en couches minces de région principale est électriquement connecté à l'électrode de pixel principale au moyen d'un premier trou d'interconnexion, le transistor en couches minces de sous-région est électriquement connecté à l'électrode de sous-pixel au moyen d'un deuxième trou d'interconnexion, et le transistor en couches minces partagé est électriquement connecté à l'électrode commune au moyen d'un troisième trou d'interconnexion, l'ouverture du troisième trou d'interconnexion étant plus petite que l'ouverture du premier trou d'interconnexion et l'ouverture du deuxième trou d'interconnexion.
PCT/CN2020/124691 2020-09-10 2020-10-29 Substrat de réseau et écran d'affichage WO2022052242A1 (fr)

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CN113314546B (zh) * 2021-05-21 2023-06-02 深圳市华星光电半导体显示技术有限公司 阵列基板及阵列基板测试方法、显示面板
CN113325635B (zh) * 2021-05-31 2022-07-12 Tcl华星光电技术有限公司 显示面板及其制作方法
CN113391491B (zh) * 2021-06-16 2023-11-28 惠州华星光电显示有限公司 液晶显示面板及显示装置
CN113534546B (zh) * 2021-07-23 2023-10-03 深圳市华星光电半导体显示技术有限公司 阵列基板以及显示面板
CN113741108B (zh) * 2021-08-31 2022-07-22 惠科股份有限公司 阵列基板、显示面板及显示装置
CN114153098A (zh) * 2021-11-30 2022-03-08 惠科股份有限公司 第一基板、显示面板、液晶显示器及显示设备
CN114236925B (zh) * 2021-12-14 2023-02-28 苏州华星光电技术有限公司 阵列基板及液晶显示面板
CN114280864A (zh) * 2021-12-17 2022-04-05 Tcl华星光电技术有限公司 阵列基板及液晶显示面板
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