WO2022052242A1 - Array substrate and display panel - Google Patents

Array substrate and display panel Download PDF

Info

Publication number
WO2022052242A1
WO2022052242A1 PCT/CN2020/124691 CN2020124691W WO2022052242A1 WO 2022052242 A1 WO2022052242 A1 WO 2022052242A1 CN 2020124691 W CN2020124691 W CN 2020124691W WO 2022052242 A1 WO2022052242 A1 WO 2022052242A1
Authority
WO
WIPO (PCT)
Prior art keywords
sub
via hole
electrode
thin film
array substrate
Prior art date
Application number
PCT/CN2020/124691
Other languages
French (fr)
Chinese (zh)
Inventor
奚苏萍
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Publication of WO2022052242A1 publication Critical patent/WO2022052242A1/en

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate and a display panel.
  • the backlight As the size of the panel becomes larger and larger, the backlight also becomes larger, which means that the heating of the backlight will increase.
  • the brightness of the backlight can be reduced by increasing the penetration rate of the panel, thereby effectively avoiding the heating phenomenon, that is, increasing the pixel (pixel) ), it is particularly necessary to increase the penetration rate of the panel accordingly.
  • Large size and high resolution means that the size of the pixel is getting smaller and smaller, and the opening area is also getting smaller. And people's requirements for color shift are getting higher and higher.
  • 8-domain display is usually used, that is, the so-called 3T or 3T plus structure is usually used, which means that it will take up more space and sacrifice accordingly. Partially open area.
  • Large-size backlights generate serious heat, and it is necessary to effectively avoid this phenomenon by increasing the transmittance. However, for high-resolution, large-size, and high-specification products, it becomes difficult to increase the transmittance.
  • the present application provides an array substrate and a display panel, which can improve the pixel aperture ratio of high-resolution large-size products, thereby improving the transmittance to solve the problem of serious heat generation of large-size backlights.
  • the present application provides an array substrate, including sub-pixels distributed in an array, each of the sub-pixels includes a main area thin film transistor, a sub area thin film transistor and a shared thin film transistor;
  • the sub-pixel includes a main area and a sub-area, a main pixel electrode is disposed corresponding to the main area, and a sub-pixel electrode is disposed corresponding to the sub-area, and the sub-pixel further includes the main pixel electrode and the sub-pixel.
  • the main area thin film transistor is electrically connected to the main pixel electrode through a first via hole
  • the sub area thin film transistor is electrically connected to the sub pixel electrode through a second via hole
  • the shared thin film transistor is electrically connected through a third via hole electrically connected to the common electrode
  • the diameter of the third via hole is smaller than the diameter of the first via hole and the diameter of the second via hole.
  • the array substrate includes:
  • a gate disposed on the substrate
  • a gate insulating layer disposed on the gate
  • an active layer disposed on the gate insulating layer corresponding to the gate
  • source/drain disposed at both ends of the active layer and in contact with the ion-doped regions of the active layer;
  • a pixel electrode layer disposed on the organic protective layer, including the main pixel electrode and the sub-pixel electrode;
  • the common electrode and the gate electrode are disposed in the same layer, the first via hole and the second via hole penetrate through the organic protective layer, and the third via hole penetrates through the gate insulating layer.
  • one of the sub-pixels is provided with a first source electrode, a second source electrode, a first drain electrode and a second drain electrode, wherein the main area thin film transistor and the sub area thin film The transistors share the first source electrode, and the sub-region thin film transistor and the shared thin film transistor share the second drain electrode.
  • a non-display area is included between the main area and the sub area of the same sub-pixel, and the main area thin film transistor, the sub area thin film transistor and the shared thin film transistor correspond to In the non-display area, at least a part of the first via hole is located in the main area, and at least a part of the second via hole is located in the sub area.
  • the projection range of the main pixel electrode on the array substrate at least partially covers the projection range of the first via hole on the array substrate, and the sub-pixel electrode is on the array substrate.
  • the projection range on the substrate at least partially covers the projection range of the second via hole on the array substrate.
  • both the main pixel electrode and the sub-pixel electrode include a trunk electrode and a branch electrode, and the first via hole and the second via hole are located at the trunk electrode correspondingly.
  • the first via hole and the second via hole are symmetrically arranged along the center line of the non-display area.
  • At least a part of the third via hole is located in the sub-region.
  • the projection range of the main pixel electrode and the sub-pixel electrode on the array substrate at least partially covers the projection range of the common electrode on the array substrate.
  • the common electrode is a transparent material.
  • the present application further provides a display panel including an array substrate, the array substrate includes sub-pixels distributed in an array, and each of the sub-pixels includes a main area thin film transistor, a sub area thin film transistor and a shared thin film transistor;
  • the sub-pixel includes a main area and a sub-area, a main pixel electrode is disposed corresponding to the main area, and a sub-pixel electrode is disposed corresponding to the sub-area, and the sub-pixel further includes the main pixel electrode and the sub-pixel.
  • the main area thin film transistor is electrically connected to the main pixel electrode through a first via hole
  • the sub area thin film transistor is electrically connected to the sub pixel electrode through a second via hole
  • the shared thin film transistor is electrically connected through a third via hole electrically connected to the common electrode
  • the diameter of the third via hole is smaller than the diameter of the first via hole and the diameter of the second via hole.
  • the array substrate includes:
  • a gate disposed on the substrate
  • a gate insulating layer disposed on the gate
  • an active layer disposed on the gate insulating layer corresponding to the gate
  • source/drain disposed at both ends of the active layer and in contact with the ion-doped regions of the active layer;
  • a pixel electrode layer disposed on the organic protective layer, including the main pixel electrode and the sub-pixel electrode;
  • the common electrode and the gate electrode are disposed in the same layer, the first via hole and the second via hole penetrate through the organic protective layer, and the third via hole penetrates through the gate insulating layer.
  • one of the sub-pixels is provided with a first source electrode, a second source electrode, a first drain electrode and a second drain electrode, wherein the main area thin film transistor and the sub area thin film The transistors share the first source electrode, and the sub-region thin film transistor and the shared thin film transistor share the second drain electrode.
  • a non-display area is included between the main area and the sub area of the same sub-pixel, and the main area thin film transistor, the sub area thin film transistor and the shared thin film transistor correspond to In the non-display area, at least a part of the first via hole is located in the main area, and at least a part of the second via hole is located in the sub area.
  • the projection range of the main pixel electrode on the array substrate at least partially covers the projection range of the first via hole on the array substrate, and the sub pixel electrode is on the array substrate.
  • the projection range on the substrate at least partially covers the projection range of the second via hole on the array substrate.
  • both the main pixel electrode and the sub-pixel electrode include a main electrode and a branch electrode, and the first via hole and the second via hole are located at the main electrode correspondingly.
  • the first via hole and the second via hole are symmetrically arranged along the center line of the non-display area.
  • At least a part of the third via hole is located in the sub-region.
  • the projection range of the main pixel electrode and the sub-pixel electrode on the array substrate at least partially covers the projection range of the common electrode on the array substrate.
  • the common electrode is a transparent material.
  • each sub-pixel includes a main area thin film transistor, a sub area thin film transistor and a shared thin film transistor, and the main area thin film transistor is electrically connected to the main pixel electrode through the first via hole.
  • the sub-region thin film transistor is electrically connected to the sub-pixel electrode through the second via hole
  • the shared thin film transistor is electrically connected to the common electrode through the third via hole.
  • the aperture of the third via hole is reduced by changing the third via hole that originally penetrated through the organic protective layer to the gate insulating layer, thereby increasing the aperture ratio and transmittance of the pixel, thus solving the problem of backlight heat generation. big technical problem.
  • FIG. 1 is a schematic structural diagram of a sub-pixel on a conventional array substrate
  • FIG. 2 is a schematic structural diagram of a sub-pixel on an array substrate provided in Embodiment 1 of the present application;
  • FIG. 3 is a schematic cross-sectional view of the array substrate provided in Embodiment 1 of the present application along the first/second via hole;
  • FIG. 4 is a schematic cross-sectional view of the array substrate according to Embodiment 1 of the present application along a third via hole;
  • FIG. 5 is a schematic structural diagram of a sub-pixel on an array substrate according to Embodiment 2 of the present application.
  • FIG. 6 is a schematic structural diagram of a sub-pixel on an array substrate provided in Embodiment 3 of the present application.
  • FIG. 7 is a schematic structural diagram of a display panel provided by the present application.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, features defined as “first”, “second” may expressly or implicitly include one or more of said features.
  • pluralit means two or more, unless otherwise expressly and specifically defined. In this application, “/” means “or”.
  • the array substrate of the present application includes sub-pixels distributed in an array. It should be noted that, for the convenience of description, only one sub-pixel is illustrated in FIG. 2 for description.
  • Each of the sub-pixels includes a main area thin film transistor T1, a sub area thin film transistor T2 and a shared thin film transistor T3.
  • Each of the sub-pixels includes a main area 10 and a sub-area 20, a non-display area is included between the main area 10 and the sub-area 20 of the same sub-pixel, the main area thin film transistor T1, the sub-area 20
  • the area thin film transistor T2 and the shared thin film transistor T3 are correspondingly located in the non-display area.
  • a gate line 30 is arranged corresponding to each row of the sub-pixels, the gate line 30 is located between the main region 10 and the sub-region 20, and a data line 40 is arranged corresponding to each column of the sub-pixels, adjacent to each other.
  • the two data lines 40 define pixel boundaries.
  • the sub-pixel is provided with a main pixel electrode 601 corresponding to the main area 10 and a sub-pixel electrode 602 corresponding to the sub-area 20.
  • the sub-pixel further includes the main pixel electrode 601 and the sub-pixel electrode 602. Common electrodes 50 arranged in different layers.
  • the array substrate includes: a base 101; a gate 102, disposed on the base 101; a gate insulating layer 103, disposed on the gate 102; an active layer 104, Corresponding to the gate 102 is disposed on the gate insulating layer 103; the source/drain 105 is disposed on both ends of the active layer 104, and is in contact with the ion-doped region of the active layer 104;
  • the organic protective layer 106 is disposed on the source/drain electrodes 105 ; the pixel electrode layers ( 601 , 602 ) are disposed on the organic protective layer 106 and include the main pixel electrode and the sub-pixel electrode.
  • the structure disposed on the same layer as the gate 102 further includes the gate line 30 , the common electrode 50 and other conventional structures.
  • the gate 102 , the gate line 30 and the common electrode 50 may be formed simultaneously from the same material and through the same mask process.
  • the structure disposed on the same layer as the source/drain 105 also includes the data line 40 and other conventional structures, etc.
  • the source/drain 105 and the data line 40 can be formed of the same material at the same time through the same mask process of.
  • an array substrate with a bottom gate structure is used as an example, but in other embodiments, the array substrate may also be a top gate structure, which is not limited here.
  • the thin film transistor T1 in the main area is electrically connected to the main pixel electrode 601 through the first via hole 100
  • the thin film transistor T2 in the sub area is connected to the sub pixel through the second via hole 200
  • the electrode 602 is electrically connected
  • the shared thin film transistor T3 is electrically connected to the common electrode 50 through the third via hole 300 .
  • the first via hole 100 and the second via hole 200 penetrate through the organic protective layer 101
  • the third via hole 300 penetrates through the gate insulating layer 102
  • the diameter of the third via hole 300 is smaller than that of the third via hole 300 .
  • a via hole 100 and the diameter of the second via hole 200 are examples of the second via hole 200 .
  • the first via hole 100 and the second via hole 200 penetrate through the organic protective layer 106 , and the third via hole 300 penetrates through the gate insulating layer 103 .
  • the defects such as uneven display brightness caused by the poor uniformity of the cell thickness of the liquid crystal cell will become more obvious. Therefore, it is usually necessary to cover the array (thin film transistor) substrate with a transparent organic protective layer (ie, the organic film on the array substrate side (Polymer Film on Array, PFA)) to change the flatness of the surface of the underlying film and prevent the electric field from interfering with each other. Therefore, the display unevenness of the liquid crystal display device caused by the terrain factor can be effectively improved, the parasitic capacitance can be reduced, the display abnormality such as flicker caused by excessive electrical load can be reduced, and the quality of the display device can be improved.
  • a transparent organic protective layer ie, the organic film on the array substrate side (Polymer Film on Array, PFA)
  • the common electrode 50 ′ and the pixel electrodes are in the same layer and are arranged around the pixel electrodes, so the main area thin film transistor T1 is connected to the main pixel electrode 601 ′
  • the first via hole 100', the second via hole 200' connecting the sub-region thin film transistor T2 and the sub-pixel electrode 602', and the third via hole 300' connecting the shared thin film transistor T3 and the common electrode are all through the organic protective layer.
  • the via holes formed through the organic protective layer are usually relatively large, so they will occupy more space in the non-display area, making the display area (ie the main area and the secondary area) The space is compressed, resulting in a reduction in the aperture ratio of the pixel.
  • the third via hole 300 originally passing through the organic protective layer 106 is changed to pass through the gate insulating layer 103.
  • the size of the via hole in the gate insulating layer 103 can be made much smaller than the size of the via hole penetrating the organic protective layer 106.
  • the size ratio of the via hole penetrating the organic protective layer 106 to the via hole penetrating the gate insulating layer 103 can be 1.5:1 to 4:1.
  • the diameter of the via hole passing through the organic protective layer 106 is 9 mm, and the diameter of the via hole passing through the gate insulating layer 103 is 4 mm. Therefore, the present application can reduce the aperture of the third via hole 300 , thereby reducing the space ratio of the non-display area between the main area 10 and the sub area 20 , thereby improving the aperture ratio and transmittance of the pixel, thus reducing the Reduce the brightness of the backlight and reduce the power, so as to effectively solve the technical problem of large backlight heat.
  • the sub-region thin film transistor T2 and the shared thin film transistor T3 are combined and designed, that is, one of the sub-pixels is correspondingly provided with a first source electrode 1051, a second source electrode 1052, a first drain electrode 1053 and a second drain electrode 1054, wherein the main area thin film transistor T1 and the sub area thin film transistor T2 share the first source electrode 1051, and the sub area thin film transistor T2 shares the first source electrode 1051.
  • the thin film transistor T2 and the shared thin film transistor T3 share the second drain electrode 1054 .
  • the sub-pixel electrode 602' leads out two lines through the second via hole 200' to form the drain D1 of the sub-region thin film transistor T2 and the drain D2 of the shared thin film transistor T3, respectively.
  • a line is drawn from the sub-pixel electrode 602 through the second via hole 200 to form the second drain electrode 1054 , and the second drain electrode 1054 is used as the drain of the sub-region thin film transistor T2
  • the pole is also used as the drain of the shared thin film transistor T3.
  • the present application can reduce the wiring in the non-display area between the main area 10 and the sub area 20, because the sub area thin film transistor T2 and the shared thin film transistor T3 are combined and designed, so that The space ratio of the non-display area is reduced, thereby further increasing the aperture ratio and transmittance of the pixels, and further reducing the brightness and power of the backlight.
  • the common electrode line 50 is made of a transparent material, and the projection range of the main pixel electrode 601 and the sub-pixel electrode 602 on the array substrate at least partially covers the common electrode 50 on the Projection range on the array substrate. Understandably, this projection is an orthographic projection.
  • the projection range of the pixel electrode layers ( 601 , 602 ) on the array substrate at least covers the projection range of the portion of the common electrode 50 corresponding to the data line 40 on the array substrate. Since the common electrode line 50 is made of transparent material, the pixel electrode layers ( 601 , 602 ) can cover the top of the common electrode 50 .
  • the pixel electrode layer ( 601 , 602 ) covers the part of the common electrode 50 corresponding to the direction of the data line 40 , since the pixel electrode layer ( 601 , 602 ) increases in width in the direction along the gate line 30 , Therefore, the aperture ratio of the pixel is increased, thereby improving the transmittance of the pixel, so that the brightness of the backlight matched with the array substrate is appropriately reduced, thereby reducing the heat generation of the backlight.
  • the projection range of the pixel electrode layers (601, 602) on the array substrate completely covers the projection range of the common electrode 50 on the array substrate. Since the pixel electrode layer (601, 602) increases the length in the direction of the data line 40, that is, the pixel electrode layer (601, 602) also covers the part of the common electrode 50 corresponding to the direction of the gate line 30, Therefore, the aperture ratio and transmittance of the pixel can be further improved.
  • FIG. 5 it is a schematic structural diagram of a sub-pixel on the array substrate provided in the second embodiment of the present application.
  • the structure of the array substrate of this embodiment is the same/similar to the array substrate of the above-mentioned first embodiment, the difference is that in this embodiment, the first via hole 100 and the second via hole 200 are close to the side of the pixel opening area, That is, at least a part of the first via hole 100 is located in the main area 10 , and at least a part of the second via hole 200 is located in the sub area 20 , thereby reducing the size of the main area 10 and the sub area 20 The area of the non-display area in between, thereby increasing the aperture ratio of the pixel.
  • the projection range of the main pixel electrode 601 on the array substrate at least partially covers the projection range of the first via hole 100 on the array substrate, and the sub-pixel electrode 602 is on the array substrate The projection range of at least partially covers the projection range of the second via hole 200 on the array substrate.
  • half of the first via hole 100 is located in the main area 10
  • half of the second via hole 200 is located in the secondary area 20 , which may be determined according to actual conditions.
  • the first via hole 100 is completely disposed in the main area 10
  • the second via hole 200 is completely disposed in the sub area 20 , so that all the The space ratio of the non-display area between the main area 10 and the secondary area 20 is reduced.
  • the main pixel electrode 601 and the sub-pixel electrode 602 both include a main electrode 60a and a branch electrode 60b, and the main electrode 60a can be in the shape of a "cross", or a shape of a "field", or other The shape is not limited here.
  • the first via hole 100 and the second via hole 200 are located at the main electrode 60a correspondingly, therefore, the arrangement of the first via hole 100 and the second via hole 200 will not affect the deflection of the liquid crystal, It will not affect the display effect.
  • first via hole 100 and the second via hole 200 are located within the coverage area of the trunk electrode 60a, so the aperture ratio of the pixel and the display effect can be improved.
  • first via hole 100 and the second via hole 200 may be symmetrically arranged along the center line of the non-display area.
  • the first via hole 100 and the second via hole 200 are respectively disposed in the main area 10 and the sub area 20 , so it is possible to The space of the non-display area is further saved, thereby further improving the aperture ratio and transmittance of the pixel, and can effectively solve the technical problem of large backlight heat.
  • FIG. 6 it is a schematic structural diagram of a sub-pixel on the array substrate provided in the third embodiment of the present application.
  • the structure of the array substrate of this embodiment is the same/similar to the array substrate of the above-mentioned second embodiment, the difference is that at least a part of the third via hole 300 of this embodiment is located in the sub-region 20, thereby further increasing the pixel density opening rate.
  • the projection range of the sub-pixel electrode 602 on the array substrate at least partially covers the projection range of the third via hole 300 on the array substrate.
  • the third via hole 300 is completely disposed in the sub-region 20, and the third via hole 300 is correspondingly located at the main electrode 60a. Therefore, the The setting of the third via hole 300 will not affect the deflection of the liquid crystal, and thus will not affect the display effect.
  • the third via hole 300 is located within the coverage area of the trunk electrode 60a, so the aperture ratio of the pixel and the display effect can be improved.
  • this embodiment can further save the space of the non-display area because the third via hole 300 is disposed in the sub-region 20, thereby further increasing the opening of the pixel. It can effectively solve the technical problem of large backlight heat.
  • the main area 10 further includes a main storage electrode (not shown), the main storage electrode and the common electrode corresponding to the main area 10 50 is insulated by a dielectric layer and forms a main storage capacitor;
  • the sub-region 20 further includes a sub-storage electrode (not shown), and the sub-storage electrode and the common electrode 50 corresponding to the sub-region 20 pass through the dielectric layer.
  • the electrical layer insulates and forms a secondary storage capacitor.
  • the projections of the main storage electrodes and the secondary storage electrodes on the array substrate are both located within the projection range of the pixel electrode layers (601, 602) on the array substrate.
  • the main storage electrode and the secondary storage electrode are both transparent electrodes, so the light transmittance and display effect of the sub-pixels will not be affected. Therefore, the area of the non-display area is further reduced, the aperture ratio of the pixel is increased, and the transmittance of the sub-pixel is further improved.
  • the present application also provides a display panel including the above-mentioned array substrate.
  • the display panel is a liquid crystal display panel.
  • the display panel includes an array substrate 1 , a color filter substrate 2 and a liquid crystal layer between the array substrate 1 and the color filter substrate 2 . 3.
  • the display panel of the present application has high pixel aperture ratio and transmittance, so the technical problem of large backlight heat can be solved.

Abstract

Provided by the present application are an array substrate and a display panel. A sub-pixel of the array substrate comprises a main region thin-film transistor, a sub-region thin-film transistor, and a shared thin-film transistor. The sub-pixel further comprises a main pixel electrode and a sub-pixel electrode, as well as a common electrode. The main region thin-film transistor is electrically connected to the main pixel electrode by means of a first via hole, the sub-region thin-film transistor is electrically connected to the sub-pixel electrode by means of a second via hole, and the shared thin-film transistor is electrically connected to the common electrode by means of a third via hole, wherein the aperture of the third via hole is smaller than the aperture of the first via hole and the aperture of the second via hole.

Description

一种阵列基板、显示面板An array substrate and a display panel 技术领域technical field
本申请涉及显示技术领域，尤其涉及一种阵列基板、显示面板。The present application relates to the field of display technology, and in particular, to an array substrate and a display panel.
背景技术Background technique
随着面板尺寸越来越大，背光也越来越大，这意味着背光发热会增加，可以通过提高面板的穿透率来减小背光的亮度，从而有效避免发热现象，即提升像素（pixel）的开口率，相应提高面板穿透率显得尤为必要。大尺寸高解析度意味着pixel的尺寸越来越小，开口区也随之变小。且人们对色偏的规格要求越来越高，对于VA产品，通常采用8畴显示，即通常要采用所谓的3T or 3T plus结构, 这意味着会占用更多的空间的同时会相应地牺牲部分开口区。而大尺寸背光产热严重，需要通过提高穿透率来有效避免这一现象的产生，但是，对于高解析度大尺寸高规格产品，提高穿透率变得很难。As the size of the panel becomes larger and larger, the backlight also becomes larger, which means that the heating of the backlight will increase. The brightness of the backlight can be reduced by increasing the penetration rate of the panel, thereby effectively avoiding the heating phenomenon, that is, increasing the pixel (pixel) ), it is particularly necessary to increase the penetration rate of the panel accordingly. Large size and high resolution means that the size of the pixel is getting smaller and smaller, and the opening area is also getting smaller. And people's requirements for color shift are getting higher and higher. For VA products, 8-domain display is usually used, that is, the so-called 3T or 3T plus structure is usually used, which means that it will take up more space and sacrifice accordingly. Partially open area. Large-size backlights generate serious heat, and it is necessary to effectively avoid this phenomenon by increasing the transmittance. However, for high-resolution, large-size, and high-specification products, it becomes difficult to increase the transmittance.
因此，现有技术存在缺陷，急需解决。Therefore, there are defects in the prior art, which need to be solved urgently.
技术问题technical problem
本申请提供一种阵列基板、显示面板，能够提高高解析度大尺寸产品的像素开口率，从而提升穿透率以解决大尺寸背光产热严重的问题。The present application provides an array substrate and a display panel, which can improve the pixel aperture ratio of high-resolution large-size products, thereby improving the transmittance to solve the problem of serious heat generation of large-size backlights.
技术解决方案technical solutions
为解决上述问题，本申请提供的技术方案如下：In order to solve the above-mentioned problems, the technical solutions provided by this application are as follows:
本申请提供一种阵列基板，包括阵列分布的子像素，每一所述子像素包括主区薄膜晶体管、次区薄膜晶体管以及共享薄膜晶体管；The present application provides an array substrate, including sub-pixels distributed in an array, each of the sub-pixels includes a main area thin film transistor, a sub area thin film transistor and a shared thin film transistor;
所述子像素包括主区和次区，对应所述主区设置有主像素电极，对应所述次区设置有次像素电极，所述子像素还包括与所述主像素电极以及所述次像素电极异层设置的公共电极；The sub-pixel includes a main area and a sub-area, a main pixel electrode is disposed corresponding to the main area, and a sub-pixel electrode is disposed corresponding to the sub-area, and the sub-pixel further includes the main pixel electrode and the sub-pixel. Common electrodes arranged in different layers of electrodes;
所述主区薄膜晶体管通过第一过孔与所述主像素电极电连接，所述次区薄膜晶体管通过第二过孔与所述次像素电极电连接，所述共享薄膜晶体管通过第三过孔与所述公共电极电连接；The main area thin film transistor is electrically connected to the main pixel electrode through a first via hole, the sub area thin film transistor is electrically connected to the sub pixel electrode through a second via hole, and the shared thin film transistor is electrically connected through a third via hole electrically connected to the common electrode;
其中，所述第三过孔的孔径小于所述第一过孔以及所述第二过孔的孔径。Wherein, the diameter of the third via hole is smaller than the diameter of the first via hole and the diameter of the second via hole.
在本申请的阵列基板中，所述阵列基板包括：In the array substrate of the present application, the array substrate includes:
基底；base;
栅极，设置于所述基底上；a gate, disposed on the substrate;
栅极绝缘层，设置于所述栅极上；a gate insulating layer, disposed on the gate;
有源层，对应所述栅极设置于所述栅极绝缘层上；an active layer, disposed on the gate insulating layer corresponding to the gate;
源/漏极，设置于所述有源层的两端，并与所述有源层的离子掺杂区接触；source/drain, disposed at both ends of the active layer and in contact with the ion-doped regions of the active layer;
有机保护层，设置于所述源/漏极上；an organic protective layer, disposed on the source/drain;
像素电极层，设置于所述有机保护层上，包括所述主像素电极和所述次像素电极；a pixel electrode layer, disposed on the organic protective layer, including the main pixel electrode and the sub-pixel electrode;
所述公共电极与所述栅极同层设置，所述第一过孔以及所述第二过孔贯穿所述有机保护层，所述第三过孔贯穿栅极绝缘层。The common electrode and the gate electrode are disposed in the same layer, the first via hole and the second via hole penetrate through the organic protective layer, and the third via hole penetrates through the gate insulating layer.
在本申请的阵列基板中，一所述子像素对应设置有第一源极、第二源极、第一漏极以及第二漏极，其中，所述主区薄膜晶体管和所述次区薄膜晶体管共用所述第一源极，所述次区薄膜晶体管和所述共享薄膜晶体管共用所述第二漏极。In the array substrate of the present application, one of the sub-pixels is provided with a first source electrode, a second source electrode, a first drain electrode and a second drain electrode, wherein the main area thin film transistor and the sub area thin film The transistors share the first source electrode, and the sub-region thin film transistor and the shared thin film transistor share the second drain electrode.
在本申请的阵列基板中，同一所述子像素的所述主区和所述次区之间包括非显示区，所述主区薄膜晶体管、所述次区薄膜晶体管以及所述共享薄膜晶体管对应位于所述非显示区内，其中，所述第一过孔至少一部分位于所述主区内，所述第二过孔至少一部分位于所述次区内。In the array substrate of the present application, a non-display area is included between the main area and the sub area of the same sub-pixel, and the main area thin film transistor, the sub area thin film transistor and the shared thin film transistor correspond to In the non-display area, at least a part of the first via hole is located in the main area, and at least a part of the second via hole is located in the sub area.
在本申请的阵列基板中，所述主像素电极在所述阵列基板上的投影范围至少部分覆盖所述第一过孔在所述阵列基板上的投影范围，所述次像素电极在所述阵列基板上的投影范围至少部分覆盖所述第二过孔在所述阵列基板上的投影范围。In the array substrate of the present application, the projection range of the main pixel electrode on the array substrate at least partially covers the projection range of the first via hole on the array substrate, and the sub-pixel electrode is on the array substrate. The projection range on the substrate at least partially covers the projection range of the second via hole on the array substrate.
在本申请的阵列基板中，所述主像素电极与所述次像素电极均包括主干电极和支干电极，所述第一过孔与所述第二过孔对应位于所述主干电极处。In the array substrate of the present application, both the main pixel electrode and the sub-pixel electrode include a trunk electrode and a branch electrode, and the first via hole and the second via hole are located at the trunk electrode correspondingly.
在本申请的阵列基板中，所述第一过孔与所述第二过孔沿所述非显示区的中心线对称设置。In the array substrate of the present application, the first via hole and the second via hole are symmetrically arranged along the center line of the non-display area.
在本申请的阵列基板中，所述第三过孔至少一部分位于所述次区内。In the array substrate of the present application, at least a part of the third via hole is located in the sub-region.
在本申请的阵列基板中，所述主像素电极与所述次像素电极在所述阵列基板上的投影范围至少部分覆盖所述公共电极在所述阵列基板上的投影范围。In the array substrate of the present application, the projection range of the main pixel electrode and the sub-pixel electrode on the array substrate at least partially covers the projection range of the common electrode on the array substrate.
在本申请的阵列基板中，所述公共电极为透明材料。In the array substrate of the present application, the common electrode is a transparent material.
为解决上述问题，本申请还提供一种显示面板，包括阵列基板，所述阵列基板包括阵列分布的子像素，每一所述子像素包括主区薄膜晶体管、次区薄膜晶体管以及共享薄膜晶体管；In order to solve the above problems, the present application further provides a display panel including an array substrate, the array substrate includes sub-pixels distributed in an array, and each of the sub-pixels includes a main area thin film transistor, a sub area thin film transistor and a shared thin film transistor;
所述子像素包括主区和次区，对应所述主区设置有主像素电极，对应所述次区设置有次像素电极，所述子像素还包括与所述主像素电极以及所述次像素电极异层设置的公共电极；The sub-pixel includes a main area and a sub-area, a main pixel electrode is disposed corresponding to the main area, and a sub-pixel electrode is disposed corresponding to the sub-area, and the sub-pixel further includes the main pixel electrode and the sub-pixel. Common electrodes arranged in different layers of electrodes;
所述主区薄膜晶体管通过第一过孔与所述主像素电极电连接，所述次区薄膜晶体管通过第二过孔与所述次像素电极电连接，所述共享薄膜晶体管通过第三过孔与所述公共电极电连接；The main area thin film transistor is electrically connected to the main pixel electrode through a first via hole, the sub area thin film transistor is electrically connected to the sub pixel electrode through a second via hole, and the shared thin film transistor is electrically connected through a third via hole electrically connected to the common electrode;
其中，所述第三过孔的孔径小于所述第一过孔以及所述第二过孔的孔径。Wherein, the diameter of the third via hole is smaller than the diameter of the first via hole and the diameter of the second via hole.
在本申请的显示面板中，所述阵列基板包括：In the display panel of the present application, the array substrate includes:
基底；base;
栅极，设置于所述基底上；a gate, disposed on the substrate;
栅极绝缘层，设置于所述栅极上；a gate insulating layer, disposed on the gate;
有源层，对应所述栅极设置于所述栅极绝缘层上；an active layer, disposed on the gate insulating layer corresponding to the gate;
源/漏极，设置于所述有源层的两端，并与所述有源层的离子掺杂区接触；source/drain, disposed at both ends of the active layer and in contact with the ion-doped regions of the active layer;
有机保护层，设置于所述源/漏极上；an organic protective layer, disposed on the source/drain;
像素电极层，设置于所述有机保护层上，包括所述主像素电极和所述次像素电极；a pixel electrode layer, disposed on the organic protective layer, including the main pixel electrode and the sub-pixel electrode;
所述公共电极与所述栅极同层设置，所述第一过孔以及所述第二过孔贯穿所述有机保护层，所述第三过孔贯穿栅极绝缘层。The common electrode and the gate electrode are disposed in the same layer, the first via hole and the second via hole penetrate through the organic protective layer, and the third via hole penetrates through the gate insulating layer.
在本申请的显示面板中，一所述子像素对应设置有第一源极、第二源极、第一漏极以及第二漏极，其中，所述主区薄膜晶体管和所述次区薄膜晶体管共用所述第一源极，所述次区薄膜晶体管和所述共享薄膜晶体管共用所述第二漏极。In the display panel of the present application, one of the sub-pixels is provided with a first source electrode, a second source electrode, a first drain electrode and a second drain electrode, wherein the main area thin film transistor and the sub area thin film The transistors share the first source electrode, and the sub-region thin film transistor and the shared thin film transistor share the second drain electrode.
在本申请的显示面板中，同一所述子像素的所述主区和所述次区之间包括非显示区，所述主区薄膜晶体管、所述次区薄膜晶体管以及所述共享薄膜晶体管对应位于所述非显示区内，其中，所述第一过孔至少一部分位于所述主区内，所述第二过孔至少一部分位于所述次区内。In the display panel of the present application, a non-display area is included between the main area and the sub area of the same sub-pixel, and the main area thin film transistor, the sub area thin film transistor and the shared thin film transistor correspond to In the non-display area, at least a part of the first via hole is located in the main area, and at least a part of the second via hole is located in the sub area.
在本申请的显示面板中，所述主像素电极在所述阵列基板上的投影范围至少部分覆盖所述第一过孔在所述阵列基板上的投影范围，所述次像素电极在所述阵列基板上的投影范围至少部分覆盖所述第二过孔在所述阵列基板上的投影范围。In the display panel of the present application, the projection range of the main pixel electrode on the array substrate at least partially covers the projection range of the first via hole on the array substrate, and the sub pixel electrode is on the array substrate. The projection range on the substrate at least partially covers the projection range of the second via hole on the array substrate.
在本申请的显示面板中，所述主像素电极与所述次像素电极均包括主干电极和支干电极，所述第一过孔与所述第二过孔对应位于所述主干电极处。In the display panel of the present application, both the main pixel electrode and the sub-pixel electrode include a main electrode and a branch electrode, and the first via hole and the second via hole are located at the main electrode correspondingly.
在本申请的显示面板中，所述第一过孔与所述第二过孔沿所述非显示区的中心线对称设置。In the display panel of the present application, the first via hole and the second via hole are symmetrically arranged along the center line of the non-display area.
在本申请的显示面板中，所述第三过孔至少一部分位于所述次区内。In the display panel of the present application, at least a part of the third via hole is located in the sub-region.
在本申请的显示面板中，所述主像素电极与所述次像素电极在所述阵列基板上的投影范围至少部分覆盖所述公共电极在所述阵列基板上的投影范围。In the display panel of the present application, the projection range of the main pixel electrode and the sub-pixel electrode on the array substrate at least partially covers the projection range of the common electrode on the array substrate.
在本申请的显示面板中，所述公共电极为透明材料。In the display panel of the present application, the common electrode is a transparent material.
有益效果beneficial effect
本申请的有益效果为：本申请提供的阵列基板、显示面板，其每个子像素包括主区薄膜晶体管、次区薄膜晶体管以及共享薄膜晶体管，主区薄膜晶体管通过第一过孔与主像素电极电连接，次区薄膜晶体管通过第二过孔与次像素电极电连接，共享薄膜晶体管通过第三过孔与公共电极电连接。本申请通过将原本贯穿有机保护层的第三过孔改为贯穿栅极绝缘层，从而减小第三过孔的孔径，进而提高像素的开口率和穿透率，因此便可解决背光热量较大的技术问题。The beneficial effects of the present application are as follows: in the array substrate and display panel provided by the present application, each sub-pixel includes a main area thin film transistor, a sub area thin film transistor and a shared thin film transistor, and the main area thin film transistor is electrically connected to the main pixel electrode through the first via hole. connection, the sub-region thin film transistor is electrically connected to the sub-pixel electrode through the second via hole, and the shared thin film transistor is electrically connected to the common electrode through the third via hole. In the present application, the aperture of the third via hole is reduced by changing the third via hole that originally penetrated through the organic protective layer to the gate insulating layer, thereby increasing the aperture ratio and transmittance of the pixel, thus solving the problem of backlight heat generation. big technical problem.
附图说明Description of drawings
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。The technical solutions and other beneficial effects of the present application will be apparent through the detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings.
图1为传统的阵列基板上的子像素的结构示意图；FIG. 1 is a schematic structural diagram of a sub-pixel on a conventional array substrate;
图2为本申请实施例一提供的阵列基板上的子像素的结构示意图；FIG. 2 is a schematic structural diagram of a sub-pixel on an array substrate provided in Embodiment 1 of the present application;
图3为本申请实施例一提供的阵列基板沿第一/二过孔的剖面示意图；3 is a schematic cross-sectional view of the array substrate provided in Embodiment 1 of the present application along the first/second via hole;
图4为本申请实施例一提供的阵列基板沿第三过孔的剖面示意图；4 is a schematic cross-sectional view of the array substrate according to Embodiment 1 of the present application along a third via hole;
图5为本申请实施例二提供的阵列基板上的子像素的结构示意图；FIG. 5 is a schematic structural diagram of a sub-pixel on an array substrate according to Embodiment 2 of the present application;
图6为本申请实施例三提供的阵列基板上的子像素的结构示意图；6 is a schematic structural diagram of a sub-pixel on an array substrate provided in Embodiment 3 of the present application;
图7为本申请提供的显示面板的结构示意图。FIG. 7 is a schematic structural diagram of a display panel provided by the present application.
本发明的实施方式Embodiments of the present invention
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.
在本申请的描述中，需要理解的是，术语“纵向”、“横向”、“长度”、“宽度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。在本申请中，“/”表示“或者”的意思。In the description of this application, it should be understood that the terms "portrait", "horizontal", "length", "width", "upper", "lower", "front", "rear", "left", " The orientation or positional relationship indicated by "right", "vertical", "horizontal", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying the indicated device. Or elements must have a particular orientation, be constructed and operate in a particular orientation, and therefore should not be construed as a limitation of the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, features defined as "first", "second" may expressly or implicitly include one or more of said features. In the description of the present application, "plurality" means two or more, unless otherwise expressly and specifically defined. In this application, "/" means "or".
本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。The application may repeat reference numerals and/or reference letters in different instances for the purpose of simplicity and clarity and not in itself indicative of the relationship between the various embodiments and/or arrangements discussed.
以下请结合具体实施例对本申请的阵列基板进行详细描述。The array substrate of the present application will be described in detail below with reference to specific embodiments.
实施例一Example 1
如图2所示，本申请的阵列基板包括阵列分布的子像素，需要说明的是，此处为了方便说明，图2中仅例举了一个子像素进行说明。每一所述子像素包括主区薄膜晶体管T1、次区薄膜晶体管T2以及共享薄膜晶体管T3。每个所述子像素包括主区10和次区20，同一所述子像素的所述主区10和所述次区20之间包括非显示区，所述主区薄膜晶体管T1、所述次区薄膜晶体管T2以及所述共享薄膜晶体管T3对应位于所述非显示区内。对应每一行所述子像素设置一条栅极线30，所述栅极线30位于所述主区10与所述次区20之间，对应每一列所述子像素设置一条数据线40，相邻两所述数据线40界定出像素边界。所述子像素对应所述主区10设置有主像素电极601，对应所述次区20设置有次像素电极602，所述子像素还包括与所述主像素电极601以及所述次像素电极602异层设置的公共电极50。As shown in FIG. 2 , the array substrate of the present application includes sub-pixels distributed in an array. It should be noted that, for the convenience of description, only one sub-pixel is illustrated in FIG. 2 for description. Each of the sub-pixels includes a main area thin film transistor T1, a sub area thin film transistor T2 and a shared thin film transistor T3. Each of the sub-pixels includes a main area 10 and a sub-area 20, a non-display area is included between the main area 10 and the sub-area 20 of the same sub-pixel, the main area thin film transistor T1, the sub-area 20 The area thin film transistor T2 and the shared thin film transistor T3 are correspondingly located in the non-display area. A gate line 30 is arranged corresponding to each row of the sub-pixels, the gate line 30 is located between the main region 10 and the sub-region 20, and a data line 40 is arranged corresponding to each column of the sub-pixels, adjacent to each other. The two data lines 40 define pixel boundaries. The sub-pixel is provided with a main pixel electrode 601 corresponding to the main area 10 and a sub-pixel electrode 602 corresponding to the sub-area 20. The sub-pixel further includes the main pixel electrode 601 and the sub-pixel electrode 602. Common electrodes 50 arranged in different layers.
结合图3和图4所示，所述阵列基板包括：基底101；栅极102，设置于所述基底101上；栅极绝缘层103，设置于所述栅极102上；有源层104，对应所述栅极102设置于所述栅极绝缘层103上；源/漏极105，设置于所述有源层104的两端，并与所述有源层104的离子掺杂区接触；有机保护层106，设置于所述源/漏极105上；像素电极层（601,602），设置于所述有机保护层106上，包括所述主像素电极和所述次像素电极。3 and 4, the array substrate includes: a base 101; a gate 102, disposed on the base 101; a gate insulating layer 103, disposed on the gate 102; an active layer 104, Corresponding to the gate 102 is disposed on the gate insulating layer 103; the source/drain 105 is disposed on both ends of the active layer 104, and is in contact with the ion-doped region of the active layer 104; The organic protective layer 106 is disposed on the source/drain electrodes 105 ; the pixel electrode layers ( 601 , 602 ) are disposed on the organic protective layer 106 and include the main pixel electrode and the sub-pixel electrode.
其中，与所述栅极102同层设置的结构还包括所述栅极线30、所述公共电极50以及其他常规结构等，所述栅极102、所述栅极线30、所述公共电极50可以为同材料经同一光罩工艺同时形成的。The structure disposed on the same layer as the gate 102 further includes the gate line 30 , the common electrode 50 and other conventional structures. The gate 102 , the gate line 30 and the common electrode 50 may be formed simultaneously from the same material and through the same mask process.
与所述源/漏极105同层设置的结构还包括所述数据线40以及其他常规结构等，所述源/漏极105与所述数据线40可以为同材料经同一光罩工艺同时形成的。The structure disposed on the same layer as the source/drain 105 also includes the data line 40 and other conventional structures, etc. The source/drain 105 and the data line 40 can be formed of the same material at the same time through the same mask process of.
需要说明的是，本实施例中以底栅结构的阵列基板为例，但在其他实施例中，所述阵列基板也可以为顶栅结构，此处不做限制。It should be noted that, in this embodiment, an array substrate with a bottom gate structure is used as an example, but in other embodiments, the array substrate may also be a top gate structure, which is not limited here.
结合图2-图4所示，所述主区薄膜晶体管T1通过第一过孔100与所述主像素电极601电连接，所述次区薄膜晶体管T2通过第二过孔200与所述次像素电极602电连接，所述共享薄膜晶体管T3通过第三过孔300与所述公共电极50电连接。其中，所述第一过孔100以及所述第二过孔200贯穿有机保护层101，所述第三过孔300贯穿栅极绝缘层102，所述第三过孔300的孔径小于所述第一过孔100以及所述第二过孔200的孔径。Referring to FIGS. 2 to 4 , the thin film transistor T1 in the main area is electrically connected to the main pixel electrode 601 through the first via hole 100 , and the thin film transistor T2 in the sub area is connected to the sub pixel through the second via hole 200 . The electrode 602 is electrically connected, and the shared thin film transistor T3 is electrically connected to the common electrode 50 through the third via hole 300 . The first via hole 100 and the second via hole 200 penetrate through the organic protective layer 101 , the third via hole 300 penetrates through the gate insulating layer 102 , and the diameter of the third via hole 300 is smaller than that of the third via hole 300 . A via hole 100 and the diameter of the second via hole 200 .
其中，所述第一过孔100以及所述第二过孔200贯穿所述有机保护层106，所述第三过孔300贯穿所述栅极绝缘层103。The first via hole 100 and the second via hole 200 penetrate through the organic protective layer 106 , and the third via hole 300 penetrates through the gate insulating layer 103 .
随着液晶显示装置尺寸的增大，由液晶盒盒厚的均一性不佳导致的显示亮度不均等不良将会更加明显。因此，在阵列(薄膜晶体管)基板上通常需要覆盖一层透明的有机保护层（即阵列基板侧有机膜 (Polymer Film on Array，PFA)）来改变下层膜表面的平整性，防止电场互相干扰，从而可以有效改善由于地形因素造成的液晶显示装置的显示不均，降低寄生电容，减少由电负载过大造成的闪烁等显示异常，提升显示装置的品质。As the size of the liquid crystal display device increases, the defects such as uneven display brightness caused by the poor uniformity of the cell thickness of the liquid crystal cell will become more obvious. Therefore, it is usually necessary to cover the array (thin film transistor) substrate with a transparent organic protective layer (ie, the organic film on the array substrate side (Polymer Film on Array, PFA)) to change the flatness of the surface of the underlying film and prevent the electric field from interfering with each other. Therefore, the display unevenness of the liquid crystal display device caused by the terrain factor can be effectively improved, the parasitic capacitance can be reduced, the display abnormality such as flicker caused by excessive electrical load can be reduced, and the quality of the display device can be improved.
但是在一些传统结构中，如图1所示，公共电极50’与像素电极（601’、602’）同层并设置在像素电极的周边，所以主区薄膜晶体管T1与主像素电极601’连接的第一过孔100’、次区薄膜晶体管T2与次像素电极602’连接的第二过孔200’、以及共享薄膜晶体管T3与公共电极连接的第三过孔300’均是贯穿有机保护层的过孔，由于制程工艺及设备等条件的影响，形成的贯穿有机保护层的过孔通常会比较大，因此会占据非显示区较多的空间，使得显示区（即主区和次区）的空间被压缩，导致像素的开口率降低。However, in some conventional structures, as shown in FIG. 1 , the common electrode 50 ′ and the pixel electrodes ( 601 ′, 602 ′) are in the same layer and are arranged around the pixel electrodes, so the main area thin film transistor T1 is connected to the main pixel electrode 601 ′ The first via hole 100', the second via hole 200' connecting the sub-region thin film transistor T2 and the sub-pixel electrode 602', and the third via hole 300' connecting the shared thin film transistor T3 and the common electrode are all through the organic protective layer. Due to the influence of process technology and equipment and other conditions, the via holes formed through the organic protective layer are usually relatively large, so they will occupy more space in the non-display area, making the display area (ie the main area and the secondary area) The space is compressed, resulting in a reduction in the aperture ratio of the pixel.
而本申请通过将公共电极50设置于与栅极102同层，将原本贯穿有机保护层106的第三过孔300改为贯穿栅极绝缘层103，按目前现有的工艺制程水准，贯穿栅极绝缘层103的过孔尺寸可以做的比贯穿有机保护层106的过孔尺寸小很多，例如，贯穿有机保护层106的过孔与贯穿栅极绝缘层103的过孔的尺寸比例可以做到1.5:1至4:1。In the present application, by disposing the common electrode 50 on the same layer as the gate electrode 102, the third via hole 300 originally passing through the organic protective layer 106 is changed to pass through the gate insulating layer 103. The size of the via hole in the gate insulating layer 103 can be made much smaller than the size of the via hole penetrating the organic protective layer 106. For example, the size ratio of the via hole penetrating the organic protective layer 106 to the via hole penetrating the gate insulating layer 103 can be 1.5:1 to 4:1.
在一种实施例中，贯穿所述有机保护层106的过孔的孔径为9mm，贯穿所述栅极绝缘层103的过孔的孔径为4mm。因此，本申请可以减小第三过孔300的孔径，从而减小主区10与次区20之间的非显示区的空间占比，进而提高像素的开口率和穿透率，因此可以减小背光的亮度、降低功率，以此有效解决背光热量较大的技术问题。In an embodiment, the diameter of the via hole passing through the organic protective layer 106 is 9 mm, and the diameter of the via hole passing through the gate insulating layer 103 is 4 mm. Therefore, the present application can reduce the aperture of the third via hole 300 , thereby reducing the space ratio of the non-display area between the main area 10 and the sub area 20 , thereby improving the aperture ratio and transmittance of the pixel, thus reducing the Reduce the brightness of the backlight and reduce the power, so as to effectively solve the technical problem of large backlight heat.
如图2所示，本实施例为了进一步增大像素的开口率和穿透率，将次区薄膜晶体管T2与共享薄膜晶体管T3进行合并设计，即一所述子像素对应设置有第一源极1051、第二源极1052、第一漏极1053以及第二漏极1054，其中，所述主区薄膜晶体管T1和所述次区薄膜晶体管T2共用所述第一源极1051，所述次区薄膜晶体管T2和所述共享薄膜晶体管T3共用所述第二漏极1054。As shown in FIG. 2 , in this embodiment, in order to further increase the aperture ratio and transmittance of the pixel, the sub-region thin film transistor T2 and the shared thin film transistor T3 are combined and designed, that is, one of the sub-pixels is correspondingly provided with a first source electrode 1051, a second source electrode 1052, a first drain electrode 1053 and a second drain electrode 1054, wherein the main area thin film transistor T1 and the sub area thin film transistor T2 share the first source electrode 1051, and the sub area thin film transistor T2 shares the first source electrode 1051. The thin film transistor T2 and the shared thin film transistor T3 share the second drain electrode 1054 .
也就是说，在图1中，次像素电极602’通过第二过孔200’ 引出两条线分别形成次区薄膜晶体管T2的漏极D1以及共享薄膜晶体管T3的漏极D2。而本申请中，所述次像素电极602通过所述第二过孔200引出一条线形成所述第二漏极1054，所述第二漏极1054即用作所述次区薄膜晶体管T2的漏极，也用作所述共享薄膜晶体管T3的漏极。That is, in FIG. 1 , the sub-pixel electrode 602' leads out two lines through the second via hole 200' to form the drain D1 of the sub-region thin film transistor T2 and the drain D2 of the shared thin film transistor T3, respectively. In this application, a line is drawn from the sub-pixel electrode 602 through the second via hole 200 to form the second drain electrode 1054 , and the second drain electrode 1054 is used as the drain of the sub-region thin film transistor T2 The pole is also used as the drain of the shared thin film transistor T3.
因此，本申请相较于传统结构可以减少所述主区10与所述次区20之间的非显示区内的线路布线，由于将次区薄膜晶体管T2与共享薄膜晶体管T3进行合并设计，从而减少所述非显示区的空间占比，进而进一步增大像素的开口率和穿透率，进一步减小背光的亮度及功率。Therefore, compared with the conventional structure, the present application can reduce the wiring in the non-display area between the main area 10 and the sub area 20, because the sub area thin film transistor T2 and the shared thin film transistor T3 are combined and designed, so that The space ratio of the non-display area is reduced, thereby further increasing the aperture ratio and transmittance of the pixels, and further reducing the brightness and power of the backlight.
在一种实施例中，所述公共电极线50为透明材质，所述主像素电极601与所述次像素电极602在所述阵列基板上的投影范围至少部分覆盖所述公共电极50在所述阵列基板上的投影范围。可以理解的是，该投影为正投影。In an embodiment, the common electrode line 50 is made of a transparent material, and the projection range of the main pixel electrode 601 and the sub-pixel electrode 602 on the array substrate at least partially covers the common electrode 50 on the Projection range on the array substrate. Understandably, this projection is an orthographic projection.
进一步地，所述像素电极层（601,602）在所述阵列基板上的投影范围至少覆盖所述公共电极50对应所述数据线40方向上的部分在所述阵列基板上的投影范围。由于所述公共电极线50为透明材质，因此所述像素电极层（601,602）可覆盖于所述公共电极50的上方。Further, the projection range of the pixel electrode layers ( 601 , 602 ) on the array substrate at least covers the projection range of the portion of the common electrode 50 corresponding to the data line 40 on the array substrate. Since the common electrode line 50 is made of transparent material, the pixel electrode layers ( 601 , 602 ) can cover the top of the common electrode 50 .
当所述像素电极层（601,602）覆盖所述公共电极50对应所述数据线40方向的部分时，由于所述像素电极层（601,602）在沿所述栅极线30的方向上增加了宽度，因此使得像素的开口率增大，从而提高了像素的穿透率，使得与该阵列基板搭配的背光的亮度适当的降低，进而降低背光的产热。When the pixel electrode layer ( 601 , 602 ) covers the part of the common electrode 50 corresponding to the direction of the data line 40 , since the pixel electrode layer ( 601 , 602 ) increases in width in the direction along the gate line 30 , Therefore, the aperture ratio of the pixel is increased, thereby improving the transmittance of the pixel, so that the brightness of the backlight matched with the array substrate is appropriately reduced, thereby reducing the heat generation of the backlight.
进一步地，所述像素电极层（601,602）在所述阵列基板上的投影范围完全覆盖所述公共电极50在所述阵列基板上的投影范围。由于所述像素电极层（601,602）又在所述数据线40的方向上增加了长度，即所述像素电极层（601,602）还覆盖所述公共电极50对应所述栅极线30方向的部分，因此，可进一步提高像素的开口率和穿透率。Further, the projection range of the pixel electrode layers (601, 602) on the array substrate completely covers the projection range of the common electrode 50 on the array substrate. Since the pixel electrode layer (601, 602) increases the length in the direction of the data line 40, that is, the pixel electrode layer (601, 602) also covers the part of the common electrode 50 corresponding to the direction of the gate line 30, Therefore, the aperture ratio and transmittance of the pixel can be further improved.
实施例二Embodiment 2
如图5所示，为本申请实施例二提供的阵列基板上的子像素的结构示意图。本实施例的阵列基板与上述实施例一的阵列基板的结构相同/相似，区别在于：本实施例中所述第一过孔100以及所述第二过孔200向像素开口区一侧靠近，即所述第一过孔100至少一部分位于所述主区10内，所述第二过孔200至少一部分位于所述次区20内，以此减小所述主区10与所述次区20之间的非显示区的面积，从而增大像素的开口率。As shown in FIG. 5 , it is a schematic structural diagram of a sub-pixel on the array substrate provided in the second embodiment of the present application. The structure of the array substrate of this embodiment is the same/similar to the array substrate of the above-mentioned first embodiment, the difference is that in this embodiment, the first via hole 100 and the second via hole 200 are close to the side of the pixel opening area, That is, at least a part of the first via hole 100 is located in the main area 10 , and at least a part of the second via hole 200 is located in the sub area 20 , thereby reducing the size of the main area 10 and the sub area 20 The area of the non-display area in between, thereby increasing the aperture ratio of the pixel.
进一步的，所述主像素电极601在所述阵列基板上的投影范围至少部分覆盖所述第一过孔100在所述阵列基板上的投影范围，所述次像素电极602在所述阵列基板上的投影范围至少部分覆盖所述第二过孔200在所述阵列基板上的投影范围。Further, the projection range of the main pixel electrode 601 on the array substrate at least partially covers the projection range of the first via hole 100 on the array substrate, and the sub-pixel electrode 602 is on the array substrate The projection range of at least partially covers the projection range of the second via hole 200 on the array substrate.
例如，所述第一过孔100的一半位于所述主区10内，所述第二过孔200的一半位于所述次区20内，具体可根据实际情况而定。For example, half of the first via hole 100 is located in the main area 10 , and half of the second via hole 200 is located in the secondary area 20 , which may be determined according to actual conditions.
为了实现像素开口率的最大化，本实施例中所述第一过孔100完全设置于所述主区10内，以及所述第二过孔200完全设置于所述次区20内，使得所述主区10与所述次区20之间的非显示区的空间占比减小。In order to maximize the pixel aperture ratio, in this embodiment, the first via hole 100 is completely disposed in the main area 10 , and the second via hole 200 is completely disposed in the sub area 20 , so that all the The space ratio of the non-display area between the main area 10 and the secondary area 20 is reduced.
进一步的，所述主像素电极601与所述次像素电极602均包括主干电极60a和支干电极60b，所述主干电极60a可以为“十”字形，也可以为“田”字形，或是其他形状，此处不做限制。所述第一过孔100与所述第二过孔200对应位于所述主干电极60a处，因此，所述第一过孔100与所述第二过孔200的设置不会影响液晶的偏转，也就不会影响到显示效果。Further, the main pixel electrode 601 and the sub-pixel electrode 602 both include a main electrode 60a and a branch electrode 60b, and the main electrode 60a can be in the shape of a "cross", or a shape of a "field", or other The shape is not limited here. The first via hole 100 and the second via hole 200 are located at the main electrode 60a correspondingly, therefore, the arrangement of the first via hole 100 and the second via hole 200 will not affect the deflection of the liquid crystal, It will not affect the display effect.
进一步的，所述第一过孔100与所述第二过孔200位于所述主干电极60a的覆盖范围内，因此，可以提高像素的开口率以及显示效果。Further, the first via hole 100 and the second via hole 200 are located within the coverage area of the trunk electrode 60a, so the aperture ratio of the pixel and the display effect can be improved.
进一步的，为了优化空间设计，所述第一过孔100与所述第二过孔200可以沿所述非显示区的中心线对称设置。Further, in order to optimize the space design, the first via hole 100 and the second via hole 200 may be symmetrically arranged along the center line of the non-display area.
本实施例相较于上述实施例一，由于本实施例将所述第一过孔100与所述第二过孔200分别设置于所述主区10内以及所述次区20内，因此可以进一步节省所述非显示区的空间，从而进一步提高像素的开口率和穿透率，可以有效解决背光热量较大的技术问题。Compared with the above-mentioned first embodiment, in this embodiment, the first via hole 100 and the second via hole 200 are respectively disposed in the main area 10 and the sub area 20 , so it is possible to The space of the non-display area is further saved, thereby further improving the aperture ratio and transmittance of the pixel, and can effectively solve the technical problem of large backlight heat.
实施例三Embodiment 3
如图6所示，为本申请实施例三提供的阵列基板上的子像素的结构示意图。本实施例的阵列基板与上述实施例二的阵列基板的结构相同/相似，区别在于：本实施例的所述第三过孔300至少一部分位于所述次区20内，从而进一步增大像素的开口率。As shown in FIG. 6 , it is a schematic structural diagram of a sub-pixel on the array substrate provided in the third embodiment of the present application. The structure of the array substrate of this embodiment is the same/similar to the array substrate of the above-mentioned second embodiment, the difference is that at least a part of the third via hole 300 of this embodiment is located in the sub-region 20, thereby further increasing the pixel density opening rate.
其中，所述次像素电极602在所述阵列基板上的投影范围至少部分覆盖所述第三过孔300在所述阵列基板上的投影范围。The projection range of the sub-pixel electrode 602 on the array substrate at least partially covers the projection range of the third via hole 300 on the array substrate.
为了实现像素开口率的最大化，本实施例中所述第三过孔300完全设置于所述次区20内，所述第三过孔300对应位于所述主干电极60a处，因此，所述第三过孔300的设置不会影响液晶的偏转，也就不会影响到显示效果。In order to maximize the pixel aperture ratio, in this embodiment, the third via hole 300 is completely disposed in the sub-region 20, and the third via hole 300 is correspondingly located at the main electrode 60a. Therefore, the The setting of the third via hole 300 will not affect the deflection of the liquid crystal, and thus will not affect the display effect.
进一步的，所述第三过孔300位于所述主干电极60a的覆盖范围内，因此，可以提高像素的开口率以及显示效果。Further, the third via hole 300 is located within the coverage area of the trunk electrode 60a, so the aperture ratio of the pixel and the display effect can be improved.
本实施例相较于上述实施例二，由于本实施例将所述第三过孔300设置于所述次区20内，因此可以进一步节省所述非显示区的空间，从而进一步提高像素的开口率和穿透率，可以有效解决背光热量较大的技术问题。Compared with the second embodiment described above, this embodiment can further save the space of the non-display area because the third via hole 300 is disposed in the sub-region 20, thereby further increasing the opening of the pixel. It can effectively solve the technical problem of large backlight heat.
在一种实施例中，与上述实施例相比，区别在于：所述主区10还包括主存储电极（未图示），所述主存储电极与对应所述主区10的所述公共电极50通过介电层绝缘并形成主存储电容；所述次区20还包括次存储电极（未图示），所述次存储电极与对应所述次区20的所述公共电极50通过所述介电层绝缘并形成次存储电容。In an embodiment, compared with the above-mentioned embodiment, the difference is that the main area 10 further includes a main storage electrode (not shown), the main storage electrode and the common electrode corresponding to the main area 10 50 is insulated by a dielectric layer and forms a main storage capacitor; the sub-region 20 further includes a sub-storage electrode (not shown), and the sub-storage electrode and the common electrode 50 corresponding to the sub-region 20 pass through the dielectric layer. The electrical layer insulates and forms a secondary storage capacitor.
其中，所述主存储电极与所述次存储电极在所述阵列基板上的投影均位于所述像素电极层（601,602）在所述阵列基板上的投影范围内。所述主存储电极与所述次存储电极均为透明电极，因此不会影响子像素的透光率及显示效果。从而，进一步减小所述非显示区的面积，增大像素的开口率，进而提高子像素的穿透率。Wherein, the projections of the main storage electrodes and the secondary storage electrodes on the array substrate are both located within the projection range of the pixel electrode layers (601, 602) on the array substrate. The main storage electrode and the secondary storage electrode are both transparent electrodes, so the light transmittance and display effect of the sub-pixels will not be affected. Therefore, the area of the non-display area is further reduced, the aperture ratio of the pixel is increased, and the transmittance of the sub-pixel is further improved.
本申请还提供一种显示面板，包括如上所述的阵列基板。具体的，所述显示面板为液晶显示面板，如图7所示，所述显示面板包括阵列基板1、彩膜基板2以及位于所述阵列基板1与所述彩膜基板2之间的液晶层3。本申请的显示面板具有较高的像素开口率和穿透率，因此便可解决背光热量较大的技术问题。The present application also provides a display panel including the above-mentioned array substrate. Specifically, the display panel is a liquid crystal display panel. As shown in FIG. 7 , the display panel includes an array substrate 1 , a color filter substrate 2 and a liquid crystal layer between the array substrate 1 and the color filter substrate 2 . 3. The display panel of the present application has high pixel aperture ratio and transmittance, so the technical problem of large backlight heat can be solved.
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。To sum up, although the present application has disclosed the above-mentioned preferred embodiments, the above-mentioned preferred embodiments are not intended to limit the present application. Those of ordinary skill in the art, without departing from the spirit and scope of this application, can Therefore, the scope of protection of the present application is subject to the scope defined by the claims.

Claims (20)

  1. 一种阵列基板，其中，包括阵列分布的子像素，每一所述子像素包括主区薄膜晶体管、次区薄膜晶体管以及共享薄膜晶体管；An array substrate, comprising sub-pixels distributed in an array, each of the sub-pixels including a main area thin film transistor, a sub area thin film transistor and a shared thin film transistor;
    所述子像素包括主区和次区，对应所述主区设置有主像素电极，对应所述次区设置有次像素电极，所述子像素还包括与所述主像素电极以及所述次像素电极异层设置的公共电极；The sub-pixel includes a main area and a sub-area, a main pixel electrode is disposed corresponding to the main area, and a sub-pixel electrode is disposed corresponding to the sub-area, and the sub-pixel further includes the main pixel electrode and the sub-pixel. Common electrodes arranged in different layers of electrodes;
    所述主区薄膜晶体管通过第一过孔与所述主像素电极电连接，所述次区薄膜晶体管通过第二过孔与所述次像素电极电连接，所述共享薄膜晶体管通过第三过孔与所述公共电极电连接；The main area thin film transistor is electrically connected to the main pixel electrode through a first via hole, the sub area thin film transistor is electrically connected to the sub pixel electrode through a second via hole, and the shared thin film transistor is electrically connected through a third via hole electrically connected to the common electrode;
    其中，所述第三过孔的孔径小于所述第一过孔以及所述第二过孔的孔径。Wherein, the diameter of the third via hole is smaller than the diameter of the first via hole and the diameter of the second via hole.
  2. 根据权利要求1所述的阵列基板，其中，所述阵列基板包括：The array substrate of claim 1, wherein the array substrate comprises:
    基底；base;
    栅极，设置于所述基底上；a gate, disposed on the substrate;
    栅极绝缘层，设置于所述栅极上；a gate insulating layer, disposed on the gate;
    有源层，对应所述栅极设置于所述栅极绝缘层上；an active layer, disposed on the gate insulating layer corresponding to the gate;
    源/漏极，设置于所述有源层的两端，并与所述有源层的离子掺杂区接触；source/drain, disposed at both ends of the active layer and in contact with the ion-doped regions of the active layer;
    有机保护层，设置于所述源/漏极上；an organic protective layer, disposed on the source/drain;
    像素电极层，设置于所述有机保护层上，包括所述主像素电极和所述次像素电极；a pixel electrode layer, disposed on the organic protective layer, including the main pixel electrode and the sub-pixel electrode;
    所述公共电极与所述栅极同层设置，所述第一过孔以及所述第二过孔贯穿所述有机保护层，所述第三过孔贯穿栅极绝缘层。The common electrode and the gate electrode are disposed in the same layer, the first via hole and the second via hole penetrate through the organic protective layer, and the third via hole penetrates through the gate insulating layer.
  3. 根据权利要求1所述的阵列基板，其中，一所述子像素对应设置有第一源极、第二源极、第一漏极以及第二漏极，其中，所述主区薄膜晶体管和所述次区薄膜晶体管共用所述第一源极，所述次区薄膜晶体管和所述共享薄膜晶体管共用所述第二漏极。The array substrate according to claim 1, wherein a first source electrode, a second source electrode, a first drain electrode and a second drain electrode are correspondingly disposed on one of the sub-pixels, wherein the main area thin film transistor and all the The sub-region thin film transistors share the first source electrode, and the sub-region thin film transistors and the shared thin film transistor share the second drain electrode.
  4. 根据权利要求1所述的阵列基板，其中，同一所述子像素的所述主区和所述次区之间包括非显示区，所述主区薄膜晶体管、所述次区薄膜晶体管以及所述共享薄膜晶体管对应位于所述非显示区内，其中，所述第一过孔至少一部分位于所述主区内，所述第二过孔至少一部分位于所述次区内。The array substrate according to claim 1, wherein a non-display area is included between the main area and the sub area of the same sub-pixel, the main area thin film transistor, the sub area thin film transistor and the sub area thin film transistor The shared thin film transistors are correspondingly located in the non-display area, wherein at least a part of the first via hole is located in the main area, and at least a part of the second via hole is located in the sub area.
  5. 根据权利要求4所述的阵列基板，其中，所述主像素电极在所述阵列基板上的投影范围至少部分覆盖所述第一过孔在所述阵列基板上的投影范围，所述次像素电极在所述阵列基板上的投影范围至少部分覆盖所述第二过孔在所述阵列基板上的投影范围。The array substrate according to claim 4, wherein the projection range of the main pixel electrode on the array substrate at least partially covers the projection range of the first via hole on the array substrate, and the sub pixel electrode The projected range on the array substrate at least partially covers the projected range of the second via hole on the array substrate.
  6. 根据权利要求4所述的阵列基板，其中，所述主像素电极与所述次像素电极均包括主干电极和支干电极，所述第一过孔与所述第二过孔对应位于所述主干电极处。The array substrate according to claim 4, wherein the main pixel electrode and the sub-pixel electrode each comprise a main electrode and a branch electrode, and the first via hole and the second via hole are located in the main line correspondingly at the electrode.
  7. 根据权利要求6所述的阵列基板，其中，所述第一过孔与所述第二过孔沿所述非显示区的中心线对称设置。The array substrate according to claim 6, wherein the first via hole and the second via hole are symmetrically arranged along a center line of the non-display area.
  8. 根据权利要求4所述的阵列基板，其中，所述第三过孔至少一部分位于所述次区内。The array substrate of claim 4, wherein at least a part of the third via hole is located in the sub-region.
  9. 根据权利要求1所述的阵列基板，其中，所述主像素电极与所述次像素电极在所述阵列基板上的投影范围至少部分覆盖所述公共电极在所述阵列基板上的投影范围。The array substrate according to claim 1, wherein the projection range of the main pixel electrode and the sub-pixel electrode on the array substrate at least partially covers the projection range of the common electrode on the array substrate.
  10. 根据权利要求9所述的阵列基板，其中，所述公共电极为透明材料。The array substrate of claim 9, wherein the common electrode is a transparent material.
  11. 一种显示面板，其中，包括阵列基板，所述阵列基板包括阵列分布的子像素，每一所述子像素包括主区薄膜晶体管、次区薄膜晶体管以及共享薄膜晶体管；A display panel, comprising an array substrate, the array substrate comprising sub-pixels distributed in an array, each of the sub-pixels comprising a main area thin film transistor, a sub area thin film transistor and a shared thin film transistor;
    所述子像素包括主区和次区，对应所述主区设置有主像素电极，对应所述次区设置有次像素电极，所述子像素还包括与所述主像素电极以及所述次像素电极异层设置的公共电极；The sub-pixel includes a main area and a sub-area, a main pixel electrode is arranged corresponding to the main area, and a sub-pixel electrode is arranged corresponding to the sub-area, and the sub-pixel further includes the main pixel electrode and the sub-pixel. Common electrodes arranged in different layers of electrodes;
    所述主区薄膜晶体管通过第一过孔与所述主像素电极电连接，所述次区薄膜晶体管通过第二过孔与所述次像素电极电连接，所述共享薄膜晶体管通过第三过孔与所述公共电极电连接；The main area thin film transistor is electrically connected to the main pixel electrode through a first via hole, the sub area thin film transistor is electrically connected to the sub pixel electrode through a second via hole, and the shared thin film transistor is electrically connected through a third via hole electrically connected to the common electrode;
    其中，所述第三过孔的孔径小于所述第一过孔以及所述第二过孔的孔径。Wherein, the diameter of the third via hole is smaller than the diameter of the first via hole and the diameter of the second via hole.
  12. 根据权利要求11所述的显示面板，其中，所述阵列基板包括：The display panel of claim 11, wherein the array substrate comprises:
    基底；base;
    栅极，设置于所述基底上；a gate, disposed on the substrate;
    栅极绝缘层，设置于所述栅极上；a gate insulating layer, disposed on the gate;
    有源层，对应所述栅极设置于所述栅极绝缘层上；an active layer, disposed on the gate insulating layer corresponding to the gate;
    源/漏极，设置于所述有源层的两端，并与所述有源层的离子掺杂区接触；source/drain, disposed at both ends of the active layer and in contact with the ion-doped regions of the active layer;
    有机保护层，设置于所述源/漏极上；an organic protective layer, disposed on the source/drain;
    像素电极层，设置于所述有机保护层上，包括所述主像素电极和所述次像素电极；a pixel electrode layer, disposed on the organic protective layer, including the main pixel electrode and the sub-pixel electrode;
    所述公共电极与所述栅极同层设置，所述第一过孔以及所述第二过孔贯穿所述有机保护层，所述第三过孔贯穿栅极绝缘层。The common electrode and the gate electrode are disposed in the same layer, the first via hole and the second via hole penetrate through the organic protective layer, and the third via hole penetrates through the gate insulating layer.
  13. 根据权利要求11所述的显示面板，其中，一所述子像素对应设置有第一源极、第二源极、第一漏极以及第二漏极，其中，所述主区薄膜晶体管和所述次区薄膜晶体管共用所述第一源极，所述次区薄膜晶体管和所述共享薄膜晶体管共用所述第二漏极。The display panel according to claim 11, wherein a first source electrode, a second source electrode, a first drain electrode and a second drain electrode are correspondingly disposed on one of the sub-pixels, wherein the main area thin film transistor and all the The sub-region thin film transistors share the first source electrode, and the sub-region thin film transistors and the shared thin film transistor share the second drain electrode.
  14. 根据权利要求11所述的显示面板，其中，同一所述子像素的所述主区和所述次区之间包括非显示区，所述主区薄膜晶体管、所述次区薄膜晶体管以及所述共享薄膜晶体管对应位于所述非显示区内，其中，所述第一过孔至少一部分位于所述主区内，所述第二过孔至少一部分位于所述次区内。The display panel according to claim 11, wherein a non-display area is included between the main area and the sub area of the same sub-pixel, the main area thin film transistor, the sub area thin film transistor and the sub area thin film transistor The shared thin film transistors are correspondingly located in the non-display area, wherein at least a part of the first via hole is located in the main area, and at least a part of the second via hole is located in the sub area.
  15. 根据权利要求14所述的显示面板，其中，所述主像素电极在所述阵列基板上的投影范围至少部分覆盖所述第一过孔在所述阵列基板上的投影范围，所述次像素电极在所述阵列基板上的投影范围至少部分覆盖所述第二过孔在所述阵列基板上的投影范围。The display panel according to claim 14, wherein a projection range of the main pixel electrode on the array substrate at least partially covers a projection range of the first via hole on the array substrate, and the sub pixel electrode The projection range on the array substrate at least partially covers the projection range of the second via hole on the array substrate.
  16. 根据权利要求14所述的显示面板，其中，所述主像素电极与所述次像素电极均包括主干电极和支干电极，所述第一过孔与所述第二过孔对应位于所述主干电极处。The display panel according to claim 14 , wherein the main pixel electrode and the sub-pixel electrode each comprise a trunk electrode and a branch electrode, and the first via hole and the second via hole are located in the trunk correspondingly at the electrode.
  17. 根据权利要求16所述的显示面板，其中，所述第一过孔与所述第二过孔沿所述非显示区的中心线对称设置。The display panel of claim 16 , wherein the first via hole and the second via hole are symmetrically arranged along a center line of the non-display area.
  18. 根据权利要求14所述的显示面板，其中，所述第三过孔至少一部分位于所述次区内。The display panel of claim 14, wherein at least a part of the third via hole is located in the sub-region.
  19. 根据权利要求11所述的显示面板，其中，所述主像素电极与所述次像素电极在所述阵列基板上的投影范围至少部分覆盖所述公共电极在所述阵列基板上的投影范围。The display panel according to claim 11, wherein the projection range of the main pixel electrode and the sub-pixel electrode on the array substrate at least partially covers the projection range of the common electrode on the array substrate.
  20. 根据权利要求19所述的显示面板，其中，所述公共电极为透明材料。The display panel of claim 19, wherein the common electrode is a transparent material.
PCT/CN2020/124691 2020-09-10 2020-10-29 Array substrate and display panel WO2022052242A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010944769.4 2020-09-10
CN202010944769.4A CN112068371A (en) 2020-09-10 2020-09-10 Array substrate and display panel

Publications (1)

Publication Number Publication Date
WO2022052242A1 true WO2022052242A1 (en) 2022-03-17

Family

ID=73663326

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/124691 WO2022052242A1 (en) 2020-09-10 2020-10-29 Array substrate and display panel

Country Status (2)

Country Link
CN (1) CN112068371A (en)
WO (1) WO2022052242A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114815423A (en) * 2022-04-29 2022-07-29 苏州华星光电技术有限公司 Display panel manufacturing method

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112596306B (en) * 2021-01-06 2023-11-28 深圳市华星光电半导体显示技术有限公司 Array substrate and display panel
CN113314546B (en) * 2021-05-21 2023-06-02 深圳市华星光电半导体显示技术有限公司 Array substrate, array substrate testing method and display panel
CN113325635B (en) * 2021-05-31 2022-07-12 Tcl华星光电技术有限公司 Display panel and manufacturing method thereof
CN113391491B (en) * 2021-06-16 2023-11-28 惠州华星光电显示有限公司 Liquid crystal display panel and display device
CN113534546B (en) * 2021-07-23 2023-10-03 深圳市华星光电半导体显示技术有限公司 Array substrate and display panel
CN113741108B (en) * 2021-08-31 2022-07-22 惠科股份有限公司 Array substrate, display panel and display device
CN114153098A (en) * 2021-11-30 2022-03-08 惠科股份有限公司 First substrate, display panel, liquid crystal display and display device
CN114236925B (en) * 2021-12-14 2023-02-28 苏州华星光电技术有限公司 Array substrate and liquid crystal display panel
CN114280864A (en) * 2021-12-17 2022-04-05 Tcl华星光电技术有限公司 Array substrate and liquid crystal display panel
CN115145082A (en) * 2022-07-18 2022-10-04 滁州惠科光电科技有限公司 Pixel structure, array substrate and display panel
CN115377127B (en) * 2022-10-25 2023-01-31 惠科股份有限公司 Array substrate, preparation method thereof and display panel

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100237350A1 (en) * 2007-06-07 2010-09-23 Chunghwa Picture Tubes, Ltd. Pixel structure
CN104122724A (en) * 2014-07-04 2014-10-29 深圳市华星光电技术有限公司 Low-color-error liquid crystal array substrate and drive method thereof
CN104865763A (en) * 2015-06-12 2015-08-26 深圳市华星光电技术有限公司 Array substrate
CN105807520A (en) * 2016-05-20 2016-07-27 深圳市华星光电技术有限公司 3t pixel structure and liquid crystal display device
CN111176041A (en) * 2020-02-21 2020-05-19 Tcl华星光电技术有限公司 Pixel structure and pixel circuit

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101975263B1 (en) * 2012-02-07 2019-05-08 삼성디스플레이 주식회사 Thin film transistor display panel and method of manufacturing the same
US10541255B2 (en) * 2017-04-05 2020-01-21 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Array substrate having sub-pixels including main region pixel electrode and secondary region pixel electrode that have branch electrodes and slits having different widths
CN110174787B (en) * 2019-05-06 2021-11-30 惠科股份有限公司 Array substrate, manufacturing method thereof and display device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100237350A1 (en) * 2007-06-07 2010-09-23 Chunghwa Picture Tubes, Ltd. Pixel structure
CN104122724A (en) * 2014-07-04 2014-10-29 深圳市华星光电技术有限公司 Low-color-error liquid crystal array substrate and drive method thereof
CN104865763A (en) * 2015-06-12 2015-08-26 深圳市华星光电技术有限公司 Array substrate
CN105807520A (en) * 2016-05-20 2016-07-27 深圳市华星光电技术有限公司 3t pixel structure and liquid crystal display device
CN111176041A (en) * 2020-02-21 2020-05-19 Tcl华星光电技术有限公司 Pixel structure and pixel circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114815423A (en) * 2022-04-29 2022-07-29 苏州华星光电技术有限公司 Display panel manufacturing method
CN114815423B (en) * 2022-04-29 2023-12-15 苏州华星光电技术有限公司 Display panel manufacturing method

Also Published As

Publication number Publication date
CN112068371A (en) 2020-12-11

Similar Documents

Publication Publication Date Title
WO2022052242A1 (en) Array substrate and display panel
CN111474758B (en) Display panel and display device
CN101308294B (en) In-plane switching mode liquid crystal display device and manufacture method thereof
CN103915448B (en) Thin-film transistor display panel
CN111176041A (en) Pixel structure and pixel circuit
CN1573488B (en) Liquid crystal display and thin film transistor array panel therefor
CN113311624A (en) Array substrate and display panel
KR101622655B1 (en) Liquid crystal display device and method of fabricating the same
KR20120134245A (en) Thin film transistor substrate and method of fabricating the same
US8189130B2 (en) Array substrate, liquid crystal display panel and method for manufacturing the same
CN111580316B (en) Display panel and electronic device
CN111221189B (en) Pixel structure, array substrate and display panel
WO2022193337A1 (en) Array substrate and display panel
CN112748616A (en) Array substrate, manufacturing method of array substrate, display panel and display device
US20210080791A1 (en) Display device and display panel thereof, and manufacturing method for display device
US20220293708A1 (en) Display substrate, method for manufacturing display substrate, and display device
KR20100063184A (en) Liquid crystal display device and manufacturing method thereof
US5734448A (en) LCD having a capacitor with two lower capacitor electrodes and a reflective pixel electrode serving as an upper electrode
WO2013037236A1 (en) Array substrate and liquid crystal display panel
US8941804B2 (en) Liquid crystal display device
US9841639B2 (en) Touch display panel and fabrication method thereof, and display device
CN107678220B (en) Display panel and display device
US20210286224A1 (en) Display panel
US20210405470A1 (en) Liquid crystal display panel and display device
KR20130060603A (en) Array substrate for fringe field switching mode liquid crystal display device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20953027

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20953027

Country of ref document: EP

Kind code of ref document: A1