CN114153098A

CN114153098A - First substrate, display panel, liquid crystal display and display device

Info

Publication number: CN114153098A
Application number: CN202111453078.5A
Authority: CN
Inventors: 廖凯; 李荣荣
Original assignee: HKC Co Ltd
Current assignee: HKC Co Ltd
Priority date: 2021-11-30
Filing date: 2021-11-30
Publication date: 2022-03-08

Abstract

The application provides a first substrate, a display panel comprising the first substrate, a liquid crystal display and a display device. The first substrate is provided with the shared electrode which is positioned on the same metal layer with the data line and is close to the data line, so that the coupling capacitance between the data line and the pixel electrode is reduced, and the vertical crosstalk phenomenon of the display panel is improved.

Description

First substrate, display panel, liquid crystal display and display device

Technical Field

The present application relates to the field of display technologies, and in particular, to a first substrate, a display panel, a liquid crystal display, and a display device.

Background

A Liquid Crystal Display (LCD) generally includes a Display panel and a backlight module. The lcd needs to emit light normally by the light source provided by the backlight module. Generally, a display panel is formed by bonding two glass substrates, liquid crystal is filled between the two glass substrates, a pixel electrode layer and a common electrode layer are respectively arranged on the opposite inner sides of the two glass substrates, the rotation direction of liquid crystal molecules is controlled by using voltage field intensity, and light of a backlight module is refracted to generate a picture.

In the existing display panel, vertical crosstalk is a common bad phenomenon, and the brightness of the display screen is easy to be abnormal.

Disclosure of Invention

In a first aspect, the present application provides a first substrate, including a plurality of sub-pixels arranged in an array, each sub-pixel all includes main area and subregion, each row the sub-pixel corresponds sets up a data line, each row the sub-pixel corresponds sets up a scanning line, the scanning line is located between main area and the subregion.

The first substrate further comprises a main pixel electrode and a secondary pixel electrode which are arranged on the same layer, the main pixel electrode is located in the main area, the secondary pixel electrode is located in the secondary area, and the main pixel electrode and the secondary pixel electrode are both located on the upper layer of the data lines and located between two adjacent data lines.

The first substrate further comprises a shared electrode, the shared electrode and the data line are arranged on the same layer, the shared electrode comprises a first section and a third section, the first section is located below one side, close to the data line, of the main pixel electrode, and the third section is located below one side, close to the data line, of the sub pixel electrode.

The shared electrode further comprises a second segment and a fourth segment, the second segment is positioned below one side of the main pixel electrode close to the other data line, and the fourth segment is positioned below one side of the sub pixel electrode close to the other data line.

The first substrate further comprises a common electrode, the common electrode is located on the lower layer of the data line and the lower layer of the shared electrode, the common electrode comprises a first branch and a second branch, the first branch is located below the middle of the main pixel electrode, and the second branch is located below the middle of the sub-pixel electrode.

The first substrate further comprises a common electrode, the common electrode is located on the lower layer of the data line and the shared electrode, the common electrode comprises a first branch and a third branch, the first branch is located below the first section, and the third branch is located below the third section.

The width of the first branch is larger than that of the first section.

The first substrate further comprises a common electrode, the common electrode is located on the lower layer of the data line and the lower layer of the shared electrode, the common electrode comprises a first branch, a second branch, a third branch and a fourth branch, the first branch and the second branch are respectively located below the first section and the second section, and the third branch and the fourth branch are respectively located below the third section and the fourth section.

The first substrate further comprises a main thin film transistor, a secondary thin film transistor and a shared thin film transistor.

The source electrode of the main thin film transistor is electrically connected with the data line, the grid electrode of the main thin film transistor is electrically connected with the scanning line, and the drain electrode of the main thin film transistor is electrically connected with the main pixel electrode.

The source electrode of the secondary thin film transistor is electrically connected with the data line, the grid electrode of the secondary thin film transistor is electrically connected with the scanning line, and the drain electrode of the secondary thin film transistor is electrically connected with the secondary pixel electrode.

The grid electrode of the shared thin film transistor is electrically connected with the scanning line, the source electrode of the shared thin film transistor is electrically connected with the shared electrode, and the drain electrode of the shared thin film transistor is electrically connected with the sub-pixel electrode.

In a second aspect, the present application further provides a display panel, including any one of the first substrate, the second substrate, and the liquid crystal layer, where the second substrate is disposed opposite to the first substrate, and the liquid crystal layer is disposed between the second substrate and the first substrate.

The first substrate comprises a color resistance layer, and the color resistance layer is positioned on the upper layer of the shared electrode of the first substrate and positioned on the lower layer of the main pixel electrode and the sub pixel electrode of the first substrate.

In a third aspect, the present application further provides a display device, including any one of the display panel and the backlight module, where the display panel is located on a light emitting side of the backlight module.

In the present application, since the first segment, the second segment, the third segment, and the fourth segment of the common electrode are disposed close to the adjacent data lines, the multi-segment structure of the common electrode can form a coupling capacitance together with the adjacent data lines. Since the data line and the shared electrode are disposed in the same layer and are formed of metals in the same layer, compared with the case where the data line and the shared electrode are formed of metals in different layers, in this embodiment, the coupling capacitance generated between the data line and the shared electrode is large, and the coupling capacitance generated between the data line and the shared electrode can cancel the coupling capacitance generated between the pixel electrode and the data line to some extent, so that the coupling capacitance generated between the pixel electrode and the data line is reduced.

The main reason for the vertical crosstalk of the display panel is that the coupling capacitance between the pixel electrode and the data line is too large, and the potential of the pixel point is affected by the data signal, so that the brightness is changed. In addition, the routing arrangement scheme in this embodiment can also ensure that the display panel has a higher pixel aperture ratio.

Drawings

Fig. 1 is a schematic structural diagram of a first substrate provided in the present application;

FIG. 2 is a schematic view of a sub-pixel of the first substrate of FIG. 1 in one embodiment;

FIG. 3 is a schematic cross-sectional view of the sub-pixel of FIG. 2 taken along line A-A;

FIG. 4 is a schematic cross-sectional view of the sub-pixel of FIG. 2 taken along line B-B;

FIG. 5 is a circuit schematic of the sub-pixel of FIG. 2;

FIG. 6 is a schematic view of a sub-pixel of the first substrate shown in FIG. 1 in another embodiment;

FIG. 7 is a schematic cross-sectional view of the sub-pixel of FIG. 6 taken along line C-C;

FIG. 8 is a schematic cross-sectional view of the sub-pixel of FIG. 6 taken along line D-D;

fig. 9 is a schematic structural diagram of a display panel provided in the present application;

fig. 10 is a schematic structural diagram of a display device provided in the present application.

Description of the reference numerals

1, a sub-pixel; 2, a data line; 3, scanning lines; 4, a pixel electrode; 4a, a main pixel electrode; 4b, a sub-pixel electrode; 5, sharing an electrode; 6, a common electrode; 7, a main thin film transistor; 8, a sub-thin film transistor; 9, sharing a thin film transistor; 11, a primary zone; 12, a secondary zone; 21, a lower glass substrate; 22, a first insulating layer; 23, a second insulating layer; 51, a first portion; 51a, a first segment; 51b, a second segment; 52, a second portion; 52a, a third segment; 52b, fourth segment; 53, a connecting portion; 61, a first branch; 62, a second branch; 63, a first branch; 64, a second branch; 65, third branch; 66, a fourth branch; 100, a first substrate; 110, a first substrate; 120, a second substrate; 130, a liquid crystal layer; 200, a display panel; 210, a backlight module; 300, a display device.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings. In the description of the embodiments of the present application, "a plurality" means two or more. In addition, "and/or" in the text is only an association relationship describing an association object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone.

The terms "first", "second", and the like are used hereinafter for descriptive purposes only and are not to be construed as implying or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

The directional terms used in the embodiments of the present application, such as "upper", "lower", and the like, are used solely in reference to the orientation of the drawings, and thus are used for better and clearer illustration and understanding of the embodiments of the present application, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be considered limiting of the embodiments of the present application.

In the description of the embodiments of the present application, it should be noted that the terms "connected" and "disposed" are to be interpreted broadly, unless explicitly stated or limited otherwise, and for example, "connected" may or may not be detachably connected; may be directly connected or indirectly connected through an intermediate.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a first substrate 100 provided in the present application.

In this embodiment, the first substrate 100 may be applied to a display panel. The first substrate 100 includes a plurality of sub-pixels 1 arranged in an array, and each sub-pixel 1 includes a main region 11 and a sub-region 12. The sub-pixel 1 may be designed in eight domains, and the main region 11 and the sub-region 12 are respectively designed in four domains, so as to improve the viewing angle of the display panel. Each column of sub-pixels 1 is correspondingly provided with a data line 2, each row of sub-pixels 1 is correspondingly provided with a scanning line 3, and the scanning line 3 is positioned between the main area 11 and the sub-area 12. The scanning lines 3 may also be referred to as gate lines.

Referring to fig. 2 to 4, fig. 2 is a schematic structural diagram of a sub-pixel 1 of the first substrate 100 shown in fig. 1 in an embodiment, fig. 3 is a schematic cross-sectional structure of the sub-pixel 1 shown in fig. 2 taken along a-a, and fig. 4 is a schematic cross-sectional structure of the sub-pixel 1 shown in fig. 2 taken along B-B. Fig. 3 and 4 each show only a partial layer structure of the sub-pixel 1.

In this embodiment, the first substrate 100 further includes a pixel electrode 4, a common electrode 5, and a common electrode 6. The pixel electrode 4 includes a main pixel electrode 4a and a sub-pixel electrode 4b disposed on the same layer, the main pixel electrode 4a is located in the main area 11, the sub-pixel electrode 4b is located in the sub-area 12, and the main pixel electrode 4a and the sub-pixel electrode 4b are both located on the upper layer of the data line 2 and located between two adjacent data lines 2. The main pixel electrode 4a and the sub-pixel electrode 4b may be made of a transparent metal oxide, such as Indium Tin Oxide (ITO).

It will be appreciated that the first substrate 100 is typically formed by stacking a plurality of layers, with the first layer being a lower layer and the second layer being an upper layer, typically on the side of the lower layer remote from the substrate. For example, the first substrate 100 may include a lower glass substrate 21, a first metal layer, a first insulating layer 22, a second metal layer, a second insulating layer 23, and a third metal layer from bottom to top. The common electrode 6 is formed on the first metal layer, the common electrode 5 and the data line 2 are formed on the second metal layer, and the pixel electrode 4 is formed on the third metal layer. In the present application, "the main pixel electrode 4a and the sub-pixel electrode 4b are both located at the upper layer of the data line 2" does not mean that the main pixel electrode 4a and the sub-pixel electrode 4b can only be adjacent to the data line 2, and may also be a case where another spacer layer is present between the two. The remaining descriptions in this application relating to "upper layer" and "lower layer" should be understood as such.

The common electrode 5 is disposed on the same layer as the data line 2, and the common electrode 5 includes a first portion 51, a second portion 52, and a connecting portion 53. In fig. 2, in order to highlight the position of the common electrode 5, a filling pattern is added in the area where the common electrode 5 is located for illustration.

The first portion 51 is located in the main region 11 and includes a first segment 51a and a second segment 51b arranged at an interval, the first segment 51a is located below a side of the main pixel electrode 4a close to the data line 2, and the second segment 51b is located below a side of the main pixel electrode 4a close to the other data line 2. The second portion 52 is located in the sub-region 12 and includes a third segment 52a and a fourth segment 52b which are spaced apart, the third segment 52a is located below a side of the sub-pixel electrode 4b close to the data line 2, and the fourth segment 52b is located below a side of the sub-pixel electrode 4b close to the other data line 2. The connecting portion 53 connects the first portion 51 and the second portion 52. In other embodiments, the shared electrode 5 may not be provided with the second segment 51b and/or the fourth segment 52 b.

Wherein, the common electrode 6 is positioned at the lower layer of the data line 2 and the shared electrode 5. The common electrode 6 includes a first branch 61 and a second branch 62; the first branch 61 may be located in the main region 11, the first branch 61 being located below the middle of the main pixel electrode 4 a; the second branch 62 may be located in the sub-region 12, and the second branch 62 is located below the middle of the sub-pixel electrode 4 b. The first and/or

second branches

61, 62 may be parallel to the data line 2. The common electrode 6 may also have other branches, which are not described herein.

The side of the main pixel electrode 4a close to the data line 2 and the side of the main pixel electrode 4a close to the other data line 2 are opposite sides of the main pixel electrode 4a, and the middle of the main pixel electrode 4a is a central area of the main pixel electrode 4a relative to the two sides. The side of the sub-pixel electrode 4b close to the data line 2 and the side of the sub-pixel electrode 4b close to the other data line 2 are opposite sides of the sub-pixel electrode 4b, and the middle of the sub-pixel electrode 4b is the central area of the sub-pixel electrode 4b relative to the two sides.

In the present embodiment, since the first segment 51a, the second segment 51b, the third segment 52a, and the fourth segment 52b of the common electrode 5 are disposed close to the adjacent data lines 2, the multi-segment structure of the common electrode 5 can form a coupling capacitance together with the adjacent data lines 2. Since the data line 2 and the common electrode 5 are disposed in the same layer and are formed of the same layer of metal, compared with the case where the data line 2 and the common electrode 5 are formed of different layers of metal, in this embodiment, the coupling capacitance generated between the data line 2 and the common electrode 5 is relatively large, and the coupling capacitance generated between the data line 2 and the common electrode 5 can cancel the coupling capacitance generated between the pixel electrode 4 and the data line 2 to some extent, so that the coupling capacitance generated between the pixel electrode 4 and the data line 2 is reduced.

Since the main reason for the vertical crosstalk of the display panel is that the coupling capacitance (Cpd) between the pixel electrode and the data line is too large, and the potential of the pixel is affected by the data signal, so that the luminance variation is generated, the first substrate 100 of this embodiment can effectively improve the vertical crosstalk of the display panel by reducing the coupling capacitance generated between the pixel electrode 4 and the data line 2, and improve the display effect of the display panel. In addition, the routing arrangement scheme in this embodiment can also ensure that the display panel has a higher pixel aperture ratio.

It should be understood that in fig. 2, in order to better illustrate the positional relationship of the main pixel electrode 4a, the sub-pixel electrode 4b, the data line 2, the shared electrode 5 and the common electrode 6, the positions of the partial line segments are finely adjusted, and the figure does not constitute a limitation on specific positions of the main pixel electrode 4a, the sub-pixel electrode 4b, the data line 2, the shared electrode 5 and the common electrode 6. Fig. 3 and 4 are mainly used to illustrate the relative position relationship between the main pixel electrode 4a, the sub-pixel electrode 4b, the data line 2, the shared electrode 5 and the common electrode 6, and the specific hierarchical structure of the first substrate 100 is not limited in this application.

Referring to fig. 2 and 5 in combination, fig. 5 is a schematic circuit diagram of the sub-pixel 1 shown in fig. 2.

In this embodiment, the sub-pixel 1 may be a three-transistor design. Illustratively, the sub-pixel 1 further includes a main thin film transistor 7, a sub-thin film transistor 8, and a shared thin film transistor 9. The source of the main thin film transistor 7 is electrically connected to the data line 2, the gate of the main thin film transistor 7 is electrically connected to the scan line 3, and the drain of the main thin film transistor 7 is electrically connected to the main pixel electrode 4 a. The source of the sub-thin film transistor 8 is electrically connected to the data line 2, the gate of the sub-thin film transistor 8 is electrically connected to the scan line 3, and the drain of the sub-thin film transistor 8 is electrically connected to the sub-pixel electrode 4 b. The gate of the shared thin film transistor 9 is electrically connected to the scanning line 3, the source of the shared thin film transistor 9 is electrically connected to the shared electrode 5, and the drain of the shared thin film transistor 9 is electrically connected to the sub-pixel electrode 4 b.

In this embodiment, the common electrode 5 can input a common voltage to the sub-pixel electrode 4b through the common thin film transistor 9 connected thereto to adjust the charging rate of the sub-region 12, so that the main region 11 and the sub-region 12 have different charging rates, thereby improving the color richness of the display panel.

Referring to fig. 6 to 8, fig. 6 is a schematic structural diagram of a sub-pixel 1 of the first substrate 100 shown in fig. 1 in another embodiment, fig. 7 is a schematic cross-sectional structure of the sub-pixel 1 shown in fig. 6 taken along a line C-C, and fig. 8 is a schematic cross-sectional structure of the sub-pixel 1 shown in fig. 6 taken along a line D-D. Fig. 7 and 8 each show only a partial layer structure of the sub-pixel 1.

In this embodiment, the first substrate 100 further includes a pixel electrode 4, a common electrode 5, and a common electrode 6. The pixel electrode 4 includes a main pixel electrode 4a and a sub-pixel electrode 4b disposed on the same layer, the main pixel electrode 4a is located in the main area 11, the sub-pixel electrode 4b is located in the sub-area 12, and the main pixel electrode 4a and the sub-pixel electrode 4b are both located on the upper layer of the data line 2 and located between two adjacent data lines 2. The main pixel electrode 4a and the sub pixel electrode 4b may be made of a transparent metal oxide, for example, indium tin oxide.

It will be appreciated that the first substrate 100 is typically formed by stacking a plurality of layers, with the first layer being a lower layer and the second layer being an upper layer, typically on the side of the lower layer remote from the substrate. For example, the first substrate 100 may include a lower glass substrate 21, a first metal layer, a first insulating layer 22, a second metal layer, a second insulating layer 23, and a third metal layer from bottom to top. The common electrode 6 is formed on the first metal layer, the common electrode 5 and the data line 2 are formed on the second metal layer, and the pixel electrode 4 is formed on the third metal layer.

The common electrode 5 is disposed on the same layer as the data line 2, and the common electrode 5 includes a first portion 51, a second portion 52, and a connecting portion 53. In fig. 6, in order to highlight the position of the common electrode 5, a filling pattern is added in the area where the common electrode 5 is located for illustration.

The sub-pixel 1 of the present embodiment is different from the sub-pixel 1 shown in fig. 2 in that: the common electrode 6 is positioned at the lower layer of the data line 2 and the shared electrode 5, and the common electrode 6 comprises a first branch 63, a second branch 64, a third branch 65 and a fourth branch 66; the first and

second branches

63, 64 may be located in the main zone 11, the first and

second branches

63, 64 being located below the first and

second sections

51a, 51b, respectively; third and

fourth branches

65, 66 may be located in secondary zone 12, with third and

fourth branches

65, 66 located below third and

fourth segments

52a, 52b, respectively. The first branch 63 and/or the second branch 64 may be parallel to the data line 2; the third and/or

fourth branches

65, 66 may be parallel to the data line 2. In other embodiments, the common electrode 6 may not be provided with the second and/or

fourth branches

64 and 66. The common electrode 6 may also have other branches, which are not described herein.

It is to be understood that the sub-pixel 1 of the present embodiment is substantially the same as the sub-pixel 1 shown in fig. 2 in terms of the configuration, circuit principle, and the like, except for the above-described differences, and a partially overlapping description will be omitted here.

One side of the main pixel electrode 4a close to the data line 2 and one side of the main pixel electrode 4a close to the other data line 2 are two sides of the main pixel electrode 4a which are oppositely arranged. The side of the sub-pixel electrode 4b close to the data line 2 and the side of the sub-pixel electrode 4b close to the other data line 2 are the two sides of the sub-pixel electrode 4b which are oppositely arranged.

In the present embodiment, since the first segment 51a, the second segment 51b, the third segment 52a, and the fourth segment 52b of the common electrode 5 are disposed close to the adjacent data lines 2, the multi-segment structure of the common electrode 5 can form a coupling capacitance together with the adjacent data lines 2.

Because the data line 2 and the common electrode 5 are disposed on the same layer and are metal on the same layer, compared with the case where the data line 2 and the common electrode 5 are metal on different layers, in this embodiment, the coupling capacitance generated between the data line 2 and the common electrode 5 is relatively large, and the coupling capacitance generated between the data line 2 and the common electrode 5 can be offset with the coupling capacitance generated between the pixel electrode 4 and the data line 2 to some extent, so that the coupling capacitance generated between the pixel electrode 4 and the data line 2 is reduced, thereby effectively improving the vertical crosstalk phenomenon of the display panel and improving the display effect of the display panel.

In addition, since the first, second, third, and

fourth branches

63, 64, 65, and 66 of the common electrode 6 are respectively located below the first, second, third, and

fourth segments

51a, 51b, 52a, and 52b of the common electrode 5, the first, second, third, and

fourth branches

63, 64, 65, and 66 of the common electrode are also disposed close to the data line 2, and the multi-segment structure of the common electrode 6 can form a coupling capacitance together with the data line 2.

In this embodiment, the coupling capacitance generated between the data line 2 and the common electrode 6 may also cancel the coupling capacitance generated between the pixel electrode 4 and the data line 2 to a certain extent, so as to reduce the coupling capacitance generated between the pixel electrode 4 and the data line 2, thereby effectively improving the vertical crosstalk phenomenon of the display panel. In this embodiment, the coupling capacitance generated between the data line 2 and the common electrode 5 and the coupling capacitance generated between the data line 2 and the common electrode 6 cancel the coupling capacitance generated between the pixel electrode 4 and the data line 2 together, so that the effect of improving the vertical crosstalk is better.

In this embodiment, the trace width of the first branch 63 may be greater than the trace width of the first segment 51 a. In addition, the track width of the second branch 64 is greater than that of the second section 51b, the track width of the third branch 65 is greater than that of the third section 52a, and the track width of the fourth branch 66 is greater than that of the fourth section 52 b.

In this embodiment, since the plurality of branches (63/64/65/66) of the common electrode 6 are respectively located below the plurality of segments of traces (51a/51b/52a/52b) of the common electrode 5, the trace width of the plurality of branches (63/64/65/66) of the common electrode 6 is increased, so that the trace width of the plurality of branches of the common electrode 6 is greater than the trace width of the plurality of segments of traces (51a/51b/52a/52b) of the common electrode 5, thereby reducing the risk of wire breakage of the plurality of segments of traces (51a/51b/52a/52b) of the common electrode 5.

It should be understood that in fig. 6, in order to better illustrate the positional relationship of the main pixel electrode 4a, the sub-pixel electrode 4b, the data line 2, the shared electrode 5 and the common electrode 6, the positions of the partial line segments are finely adjusted, and the figure does not constitute a limitation on specific positions of the main pixel electrode 4a, the sub-pixel electrode 4b, the data line 2, the shared electrode 5 and the common electrode 6. Fig. 7 and 8 are mainly used to illustrate the relative position relationship between the main pixel electrode 4a, the sub-pixel electrode 4b, the data line 2, the shared electrode 5 and the common electrode 6, and the specific hierarchical structure of the first substrate 100 is not limited in the present application.

Referring to fig. 9, fig. 9 is a schematic structural diagram of a display panel 200 according to the present application.

The present application further provides a display panel 200, the display panel 200 may include a first substrate 110, a second substrate 120 and a liquid crystal layer 130, the second substrate 120 is disposed opposite to the first substrate 110, and the liquid crystal layer 130 is disposed between the second substrate 120 and the first substrate 110. The first substrate 110 may include the above-mentioned structure of the first substrate 100.

Among them, the display panel 200 may adopt a Vertical Alignment (VA) display mode.

For example, the second substrate 120 may include a common electrode layer for forming a voltage difference with the main pixel electrode and the sub pixel electrode of the first substrate 110 to control the turning of the liquid crystal in the liquid crystal layer 130. The second substrate 120 may further include an upper glass substrate and a Black Matrix (BM) layer.

For example, the first substrate 110 may further include a color resistance layer on the upper layer of the common electrode and on the lower layer of the main pixel electrode and the sub-pixel electrode. Illustratively, the color resist layer may include a red color resist block, a green color resist block, a blue color resist block, and the like. In other embodiments, the color resist layer may also be located on the second substrate 120.

Referring to fig. 10, fig. 10 is a schematic structural diagram of a display device 300 provided in the present application.

The present application further provides a display device 300, the display device 300 includes the above mentioned display panel 200 and the backlight module 210, and the display panel 200 is located at the light emitting side of the backlight module 210.

The present application also provides a display apparatus including the above-mentioned display device 300. The display device can be an electronic product such as a mobile phone, a tablet computer, a notebook computer, a wearable device, a camera and the like.

The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A first substrate comprises a plurality of sub-pixels arranged in an array, each sub-pixel comprises a main area and a sub-area, each column of sub-pixels is correspondingly provided with a data line, each row of sub-pixels is correspondingly provided with a scanning line, the scanning line is positioned between the main area and the sub-area, the first substrate further comprises a main pixel electrode and a sub-pixel electrode which are arranged on the same layer, the main pixel electrode is positioned in the main area, the sub-pixel electrode is positioned in the sub-area, the main pixel electrode and the sub-pixel electrode are both positioned on the upper layer of the data line and positioned between two adjacent data lines,

2. The first substrate according to claim 1, wherein the common electrode further comprises a second segment and a fourth segment, the second segment is located below a side of the main pixel electrode close to another one of the data lines, and the fourth segment is located below a side of the sub pixel electrode close to another one of the data lines.

3. The first substrate according to claim 1 or 2, further comprising a common electrode underlying the data line and the common electrode, wherein the common electrode comprises a first branch and a second branch, the first branch is located below a middle portion of the main pixel electrode, and the second branch is located below a middle portion of the sub-pixel electrode.

4. The first substrate according to claim 1 or 2, further comprising a common electrode, wherein the common electrode is located at a lower layer of the data line and the common electrode, the common electrode comprises a first branch and a third branch, the first branch is located below the first segment, and the third branch is located below the third segment.

5. The first substrate of claim 4, wherein the first branch has a trace width greater than a trace width of the first segment.

6. The first substrate according to claim 2, further comprising a common electrode, wherein the common electrode is located at a lower layer of the data line and the common electrode, the common electrode comprises a first branch, a second branch, a third branch and a fourth branch, the first branch and the second branch are respectively located below the first segment and the second segment, and the third branch and the fourth branch are respectively located below the third segment and the fourth segment.

7. The first substrate according to claim 1 or 2, wherein the first substrate further comprises a main thin film transistor, a sub thin film transistor, and a shared thin film transistor;

the source electrode of the main thin film transistor is electrically connected with the data line, the grid electrode of the main thin film transistor is electrically connected with the scanning line, and the drain electrode of the main thin film transistor is electrically connected with the main pixel electrode;

the source electrode of the secondary thin film transistor is electrically connected with the data line, the grid electrode of the secondary thin film transistor is electrically connected with the scanning line, and the drain electrode of the secondary thin film transistor is electrically connected with the secondary pixel electrode;

8. A display panel comprising the first substrate, the second substrate and the liquid crystal layer of claims 1 to 7, wherein the second substrate is disposed opposite to the first substrate, and the liquid crystal layer is disposed between the second substrate and the first substrate.

9. The display panel according to claim 8, wherein the first substrate comprises a color resist layer on an upper layer of the common electrode of the first substrate and on a lower layer of the main pixel electrode and the sub pixel electrode of the first substrate.

10. A display device comprising the display panel of claim 8 or 9 and a backlight module, wherein the display panel is located at a light-emitting side of the backlight module.