CN112068371A - Array substrate and display panel - Google Patents
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- CN112068371A CN112068371A CN202010944769.4A CN202010944769A CN112068371A CN 112068371 A CN112068371 A CN 112068371A CN 202010944769 A CN202010944769 A CN 202010944769A CN 112068371 A CN112068371 A CN 112068371A
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- 239000010410 layer Substances 0.000 claims abstract description 53
- 239000010409 thin film Substances 0.000 claims abstract description 50
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- 238000000034 method Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 239000012780 transparent material Substances 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
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- 229920006254 polymer film Polymers 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/40—Arrangements for improving the aperture ratio
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- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Computer Hardware Design (AREA)
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Abstract
The application provides an array substrate and a display panel, wherein the array substrate comprises a plurality of sub-pixels, and each sub-pixel comprises a main area thin film transistor, a sub-area thin film transistor and a shared thin film transistor. The sub-pixel comprises a main area and a sub-area, a main pixel electrode is arranged corresponding to the main area, a sub-pixel electrode is arranged corresponding to the sub-area, and the sub-pixel further comprises a common electrode which is arranged in a different layer with the main pixel electrode and the sub-pixel electrode. The main area thin film transistor is electrically connected with the main pixel electrode through a first through hole, the secondary area thin film transistor is electrically connected with the secondary pixel electrode through a second through hole, and the shared thin film transistor is electrically connected with the common electrode through a third through hole; and the aperture of the third via hole is smaller than the apertures of the first via hole and the second via hole. This application changes the third via hole that originally runs through organic protective layer into and runs through the gate insulation layer to reduce the aperture of third via hole, and then improve the aperture opening ratio and the penetration rate of pixel.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate and a display panel.
Background
As the size of the panel is larger and larger, the backlight is also larger and larger, which means that the heat generated by the backlight is increased, and the luminance of the backlight can be reduced by increasing the transmittance of the panel, so as to effectively avoid the heat generation phenomenon, that is, to increase the aperture ratio of the pixels (pixels), and it is particularly necessary to increase the transmittance of the panel accordingly. The large size and high resolution mean that the size of pixels becomes smaller and smaller, and the open area becomes smaller. And the requirements for color shift are higher and higher, for VA products, 8-domain display is usually adopted, that is, a so-called 3T or 3T plus structure is usually adopted, which means that more space is occupied and at the same time a part of the opening area is sacrificed accordingly. However, it is difficult to increase the transmittance of high-resolution, large-size and high-specification products.
Therefore, the prior art has defects which need to be solved urgently.
Disclosure of Invention
The application provides an array substrate and a display panel, which can improve the pixel aperture opening ratio of a high-resolution large-size product, thereby improving the penetration rate to solve the problem of serious heat generation of large-size backlight.
In order to solve the above problems, the technical solution provided by the present application is as follows:
the application provides an array substrate, which comprises sub-pixels distributed in an array, wherein each sub-pixel comprises a main area thin film transistor, a sub-area thin film transistor and a shared thin film transistor;
the sub-pixels comprise a main area and a sub-area, main pixel electrodes are arranged corresponding to the main area, sub-pixel electrodes are arranged corresponding to the sub-area, and the sub-pixels further comprise common electrodes which are arranged in different layers with the main pixel electrodes and the sub-pixel electrodes;
the main area thin film transistor is electrically connected with the main pixel electrode through a first through hole, the secondary area thin film transistor is electrically connected with the secondary pixel electrode through a second through hole, and the shared thin film transistor is electrically connected with the common electrode through a third through hole;
wherein the aperture of the third via is smaller than the apertures of the first and second vias.
In the array substrate of the present application, the array substrate includes:
a substrate;
the grid is arranged on the substrate;
a gate insulating layer disposed on the gate electrode;
an active layer disposed on the gate insulating layer corresponding to the gate electrode;
the source/drain electrodes are arranged at two ends of the active layer and are in contact with the ion doping regions of the active layer;
an organic protective layer disposed on the source/drain electrode;
the pixel electrode layer is arranged on the organic protective layer and comprises the main pixel electrode and the sub pixel electrode;
the common electrode and the grid electrode are arranged on the same layer, the first through hole and the second through hole penetrate through the organic protective layer, and the third through hole penetrates through the grid electrode insulating layer.
In the array substrate of the application, one the sub-pixels are correspondingly provided with a first source electrode, a second source electrode, a first drain electrode and a second drain electrode, wherein the main area thin film transistor and the sub area thin film transistor share the first source electrode, and the sub area thin film transistor and the shared thin film transistor share the second drain electrode.
In the array substrate of this application, same the sub-pixel the main district with including the non-display area between the subregion, main district thin film transistor the subregion thin film transistor and sharing thin film transistor correspondence is located in the non-display area, wherein, first via hole at least some is located in the main district, second via hole at least some is located in the subregion.
In the array substrate of the present application, a projection range of the main pixel electrode on the array substrate at least partially covers a projection range of the first via hole on the array substrate, and a projection range of the sub pixel electrode on the array substrate at least partially covers a projection range of the second via hole on the array substrate.
In the array substrate of the present application, the main pixel electrode and the sub-pixel electrode each include a trunk electrode and a branch electrode, and the first via hole and the second via hole are correspondingly located at the trunk electrode.
In the array substrate, the first via hole and the second via hole are symmetrically arranged along a center line of the non-display area.
In the array substrate, at least a part of the third via hole is located in the sub-region.
In the array substrate of the present application, the projection range of the main pixel electrode and the sub-pixel electrode on the array substrate at least partially covers the projection range of the common electrode on the array substrate.
In order to solve the above problem, the present application further provides a display panel including the array substrate as described above.
The beneficial effect of this application does: the application provides an array substrate, display panel, its every sub-pixel includes main district thin film transistor, subregion thin film transistor and sharing thin film transistor, and main district thin film transistor is connected with main pixel electrode electricity through first via hole, and subregion thin film transistor is connected with subpixel electrode electricity through second via hole, and sharing thin film transistor is connected with common electrode electricity through the third via hole. This application changes the third via hole that originally runs through organic protective layer into and runs through the gate insulation layer to reduce the aperture of third via hole, and then improve the aperture opening ratio and the penetration rate of pixel, consequently alright solve the great technical problem of heat in a poor light.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a sub-pixel on a conventional array substrate;
fig. 2 is a schematic structural diagram of a sub-pixel on an array substrate according to an embodiment of the present disclosure;
fig. 3 is a schematic cross-sectional view of an array substrate along first/second vias according to an embodiment of the present application;
fig. 4 is a schematic cross-sectional view of an array substrate along a third via according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a sub-pixel on an array substrate according to a second embodiment of the present application;
fig. 6 is a schematic structural diagram of a sub-pixel on an array substrate according to a third embodiment of the present application;
fig. 7 is a schematic structural diagram of a display panel provided in the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "longitudinal," "lateral," "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," and the like are used in the orientation or positional relationship indicated in the drawings, which are based on the orientation or positional relationship shown in the drawings, and are used merely for convenience of description and for simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and therefore should not be considered as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise. In this application, "/" means "or".
The present application may repeat reference numerals and/or letters in the various examples, which have been repeated for purposes of simplicity and clarity and do not in themselves dictate a relationship between the various embodiments and/or arrangements discussed.
The array substrate of the present application is described in detail with reference to the following embodiments.
Example one
As shown in fig. 2, the array substrate of the present application includes sub-pixels distributed in an array, and for convenience of description, only one sub-pixel is illustrated in fig. 2. Each of the sub-pixels includes a main region thin film transistor T1, a sub-region thin film transistor T2, and a shared thin film transistor T3. Each of the sub-pixels includes a main region 10 and a sub-region 20, a non-display region is included between the main region 10 and the sub-region 20 of the same sub-pixel, and the main region thin film transistor T1, the sub-region thin film transistor T2 and the shared thin film transistor T3 are correspondingly located in the non-display region. A gate line 30 is disposed corresponding to each row of the sub-pixels, the gate line 30 is located between the main area 10 and the sub-area 20, a data line 40 is disposed corresponding to each column of the sub-pixels, and two adjacent data lines 40 define a pixel boundary. The sub-pixel is provided with a main pixel electrode 601 corresponding to the main area 10, a sub-pixel electrode 602 corresponding to the sub-area 20, and the sub-pixel further includes a common electrode 50 arranged in a different layer from the main pixel electrode 601 and the sub-pixel electrode 602.
As shown in fig. 3 and 4, the array substrate includes: a substrate 101; a gate 102 disposed on the substrate 101; a gate insulating layer 103 disposed on the gate electrode 102; an active layer 104 disposed on the gate insulating layer 103 corresponding to the gate electrode 102; source/drain electrodes 105 disposed at both ends of the active layer 104 and contacting the ion-doped regions of the active layer 104; an organic protection layer 106 disposed on the source/drain electrode 105; and pixel electrode layers (601,602) arranged on the organic protective layer 106 and including the main pixel electrode and the sub-pixel electrode.
The structure disposed on the same layer as the gate electrode 102 further includes the gate line 30, the common electrode 50, and other conventional structures, and the gate electrode 102, the gate line 30, and the common electrode 50 may be formed simultaneously from the same material through the same mask process.
The structure disposed on the same layer as the source/drain electrode 105 also includes the data line 40, and other conventional structures, etc., and the source/drain electrode 105 and the data line 40 may be formed simultaneously by the same material through the same mask process.
It should be noted that, in this embodiment, the array substrate with the bottom gate structure is taken as an example, but in other embodiments, the array substrate may also be a top gate structure, and this is not limited herein.
As shown in fig. 2 to 4, the main thin film transistor T1 is electrically connected to the main pixel electrode 601 through a first via 100, the sub-thin film transistor T2 is electrically connected to the sub-pixel electrode 602 through a second via 200, and the shared thin film transistor T3 is electrically connected to the common electrode 50 through a third via 300. The first via hole 100 and the second via hole 200 penetrate through the organic protection layer 101, the third via hole 300 penetrates through the gate insulation layer 102, and the aperture of the third via hole 300 is smaller than the aperture of the first via hole 100 and the aperture of the second via hole 200.
The first via hole 100 and the second via hole 200 penetrate through the organic protection layer 106, and the third via hole 300 penetrates through the gate insulating layer 103.
As the size of the liquid crystal display device increases, the display luminance unevenness caused by the poor uniformity of the cell thickness becomes more remarkable. Therefore, a transparent organic protective layer (i.e., a Polymer Film on Array (PFA)) is usually required to cover the Array (thin Film transistor) substrate to change the flatness of the lower Film surface and prevent the electric fields from interfering with each other, so as to effectively improve the display unevenness of the liquid crystal display device caused by topographic factors, reduce the parasitic capacitance, reduce the display abnormalities such as flicker caused by an excessive electrical load, and improve the quality of the display device.
However, in some conventional structures, as shown in fig. 1, the common electrode 50 'and the pixel electrodes (601', 602 ') are in the same layer and are disposed at the periphery of the pixel electrodes, so the first via hole 100' connecting the main tft T1 and the main pixel electrode 601 ', the second via hole 200' connecting the sub tft T2 and the sub pixel electrode 602 ', and the third via hole 300' connecting the shared tft T3 and the common electrode are all via holes penetrating through the organic protective layer.
In the present application, the common electrode 50 is disposed on the same layer as the gate electrode 102, and the third via 300 originally penetrating through the organic protective layer 106 is changed to penetrate through the gate insulating layer 103, so that the size of the via penetrating through the gate insulating layer 103 can be made much smaller than that of the via penetrating through the organic protective layer 106 according to the current process level, for example, the size ratio of the via penetrating through the organic protective layer 106 to the via penetrating through the gate insulating layer 103 can be 1.5:1 to 4: 1.
In one embodiment, the aperture of the via penetrating through the organic protection layer 106 is 9mm, and the aperture of the via penetrating through the gate insulating layer 103 is 4 mm. Therefore, the aperture of the third via hole 300 can be reduced, so that the space ratio of the non-display area between the main area 10 and the sub-area 20 is reduced, the aperture ratio and the transmittance of the pixel are improved, the luminance of the backlight can be reduced, and the power can be reduced, thereby effectively solving the technical problem of large backlight heat.
As shown in fig. 2, in order to further increase the aperture ratio and the transmittance of the pixel, the present embodiment combines the sub-tft T2 and the common tft T3, that is, a first source 1051, a second source 1052, a first drain 1053, and a second drain 1054 are correspondingly disposed on one of the sub-pixels, wherein the main tft T1 and the sub-tft T2 share the first source 1051, and the sub-tft T2 and the common tft T3 share the second drain 1054.
That is, in fig. 1, the sub-pixel electrode 602 'draws two lines through the second via hole 200' to form the drain electrode D1 of the sub-area tft T2 and the drain electrode D2 of the shared tft T3, respectively. In the present application, the sub-pixel electrode 602 draws a line through the second via 200 to form the second drain 1054, and the second drain 1054 serves as the drain of the sub-area tft T2 and the drain of the common tft T3.
Therefore, compared with the conventional structure, the present application can reduce the wiring in the non-display region between the main region 10 and the sub-region 20, and the design of combining the sub-region thin film transistor T2 with the shared thin film transistor T3 reduces the space occupation ratio of the non-display region, thereby further increasing the aperture ratio and transmittance of the pixel, and further reducing the brightness and power of the backlight.
In an embodiment, the common electrode line 50 is made of a transparent material, and a projection range of the main pixel electrode 601 and the sub pixel electrode 602 on the array substrate at least partially covers a projection range of the common electrode 50 on the array substrate. It will be appreciated that the projection is a forward projection.
Further, the projection range of the pixel electrode layers (601,602) on the array substrate at least covers the projection range of the part of the common electrode 50 corresponding to the data line 40 on the array substrate. Since the common electrode line 50 is made of a transparent material, the pixel electrode layers (601,602) can cover the common electrode 50.
When the pixel electrode layers (601,602) cover the portions of the common electrode 50 corresponding to the data line 40, the pixel electrode layers (601,602) have increased widths in the direction along the gate line 30, so that the aperture ratio of the pixel is increased, the transmittance of the pixel is increased, the brightness of the backlight matched with the array substrate is properly reduced, and the heat generation of the backlight is reduced.
Further, the projection range of the pixel electrode layers (601,602) on the array substrate completely covers the projection range of the common electrode 50 on the array substrate. Since the pixel electrode layer
(601,602) is increased in length in the direction of the data line 40, that is, the pixel electrode layer (601,602) also covers the portion of the common electrode 50 corresponding to the direction of the gate line 30, and therefore, the aperture ratio and the transmittance of the pixel can be further improved.
Example two
Fig. 5 is a schematic structural diagram of a sub-pixel on an array substrate according to a second embodiment of the present disclosure. The array substrate of this embodiment has the same/similar structure as the array substrate of the first embodiment, except that: in this embodiment, the first via hole 100 and the second via hole 200 are close to the pixel opening area, that is, at least a part of the first via hole 100 is located in the main area 10, and at least a part of the second via hole 200 is located in the sub area 20, so as to reduce the area of the non-display area between the main area 10 and the sub area 20, thereby increasing the pixel opening ratio.
Further, the projection range of the main pixel electrode 601 on the array substrate at least partially covers the projection range of the first via 100 on the array substrate, and the projection range of the sub pixel electrode 602 on the array substrate at least partially covers the projection range of the second via 200 on the array substrate.
For example, half of the first via 100 is located in the main region 10, and half of the second via 200 is located in the sub-region 20, which may be determined according to the actual situation.
In order to maximize the pixel aperture ratio, in the present embodiment, the first via hole 100 is completely disposed in the main region 10, and the second via hole 200 is completely disposed in the sub region 20, so that the space occupation ratio of the non-display region between the main region 10 and the sub region 20 is reduced.
Further, the main pixel electrode 601 and the sub-pixel electrode 602 both include a main electrode 60a and a branch electrode 60b, and the main electrode 60a may be in a cross shape, a field shape, or other shapes, which is not limited herein. The first via hole 100 and the second via hole 200 are correspondingly located at the trunk electrode 60a, so that the first via hole 100 and the second via hole 200 do not affect the deflection of the liquid crystal, and the display effect is not affected.
Further, the first via hole 100 and the second via hole 200 are located in the coverage area of the main electrode 60a, so that the aperture ratio and the display effect of the pixel can be improved.
Further, in order to optimize the spatial design, the first via hole 100 and the second via hole 200 may be symmetrically disposed along a center line of the non-display area.
Compared with the first embodiment, in the present embodiment, since the first via hole 100 and the second via hole 200 are respectively disposed in the main region 10 and the sub-region 20, the space of the non-display region can be further saved, so as to further improve the aperture ratio and the transmittance of the pixel, and effectively solve the technical problem of large backlight heat.
EXAMPLE III
Fig. 6 is a schematic structural diagram of a sub-pixel on an array substrate according to a third embodiment of the present application. The array substrate of this embodiment has the same/similar structure as the array substrate of the second embodiment, except that: at least a portion of the third via 300 of the present embodiment is located in the sub-region 20, so as to further increase the aperture ratio of the pixel.
The projection range of the sub-pixel electrode 602 on the array substrate at least partially covers the projection range of the third via 300 on the array substrate.
In order to maximize the pixel aperture ratio, in this embodiment, the third via 300 is completely disposed in the sub-region 20, and the third via 300 is correspondingly located at the main electrode 60a, so that the disposition of the third via 300 does not affect the deflection of the liquid crystal, and the display effect is not affected.
Further, the third via 300 is located in the coverage area of the main electrode 60a, so that the aperture ratio and the display effect of the pixel can be improved.
Compared to the second embodiment, since the third via 300 is disposed in the sub-region 20, the space of the non-display region can be further saved, so as to further improve the aperture ratio and the transmittance of the pixel, and effectively solve the technical problem of large backlight heat.
In one embodiment, the difference compared to the above embodiment is: the main region 10 further includes a main storage electrode (not shown) insulated from the common electrode 50 corresponding to the main region 10 by a dielectric layer and forming a main storage capacitance; the sub-region 20 further includes a sub-storage electrode (not shown) insulated from the common electrode 50 corresponding to the sub-region 20 by the dielectric layer and forming a sub-storage capacitor.
Wherein, the projection of the main storage electrode and the secondary storage electrode on the array substrate are both positioned in the projection range of the pixel electrode layer (601,602) on the array substrate. The main storage electrode and the secondary storage electrode are transparent electrodes, so that the light transmittance and the display effect of the sub-pixels are not influenced. Therefore, the area of the non-display area is further reduced, the aperture opening ratio of the pixel is increased, and the penetration rate of the sub-pixel is further improved.
The application also provides a display panel, which comprises the array substrate. Specifically, the display panel is a liquid crystal display panel, and as shown in fig. 7, the display panel includes an array substrate 1, a color filter substrate 2, and a liquid crystal layer 3 located between the array substrate 1 and the color filter substrate 2. The display panel has high pixel aperture ratio and penetration rate, so that the technical problem of high backlight heat can be solved.
In summary, although the present application has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present application, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, so that the scope of the present application shall be determined by the appended claims.
Claims (10)
1. An array substrate is characterized by comprising sub-pixels distributed in an array, wherein each sub-pixel comprises a main area thin film transistor, a sub-area thin film transistor and a shared thin film transistor;
the sub-pixels comprise a main area and a sub-area, main pixel electrodes are arranged corresponding to the main area, sub-pixel electrodes are arranged corresponding to the sub-area, and the sub-pixels further comprise common electrodes which are arranged in different layers with the main pixel electrodes and the sub-pixel electrodes;
the main area thin film transistor is electrically connected with the main pixel electrode through a first through hole, the secondary area thin film transistor is electrically connected with the secondary pixel electrode through a second through hole, and the shared thin film transistor is electrically connected with the common electrode through a third through hole;
wherein the aperture of the third via is smaller than the apertures of the first and second vias.
2. The array substrate of claim 1, wherein the array substrate comprises:
a substrate;
the grid is arranged on the substrate;
a gate insulating layer disposed on the gate electrode;
an active layer disposed on the gate insulating layer corresponding to the gate electrode;
the source/drain electrodes are arranged at two ends of the active layer and are in contact with the ion doping regions of the active layer;
an organic protective layer disposed on the source/drain electrode;
the pixel electrode layer is arranged on the organic protective layer and comprises the main pixel electrode and the sub pixel electrode;
the common electrode and the grid electrode are arranged on the same layer, the first through hole and the second through hole penetrate through the organic protective layer, and the third through hole penetrates through the grid electrode insulating layer.
3. The array substrate of claim 1, wherein a first source, a second source, a first drain and a second drain are disposed in correspondence with each of the sub-pixels, wherein the main thin film transistor and the sub-thin film transistor share the first source, and the sub-thin film transistor and the shared thin film transistor share the second drain.
4. The array substrate of claim 1, wherein a non-display area is included between the main area and the sub-area of the same sub-pixel, and the main area thin film transistor, the sub-area thin film transistor and the shared thin film transistor are correspondingly located in the non-display area, wherein at least a portion of the first via hole is located in the main area, and at least a portion of the second via hole is located in the sub-area.
5. The array substrate of claim 4, wherein a projection range of the main pixel electrode on the array substrate at least partially covers a projection range of the first via hole on the array substrate, and a projection range of the sub pixel electrode on the array substrate at least partially covers a projection range of the second via hole on the array substrate.
6. The array substrate of claim 4, wherein the main pixel electrode and the sub-pixel electrode each comprise a trunk electrode and a branch electrode, and the first via hole and the second via hole are correspondingly located at the trunk electrode.
7. The array substrate of claim 6, wherein the first via and the second via are symmetrically disposed along a center line of the non-display area.
8. The array substrate of claim 4, wherein at least a portion of the third via is located within the sub-region.
9. The array substrate of claim 1, wherein the projection range of the main pixel electrode and the sub-pixel electrode on the array substrate at least partially covers the projection range of the common electrode on the array substrate.
10. A display panel comprising the array substrate according to any one of claims 1 to 9.
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| CN202010944769.4A CN112068371A (en) | 2020-09-10 | 2020-09-10 | Array substrate and display panel |
| PCT/CN2020/124691 WO2022052242A1 (en) | 2020-09-10 | 2020-10-29 | Array substrate and display panel |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010944769.4A CN112068371A (en) | 2020-09-10 | 2020-09-10 | Array substrate and display panel |
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| WO (1) | WO2022052242A1 (en) |
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| CN112596306A (en) * | 2021-01-06 | 2021-04-02 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
| CN113314546A (en) * | 2021-05-21 | 2021-08-27 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, array substrate testing method and display panel |
| CN113325635A (en) * | 2021-05-31 | 2021-08-31 | Tcl华星光电技术有限公司 | Display panel and manufacturing method thereof |
| CN113391491A (en) * | 2021-06-16 | 2021-09-14 | 惠州华星光电显示有限公司 | Liquid crystal display panel and display device |
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| CN115377127A (en) * | 2022-10-25 | 2022-11-22 | 惠科股份有限公司 | Array substrate, preparation method thereof and display panel |
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| CN113325635B (en) * | 2021-05-31 | 2022-07-12 | Tcl华星光电技术有限公司 | Display panel and manufacturing method thereof |
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| CN113741108A (en) * | 2021-08-31 | 2021-12-03 | 惠科股份有限公司 | Array substrate, display panel and display device |
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