CN114690490A

CN114690490A - Array substrate and display panel thereof

Info

Publication number: CN114690490A
Application number: CN202210272061.8A
Authority: CN
Inventors: 张驰; 王坤; 李亚锋
Original assignee: Wuhan China Star Optoelectronics Technology Co Ltd
Current assignee: Wuhan China Star Optoelectronics Technology Co Ltd
Priority date: 2022-03-18
Filing date: 2022-03-18
Publication date: 2022-07-01

Abstract

The application provides an array substrate and a display panel thereof; the array substrate comprises a plurality of scanning lines and a plurality of data lines which are arranged in a crossed mode, wherein the plurality of scanning lines and the plurality of data lines enclose a plurality of sub-pixel units; this application is walked the connecting hole setting of line and common electrode layer at common electrode through being used for connecting common electrode and is walked the one side of keeping away from the scanning line, makes the connecting hole not occupy common electrode and walks the region between line and the scanning line, and common electrode walks the interval of line and scanning line can be littleer, and then reduces common electrode and walks the light tight regional area between line and the scanning line, increases open area, effectively promotes the pixel aperture ratio.

Description

Array substrate and display panel thereof

Technical Field

The application relates to the field of display technology, in particular to an array substrate and a display panel thereof.

Background

In the array substrate of the display panel, since the impedance of the common electrode layer is large, a signal transmission delay due to the impedance of the common electrode layer between the periphery of the display region and the center of the display region is large, so that the voltage in the plane of the common electrode layer is not uniform, and an in-plane flicker phenomenon is easily caused.

At present, signal transmission delay caused by impedance of the common electrode layer can be reduced by designing a common electrode routing network, and the common electrode routing network is connected with the common electrode layer through a connecting hole in each sub-pixel unit. However, since the connection hole connecting the common electrode trace and the common electrode layer is usually opaque and is generally disposed in the opaque region between the common electrode trace and the scan line, the opaque region of the pixel is increased, and the aperture ratio of the pixel is reduced.

Disclosure of Invention

The application provides an array substrate and a display panel, which aims to solve the technical problem that the aperture opening ratio of pixels is reduced due to the fact that the signal transmission delay of a common electrode is reduced by designing a common electrode routing of the current display panel.

In order to solve the technical problem, the technical scheme provided by the application is as follows:

the application provides an array substrate, which comprises a plurality of scanning lines and a plurality of data lines which are arranged in a crossed mode, wherein the plurality of scanning lines and the plurality of data lines enclose a plurality of sub-pixel units;

the array substrate includes:

a substrate;

a common electrode layer disposed on the substrate; and

at least one common electrode routing wire positioned on one side of the common electrode layer;

at least part of the common electrode wires are arranged in parallel to the scanning lines and are connected with the common electrode layer through connecting holes, and the connecting holes are located on one side, far away from the scanning lines, of the common electrode wires.

In the array substrate of the present application, the common electrode trace includes a plurality of first common electrode traces and a plurality of second common electrode traces, and the first common electrode traces and the second common electrode traces are arranged in a crossing manner;

the first common electrode routing line is arranged along the extending direction of the scanning line, and the second common electrode routing line is arranged along the extending direction of the data line.

In the array substrate of the present application, the array substrate includes a thin film transistor region and a pixel electrode region located at least one side of the thin film transistor region;

the scanning lines and the first common electrode routing are located in the thin film transistor area, and the connecting holes are located in the pixel electrode area.

In the array substrate of the present application, the array substrate further includes a thin film transistor disposed in the thin film transistor region, the thin film transistor includes a source electrode and a drain electrode, and the source electrode and the drain electrode are located between the first common electrode trace and the scan line;

the width of the source electrode or/and the drain electrode in a first direction is larger than the distance between the scanning line and the first common electrode routing in a second direction;

the first direction is parallel to the extending direction of the scanning lines, and the second direction is parallel to the extending direction of the data lines.

In the display panel of the present application, the number of the connection holes is smaller than the number of the sub-pixel units.

The application also provides a display panel, which comprises a color film substrate, a liquid crystal layer and the array substrate, wherein the liquid crystal layer is arranged between the color film substrate and the array substrate.

In the display panel of the present application, the display panel further includes a plurality of columnar stays located within the liquid crystal layer;

the array substrate or the color film substrate further comprises a light shielding layer, and orthographic projections of the columnar support and the connecting hole on the light shielding layer are located in the light shielding layer.

In the display panel of the application, a spacer layer corresponding to the columnar support is arranged on one side of the array substrate or the color film substrate, which is close to the liquid crystal layer;

the orthographic projection of the columnar support on the spacer layer is located in the spacer layer, and the orthographic projection of the spacer layer on the light shielding layer is located in the light shielding layer.

In the display panel of the present application, the columnar supports include first columnar supports and second columnar supports, and the light shielding layer includes first light shielding portions corresponding to the first columnar supports and second light shielding portions corresponding to the second columnar supports;

in the light emitting direction of the display panel, the size of the first columnar support is larger than that of the second columnar support, and in the top view of the display panel, the plane size of the first light shielding part is larger than that of the second light shielding part.

In the display panel of the present application, an orthographic projection of the connection hole on the light shielding layer is located inside the first light shielding portion.

Advantageous effects

This application is through being used for connecting the common electrode walk the line with the connecting hole setting of common electrode layer is in the common electrode walks the line and keeps away from one side of scanning line makes the connecting hole does not occupy the common electrode walk the line with region between the scanning line, the common electrode walk the line with the interval of scanning line can be littleer, and then reduces the common electrode walk the line with the area in light tight region between the scanning line increases open area, effectively promotes the pixel aperture ratio.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic plan view of a common electrode routing network in the prior art;

FIG. 2 is a schematic diagram of the relative positions of a connection hole, a scan line and a common electrode trace in the prior art;

fig. 3 is a schematic plan view of an array substrate according to the present application;

FIG. 4 is a schematic structural diagram of a common electrode trace according to the present application;

FIG. 5 is a schematic view of a film structure of an array substrate according to the present application;

FIG. 6 is a schematic view of a partial plan structure of an array substrate according to the present application;

fig. 7 is a schematic view of the overall structure of the display panel according to the present application.

Description of reference numerals:

the liquid crystal display device comprises an array substrate 100, a thin film transistor region 101, a pixel electrode region 102, a scanning line 110, a data line 120, a common electrode wire 130, a first common electrode wire 131, a second common electrode wire 132, a connecting hole 133, a thin film transistor 140, an active layer 141, a source electrode 142, a drain electrode 143, a gate electrode 144, a substrate 150, a pixel electrode 160, a common electrode layer 170, a color film substrate 200, a liquid crystal layer 300, a columnar support 400, a first columnar support 410, a second columnar support 420, a light shielding layer 500, a first light shielding portion 510, a second light shielding portion 520, a spacer 600 and an alignment layer 700.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In the present application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, and more particularly to the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.

In a high-resolution display panel, especially in a product using Low Temperature Polysilicon (LTPS) technology, since the impedance of a common electrode layer on an array substrate is large, a signal transmission delay due to the impedance of the common electrode layer between the periphery of a display region and the center of the display region is large, voltage in the plane of the common electrode layer is not uniform, and an in-plane flicker phenomenon is easily caused.

At this stage, the signal transmission delay caused by the impedance of the common electrode layer can be reduced by designing the common electrode trace. As shown in fig. 1, the common electrode trace is connected to the common electrode layer through a connection hole in each pixel, the location of the connection hole corresponds to the position of a circle in the figure, and the common electrode trace is connected to the common voltage terminal, because the common electrode trace is usually a metal wire, and its impedance is about 1/100 of the common electrode layer made of Indium Tin Oxide (ITO), the impedance delay of the common voltage signal can be effectively reduced.

However, as shown in fig. 2, since the connection hole 133 connecting the common electrode trace 130 and the common electrode layer 170 is usually opaque, the connection hole 133 is generally disposed in the opaque region between the common electrode trace 130 and the scan line 110, which results in an increase of the opaque region of the pixel and a decrease of the pixel aperture ratio. Moreover, as the pixel resolution of the product increases and the pixel size gradually decreases, the switching distance d1 between the connection hole 133 and the tft 140 of the sub-pixel unit is too small, which easily causes a short-circuit problem of the tft switch. The present application proposes the following solutions based on the above technical problems.

Referring to fig. 3 to 7, the present application provides an array substrate including a plurality of scan lines 110 and a plurality of data lines 120 that are arranged in a crossing manner, wherein the plurality of scan lines 110 and the plurality of data lines 120 enclose a plurality of sub-pixel units. The array substrate 100 includes a substrate 150, a common electrode layer 170 disposed on the substrate 150, and at least one common electrode trace 130 located at one side of the common electrode layer 170. At least a portion of the common electrode trace 130 is disposed parallel to the scan line 110 and connected to the common electrode layer 170 through a connection hole 133, and the connection hole 133 is located on a side of the common electrode trace 130 away from the scan line 110.

This application is through being used for connecting common electrode is walked 130 with the connecting hole 133 of common electrode layer 170 sets up common electrode is walked 130 and is kept away from one side of scanning line 110 makes connecting hole 133 does not occupy common electrode is walked 130 with the region between the scanning line 110, common electrode is walked 130 with the interval of scanning line 110 can be littleer, and then reduces common electrode is walked 130 with the light tight regional area between the scanning line 110, increase open area, effectively promote the pixel aperture ratio.

The technical solution of the present application will now be described with reference to specific embodiments. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments.

In this embodiment, the substrate 150 may be a glass substrate or a transparent polyimide substrate.

In this embodiment, the common electrode layer 170 may be a transparent conductive film material, such as an Indium Tin Oxide (ITO) material.

In this embodiment, the data line 120, the scan line 110 and the common electrode trace 130 can be low-impedance conductive metal lines, such as Cu, Al, Ag, etc.

Referring to fig. 3 and 4, fig. 3 is a schematic plan view of an array substrate according to the present application, and fig. 4 is a schematic structural view of a common electrode trace according to the present application. In the array substrate of the present application, the common electrode trace 130 may include a plurality of first common electrode traces 131 and a plurality of second common electrode traces 132, and the first common electrode traces 131 are crossed with the second common electrode traces 132 and electrically connected to each other.

In this embodiment, by setting the structure that the plurality of first common electrode traces 131 and the plurality of second common electrode traces 132 are crossed and electrically connected, the plurality of common electrode traces 130 form a mesh structure, so as to transmit common voltage signals more quickly and uniformly, and have a better voltage stabilizing effect on the common electrode layer 170.

In this embodiment, the first common electrode trace 131 may be disposed along an extending direction of the scan line 110, and the second common electrode trace 132 may be disposed along an extending direction of the data line 120. At this time, an orthogonal projection of the first common electrode trace 131 on the substrate 150 may overlap or partially overlap an orthogonal projection of the data line 120 on the substrate 150, or an orthogonal projection of the first common electrode trace 131 on the substrate 150 may not overlap an orthogonal projection of the data line 120 on the substrate 150 but be close to each other. Similarly, the orthographic projection of the second common electrode trace 132 on the substrate 150 may overlap or partially overlap with the orthographic projection of the scan line 110 on the substrate 150, or the orthographic projection of the second common electrode trace 132 on the substrate 150 may not overlap with but be close to the orthographic projection of the scan line 110 on the substrate 150.

In this embodiment, through the above arrangement, the common electrode trace 130 layer can be exactly disposed in the opaque region formed by the data line 120 and the scan line 110, so as to avoid or improve the problem of the opaque region increase caused by the common electrode layer 170, and thus, the pixel aperture ratio can be kept high.

Referring to fig. 3, in the array substrate of the present application, the array substrate 100 may include a thin film transistor region 101 and a pixel electrode region 102 on at least one side of the thin film transistor region 101. In this embodiment, the tft region 101 is an opaque region, and the pixel electrode region 102 is a transparent region, i.e., an open region.

In this embodiment, an orthographic projection of the first common electrode trace 131 on the substrate 150 may not overlap with an orthographic projection of the scan line 110 on the substrate 150, that is, the orthographic projection of the first common electrode trace 131 on the substrate 150 may be separately disposed, but both the scan line 110 and the first common electrode trace 131 may be located in the thin film transistor region 101, so that the first common trace may be disposed in an original opaque region to avoid or reduce loss of an aperture ratio.

In this embodiment, the connection hole 133 can be located in the pixel electrode region 102, that is, the connection hole 133 is located outside the tft region 101 between the first common electrode trace 131 and the scan line 110, so as to reduce the width of the opaque tft region 101, effectively reduce the area of the opaque region, and improve the pixel aperture ratio. It should be noted that although the connection hole 133 located in the pixel electrode region 102 also causes a decrease in the aperture ratio of the pixel electrode region 102 to some extent, the decrease in the aperture ratio of the connection hole 133 located in the pixel electrode region 102 is smaller than the decrease in the aperture ratio caused by the connection hole 133 located in the tft region 101.

Referring to fig. 4, in the array substrate of the present application, since the connection holes 133 are disposed in the pixel electrode region 102, in order to reduce an aperture ratio loss of the connection holes 133 to the pixel electrode region 102 as much as possible, the number of the connection holes 133 may be smaller than the number of the sub-pixel units. In other words, in the present embodiment, the connection holes 133 are not disposed in each sub-pixel unit, so as to reduce the number of the connection holes 133 and reduce the loss of the overall aperture ratio of the connection holes 133 to the array substrate 100.

Further, the number of the connection holes 133 may be smaller than the number of pixels configured by the sub-pixel unit. That is, in the present embodiment, the connection hole 133 is not provided in every pixel, thereby further reducing the number of the connection holes 133.

In the embodiment of the present application, the connection hole 133 is disposed in the pixel electrode region 102 on the side of the common electrode trace 130 away from the scan line 110, so that the distance between the common electrode trace 130 and the scan line 110 can be smaller, the area of the opening region is increased, and the pixel aperture ratio is effectively improved. Moreover, since the connection hole 133 of the common electrode trace 130 and the common electrode layer 170 in the embodiment of the present disclosure is located outside the tft region 101, there is no short circuit problem caused by the close distance between the connection hole 133 and the source electrode 142 or the drain electrode 143 of the tft 140 of the sub-pixel with smaller size under high resolution. The number of the connecting holes 133 is correspondingly reduced, so that the reduction of the aperture opening ratio of the connecting holes 133 in the pixel electrode region 102 is reduced, and the pixel aperture opening ratio is further improved.

Referring to fig. 3 and 5, fig. 5 is a schematic view illustrating a film structure of the array substrate according to the present application, in the array substrate according to the present application, the array substrate 100 may further include a thin film transistor 140 disposed in the thin film transistor region 101, and the thin film transistor 140 may include an active layer 141, a gate electrode 144, a source electrode 142, and a drain electrode 143. The gate electrode 144 is insulated from the active layer 141, and the source electrode 142 and the drain electrode 143 are separately disposed and overlap on both sides of the active layer 141. The gate electrode 144 is electrically connected to the scan line 110, the source electrode 142/drain electrode 143 is electrically connected to the data line 120, and the drain electrode 143/source electrode 142 is electrically connected to the pixel electrode 160 in the pixel electrode region 102. The scanning signal in the scanning line 110 controls the on and off of the circuits of the source electrode 142 and the drain electrode 143 through the gate electrode 144, and the data signal in the data line 120 is transmitted to the pixel electrode 160 through the source electrode 142 and the drain electrode 143, and forms an electric field with the common electrode layer 170 to drive the liquid crystal in the liquid crystal display panel to deflect.

In this embodiment, the source electrode 142 and the drain electrode 143 may be located between the first common electrode trace 131 and the scan line 110, in other words, an orthogonal projection of the source electrode 142 and the drain electrode 143 on the substrate 150 is located between an orthogonal projection of the first common trace on the substrate 150 and an orthogonal projection of the scan line 110 on the substrate 150.

In this embodiment, the source electrode 142 and the drain electrode 143 are arranged along the extending direction of the scan line 110, two sides of the active layer 141 are electrically connected to the source electrode 142 and the drain electrode 143, respectively, and an orthographic projection of the scan line 110 on the active layer 141 partially overlaps the active layer 141.

In this embodiment, two or more vias may be disposed in a film layer corresponding to the source electrode 142 or/and the drain electrode 143 of the array substrate 100, so as to electrically connect the source electrode 142 or/and the drain electrode 143 with the pixel electrode 160, the active layer 141, or other conductive film layers.

Referring to fig. 6, fig. 6 is a schematic view of a partial planar structure of the array substrate 100 according to the present application, in this embodiment, two or more via holes corresponding to the source electrode 142 or/and the drain electrode 143 may be arranged along a first direction, the first direction being parallel to an extending direction of the scan line 110, so that a distance d2 between the scan line 110 and the first common electrode trace 131 in a second direction may be smaller than a width d3 of the source electrode 142 or/and the drain electrode 143 in the first direction, and the second direction being parallel to the extending direction of the data line 120.

Through the above arrangement, the distance between the scan line 110 and the first common electrode trace 131 can be prevented from increasing, which is beneficial to reducing the width of the thin film transistor region 101 along the second direction, thereby reducing the area of the opaque region and improving the aperture ratio. Moreover, in this embodiment, since the common electrode trace 130 and the connection hole 133 of the common electrode layer 170 are located outside the tft region 101, there is no short circuit problem caused by the close distance between the source electrode 142 or the drain electrode 143 of the tft 140 of the sub-pixel with smaller size and the connection hole 133 under high resolution.

Referring to fig. 7, the display panel may include a color film substrate 200, a liquid crystal layer 300 and the array substrate 100 in the above embodiments, where the liquid crystal layer 300 is disposed between the color film substrate 200 and the array substrate 100.

Referring to fig. 7, fig. 7 is a schematic view of an overall structure of the display panel of the present application, in the display panel of the present application, the display panel may further include a plurality of columnar supports 400 located in the liquid crystal layer 300, the columnar supports 400 may be in a cylindrical shape, a truncated cone shape, a truncated pyramid shape, or an ellipsoid shape with a long axis parallel to a light emitting direction of the display panel, and the columnar supports 400 are used for supporting a liquid crystal cell formed by the color film substrate 200 and the array substrate 100.

In this embodiment, the array substrate 100 or the color filter substrate 200 may further include a light-shielding layer 500, where the light-shielding layer 500 may be an opaque material layer, such as a black matrix, and the black matrix is used to separate color-resistant materials of different colors on the color filter substrate 200 or the array substrate 100, so as to form sub-pixels of different colors, such as a red sub-pixel (R), a green sub-pixel (G), a blue sub-pixel (B), and avoid or reduce a cross-color problem of the sub-pixels.

In this embodiment, the orthographic projections of the columnar supports 400 and the connection holes 133 on the light shielding layer 500 may be located in the light shielding layer 500, so that the columnar supports 400 and the connection holes 133 may utilize an opaque region formed by the light shielding layer 500, thereby reducing the light transmittance loss of the display panel.

Referring to fig. 7, in the display panel of the present application, a spacer layer 600 corresponding to the pillar-shaped support 400 is disposed on one side of the array substrate 100 or the color filter substrate 200 close to the liquid crystal layer 300. That is, a spacer layer 600 is disposed on a side surface of the array substrate 100 or the color filter substrate 200 contacting the liquid crystal layer 300, and the pillar-shaped support 400 is disposed on the spacer layer 600.

In this embodiment, the orthographic projection of the columnar support 400 on the spacer layer 600 can be entirely located in the spacer layer 600, so that the spacer layer 600 can support the columnar support 400 more sufficiently and stably.

In this embodiment, the orthographic projection of the spacer layer 600 on the light-shielding layer 500 may be entirely located in the light-shielding layer 500, so that the spacer layer 600 having an area larger than the cross-sectional area of the columnar spacer can be completely shielded by the light-shielding layer 500 (i.e., the black matrix), the occupation of the spacer layer 600 on the opening area of the display panel is further reduced, and the aperture ratio is improved.

Referring to fig. 7, in the display panel of the present application, the pillar-shaped supports 400 may include at least one first pillar-shaped support 410 and a plurality of second pillar-shaped supports 420, and in a light emitting direction of the display panel, a size of the first pillar-shaped support 410 is larger than a size of the second pillar-shaped support 420. In other words, in the light emitting direction of the display panel, the height of the first columnar support 410 is greater than that of the second columnar support 420, that is, the first columnar support 410 corresponds to Main PS in a conventional liquid crystal display panel, and the second columnar support 420 corresponds to Sub PS in a conventional liquid crystal display panel.

As with the distribution rule of the column supports 400 in the conventional lcd panel, in this embodiment, the number of the first column supports 410 is less than the number of the second column supports 420, and the second column supports 420 are distributed around the first column supports 410 with the first column supports 410 as the center.

In this embodiment, the light shielding layer 500 may include a first light shielding portion 510 corresponding to the first pillar-shaped support 410 and a second light shielding portion 520 corresponding to the second pillar-shaped support 420. That is, the orthographic projection of the first columnar spacer 410 on the light shielding layer 500 is located within the first light shielding portion 510, and the orthographic projection of the second columnar spacer 420 on the light shielding layer 500 is located within the second light shielding portion 520.

In the present embodiment, in a top view of the display panel, the planar size of the first light shielding portion 510 may be larger than the planar size of the second light shielding portion 520, in other words, the area of the first light shielding portion 510 may be larger than the area of the second light shielding portion 520. The first light shielding portions 510 and the second light shielding portions 520 may have similar shapes but different sizes. As shown in fig. 3, the first light shielding portion 510 and the second light shielding portion 520 may be regular octagons, but the side length of the octagon of the second light shielding portion 520 is larger than that of the octagon of the first light shielding portion 510.

The shapes of the first light shielding portion 510 and the second light shielding portion 520 may be other shapes, such as a circle, a square, a rectangle, etc., and the embodiment of the present application is described only by taking the case where the first light shielding portion 510 and the second light shielding portion 520 are octagonal, and does not represent a specific limitation on the shapes thereof.

In this embodiment, by setting the area of the first light shielding portion 510 corresponding to the first columnar support 410 to be larger, when the first columnar support 410 is pressed to slide out to the alignment layer 700 on the surface of the array substrate 100 or the color filter substrate 200, the size of the first light shielding portion 510 can still be larger than the height of the first columnar support 410, and the first light shielding portion 510 can still perform a sufficient shielding function on the first columnar support 410, so as to prevent the light leakage problem caused by the toppling and displacement of the first columnar support 410.

Meanwhile, in the present embodiment, the area of the second light shielding portion 520 corresponding to the second columnar support 420 is set to be smaller, so that on the premise of sufficiently shielding the second columnar support 420, the light shielding area of the light shielding layer 500 can be further reduced, thereby improving the light transmittance of the display panel.

In the display panel of the present application, an orthogonal projection of the connection hole 133 on the light shielding layer 500 may be located inside the first light shielding portion 510. In other words, the connection hole 133 may be disposed at a position corresponding to the first light shielding portion 510. As is well known, in the liquid crystal display panel, the number of the column supports 400 is much smaller than the number of the Sub-pixels, wherein the number of Main PS is much smaller than the number of Sub PS. Therefore, in the present embodiment, by disposing the connection holes 133 at the positions corresponding to the first light-shielding portions 510, that is, by disposing the connection holes 133 near the first pillar-shaped supports 410, on one hand, the number of the connection holes 133 is greatly reduced, and the influence of the connection holes 133 on the light transmittance of the pixel electrode region 102 is reduced, and on the other hand, the connection holes 133 can be sufficiently shielded by the first light-shielding portions 510 having a large area.

In the embodiment of the present application, the connection hole 133 is disposed at a position corresponding to the first light-shielding portion 510 of the light-shielding layer 500, so that the first light-shielding portion 510 can not only shield the first columnar support 410, but also sufficiently shield the connection hole 133. Moreover, since the connection holes 133 need to be disposed at positions corresponding to the first light-shielding portions 510, the number of the connection holes 133 is not more than the number of the first pillar-shaped supports 410, so that the number of the connection holes 133 is greatly reduced, and the loss of the aperture ratio of the connection holes 133 to the pixel electrode regions 102 is effectively reduced.

The array substrate and the display panel thereof provided by the embodiments of the present application are described in detail above, and the principles and embodiments of the present application are explained herein by applying specific examples, and the description of the embodiments is only used to help understand the method and the core concept of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. The array substrate is characterized by comprising a plurality of scanning lines and a plurality of data lines which are arranged in a crossed mode, wherein the plurality of scanning lines and the plurality of data lines form a plurality of sub-pixel units in a surrounding mode;

the array substrate includes:

a substrate;

a common electrode layer disposed on the substrate; and

at least one common electrode routing wire is positioned on one side of the common electrode layer;

2. The array substrate according to claim 1, wherein the common electrode trace comprises a plurality of first common electrode traces and a plurality of second common electrode traces, and the first common electrode traces and the second common electrode traces are arranged in a crossing manner;

3. The array substrate of claim 2, wherein the array substrate comprises a thin film transistor region and a pixel electrode region at least one side of the thin film transistor region;

the scanning lines and the first common electrode wiring are located in the thin film transistor area, and the connecting holes are located in the pixel electrode area.

4. The array substrate of claim 3, further comprising a thin film transistor disposed in the thin film transistor region, wherein the thin film transistor comprises a source and a drain, and the source and the drain are located between the first common electrode trace and the scan line;

the width of the source electrode or/and the drain electrode in the first direction is larger than the distance between the scanning line and the first common electrode routing in the second direction;

5. The array substrate of claim 1, wherein the number of the connection holes is less than the number of the sub-pixel units.

6. A display panel, comprising a color filter substrate, a liquid crystal layer and the array substrate of any one of claims 1 to 5, wherein the liquid crystal layer is disposed between the color filter substrate and the array substrate.

7. The display panel of claim 6, further comprising a plurality of columnar supports within the liquid crystal layer;

8. The display panel according to claim 7, wherein a spacer layer corresponding to the columnar support is disposed on one side of the array substrate or the color film substrate, which is close to the liquid crystal layer;

9. The display panel according to claim 7, wherein the columnar supports include a first columnar support and a second columnar support, and wherein the light-shielding layer includes a first light-shielding portion corresponding to the first columnar support and a second light-shielding portion corresponding to the second columnar support;

10. The display panel according to claim 9, wherein an orthogonal projection of the connection hole on the light shielding layer is located inside the first light shielding portion.