CN113311624A - Array substrate and display panel - Google Patents
Array substrate and display panel Download PDFInfo
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- CN113311624A CN113311624A CN202110366376.4A CN202110366376A CN113311624A CN 113311624 A CN113311624 A CN 113311624A CN 202110366376 A CN202110366376 A CN 202110366376A CN 113311624 A CN113311624 A CN 113311624A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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Abstract
The application provides an array substrate and a display panel. The array substrate comprises a plurality of scanning lines, a plurality of data lines without black matrixes and a plurality of sub-pixels, wherein the data lines are positioned above the data lines, and the sub-pixels are defined by the crossing of the scanning lines and the data lines; each sub-pixel is divided into a main pixel area and a sub-pixel area, a scanning line is respectively arranged corresponding to each row of sub-pixels, and the scanning line is arranged between the main pixel area and the sub-pixel area; the main pixel region comprises a first thin film transistor, a main region storage capacitor and a main region liquid crystal capacitor, and the auxiliary pixel region comprises a second thin film transistor, a third thin film transistor, an auxiliary region storage capacitor and an auxiliary region liquid crystal capacitor; the drain electrode of the third thin film transistor is connected with the data line without the black matrix, so that the aperture opening ratio of the pixel is increased, a preset electrode is omitted, and the probability of poor pixel is effectively reduced.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate and a display panel.
Background
In the 3T Pixel unit structure, the Pixel unit is divided into a Main Pixel area (Main Pixel) and a sub Pixel area (sub Pixel), and in the prior art, the viewing angle problem is improved by the difference of the inversion degree of the liquid crystal in the Main Pixel area and the sub Pixel area.
The main pixel region is driven by a first Thin Film Transistor (TFT), and the sub-pixel region is commonly driven by a second TFT and a third TFT for pulling down a voltage of the sub-pixel region. The grid electrode of the first thin film transistor in the main pixel region is connected with the corresponding scanning line Gate, the source electrode of the first thin film transistor is connected with the corresponding Data line Data, and the drain electrode of the first thin film transistor is connected with the main pixel electrode; the grid electrode of the second thin film transistor in the sub-pixel region is connected with the corresponding scanning line, the source electrode of the second thin film transistor is connected with the data line, the drain electrode of the second thin film transistor is connected with the slave pixel electrode, the grid electrode of the third thin film transistor is connected with the corresponding scanning line, the source electrode of the third thin film transistor is connected with the drain electrode of the second thin film transistor, and the drain electrode of the third thin film transistor is connected with a preset electrode (sharebar) electrode.
However, in the pixel design, the drain of the third thin film transistor is connected to a preset electrode (sharebar) electrode, the preset electrode is located below the pixel electrode (ITO) trunk, poor alignment between the preset electrode and the pixel electrode may reduce the pixel penetration rate, and meanwhile, a foreign object between the preset electrode and the lower common electrode metal may cause a weak line defect, thereby reducing the production yield.
Disclosure of Invention
The application provides an array substrate and a display panel, which are used for increasing the aperture opening rate and the transmittance of pixels.
In order to realize the functions, the technical scheme provided by the application is as follows:
an array substrate comprises a plurality of scanning lines extending along the horizontal direction, a plurality of data lines extending along the vertical direction, a plurality of data lines without black matrixes and a plurality of sub-pixels, wherein the data lines are positioned above the data lines;
each sub-pixel is divided into a main pixel area and a sub-pixel area, a scanning line is respectively arranged corresponding to each row of sub-pixels, and the scanning line is arranged between the main pixel area and the sub-pixel area;
the main pixel area of the sub-pixel comprises a first thin film transistor, a main area storage capacitor and a main area liquid crystal capacitor, and the auxiliary pixel area of the sub-pixel comprises a second thin film transistor, a third thin film transistor, an auxiliary area storage capacitor and an auxiliary area liquid crystal capacitor;
and the drain electrode of the third thin film transistor is connected with the data line without the black matrix.
In the array substrate of the present application, the array substrate includes:
a substrate base plate;
the first metal layer is positioned on the substrate and comprises the scanning line, a grid electrode of the first thin film transistor, a grid electrode of the second thin film transistor and a grid electrode of the third thin film transistor;
the second metal layer is positioned on one side of the first metal layer, which is far away from the substrate base plate, and comprises a data line, a source electrode and a drain electrode of the first thin film transistor, a source electrode and a drain electrode of the second thin film transistor and a source electrode and a drain electrode of the third thin film transistor;
and the transparent electrode layer is positioned on one side of the second metal layer far away from the first metal layer, and comprises pixel electrodes arranged at intervals and data lines without black matrixes, and each pixel electrode comprises a main area pixel electrode arranged in a main pixel area corresponding to the sub-pixel and a sub-area pixel electrode arranged in a sub-pixel area corresponding to the sub-pixel.
In the array substrate of the present application, the array substrate further includes an insulating layer and an active layer between the first metal layer and the second metal layer, and a passivation layer between the second metal layer and the transparent electrode layer; and a through hole is formed in the passivation layer, and the data line without the black matrix is connected with the drain electrode of the third thin film transistor T3 through the through hole.
In the array substrate of the present application, a gate of the third thin film transistor is electrically connected to the corresponding scan line, and a source of the third thin film transistor is electrically connected to a drain of the second thin film transistor.
In the array substrate, the grid of the first thin film transistor is electrically connected with the corresponding scanning line, the source of the first thin film transistor is electrically connected with the corresponding data line, and the drain of the first thin film transistor is electrically connected with the first polar plate of the main area liquid crystal capacitor and the first polar plate of the main area storage capacitor.
In the array substrate, the second polar plate of the main area storage capacitor is electrically connected with the main area pixel electrode, and the second polar plate of the main liquid crystal capacitor is electrically connected with the common electrode.
In the array substrate, the grid electrode of the second thin film transistor is electrically connected with the corresponding scanning line, the source electrode of the second thin film transistor is electrically connected with the corresponding data line, and the drain electrode of the second thin film transistor is electrically connected with the first polar plate of the sub-region liquid crystal capacitor and the first polar plate of the sub-region storage capacitor.
In the array substrate, the second polar plate of the sub-region storage capacitor is electrically connected with the sub-region pixel electrode, and the second polar plate of the sub-region liquid crystal capacitor is electrically connected with the common electrode.
In the array substrate of the present application, the data line without the black matrix includes a first portion and a second portion, the first portion is parallel to the data line, and the second portion is disposed in an opening region of the corresponding sub-pixel; wherein the projection of the first portion overlaps with the corresponding data line, and the projection of the second portion overlaps with the corresponding scan line.
The application provides a display panel, which comprises the array substrate.
The beneficial effect of this application: the method comprises the steps that a preset electrode in the existing 3T pixel unit design is omitted, and the drain electrode of a third thin film transistor for reducing the voltage of a sub-pixel region of a sub-pixel is connected with a data line without a black matrix, so that the pixel aperture opening ratio and the transmittance are increased; meanwhile, the functions of reducing the voltage of the auxiliary pixel area and improving the color cast of a large visual angle are realized; and because the preset electrode is omitted, the phenomenon that the production yield is reduced because the light line is poor possibly caused by foreign matters between the preset electrode and the common electrode metal is avoided, and the electrical stability of the 3T pixel unit structural design is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of an equivalent circuit of a sub-pixel of a conventional array substrate;
fig. 2 is a top view of a sub-pixel of an array substrate according to an embodiment of the present disclosure;
FIG. 3 is a cross-sectional view of FIG. 2 at location A;
fig. 4 is an equivalent circuit schematic diagram of a sub-pixel of an array substrate according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In the present application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, and more particularly to the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.
Referring to fig. 1, an equivalent circuit diagram of a sub-pixel of a conventional array substrate is shown.
In the prior art, the sub-pixel is divided into a main pixel area 100 and a sub-pixel area 200, the main pixel area 100 is driven by a first thin film transistor T1, and the sub-pixel area is driven by a second thin film transistor T2 and a third thin film transistor T3; wherein the Gate of the first thin film transistor T1 in the main pixel region 100 is connected to the corresponding scan line Gate, the source of the first thin film transistor T1 is connected to the corresponding Data line Data, and the drain of the first thin film transistor T1 is connected to the first plate of the main region liquid crystal capacitor Clc-main and the first plate of the main region storage capacitor Cst-main; the Gate of the second thin film transistor T2 in the sub-pixel region 200 is connected to a corresponding scan line Gate, the source of the second thin film transistor T2 is connected to a Data line Data, the drain of the second thin film transistor T2 is connected to the first plate of the sub-region liquid crystal capacitor Clc-sub and the first plate of the sub-region storage capacitor Cst-sub, the Gate of the third thin film transistor T3 is connected to the corresponding scan line Gate, the source of the third thin film transistor T3 is connected to the drain of the second thin film transistor T2, and the drain of the third thin film transistor T3 is connected to a preset electrode (sharebar).
However, in the pixel design, the preset electrode (sharebar) is located below the pixel electrode (ITO) trunk, and the pixel penetration rate is reduced due to poor alignment between the preset electrode (sharebar) and the pixel electrode, and meanwhile, a foreign object between the preset electrode and the lower common electrode metal may cause a weak line defect, which may result in a reduction in production yield. Accordingly, the present application provides an array substrate and a display panel to solve the above problems.
The embodiment of the application provides an array substrate and a display panel. The following are detailed below. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments.
Referring to fig. 2, 3 and 4, the present application provides an array substrate, which includes a plurality of scan lines 80 extending along a horizontal direction, a plurality of Data lines 53 extending along a vertical direction, a plurality of Data lines (DBS) 71 without black matrix above the plurality of Data lines 53, and a plurality of sub-pixels defined by intersections of the scan lines 80 and the Data lines 53.
Each sub-pixel is divided into a main pixel area 100 and a sub-pixel area 200, a scan line 80 is respectively arranged corresponding to each row of sub-pixels, and the scan line 80 is arranged between the main pixel area 100 and the sub-pixel area 200.
The main pixel region 100 of the sub-pixel includes a first thin film transistor T1, a main region storage capacitor Cst-main, and a main region liquid crystal capacitor Clc-main, and the sub-pixel region 200 of the sub-pixel includes a second thin film transistor T2, a third thin film transistor T3, a sub-region storage capacitor Cst-sub, and a sub-region liquid crystal capacitor Clc-sub.
Wherein the drain electrode 52 of the third thin film transistor T3 is connected to the data line 71 without the black matrix.
The drain electrode 52 of the third thin film transistor T3 is connected with the data line 71 without the black matrix, so that the aperture ratio of the pixel is increased, and meanwhile, compared with the existing pixel structural design, the pixel structure omits a preset electrode, so that the phenomenon that foreign matters between the preset electrode and common electrode metal possibly cause light line failure and the reduction of the production yield is avoided.
The technical solution of the present application will now be described with reference to specific embodiments.
Example one
Referring to fig. 2, a top view of a sub-pixel of an array substrate according to an embodiment of the present disclosure is provided.
The embodiment provides an array substrate, which includes a plurality of scan lines 80 extending along a horizontal direction, a plurality of data lines 53 extending along a vertical direction, a plurality of black matrix-free data lines 71 located above the plurality of data lines 53, and a plurality of sub-pixels defined by the intersections of the scan lines 80 and the data lines 53.
Each sub-pixel is divided into a main pixel area 100 and a sub-pixel area 200, a scan line 80 is respectively arranged corresponding to each row of sub-pixels, and the scan line 80 is arranged between the main pixel area 100 and the sub-pixel area 200.
The main pixel region 100 of the sub-pixel includes a first thin film transistor T1, a main region storage capacitor Cst-main, and a main region liquid crystal capacitor Clc-main, and the sub-pixel region 200 of the sub-pixel includes a second thin film transistor T2, a third thin film transistor T3, a sub-region storage capacitor Cst-sub, and a sub-region liquid crystal capacitor Clc-sub.
In this embodiment, the length of the data line 71 of the black matrix is greater than the length of the data line 53, the data line 71 of the black matrix includes a first portion 711 and a second portion 712, the first portion 711 is parallel to the data line 53, and the second portion 712 is disposed in the opening region of the corresponding sub-pixel.
Wherein a projection of the first portion 711 of the black matrix-free data line 71 overlaps the corresponding data line 53; the projection of the second portion 712 of the data line 710 without the black matrix partially overlaps the corresponding scan line 80.
It is understood that the data line 71 without the black matrix includes the first portion 711 and the second portion 712 only for illustration, and the embodiment is not particularly limited thereto.
Referring to fig. 3, in the present embodiment, the array substrate includes a substrate 10; a first metal layer 20 on the substrate 10, the first metal layer 20 including the scan line (not shown), the gate electrode (not shown) of the first thin film transistor T1, the gate electrode (not shown) of the second thin film transistor T2, and the gate electrode 21 of the third thin film transistor T3; a second metal layer 50 on a side of the first metal layer 20 away from the substrate 10, the second metal layer 50 including a data line (not shown), a source and a drain of the first thin film transistor T1 (not shown), a source and a drain of the second thin film transistor T2 (not shown), and a source 51 and a drain 52 of the third thin film transistor T3; and a transparent electrode layer 70 located on a side of the second metal layer 50 away from the first metal layer, wherein the transparent electrode layer 70 includes pixel electrodes (not shown) and data lines 71 without black matrix, the pixel electrodes include a main pixel electrode (not shown) corresponding to the main pixel region 100 of the sub-pixel and a sub-pixel electrode (not shown) corresponding to the sub-pixel region 200 of the sub-pixel.
Specifically, in this embodiment, the array substrate further includes an insulating layer 30 and an active layer 40 between the first metal layer 20 and the second metal layer 50, and a passivation layer 60 between the second metal layer 50 and the transparent electrode layer 70; the passivation layer 60 is formed with a via hole 61, the via hole 61 is located above the drain electrode 52 of the third tft T3, and the data line 71 without the black matrix is connected to the drain electrode 52 of the third tft T3 through the via hole 61. In this embodiment, the drain electrode 52 of the third thin film transistor T3 is connected to the data line 71 without the black matrix, so that the pixel aperture ratio and the transmittance are increased.
Referring to fig. 4, an equivalent circuit of a sub-pixel of an array substrate according to an embodiment of the present disclosure is shown.
In the present embodiment, in the main pixel region 100 of the sub-pixel, the Gate of the first thin film transistor T1 is electrically connected to the corresponding scan line Gate, the source of the first thin film transistor T1 is electrically connected to the corresponding Data line Data, the drain of the first thin film transistor T1 is electrically connected to the first plate of the main region liquid crystal capacitor Clc-main and the first plate of the main region storage capacitor Cst-main, and the main region liquid crystal capacitor Clc-main and the main region storage capacitor Cst-main are respectively formed between the pixel electrode of the main pixel region 100 of the sub-pixel and the first common electrode and the second common electrode.
Specifically, the second plate of the main region storage capacitor Cst-main is electrically connected to the main region pixel electrode, and the second plate of the main liquid crystal capacitor Clc-main is electrically connected to the common electrode.
In the sub-pixel region 200 of the sub-pixel, the Gate of the second thin film transistor T2 is connected to the corresponding scan line Gate, the source of the second thin film transistor T2 is connected to the corresponding Data line Data, and the drain of the second thin film transistor T2 is connected to the first plate of the sub-region liquid crystal capacitor Clc-sub and the first plate of the sub-region storage capacitor Cst-sub, wherein a main region liquid crystal capacitor Clc-main and a main region storage capacitor Cst-main are respectively formed between the pixel electrode of the sub-pixel region 200 of the sub-pixel and the first and second common electrodes.
Specifically, the second plate of the sub-region storage capacitor Cst-sub is electrically connected to the sub-region pixel electrode, and the second plate of the sub-region liquid crystal capacitor Clc-sub is electrically connected to the common electrode.
In this embodiment, the Gate of the third tft T3 is connected to the corresponding scan line Gate, the source of the third tft T3 is connected to the drain of the second tft T2, and the drain 52 of the third tft T3 is connected to the data line 71 without black matrix.
In the embodiment, a preset electrode in the existing 3T pixel unit design is omitted, and the drain electrode of the third thin film transistor T3 for pulling down the voltage of the sub-pixel region 200 of the sub-pixel is connected with the data line 71 without a black matrix, so that the pixel aperture ratio and the transmittance are increased; meanwhile, the functions of reducing the voltage of the auxiliary pixel area and improving the color cast of a large visual angle are realized; and because the preset electrode is omitted, the phenomenon that the production yield is reduced because the light line is poor possibly caused by foreign matters between the preset electrode and the common electrode metal is avoided, and the electrical stability of the structural design of the 3T pixel unit is improved.
Example two
The embodiment also provides a display panel comprising the array substrate.
The array substrate has already been described in detail in the above embodiments, and the description is not repeated here.
The application provides an array substrate and a display panel. The array substrate comprises a plurality of scanning lines, a plurality of data lines without black matrixes and a plurality of sub-pixels, wherein the data lines are positioned above the data lines, and the sub-pixels are defined by the crossing of the scanning lines and the data lines; each sub-pixel is divided into a main pixel area and a sub-pixel area, a scanning line is respectively arranged corresponding to each row of sub-pixels, and the scanning line is arranged between the main pixel area and the sub-pixel area; the main pixel region comprises a first thin film transistor, a main region storage capacitor and a main region liquid crystal capacitor, and the auxiliary pixel region comprises a second thin film transistor, a third thin film transistor, an auxiliary region storage capacitor and an auxiliary region liquid crystal capacitor; and the drain electrode of the third thin film transistor is connected with the data line without the black matrix.
According to the pixel structure, the drain electrode of the third thin film transistor is connected with the data line (DBS) electrode line without the black matrix, so that the pixel aperture opening ratio is increased, a preset electrode is omitted, and the probability of pixel failure can be effectively reduced.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The array substrate and the display panel provided by the embodiments of the present application are described in detail above, and the principles and embodiments of the present application are described herein by applying specific examples, and the description of the embodiments is only used to help understand the method and the core concept of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. The array substrate is characterized by comprising a plurality of scanning lines extending along the horizontal direction, a plurality of data lines extending along the vertical direction, a plurality of data lines without black matrixes and a plurality of sub-pixels, wherein the data lines are positioned above the data lines;
each sub-pixel is divided into a main pixel area and a sub-pixel area, a scanning line is respectively arranged corresponding to each row of sub-pixels, and the scanning line is arranged between the main pixel area and the sub-pixel area
The main pixel area of the sub-pixel comprises a first thin film transistor, a main area storage capacitor and a main area liquid crystal capacitor, and the auxiliary pixel area of the sub-pixel comprises a second thin film transistor, a third thin film transistor, an auxiliary area storage capacitor and an auxiliary area liquid crystal capacitor;
and the drain electrode of the third thin film transistor is connected with the data line without the black matrix.
2. The array substrate of claim 1, wherein the array substrate comprises:
a substrate base plate;
the first metal layer is positioned on the substrate and comprises the scanning line, a grid electrode of the first thin film transistor, a grid electrode of the second thin film transistor and a grid electrode of the third thin film transistor;
the second metal layer is positioned on one side of the first metal layer, which is far away from the substrate base plate, and comprises the data line, the source electrode and the drain electrode of the first thin film transistor, the source electrode and the drain electrode of the second thin film transistor and the source electrode and the drain electrode of the third thin film transistor;
and the transparent electrode layer is positioned on one side of the second metal layer far away from the first metal layer, and comprises pixel electrodes arranged at intervals and data lines without black matrixes, and each pixel electrode comprises a main area pixel electrode arranged in a main pixel area corresponding to the sub-pixel and a sub-area pixel electrode arranged in a sub-pixel area corresponding to the sub-pixel.
3. The array substrate of claim 2, further comprising an insulating layer and an active layer between the first metal layer and the second metal layer, a passivation layer between the second metal layer and the transparent electrode layer; and a through hole is formed in the passivation layer, and the data line without the black matrix is connected with the drain electrode of the third thin film transistor T3 through the through hole.
4. The array substrate of claim 3, wherein a gate of the third thin film transistor is electrically connected to the corresponding scan line, and a source of the third thin film transistor is electrically connected to a drain of the second thin film transistor.
5. The array substrate of claim 2, wherein a gate of the first thin film transistor is electrically connected to the corresponding scan line, a source of the first thin film transistor is electrically connected to the corresponding data line, and a drain of the first thin film transistor is electrically connected to the first plate of the main area liquid crystal capacitor and the first plate of the main area storage capacitor.
6. The array substrate of claim 5, wherein the second plate of the main region storage capacitor is electrically connected to the main region pixel electrode and the second plate of the main liquid crystal capacitor is electrically connected to the common electrode.
7. The array substrate of claim 2, wherein the gate electrode of the second thin film transistor is electrically connected to the corresponding scan line, the source electrode of the second thin film transistor is electrically connected to the corresponding data line, and the drain electrode of the second thin film transistor is electrically connected to the first plate of the sub-region liquid crystal capacitor and the first plate of the sub-region storage capacitor.
8. The array substrate of claim 7, wherein the second plate of the sub-region storage capacitor is electrically connected to the sub-region pixel electrode, and the second plate of the sub-region liquid crystal capacitor is electrically connected to the common electrode.
9. The array substrate of claim 1, wherein the data line without the black matrix includes a first portion and a second portion, the first portion being parallel to the data line, the second portion being disposed in an opening region of the corresponding sub-pixel; wherein the projection of the first portion overlaps with the corresponding data line, and the projection of the second portion overlaps with the corresponding scan line.
10. A display panel comprising the array substrate according to any one of claims 1 to 9.
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| CN202110366376.4A CN113311624A (en) | 2021-04-06 | 2021-04-06 | Array substrate and display panel |
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| CN202110366376.4A CN113311624A (en) | 2021-04-06 | 2021-04-06 | Array substrate and display panel |
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| CN114002884A (en) * | 2021-09-30 | 2022-02-01 | 惠科股份有限公司 | Array substrate, display panel and display |
| CN114114768A (en) * | 2021-12-07 | 2022-03-01 | 深圳市华星光电半导体显示技术有限公司 | Pixel, array substrate and display device |
| CN114236924A (en) * | 2021-12-14 | 2022-03-25 | Tcl华星光电技术有限公司 | Display panel and mobile terminal |
| CN114236925A (en) * | 2021-12-14 | 2022-03-25 | 苏州华星光电技术有限公司 | Array substrate and liquid crystal display panel |
| CN114265249A (en) * | 2021-12-16 | 2022-04-01 | Tcl华星光电技术有限公司 | Array substrate and display terminal |
| CN114509903A (en) * | 2022-02-10 | 2022-05-17 | 武汉华星光电技术有限公司 | Display panel |
| CN114755865A (en) * | 2022-04-19 | 2022-07-15 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| CN115145082A (en) * | 2022-07-18 | 2022-10-04 | 滁州惠科光电科技有限公司 | Pixel structure, array substrate and display panel |
| CN116413962A (en) * | 2023-06-09 | 2023-07-11 | 深圳市华星光电半导体显示技术有限公司 | Liquid crystal display panel, preparation method thereof and liquid crystal display device |
| WO2023206295A1 (en) * | 2022-04-28 | 2023-11-02 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor, liquid crystal display panel and display device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106950768A (en) * | 2017-03-03 | 2017-07-14 | 深圳市华星光电技术有限公司 | Pixel cell and its driving method |
| CN107065350A (en) * | 2017-04-10 | 2017-08-18 | 深圳市华星光电技术有限公司 | Eight farmland 3T dot structures |
| CN109298574A (en) * | 2018-11-20 | 2019-02-01 | 深圳市华星光电技术有限公司 | A kind of array substrate and display panel |
| CN111208688A (en) * | 2020-02-27 | 2020-05-29 | 深圳市华星光电半导体显示技术有限公司 | Array substrate |
-
2021
- 2021-04-06 CN CN202110366376.4A patent/CN113311624A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106950768A (en) * | 2017-03-03 | 2017-07-14 | 深圳市华星光电技术有限公司 | Pixel cell and its driving method |
| CN107065350A (en) * | 2017-04-10 | 2017-08-18 | 深圳市华星光电技术有限公司 | Eight farmland 3T dot structures |
| CN109298574A (en) * | 2018-11-20 | 2019-02-01 | 深圳市华星光电技术有限公司 | A kind of array substrate and display panel |
| CN111208688A (en) * | 2020-02-27 | 2020-05-29 | 深圳市华星光电半导体显示技术有限公司 | Array substrate |
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| CN114114768A (en) * | 2021-12-07 | 2022-03-01 | 深圳市华星光电半导体显示技术有限公司 | Pixel, array substrate and display device |
| CN114114768B (en) * | 2021-12-07 | 2023-06-30 | 深圳市华星光电半导体显示技术有限公司 | Pixel, array substrate and display device |
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| CN114265249A (en) * | 2021-12-16 | 2022-04-01 | Tcl华星光电技术有限公司 | Array substrate and display terminal |
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| WO2023206295A1 (en) * | 2022-04-28 | 2023-11-02 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor, liquid crystal display panel and display device |
| CN115145082A (en) * | 2022-07-18 | 2022-10-04 | 滁州惠科光电科技有限公司 | Pixel structure, array substrate and display panel |
| CN116413962A (en) * | 2023-06-09 | 2023-07-11 | 深圳市华星光电半导体显示技术有限公司 | Liquid crystal display panel, preparation method thereof and liquid crystal display device |
| CN116413962B (en) * | 2023-06-09 | 2023-10-13 | 深圳市华星光电半导体显示技术有限公司 | Liquid crystal display panel, preparation method thereof and liquid crystal display device |
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