CN114002884A - Array substrate, display panel and display - Google Patents
Array substrate, display panel and display Download PDFInfo
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- CN114002884A CN114002884A CN202111169003.4A CN202111169003A CN114002884A CN 114002884 A CN114002884 A CN 114002884A CN 202111169003 A CN202111169003 A CN 202111169003A CN 114002884 A CN114002884 A CN 114002884A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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Abstract
The invention discloses an array substrate, a display panel and a display, and relates to the technical field of liquid crystal display. The array substrate comprises a plurality of scanning lines, a plurality of data lines and a plurality of sub-pixels distributed in an array manner, each sub-pixel is connected with the corresponding scanning line and data line, each sub-pixel comprises a main pixel area and a sub-pixel area, the main pixel area and the sub-pixel area respectively comprise a plurality of pixel capacitors, each pixel capacitor is connected with the scanning line and the data line connected with the corresponding sub-pixel, and each sub-pixel at least comprises three pixel capacitors; the pixel capacitors are different in charging voltage after being charged based on the corresponding data lines. According to the invention, the main pixel area and the sub-pixels in each sub-pixel are further divided, each divided area corresponds to one pixel capacitor, and the charging voltages of the pixel capacitors after charging based on the corresponding data lines are different, so that each sub-pixel obtains more voltage division intervals, and the visual angle width of the display panel is improved.
Description
Technical Field
The invention relates to the technical field of liquid crystal display, in particular to an array substrate, a display panel and a display.
Background
At present, in order to improve the viewing angle in a large-sized display device, a VA (Vertical Alignment or Vertical Alignment) display mode is mainly adopted, and a wide viewing angle of liquid crystal is realized by a multi-domain technology.
Disclosure of Invention
The invention mainly aims to provide an array substrate, a display panel and a display, and aims to solve the technical problem that the viewing angle of the display panel is narrow in the prior art.
In order to achieve the above object, the present invention provides an array substrate, where the array substrate includes a plurality of scan lines, a plurality of data lines, and a plurality of sub-pixels distributed in an array, each sub-pixel is connected to a corresponding scan line and data line, each sub-pixel includes a main pixel area and a sub-pixel area, each of the main pixel area and the sub-pixel area includes a plurality of pixel capacitors, each of the pixel capacitors is connected to the scan line and the data line connected to the corresponding sub-pixel, and each of the sub-pixels includes at least three pixel capacitors;
the pixel capacitors are different in charging voltage after being charged based on the corresponding data lines.
Optionally, the facing areas of the pixel capacitors in the sub-pixels are different.
Optionally, the array substrate further includes a plurality of thin film transistors, each pixel capacitor is electrically connected to one thin film transistor, and channel length-width ratios of the thin film transistors corresponding to the pixel capacitors in each sub-pixel are different.
Optionally, a transition metal portion is disposed between the source metal portion and the drain metal portion of the thin film transistor, the transition metal portion is not in contact with the source metal portion and the drain metal portion, and the transition metal portion is disposed on the same layer as the source metal portion and the drain metal portion.
Optionally, the main pixel area includes a first pixel capacitor and a second pixel capacitor, the sub-pixel area includes a third pixel capacitor and a fourth pixel capacitor, and the facing areas of the first pixel capacitor, the second pixel capacitor, the third pixel capacitor and the fourth pixel capacitor are different from each other.
Optionally, the first pixel capacitor and the second pixel capacitor are symmetrically arranged with respect to a column-direction center line of the main pixel region, and the third pixel capacitor and the fourth pixel capacitor are symmetrically arranged with respect to a column-direction center line of the sub-pixel region.
Optionally, the first pixel capacitor is electrically connected to the first thin film transistor, the second pixel capacitor is electrically connected to the second thin film transistor, the third pixel capacitor is electrically connected to the third thin film transistor, the fourth pixel capacitor is electrically connected to the fourth thin film transistor, and channel length-width ratios of the first thin film transistor, the second thin film transistor, the third thin film transistor, and the fourth thin film transistor are different from each other.
Optionally, the alignment electrode corresponding to each pixel capacitor has multiple directions.
In order to achieve the above object, the present invention further provides a display panel, which includes a data driving circuit, a scan driving circuit, and the array substrate as described above, wherein the array substrate is connected to the data driving circuit and the scan driving circuit.
In order to achieve the above object, the present invention further provides a display, which includes the display panel and a backlight module, wherein the backlight module is disposed on a back surface of the display panel, and the backlight module is used for providing a backlight source for the display panel.
The array substrate comprises a plurality of scanning lines, a plurality of data lines and a plurality of sub-pixels distributed in an array manner, wherein each sub-pixel is connected with the corresponding scanning line and data line, each sub-pixel comprises a main pixel area and a sub-pixel area, the main pixel area and the sub-pixel area respectively comprise a plurality of pixel capacitors, each pixel capacitor is connected with the scanning line and the data line connected with the corresponding sub-pixel, and each sub-pixel at least comprises three pixel capacitors; the pixel capacitors are different in charging voltage after being charged based on the corresponding data lines. According to the invention, the main pixel area and the sub-pixels in each sub-pixel are further divided, each divided area corresponds to one pixel capacitor, and the charging voltages of the pixel capacitors after charging based on the corresponding data lines are different, so that each sub-pixel obtains more voltage division intervals, and the visual angle width of the display panel is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
Fig. 1 is an equivalent schematic view of a pixel structure of a first embodiment of an array substrate according to the invention;
FIG. 2 is a schematic diagram of liquid crystal molecules relative to a human eye;
FIG. 3 is a schematic plan view of a pixel structure of a second embodiment of an array substrate according to the invention;
FIG. 4 is a schematic plan view of a TFT according to an embodiment of the present invention;
FIG. 5 is a schematic plan view of a TFT according to another embodiment of the present invention;
FIG. 6 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a display panel according to an embodiment of the invention.
The reference numbers illustrate:
| reference numerals | Name (R) | Reference numerals | Name (R) |
| 10 | |
100 | |
| 20 | |
110 | |
| 30 | |
120 | |
| 40 | |
130 | |
| 50 | |
140 | |
| 60 | |
150 | |
| 70 | |
160 | |
| 80 | Source metal part | T1～T4 | First to fourth |
| 90 | Drain metal portion | C1～C4 | First to fourth liquid crystal capacitors |
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that all the directional indicators (such as up, down, left, right, front, and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the movement situation, etc. in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly.
In addition, the descriptions related to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions in the embodiments may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should be considered to be absent and not within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is an equivalent schematic diagram of a pixel structure of an array substrate according to a first embodiment of the invention. The invention provides a first embodiment of an array substrate.
In the first embodiment, the array substrate includes a plurality of scan lines 10, a plurality of data lines 20, and a plurality of sub-pixels distributed in an array, each sub-pixel is connected to a corresponding scan line 10 and data line 20, each sub-pixel includes a main pixel region 30 and a sub-pixel region 40, each of the main pixel region 30 and the sub-pixel region 40 includes a plurality of pixel capacitors 50, each of the pixel capacitors 50 is connected to the scan line 10 and the data line 20 connected to the corresponding sub-pixel, and each sub-pixel includes at least three pixel capacitors 50; the pixel capacitors 50 are different in charging voltage after being charged based on the corresponding data lines 20.
It is understood that the sub-pixels can be a red pixel, a green pixel and a blue pixel, the sub-pixels are distributed in an array, and three adjacent pixels in each row are pixels with different colors; wherein the pixels of each row are driven by one scanning line 10 and the pixels of each column are driven by one data line 20. Of course, the sub-pixels may also include pixels of other colors, such as yellow pixels, and the like, which is not limited in this embodiment.
In the present embodiment, each sub-pixel includes a main pixel area 30 and a sub-pixel area 40, the main pixel area 30 and the sub-pixel area 40 further include a plurality of pixel capacitors 50, and each sub-pixel includes at least three pixel capacitors 50. For example, the main pixel region 30 may include one pixel capacitor 50, and the sub-pixel region 40 includes two or more pixel capacitors 50; or the main pixel region 30 may include two or more pixel capacitors 50, and the sub-pixel region 40 includes one pixel capacitor 50; or the main pixel region 30 and the sub-pixel region 40 each include two or more pixel capacitors 50. The pixel capacitors 50 are connected to the corresponding scan lines 10 and data lines 20 through the thin film transistors 60, specifically, each pixel capacitor 50 is connected to the drain of the thin film transistor 60, the gate of the thin film transistor 60 is connected to the scan line 10, the source of the thin film transistor 60 is connected to the data line 20, and each pixel capacitor 50 in each sub-pixel shares the same scan line 10 and the same data line 20.
It is understood that, during the pixel driving, the gate of the thin film transistor 60 is in a conducting state when receiving a high level signal on the scan line 10, and the pixel capacitor 50 receives the data voltage on the data line 20 via the thin film transistor 60. During the on-time of the thin film transistor 60, the pixel capacitor 50 enters a charging process, and its voltage gradually increases until the thin film transistor 60 is turned off. With sufficient on-time, the voltage amplitude of the pixel capacitance 50 stabilizes at the amplitude of the data voltage. In this embodiment, the charging voltage refers to the voltage of the pixel capacitor 50 when the thin film transistor 60 is turned off, and is generally equal to the data voltage.
Referring to fig. 2, fig. 2 is a schematic diagram of liquid crystal molecules relative to human eyes. The liquid crystal molecules 70 have the highest short axis light transmittance, and when the liquid crystal molecules 70 having different deflection angles exist in the display panel, a user can make the human eyes directly face the short axes of some of the liquid crystal molecules 70 even if looking at the display panel from different angles. When the display panel is viewed from the front by human eyes, the short axes of the liquid crystal molecules 70 positioned in the middle face the human eyes, and when the display panel is viewed from the side by the human eyes, the short axes of the liquid crystal molecules 70 positioned at the two sides face the human eyes, so that a wide viewing angle is realized. Therefore, the larger the deflection angle of the liquid crystal molecules 70 in the display panel, the wider the viewing angle of the display panel.
In general, to make the liquid crystal molecules 70 have different deflection directions, different initial orientations may be set for the liquid crystal molecules 70 to form a multi-domain structure for the pixel, and the liquid crystal molecules 70 are deflected under the influence of a charging voltage across the pixel capacitor 50 to obtain different deflection directions. For example, taking a conventional eight-domain structure as an example, the alignment electrodes corresponding to the main pixel region 30 and the sub-pixel region 40 have 4 alignment directions, a shared transistor and a shared electrode are additionally disposed in the sub-pixel region 40, and the sub-pixel region 40 is connected to the shared electrode through the shared transistor, so as to implement voltage division, so that the main pixel region 30 and the sub-pixel region 40 have different charging voltages, and thus the sub-pixel has 8 liquid crystal molecules with different deflection directions. However, the above-mentioned method adds the shared electrode, which is usually disposed in the opening area, so as to reduce the aperture ratio of the pixel, reduce the transmittance of the light through the display panel, and is not favorable for the image display of the display panel.
In this embodiment, the sharing transistor and the sharing electrode are eliminated, and the charging voltage of each pixel capacitor 50 is varied to realize different deflection directions of the liquid crystal molecules, thereby realizing a wide viewing angle of the display panel and improving the aperture ratio.
In a specific implementation, the charging voltage of the pixel capacitor 50 is mainly affected by the data voltage on the data line 20, the charging rate, the charging time, the capacitance parameter, and other factors. The data voltage is converted according to the video data, and the charging time is related to the scanning time corresponding to the scanning signal on the scanning line 10. Since the pixel capacitors 50 share the same scan line 10 and the same data line 20, the data voltages and the charging time corresponding to the pixel capacitors 50 are the same, and the charging rate and/or the capacitor parameters can be adjusted at the same time, so that the charging voltages of the pixel capacitors 50 after charging are different.
It can be understood that the formula according to capacitance is: c ═ epsilon S/D; wherein epsilon is a dielectric constant, D is an electrode distance, and S is an area; in the display panel, the electrode distances D of the pixel capacitors 50 are equal, and thus different capacitance values C can be obtained by adjusting the areas S. Meanwhile, as can be seen from the capacitance formula V — Q/C, the charge amount Q is inversely proportional to the capacitance value C when the voltages are the same. In a specific implementation, the pixel capacitors 50 may have different capacitance values C by setting the facing areas of the pixel capacitors 50 to different values, so that the charging voltages of the pixel capacitors 50 after being charged based on the corresponding data lines 20 are different.
It should be noted that the charging rate of the pixel capacitor 50 is mainly related to the performance of the corresponding tft 60. Therefore, similarly, the charging rate of each pixel capacitor 50 can be made different by adjusting the performance of the thin film transistor 60, and the charging voltage of each pixel capacitor 50 after charging based on the corresponding data line 20 is also made different for the same charging time. The performance of the thin film transistor 60 is mainly related to the channel length/width ratio, so that the channel length/width ratio of the thin film transistor 60 corresponding to each pixel capacitor 50 can be made different, and thus each thin film transistor 60 has a different charging rate.
In this embodiment, in order to further improve the viewing angle of the display panel, the alignment electrode corresponding to each pixel capacitor 50 has a plurality of directions; for example, the alignment electrode corresponding to the pixel capacitor 50 may have one of a two-domain structure, a four-domain structure, or a two-domain structure. If the number of the pixel capacitors 50 in each sub-pixel is three, and the alignment electrodes corresponding to the pixel capacitors 50 are all four directions, the liquid crystal molecules in the display panel have 12 deflection directions. Therefore, the present embodiment can further improve the viewing angle of the display panel in addition to the conventional multi-domain structure.
In the first embodiment, the array substrate includes a plurality of scan lines 10, a plurality of data lines 20, and a plurality of sub-pixels distributed in an array, each sub-pixel is connected to a corresponding scan line 10 and data line 20, each sub-pixel includes a main pixel region 30 and a sub-pixel region 40, each of the main pixel region 30 and the sub-pixel region 40 includes a plurality of pixel capacitors 50, each of the pixel capacitors 50 is connected to the scan line 10 and the data line 20 connected to the corresponding sub-pixel, and each sub-pixel includes at least three pixel capacitors 50; the pixel capacitors 50 are different in charging voltage after being charged based on the corresponding data lines 20. In the present embodiment, the main pixel region 30 and the sub-pixel region 40 in each sub-pixel are further divided, each divided region corresponds to one pixel capacitor 50, and the charging voltages of the pixel capacitors 50 after being charged based on the corresponding data lines 20 are different, so that each sub-pixel obtains more voltage division regions, and the viewing angle range of the display panel is improved.
Referring to fig. 3, fig. 3 is a schematic plan view of a pixel structure of an array substrate according to a second embodiment of the invention. Based on the first embodiment, the invention provides a second embodiment of the array substrate.
In the second embodiment, the number of the pixel capacitors 50 in the main pixel region 30 and the sub-pixel region 40 is two. The main pixel region 30 includes a first pixel capacitance C1 and a second pixel capacitance C2, and the sub-pixel region 40 includes a third pixel capacitance C3 and a fourth pixel capacitance C4. The first pixel capacitor C1 is electrically connected to the first tft T1, the second pixel capacitor C2 is electrically connected to the second tft T2, the third pixel capacitor C3 is electrically connected to the third tft T3, and the fourth pixel capacitor C4 is electrically connected to the fourth tft T4.
It should be noted that the schematic plan view of the pixel structure in fig. 3 only shows one side of the alignment electrode of the pixel capacitor 50. That is, the alignment electrode of the first pixel capacitor C1 is connected to the drain metal of the first thin film transistor T1, the alignment electrode of the second pixel capacitor C2 is connected to the drain metal of the second thin film transistor T2, the alignment electrode of the third pixel capacitor C3 is connected to the drain metal of the third thin film transistor T3, and the alignment electrode of the fourth pixel capacitor C4 is connected to the drain metal of the fourth thin film transistor T4. The gates of the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4 are connected to the scan line 10, and the sources of the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4 are connected to the data line 20.
In this embodiment, the positive-to-surface areas of the first pixel capacitance C1, the second pixel capacitance C2, the third pixel capacitance C3, and the fourth pixel capacitance C4 are different from each other; wherein, the opposite area is the area of projection overlap between the orientation electrode and the common electrode. Different facing areas are obtained by dividing the areas of the alignment electrodes of the first pixel capacitor C1, the second pixel capacitor C2, the third pixel capacitor C3 and the fourth pixel capacitor C4. Each alignment electrode has 4 alignment directions, and the alignment directions of the alignment electrodes may be set as needed, which is not limited in this embodiment.
For example, the facing area ratio of the first pixel capacitor C1, the second pixel capacitor C2, the third pixel capacitor C3 and the fourth pixel capacitor C4 is 2: 3: 4: 5. according to the capacitance formula: c ═ es/D, the capacitance ratio of the first pixel capacitance C1, the second pixel capacitance C2, the third pixel capacitance C3, and the fourth pixel capacitance C4 is 2: 3: 4: 5. according to the capacitance formula V ═ Q/C, when the data voltage is constant, the charge Q can be charged into each pixel in a unit time, and the voltage ratio that the first pixel capacitor C1, the second pixel capacitor C2, the third pixel capacitor C3 and the fourth pixel capacitor C4 can divide into 30: 20: 15: 12. therefore, the first pixel capacitor C1, the second pixel capacitor C2, the third pixel capacitor C3 and the fourth pixel capacitor C4 can drive the corresponding liquid crystal molecules to deflect to different angles, and further, the effect of enhancing the viewing angle at different angles is achieved; specifically, in the present embodiment, when all the alignment electrodes have 4 kinds of alignment directions, the liquid crystal molecules 70 can be deflected in 16 kinds of directions.
In this embodiment mode, in order to further improve the difference between the liquid crystal deflection angles, the channel aspect ratios of the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4 may be made different from each other. The larger the channel aspect ratio, the higher the charging performance of the transistor, and therefore, the channel aspect ratio of the first thin film transistor T1 may be made larger than the channel aspect ratio of the second thin film transistor T2, the channel aspect ratio of the second thin film transistor T2 may be made larger than the channel aspect ratio of the third thin film transistor T3, and the channel aspect ratio of the third thin film transistor T3 may be made larger than the channel aspect ratio of the fourth thin film transistor T4, thereby further enlarging the difference in charging voltage among the first pixel capacitor C1, the second pixel capacitor C2, the third pixel capacitor C3, and the fourth pixel capacitor C4.
In this embodiment, to ensure the display effect, the first pixel capacitor C1 and the second pixel capacitor C2 are symmetrically disposed with respect to the column-directional center line of the main pixel region 30, and the third pixel capacitor C3 and the fourth pixel capacitor C4 are symmetrically disposed with respect to the column-directional center line of the sub pixel region 40.
The first pixel capacitor C1, the second pixel capacitor C2, the third pixel capacitor C3 and the fourth pixel capacitor C4 are laterally symmetrical, and the liquid crystal molecules 70 with different deflection angles can be symmetrically distributed. Since the first pixel capacitor C1 and the second pixel capacitor C2 need to share the scan line 10 and the data line 20, and the alignment electrodes of both need to be close to the metal of the scan line 10 and the data line 20, the alignment electrode of the first pixel capacitor C1 can be made to half-surround the alignment electrode of the second pixel capacitor C2, so that the liquid crystal molecules 70 with different deflection angles in the main pixel region 30 are more uniformly distributed, and the sub-pixel region 40 is the same.
In the second embodiment, the main pixel region 30 includes a first pixel capacitance C1 and a second pixel capacitance C2, and the sub pixel region 40 includes a third pixel capacitance C3 and a fourth pixel capacitance C4. The first pixel capacitor C1 is electrically connected to the first tft T1, the second pixel capacitor C2 is electrically connected to the second tft T2, the third pixel capacitor C3 is electrically connected to the third tft T3, and the fourth pixel capacitor C4 is electrically connected to the fourth tft T4. The positive-to-surface areas of the first pixel capacitor C1, the second pixel capacitor C2, the third pixel capacitor C3 and the fourth pixel capacitor C4 are different from each other; channel aspect ratios of the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4 are different from each other. In this embodiment, the main pixel region 30 and the sub-pixel region 40 can realize different voltage division differences, so that the liquid crystal molecules 70 have more deflection directions, and the viewing angle width is improved.
Referring to fig. 4, fig. 4 is a schematic plan view of a thin film transistor according to an embodiment of the present invention. Based on the first embodiment and the second embodiment, the present invention provides a third embodiment of an array substrate.
In the third embodiment, the thin film transistor 50 on the array substrate includes a source metal portion 80, a drain metal portion 90, and a gate metal portion 100; a transition metal portion 110 is disposed between the source metal portion 80 and the drain metal portion 90, the transition metal portion 110 is not in contact with the source metal portion 80 and the drain metal portion 90, and the transition metal portion 110 is disposed in the same layer as the source metal portion 80 and the drain metal portion 90.
Note that the channel aspect ratio of the thin film transistor 50 refers to a ratio of a length to a width of a channel of the thin film transistor 50; here, the channel of the thin film transistor 50 refers to a portion opposing between the source metal portion 80 and the drain metal portion 90. When the thin film transistor 50 conducts electricity, electrons in the active layer flow in a channel between the source metal portion 80 and the drain metal portion 90. Therefore, the larger the channel aspect ratio of the thin film transistor 50, the higher the conductivity of the thin film transistor 50, and the faster the charging speed of the corresponding pixel capacitor 50.
In particular implementations, the performance of the thin film transistor 50 may be adjusted by adjusting the relative length (i.e., channel length) between the source metal portion 80 and the drain metal portion 90 of the thin film transistor 50, or the distance (i.e., channel width) between the source metal portion 80 and the drain metal portion 90.
In the present embodiment, a transition metal portion 110 is disposed between the source metal portion 80 and the drain metal portion 90, and the material of the transition metal portion 110 may be the same as the source metal portion 80 and the drain metal portion, such as copper or aluminum. The transition metal portion 110 may function to conduct electricity, thereby improving the conductivity of the thin film transistor 50.
It will be appreciated that the addition of the transition metal portion 110, the source metal portion 80 and the drain metal portion 90, results in the channel being divided into two portions having a channel width less than half the channel width without the transition metal portion 110, and a length that does not vary much. Thus, increasing the transition metal portion 110 corresponds to increasing the overall channel aspect ratio of the thin film transistor 50.
Referring to fig. 5, fig. 5 is a schematic plan view of a thin film transistor according to another embodiment of the present invention. In fig. 5, the source metal portion 80 and the drain metal portion 90 of the whole tft 50 are two parallel metals, a transition metal portion 110 is disposed between the source metal portion 80 and the drain metal portion 90, and the transition metal portion 110 is parallel to the source metal portion 80 and the drain metal portion 90.
It should be noted that the thin film transistor structure shown in fig. 5 occupies a smaller space area than the thin film transistor structure shown in fig. 4, and is suitable for the design of the small-sized thin film transistor 50. However, the channel length to width ratio, i.e., the conductivity, of the thin-film transistor structure shown in fig. 5 is smaller, i.e., lower, than that of the thin-film transistor structure shown in fig. 4. Therefore, the transition metal portion 110 is disposed in the thin film transistor structure shown in fig. 5, so that the conductivity can be greatly improved, and the application of the thin film transistor 50 is improved.
It should be noted that, since the transition metal portion 110 can adjust the channel aspect ratio of the thin film transistor 50, the length and/or width of the transition metal portion 110 can also be adjusted to make each thin film transistor 50 have different conductive performance. In a specific implementation, each tft 50 corresponding to each pixel capacitor 50 in the sub-pixel may have the same size parameter of the source metal portion 80, the drain metal portion 90, and the gate metal portion 100, and have different size parameters of the transition metal portion 110, so that each tft 50 has different conductivity, and the charging voltage of each pixel capacitor 50 after charging is adjusted.
In the third embodiment, the thin film transistor 50 includes a source metal portion 80, a drain metal portion 90, and a gate metal portion 100; a transition metal portion 110 is disposed between the source metal portion 80 and the drain metal portion 90, the transition metal portion 110 is not in contact with the source metal portion 80 and the drain metal portion 90, and the transition metal portion 110 is disposed in the same layer as the source metal portion 80 and the drain metal portion 90. In the present embodiment, the transition metal portion 110 is disposed between the source metal portion 80 and the drain metal portion 90 to improve the conductivity of the thin film transistor 50, and different size parameters of the transition metal portion 110 can be set in each thin film transistor 50, so that each thin film transistor 50 has different conductivity, which is beneficial to implementing a larger interval of voltage division for the pixel capacitor 50 and improving the viewing angle of the display panel.
In order to achieve the above object, the present invention further provides a display panel. Referring to fig. 6, fig. 6 is a schematic structural diagram of a display panel according to an embodiment of the invention. The display panel includes a data driving circuit 120, a scan driving circuit 130, and the array substrate 140 as described above, and the array substrate 140 is connected to the data driving circuit 120 and the scan driving circuit 130. The specific structure of the array substrate 140 refers to the above embodiments, and since the display panel can adopt the technical solutions of all the embodiments, the display panel at least has the beneficial effects brought by the technical solutions of the embodiments, and details are not repeated herein.
In order to achieve the above object, the present invention further provides a display. Referring to fig. 7, fig. 7 is a schematic structural diagram of a display according to an embodiment of the invention. The display includes the display panel 150 and the backlight module 160 as described above, the backlight module 160 is disposed on the back of the display panel 150, and the backlight module 160 is used for providing a backlight source for the display panel 150. The specific structure of the display panel 150 refers to the above embodiments, and since the display can adopt the technical solutions of all the embodiments, at least the beneficial effects brought by the technical solutions of the embodiments are achieved, and no further description is given here.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. An array substrate comprises a plurality of scanning lines, a plurality of data lines and a plurality of sub-pixels distributed in an array, wherein each sub-pixel is connected with the corresponding scanning line and the corresponding data line, and comprises a main pixel area and a sub-pixel area;
the pixel capacitors are different in charging voltage after being charged based on the corresponding data lines.
2. The array substrate of claim 1, wherein facing areas of the pixel capacitors in the sub-pixels are different.
3. The array substrate of claim 1, wherein the array substrate further comprises a plurality of thin film transistors, each pixel capacitor is electrically connected to one thin film transistor, and the channel length-to-width ratio of the thin film transistor corresponding to each pixel capacitor in each sub-pixel is different.
4. The array substrate of claim 3, wherein a transition metal portion is disposed between a source metal portion and a drain metal portion of the thin film transistor, the transition metal portion is not in contact with the source metal portion and the drain metal portion, and the transition metal portion is disposed in a same layer as the source metal portion and the drain metal portion.
5. The array substrate of claim 1, wherein the main pixel area comprises a first pixel capacitor and a second pixel capacitor, the sub-pixel area comprises a third pixel capacitor and a fourth pixel capacitor, and facing areas of the first pixel capacitor, the second pixel capacitor, the third pixel capacitor and the fourth pixel capacitor are different from each other.
6. The array substrate of claim 5, wherein the first pixel capacitor and the second pixel capacitor are symmetrically disposed with respect to a column-wise centerline of the main pixel region, and the third pixel capacitor and the fourth pixel capacitor are symmetrically disposed with respect to a column-wise centerline of the sub pixel region.
7. The array substrate of claim 5, wherein the first pixel capacitor is electrically connected to a first thin film transistor, the second pixel capacitor is electrically connected to a second thin film transistor, the third pixel capacitor is electrically connected to a third thin film transistor, the fourth pixel capacitor is electrically connected to a fourth thin film transistor, and channel aspect ratios of the first thin film transistor, the second thin film transistor, the third thin film transistor, and the fourth thin film transistor are different from each other.
8. The array substrate of any one of claims 1-7, wherein the alignment electrode for each pixel capacitor has multiple orientations.
9. A display panel comprising a data driving circuit, a scan driving circuit, and the array substrate of any one of claims 1 to 8, the array substrate being connected to the data driving circuit and the scan driving circuit.
10. A display, comprising the display panel of claim 9 and a backlight module, wherein the backlight module is disposed on a back surface of the display panel, and the backlight module is configured to provide a backlight source to the display panel.
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| CN114002884B (en) | 2022-10-21 |
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