CN105372892A - Array substrate and liquid crystal display panel - Google Patents
Array substrate and liquid crystal display panel Download PDFInfo
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- CN105372892A CN105372892A CN201510955722.7A CN201510955722A CN105372892A CN 105372892 A CN105372892 A CN 105372892A CN 201510955722 A CN201510955722 A CN 201510955722A CN 105372892 A CN105372892 A CN 105372892A
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- array base
- base palte
- pixel region
- electrically connected
- share
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
Abstract
The invention discloses an array substrate and a liquid crystal display panel. The array substrate comprises a plurality of scanning lines and a plurality of data lines. The scanning lines and the data lines are crossed to divide the array substrate into a plurality of pixel areas. Each pixel area comprises a main pixel area body and an auxiliary pixel area body. Each auxiliary pixel area body comprises a sharing capacitor, and the capacitance value of the sharing capacitor is sequentially decreased from the edge of the array substrate to the center of the array substrate. During display, the electric potential on each auxiliary pixel area body on the edge of the array substrate is smaller than the electric potential on each auxiliary pixel area body at the center, and therefore the luminance of each auxiliary pixel area body at the center of the array substrate is larger than the luminance of each auxiliary pixel area body on the edge, the aim of eliminating whitening on the two sides is achieved, and display quality is improved.
Description
Technical field
The present invention relates to LCD Technology field, particularly relate to a kind of array base palte and display panels.
Background technology
Liquid crystal display has that fuselage is thin, power saving, the many merits such as radiationless, be widely used.Liquid crystal display major part on existing market is backlight liquid crystal display, and it comprises display panels and backlight module; The principle of work of display panels places liquid crystal molecule in the middle of the glass substrate that two panels is parallel, and on two panels glass substrate, apply driving voltage to control the sense of rotation of liquid crystal molecule, so that the light refraction of backlight module is out produced picture.
In existing large scale liquid crystal display panel, the mode of bilateral turntable driving is generally taked to drive, due to the impact of delay circuit, the charge rate of display panels the right and left near the region of driving chip position can be caused higher than the charge rate of panel zone line, make that display panels the right and left is brighter and centre is darker, namely occurred the phenomenon whitened in the display panels left and right sides, this has a negative impact to the display quality of liquid crystal display.
Summary of the invention
The technical matters that the present invention mainly solves is to provide a kind of array base palte and display panels, can eliminate the phenomenon of display panels left and right sides whiting, improves display quality.
For solving the problems of the technologies described above, the technical scheme that the present invention adopts is: provide a kind of display panels, described display panels comprises:
Array base palte, comprising:
Multi-strip scanning line, is arranged on described array base palte;
A plurality of data lines, is arranged on described array base palte, and with described multi-strip scanning line, described a plurality of data lines intersects that described array base palte is divided into multiple pixel region mutually;
Color membrane substrates, is oppositely arranged with described array base palte;
Liquid crystal layer, is folded between described array base palte and described color membrane substrates;
Wherein, each described pixel region comprises main pixel region and time pixel region, each described pixel region comprises shares electric capacity, and along from the marginal position of described array base palte to the direction of the center of described array base palte, the described capacitance sharing electric capacity reduces successively, and when showing, the current potential on the secondary pixel region of the marginal position of described array base palte is less than the current potential on the secondary pixel region of the center of described array base palte.
Wherein, the described main pixel region in each described pixel region comprises:
Main switch element, be arranged on described array base palte, described main switch element comprises:
Grid, is electrically connected a corresponding sweep trace;
Source electrode, is electrically connected a corresponding data line;
Drain electrode;
Main pixel electrode, is arranged on described array base palte, and is electrically connected the described drain electrode of described main switch element;
Described pixel region in each described pixel region also comprises:
Secondary on-off element, is arranged on described array base palte, and described time on-off element comprises:
Grid, is electrically connected the sweep trace of described correspondence;
Source electrode, is electrically connected the data line of described correspondence;
Drain electrode;
Secondary pixel electrode, is arranged on described array base palte, and is electrically connected the described drain electrode of described on-off element;
Share on-off element, be arranged on described array base palte, described in share on-off element and comprise:
Grid, is electrically connected next sweep trace that the sweep trace of described correspondence is adjacent;
Source electrode, is electrically connected described pixel electrode;
Drain electrode;
Describedly share electric capacity, described in electric connection, share the described drain electrode of on-off element;
Wherein, when described next adjacent sweep trace is enabled, described in share switching elements conductive make described in share electric capacity and share electric charge on described pixel electrode.
Wherein, the described main pixel region area in each described pixel region is less than described pixel region area.
Wherein, described main switch element, described on-off element are thin film transistor (TFT) with described on-off element of sharing.
Wherein, along from the marginal position of described array base palte to the direction of the center of described array base palte, described in share electric capacity capacitance be at least two different capacitances.
For solving the problems of the technologies described above, the present invention also provides a kind of array base palte, and described array base palte comprises:
Multi-strip scanning line;
With described multi-strip scanning line, a plurality of data lines, intersects that described array base palte is divided into multiple pixel region mutually;
Wherein, each described pixel region comprises main pixel region and time pixel region, each described pixel region comprises shares electric capacity, and along from the marginal position of described array base palte to the direction of the center of described array base palte, the described capacitance sharing electric capacity reduces successively, and when showing, the current potential on the secondary pixel region of the marginal position of described array base palte is less than the current potential on the secondary pixel region of the center of described array base palte.
Wherein, the described main pixel region in each described pixel region comprises:
Main switch element, be arranged on described array base palte, described main switch element comprises:
Grid, is electrically connected a corresponding sweep trace;
Source electrode, is electrically connected a corresponding data line;
Drain electrode;
Main pixel electrode, is arranged on described array base palte, and is electrically connected the described drain electrode of described main switch element;
Described pixel region in each described pixel region also comprises:
Secondary on-off element, is arranged on described array base palte, and described time on-off element comprises:
Grid, is electrically connected the sweep trace of described correspondence;
Source electrode, is electrically connected the data line of described correspondence;
Drain electrode;
Secondary pixel electrode, is arranged on described array base palte, and is electrically connected the described drain electrode of described on-off element;
Share on-off element, be arranged on described array base palte, described in share on-off element and comprise:
Grid, is electrically connected next sweep trace that the sweep trace of described correspondence is adjacent;
Source electrode, is electrically connected described pixel electrode;
Drain electrode;
Describedly share electric capacity, described in electric connection, share the described drain electrode of on-off element;
Wherein, when described next adjacent sweep trace is enabled, described in share switching elements conductive make described in share electric capacity and share electric charge on described pixel electrode.
Wherein, the described main pixel region area in each described pixel region is less than described pixel region area.
Wherein, described main switch element, described on-off element are thin film transistor (TFT) with described on-off element of sharing.
Wherein, along from the marginal position of described display panels to the direction of the center of described display panels, described in share electric capacity capacitance be at least two different capacitances.
The invention has the beneficial effects as follows: the situation being different from prior art, described array base palte of the present invention and display panels are by along from the marginal position of described array base palte to the direction of the center of described array base palte, the capacitance sharing electric capacity described in time pixel region described in each is reduced successively, thus the different capacitances sharing electric capacity described in passing through make the current potential of corresponding described pixel region different, and then make the brightness of the secondary pixel region of described array base palte center be greater than the brightness of the secondary pixel region of the marginal position of described array base palte, the object eliminating both sides whiting is reached with this, improve display quality.
Accompanying drawing explanation
Fig. 1 is the structural representation of array base palte of the present invention;
Fig. 2 is the equivalent circuit diagram of Fig. 1;
Fig. 3 is the structural representation of display panels of the present invention.
Embodiment
Referring to Fig. 1, is the structural representation of array base palte 1 of the present invention.As shown in Figure 1, described array base palte 1 is provided with multi-strip scanning line and a plurality of data lines, sweep trace and data line are located at the one side of the close liquid crystal layer of described array base palte 1, and a plurality of data lines and multi-strip scanning line intersect that described array base palte 1 is divided into multiple pixel region 2 mutually.Usually, arranged in parallel between a plurality of data lines, arranged in parallel between multi-strip scanning line, mutual square crossing between data line and sweep trace, in other embodiments, a plurality of data lines and multi-strip scanning line also can adopt other arrangement.
Please refer to Fig. 2, it is the equivalent circuit diagram of array base palte 1 of the present invention.Each pixel region 2 comprises main pixel region 21 and time pixel region 22, the brightness of each pixel region 2 is the mixing of the brightness of described main pixel region 21 and the brightness of described pixel region 22, the area of described main pixel region 21 is less than the area of described pixel region 22, electric capacity Cdown is shared because each described pixel region 22 comprises, the described electric capacity Cdown that shares shares electric charge on described pixel region 22, during to make display, current potential on described pixel region 22 is less than the current potential on described main pixel region 21, namely the brightness on described pixel region 22 is less than the brightness on described main pixel region 21, and when designing described array base palte 1 along from the marginal position of described array base palte 1 to the direction of the center of described array base palte 1, the described capacitance sharing electric capacity Cdown reduces successively, namely in the center of described array base palte 1, the described capacitance sharing electric capacity Cdown is minimum, at the marginal position of described array base palte 1, the described capacitance sharing electric capacity Cdown is maximum, because the described electric capacity Cdown that shares can drag down current potential on described pixel region 22, so just make described array base palte 1 marginal position due to the capacitance sharing electric capacity Cdown larger, larger to described the drop-down current potential of pixel region 22, described time pixel region 22 is darker, and in the centre position of described array base palte 1, because the described capacitance sharing electric capacity Cdown is less, less to described the drop-down current potential of pixel region 22, described time pixel region 22 opposite edges position is brighter, like this when actual displayed, the brightness of the secondary pixel region 22 of the center of described array base palte 1 is higher than the brightness of the secondary pixel region 22 of the marginal position of described array base palte 1, simultaneously due to the main pixel region 21 of the center of described array base palte 1 brightness ratio described in the brightness of main pixel region 21 of marginal position of array base palte 1 low, therefore after described main pixel region 21 with the luminance mix of described pixel region 22, make whole described array base palte 1 brightness throughout even, reach the object eliminating both sides whiting, improve display quality.
In the present embodiment, along from the marginal position of described array base palte 1 to the direction of the center of described array base palte 1, the described capacitance sharing electric capacity Cdown is at least two different capacitances, also can according to design needs, along the marginal position from described array base palte 1 to the direction of the center of described array base palte 1, the described capacitance sharing electric capacity Cdown is set to multiple different capacitance.
As shown in Figure 2, main pixel region 21 in each pixel region 2 comprises main switch element T1 and main pixel electrode 31, secondary pixel region 22 in each pixel region 2 comprises time on-off element T2 and secondary pixel electrode 32, described main switch element T1, described main pixel electrode 31, described on-off element T2 and described pixel electrode 32 are separately positioned on described array base palte 1, described main switch element T1 comprises grid, source electrode and drain electrode, the grid of described main switch element T1 is electrically connected a corresponding sweep trace G1, the source electrode of described main switch element T1 is electrically connected a corresponding data line D1, the drain electrode of described main switch element T1 is connected with main pixel electrode electrical 31.Described time on-off element T2 comprises grid, source electrode and drain electrode, the grid of described on-off element T2 is electrically connected corresponding sweep trace G1, the source electrode of described on-off element T2 is electrically connected corresponding data line D1, and drain electrode and described the pixel electrode 32 of described on-off element T2 are electrically connected.
In the present embodiment, described main pixel region 21 and described pixel region 22 include liquid crystal capacitance Clc and storage capacitors Cst, described liquid crystal capacitance Clc is formed by the liquid crystal layer of pixel electrode and public electrode and pixel electrode and public electrode centre, and described storage capacitors Cst is formed by the grid of on-off element and the insulation course of drain electrode and grid and drain electrode centre.
Described pixel region 22 also comprises to be shared on-off element T3 and shares electric capacity Cdown, the described on-off element T3 that shares comprises grid, source electrode and drain electrode, the described grid sharing on-off element T3 is electrically connected adjacent next sweep trace G2 of corresponding sweep trace G1, the described source electrode sharing on-off element T3 is electrically connected secondary pixel electrode 32 in described time corresponding pixel region 22, described in share on-off element T3 drain electrode electric connection described in share electric capacity Cdown.When adjacent next sweep trace G2 is enabled, described in share on-off element T3 conducting make described in share electric capacity Cdown and share electric charge on corresponding described pixel electrode 32.
In the present embodiment, described main switch element T1, described on-off element T2 and described in share on-off element T3 and be thin film transistor (TFT).
When display panels shows, when sweep signal is scanned up to sweep trace G1 corresponding to described main switch element T1 and described on-off element T2, namely the sweep trace G1 that described main switch element T1 and described on-off element T2 is corresponding is enabled, described main switch element T1 and described on-off element T2 conducting, described main pixel electrode 31 and described pixel electrode 32 charge to same potential simultaneously, at this moment described main pixel region 21 and described pixel region 22 have same brightness, subsequently, sweep signal is scanned up to the adjacent lower scan line G2 of above-mentioned corresponding sweep trace G1, namely this adjacent lower scan line G2 is enabled, described main switch element T1 and described on-off element T2 closes, on-off element T3 conducting is shared described in being connected with described sweep trace G2, share on electric capacity Cdown described in the Partial charge of described pixel electrode 32 is transferred to, when the described capacitance sharing electric capacity Cdown is different, then described pixel electrode 32 transfer to described in share electric charge on electric capacity Cdown also just different, namely when voltage is certain, the described capacitance sharing electric capacity Cdown is larger, and the electric charge shared described in transferring on electric capacity Cdown is more, current potential on described pixel electrode 32 is less, described time pixel region 22 is darker, otherwise, then described pixel region 22 is brighter, therefore, when along from the marginal position of described array base palte 1 to the direction of the center of described array base palte 1, when the described capacitance sharing electric capacity Cdown reduces successively, then the brightness of the secondary pixel region 22 of the center of described array base palte 1 is higher than the brightness of the secondary pixel region 22 of the marginal position of described array base palte 1, simultaneously due to the main pixel region 21 of the center of described array base palte 1 brightness ratio described in the brightness of main pixel region 21 of marginal position of array base palte 1 low, therefore after described main pixel region 21 with the luminance mix of described pixel region 22, make whole described array base palte 1 brightness throughout even, reach the object eliminating both sides whiting, improve display quality.
Referring to Fig. 3, is the schematic diagram of a kind of display panels 2 of the present invention.Described display panels 2 comprises described array base palte 1, liquid crystal layer 3 and color membrane substrates 4, and described liquid crystal layer 3 is arranged between described array base palte 1 and described color membrane substrates 4.
Described array base palte is by along from the marginal position of described array base palte to the direction of the center of described array base palte, the capacitance sharing electric capacity described in time pixel region described in each is reduced successively, thus the different capacitances sharing electric capacity described in passing through make the current potential of corresponding described pixel region different, and then make the brightness of the secondary pixel region of described array base palte center be greater than the brightness of the secondary pixel region of the marginal position of described array base palte, reach with this object eliminating both sides whiting, improve display quality.
The foregoing is only embodiments of the present invention; not thereby the scope of the claims of the present invention is limited; every utilize instructions of the present invention and accompanying drawing content to do equivalent structure or equivalent flow process conversion; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present invention.
Claims (10)
1. a display panels, is characterized in that, described display panels comprises:
Array base palte, comprising:
Multi-strip scanning line, is arranged on described array base palte;
A plurality of data lines, is arranged on described array base palte, and with described multi-strip scanning line, described a plurality of data lines intersects that described array base palte is divided into multiple pixel region mutually;
Color membrane substrates, is oppositely arranged with described array base palte;
Liquid crystal layer, is folded between described array base palte and described color membrane substrates;
Wherein, each described pixel region comprises main pixel region and time pixel region, each described pixel region comprises shares electric capacity, and along from the marginal position of described array base palte to the direction of the center of described array base palte, the described capacitance sharing electric capacity reduces successively, and when showing, the current potential on the secondary pixel region of the marginal position of described array base palte is less than the current potential on the secondary pixel region of the center of described array base palte.
2. display panels according to claim 1, is characterized in that, the described main pixel region in each described pixel region comprises:
Main switch element, be arranged on described array base palte, described main switch element comprises:
Grid, is electrically connected a corresponding sweep trace;
Source electrode, is electrically connected a corresponding data line;
Drain electrode;
Main pixel electrode, is arranged on described array base palte, and is electrically connected the described drain electrode of described main switch element;
Described pixel region in each described pixel region also comprises:
Secondary on-off element, is arranged on described array base palte, and described time on-off element comprises:
Grid, is electrically connected the sweep trace of described correspondence;
Source electrode, is electrically connected the data line of described correspondence;
Drain electrode;
Secondary pixel electrode, is arranged on described array base palte, and is electrically connected the described drain electrode of described on-off element;
Share on-off element, be arranged on described array base palte, described in share on-off element and comprise:
Grid, is electrically connected next sweep trace that the sweep trace of described correspondence is adjacent;
Source electrode, is electrically connected described pixel electrode;
Drain electrode;
Describedly share electric capacity, described in electric connection, share the described drain electrode of on-off element;
Wherein, when described next adjacent sweep trace is enabled, described in share switching elements conductive make described in share electric capacity and share electric charge on described pixel electrode.
3. display panels according to claim 1, is characterized in that, the described main pixel region area in each described pixel region is less than described pixel region area.
4. display panels according to claim 2, is characterized in that, described main switch element, described on-off element are thin film transistor (TFT) with described on-off element of sharing.
5. display panels according to claim 1, is characterized in that, along from the marginal position of described array base palte to the direction of the center of described array base palte, described in share electric capacity capacitance be at least two different capacitances.
6. an array base palte, is characterized in that, described array base palte comprises:
Multi-strip scanning line;
With described multi-strip scanning line, a plurality of data lines, intersects that described array base palte is divided into multiple pixel region mutually;
Wherein, each described pixel region comprises main pixel region and time pixel region, each described pixel region comprises shares electric capacity, and along from the marginal position of described array base palte to the direction of the center of described array base palte, the described capacitance sharing electric capacity reduces successively, and when showing, the current potential on the secondary pixel region of the marginal position of described array base palte is less than the current potential on the secondary pixel region of the center of described array base palte.
7. array base palte according to claim 6, is characterized in that, the described main pixel region in each described pixel region comprises:
Main switch element, be arranged on described array base palte, described main switch element comprises:
Grid, is electrically connected a corresponding sweep trace;
Source electrode, is electrically connected a corresponding data line;
Drain electrode;
Main pixel electrode, is arranged on described array base palte, and is electrically connected the described drain electrode of described main switch element;
Described pixel region in each described pixel region also comprises:
Secondary on-off element, is arranged on described array base palte, and described time on-off element comprises:
Grid, is electrically connected the sweep trace of described correspondence;
Source electrode, is electrically connected the data line of described correspondence;
Drain electrode;
Secondary pixel electrode, is arranged on described array base palte, and is electrically connected the described drain electrode of described on-off element;
Share on-off element, be arranged on described array base palte, described in share on-off element and comprise:
Grid, is electrically connected next sweep trace that the sweep trace of described correspondence is adjacent;
Source electrode, is electrically connected described pixel electrode;
Drain electrode;
Describedly share electric capacity, described in electric connection, share the described drain electrode of on-off element;
Wherein, when described next adjacent sweep trace is enabled, described in share switching elements conductive make described in share electric capacity and share electric charge on described pixel electrode.
8. array base palte according to claim 6, is characterized in that, the described main pixel region area in each described pixel region is less than described pixel region area.
9. array base palte according to claim 7, is characterized in that, described main switch element, described on-off element are thin film transistor (TFT) with described on-off element of sharing.
10. array base palte according to claim 6, is characterized in that, along from the marginal position of described display panels to the direction of the center of described display panels, described in share electric capacity capacitance be at least two different capacitances.
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| CN201510955722.7A CN105372892B (en) | 2015-12-17 | 2015-12-17 | array substrate and liquid crystal display panel |
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| CN201510955722.7A CN105372892B (en) | 2015-12-17 | 2015-12-17 | array substrate and liquid crystal display panel |
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Cited By (11)
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| CN106054477A (en) * | 2016-07-25 | 2016-10-26 | 深圳市华星光电技术有限公司 | Pixel structure and liquid crystal display apparatus |
| CN106249499A (en) * | 2016-10-18 | 2016-12-21 | 深圳市华星光电技术有限公司 | Curved face display panel and curved-surface display device |
| CN106652805A (en) * | 2016-10-21 | 2017-05-10 | 上海天马微电子有限公司 | Display panel and display device |
| CN106652948A (en) * | 2016-12-27 | 2017-05-10 | 深圳市华星光电技术有限公司 | Driving circuit and display panel |
| CN109658900A (en) * | 2019-02-28 | 2019-04-19 | 京东方科技集团股份有限公司 | Driving method, compensation circuit and driving device, the display device of display panel |
| CN110109296A (en) * | 2019-04-12 | 2019-08-09 | 深圳市华星光电半导体显示技术有限公司 | A kind of array substrate and liquid crystal display device |
| CN110794626A (en) * | 2019-10-21 | 2020-02-14 | 深圳市华星光电半导体显示技术有限公司 | Pixel structure and liquid crystal display panel |
| CN111862831A (en) * | 2020-07-28 | 2020-10-30 | 惠科股份有限公司 | Display module and display device |
| CN113299229A (en) * | 2021-05-21 | 2021-08-24 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN114002884A (en) * | 2021-09-30 | 2022-02-01 | 惠科股份有限公司 | Array substrate, display panel and display |
| CN114815408A (en) * | 2022-04-14 | 2022-07-29 | Tcl华星光电技术有限公司 | Display panel and display device |
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