KR20130060603A - Array substrate for fringe field switching mode liquid crystal display device - Google Patents

Abstract

PURPOSE: An array substrate for a fringe field switching mode liquid crystal display device is provided to restrain the generation of a vertical crosstalk and to prevent the increase of power consumption. CONSTITUTION: A first protection layer(116a) covers a data line(105) and a thin film transistor. A pixel electrode(125) positioned in the upper part of the first protection layer is connected to the thin film transistor. A shield metal pattern(200) corresponds to the data line. A second protection layer(116b) covers the pixel electrode and the shield metal pattern. A common electrode is positioned in the upper part of the second protection layer. The shield metal pattern is completely overlapped with the data line.

Description

Array substrate for fringe field switching mode liquid crystal display device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fringe field switching mode liquid crystal display device, and more particularly, to an array substrate for a fringe field switching mode liquid crystal display device which minimizes parasitic capacitance between data wiring and a pixel electrode.

Liquid crystal display devices (LCDs), which are used for TVs and monitors due to their high contrast ratio and are advantageous for displaying moving images, are characterized by optical anisotropy and polarization of liquid crystals. The principle of image implementation by

Such a liquid crystal display is an essential component of a liquid crystal panel bonded through a liquid crystal layer between two side-by-side substrates, and realizes a difference in transmittance by changing an arrangement direction of liquid crystal molecules with an electric field in the liquid crystal panel. do.

Recently, an active matrix liquid crystal display device that drives liquid crystal with an electric field formed up-down has been widely used because of its excellent resolution and video performance. However, liquid crystal driving due to an electric field that is applied up-down has a disadvantage in that the viewing angle characteristics are inferior.

Accordingly, various methods have been proposed in order to overcome the disadvantage that the viewing angle is narrow. Among them, a liquid crystal driving method by a transverse electric field is attracting attention.

1 is a cross-sectional view schematically showing a liquid crystal panel of a general transverse electric field type liquid crystal display device.

As shown in the figure, the lower substrate 1, which is an array substrate, and the upper substrate 3, which is a color filter substrate, are spaced apart from each other and face each other. A liquid crystal layer 5 is interposed between the upper and lower substrates 1, .

A common electrode 21 and a pixel electrode 25 are formed on the same plane on the lower substrate 1. The liquid crystal layer 5 is formed by a common electric field 21 and a horizontal electric field L by the pixel electrode 25, Lt; / RTI >

As described above, in the transverse electric field type liquid crystal display device, the common electrode 21 and the pixel electrode 25 are formed on the lower substrate 1, a horizontal electric field L is generated between the two electrodes 21 and 25, Is arranged in parallel with the horizontal electric field (L) parallel to the substrates (1, 3), the viewing angle of the liquid crystal display device can be widened.

On the other hand, such a transverse field type liquid crystal display device has an advantage of improving the viewing angle, but has a disadvantage of low aperture ratio and low transmittance.

Therefore, in order to improve the disadvantage of the transverse field type liquid crystal display, a fringe field switching mode LCD is characterized in that the liquid crystal is operated by a fringe field.

The fringe field switching mode liquid crystal display device can precisely control the liquid crystal, thereby improving the aperture ratio and transmittance.

Meanwhile, in the fringe field switching mode liquid crystal display, a parasitic capacitance is generated between the data line (not shown) and the pixel electrode 25.

This parasitic capacitance acts as a resistor, affecting the level shift voltage (Vp) of the pixel voltage charged in the pixel electrode 25, so that when the parasitic capacitance increases, the parasitic capacitance increases with the pixel voltage charged in the pixel electrode 25. Coupling between the data signals supplied to the data wirings (not shown) may occur, thereby causing a defect such as vertical crosstalk.

This increases the current consumption, which has a disadvantage of affecting the reliability.

In order to reduce the parasitic capacitance generated by the pixel electrode 25 and the data wiring (not shown), a spaced interval between the pixel electrode 25 and the data wiring (not shown) may be further widened. As the pixel electrode 25 in the inside becomes smaller, the area forming the fringe field becomes smaller, resulting in a problem of lowering the aperture ratio.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a first object of the present invention is to suppress vertical crosstalk generation by minimizing parasitic capacitance between the pixel electrode and the data wiring without decreasing the aperture ratio of the fringe field switching mode liquid crystal display.

Accordingly, a second object is to prevent an increase in current consumption, and a third object is to provide a fringe field switching mode liquid crystal display device having improved display quality.

In order to achieve the object as described above, the present invention comprises a gate wiring and a data wiring to form a plurality of pixel regions by crossing each other with a gate insulating film on the substrate; A thin film transistor connected to the gate line and the data line; A first protective layer covering the data line and the thin film transistor; A pixel electrode positioned on the first passivation layer and connected to the thin film transistor; A shield metal pattern positioned on the first passivation layer and corresponding to the data line; A second protective layer covering the pixel electrode and the shield metal pattern; An array substrate for a fringe field switching mode liquid crystal display device including a common electrode disposed on the second passivation layer is provided.

The shield metal pattern completely overlaps the data line, has a width greater than that of the data line, and the shield metal pattern is applied with the same voltage as the common electrode.

In addition, the shield metal pattern is made of the same material of a transparent conductive material on the same layer as the pixel electrode, the common electrode is the outermost common electrode formed on the outermost side of each pixel area in parallel with the data wiring, An auxiliary common electrode formed in parallel with the gate wiring and a plurality of central common electrodes branched from the auxiliary common electrode and spaced apart from each other by a predetermined distance in parallel with the outermost common electrode are formed, and the pixel electrode has a plate shape.

The pixel electrode includes an auxiliary pixel pattern connected to the thin film transistor, a plurality of central pixel electrodes branching from the auxiliary pixel pattern, the common electrode has a plate shape, and the thin film transistor is a polysilicon semiconductor layer. It includes.

In addition, the polysilicon semiconductor layer is a low temperature poly-silicon (LTPS) type made of polycrystalline silicon, the thin film transistor includes an amorphous silicon semiconductor layer.

As described above, according to the present invention, by forming a shield metal pattern on the data wiring, parasitic capacitance between the data wiring and the pixel electrode can be minimized, thereby causing a defect such as vertical crosstalk. There is an effect that can be prevented, there is an effect that can be prevented from increasing the current consumption.

In addition, in order to reduce the parasitic capacitance between the pixel electrode and the data wiring, it is not necessary to form a wide interval between the pixel electrode and the data wiring, thereby preventing the problem of lowering the aperture ratio of the fringe field switching mode liquid crystal display device. It works.

1 is a cross-sectional view schematically showing a liquid crystal panel of a general transverse electric field type liquid crystal display device.
FIG. 2 is a schematic cross-sectional view of an array substrate for a fringe field switching mode liquid crystal display device according to a first embodiment of the present invention; FIG.
3 is a plan view schematically illustrating a part of an array substrate for a fringe field switching mode liquid crystal display device according to a second embodiment of the present invention;
4 is a cross-sectional view taken along the line IV-IV of FIG. 3.

Hereinafter, embodiments according to the present invention will be described in detail with reference to the drawings.

FIG. 2 is a schematic cross-sectional view of an array substrate for a fringe field switching mode liquid crystal display device according to a first embodiment of the present invention, and is a cross-sectional view of one pixel area.

As shown in the drawing, on the array substrate 101 for a fringe field switching mode liquid crystal display device, a data line 105 defining a pixel region P by crossing a plurality of gate lines (not shown) and gate lines (not shown). This is composed.

In this case, the thin film transistor Tr is formed in the switching region TrA, which is an intersection point of the gate wiring (not shown) and the data wiring 105 of the pixel region P, and the pixel electrode in the display region where the image is substantially realized. The 125 and the common electrode 121 are formed.

The thin film transistor Tr may be a semiconductor layer 115 including a gate electrode 111, a gate insulating layer 113, an active layer 115a and an ohmic contact layer 115b, and source and drain electrodes 117 and 119. Is done.

In addition, a first passivation layer 116a is formed on an entire surface of the array substrate 101 including the thin film transistor Tr, and the pixel electrode 125 has a drain contact hole 118 on the first passivation layer 116a. And are electrically connected to the drain electrode 119 of the thin film transistor Tr.

Meanwhile, as the most characteristic part of the present invention, the shield metal pattern 200 overlapping the data line 105 is formed on the first passivation layer 116a.

At this time, the array substrate 101 for the fringe field switching mode liquid crystal display device of the present invention, since the data line 105 itself forms the source electrode 117, the shield metal pattern 200 is also formed on the source electrode 117. do.

The shield metal pattern 200 is made of a transparent conductive material, and the shield metal pattern 200 is preferably made of the same material in the same layer as the pixel electrode 125.

The shield metal pattern 200 is characterized in that a predetermined voltage is applied. Furthermore, a voltage equal to the common voltage applied to the common electrode 121 is preferably applied.

Therefore, it is preferable to form a horizontal electric field between the shield metal pattern 200 and the pixel electrode 125.

The shield metal pattern 200 serves to minimize the parasitic capacitance Cdp generated by the pixel electrode 125 and the data wiring 105.

At this time, the shield metal pattern 200 is characterized in that the shield metal pattern 200 having a width (d2) than the width (d1) of the data wiring 105 is formed.

Accordingly, the shield metal pattern 200 is located closer to the pixel electrode 125 than the data line 105, thereby minimizing the parasitic capacitance Cdp between the data line 105 and the pixel electrode 125. do.

In this case, since the shield metal pattern 200 has a width d2 wider than that of the data line 105, the shield metal pattern 200 covers a part of the pixel area P, but is transparent, and thus does not affect the aperture ratio.

That is, the pixel electrode 125 forms a predetermined capacitance C with the shield metal pattern 200 positioned closer than the data wiring 105, thereby forming a gap between the data wiring 105 and the pixel electrode 125. The parasitic capacitance (Cdp) generated will be minimized.

In addition, the interference on the horizontal electric field formed between the common electrodes 121 formed on the left and right sides of the data wiring 105 and the pixel electrodes 125 adjacent to the data wiring 105 with respect to the data wiring 105 is minimized.

Through this, it is possible to prevent the occurrence of a defect such as vertical crosstalk and to prevent the consumption current from increasing.

In addition, a second passivation layer 116b is formed on the entire surface of the substrate 101 on the shield metal pattern 200, and a common electrode (ie, corresponding to each pixel region P) is formed on the second passivation layer 116b. 121) is located.

Accordingly, a voltage is applied to the pixel electrode 125 and the common electrode 121 to form a fringe field.

As described above, the array substrate 101 for the fringe field switching mode liquid crystal display device can widen the viewing angle of the liquid crystal display device by arranging the liquid crystal molecules in parallel with a horizontal electric field parallel to the substrate 101.

In addition, since the pixel electrode 125 and the common electrode 121 form a fringe field, a strong horizontal and vertical electric field is generated between the common electrode 121 and the pixel electrode 125 because a vertical electric field and a horizontal electric field are combined. It is formed.

Therefore, the liquid crystal molecules corresponding to the centers of the common electrodes 121 can be easily controlled, thereby improving the aperture ratio and the transmittance.

In particular, by forming the shield metal pattern 200 on the data line 105, the parasitic capacitance Cdp generated between the data line 105 and the pixel electrode 125 is minimized, thereby providing vertical crosstalk. It can be prevented from causing a defect such as, it is possible to prevent the current consumption increases.

3 is a plan view schematically illustrating a portion of an array substrate for a fringe field switching mode liquid crystal display according to a second embodiment of the present invention.

In this case, an enlarged view of one pixel area P including the switching device is illustrated for more detailed description.

On the other hand, prior to the description, the array substrate for fringe field switching mode liquid crystal display device of the present invention has a high mobility compared to the amorphous silicon thin film transistor, and describes a polysilicon thin film transistor having an advantage as a switching device of a high resolution panel as an example. Among the polysilicon thin film transistors, an active matrix drive type array substrate using a low temperature poly-silicon (LTPS) type thin film transistor manufactured at a temperature of 600 ° C. or less will be described as an example.

Low-temperature polysilicon has a merit that it is crystallized by irradiating a laser to amorphous silicon, and its field mobility is several hundred times higher than that of amorphous silicon, and it is possible to reduce the cost of production while reducing the production cost by mounting the driving circuit on a glass substrate.

That is, the array substrate for a liquid crystal display device of the present invention is an array substrate for a fringe field switching mode liquid crystal display device including a low-temperature polysilicon type thin film transistor, and has a high electric field mobility and precisely controls the liquid crystal, And transmittance is improved.

As illustrated, the array substrate 101 for a fringe field switching mode liquid crystal display device according to an exemplary embodiment of the present invention has a plurality of gate wirings 103 extending in a first direction, and a plurality of gate wirings 103. ), A plurality of data lines 105 extending in the second direction to define the plurality of pixel regions P are formed.

Each pixel region P is connected to the gate wiring 103 and the data wiring 105, and includes a semiconductor layer 115 made of polysilicon, a gate electrode 111, a gate insulating film 113 (see FIG. 4), The LTPS type thin film transistor Tr including the source and drain electrodes 117 and 119 spaced apart from each other is formed.

In this case, the gate electrode 111 is branched from the gate wiring 103, and the source electrode 117 is formed using the data wiring 105 itself as the source electrode 117.

Here, the semiconductor layer 115 is formed to have a planar shape having an approximately "b" shape so as to intersect the gate wiring 103, and the semiconductor layer 115 may have a heavily doped source and drain regions (115b and 115c in FIG. 4). ) And a low temperature polysilicon comprising an undoped active region (115a in FIG. 4) corresponding to the upper gate electrode 111.

In addition, a plate-shaped pixel electrode 125 connected to the drain electrode 119 of the thin film transistor Tr is formed in each pixel region P, and a passivation layer 116b (FIG. 4) is disposed on the pixel electrode 125. The common electrode 121 is formed therebetween.

The common electrode 121 branches from the outermost common electrode 121a formed in parallel with the data line 105, the auxiliary common electrode 121b formed in parallel with the gate line 103, and the auxiliary common electrode 121b. The plurality of central common electrodes 121c are formed to be spaced apart from the outermost common electrode 121a at regular intervals.

Accordingly, a voltage is applied to the pixel electrode 125 and the common electrode 121 to form a fringe field.

In this case, although the pixel electrode 125 is formed to have a plate shape in the drawing, as another variation, the common electrode 121 is formed to have a plate shape, and the pixel electrode 125 is formed of the thin film transistor Tr. An auxiliary pixel pattern (not shown) connected to the drain electrode 119 may be formed, and a plurality of central pixel electrodes (not shown) may be branched from the auxiliary pixel pattern (not shown).

On the other hand, as a most characteristic part of the present invention, each of the plurality of pixel areas (P) is formed with a shield metal pattern 200 overlapping the data wiring 105 completely and having a width (d2) than the data wiring 105 It is.

A predetermined voltage is applied to the shield metal pattern 200 to minimize the parasitic capacitance Cdp (see FIG. 4) generated by the pixel electrode 125 and the data wiring 105.

Since the characteristic configuration of the present invention can be better represented through a cross-sectional structure, it will be described in more detail with reference to the cross-sectional configuration of the array substrate for fringe field switching mode liquid crystal display according to an embodiment of the present invention.

4 is a cross-sectional view taken along the line IV-IV of FIG. 3.

In this case, for convenience of description, a portion in which the thin film transistor Tr in each pixel region P is to be formed will be defined as a switching region TrA.

As illustrated, the array substrate 101 for the fringe field switching mode liquid crystal display device has a plurality of gate wirings (103 in FIG. 3) extending in the first direction, and a plurality of gate wirings (103 in FIG. 3). A plurality of data lines 105 extending in the second direction to define the plurality of pixel regions P are formed.

In addition, corresponding to the switching region TrA of each pixel region P, a semiconductor layer 115 made of polysilicon and a gate insulating film 113 are formed on the semiconductor layer 115.

A gate wiring (103 in FIG. 3) is formed on the gate insulating layer 113 to extend in one direction with the gate electrode 111 in correspondence with the active region 115a of the semiconductor layer 115.

In addition, an interlayer insulating film 112 is formed on the entire upper surface of the gate electrode 111 and the gate wiring 103 (in FIG. 3), wherein the interlayer insulating film 112 and the lower gate insulating film 113 are formed in the active region 115a. First and second semiconductor layer contact holes 111a and 111b exposing the source and drain regions 115b and 115c respectively positioned at both sides are provided.

Next, an upper portion of the interlayer insulating layer 112 including the first and second semiconductor layer contact holes 111a and 111b may be spaced apart from each other and exposed through the first and second semiconductor layer contact holes 111a and 111b. Source and drain electrodes 117 and 119 are formed in contact with the regions 115b and 115c, respectively.

In this case, the source electrode 117 is formed using the data wiring 105 itself as the source electrode 117.

The gate electrode formed on the semiconductor layer 115 and the semiconductor layer 115 including the source and drain electrodes 117 and 119 and the source and drain regions 115b and 115c in contact with the electrodes 117 and 119. Reference numeral 111 is an LTPS type driving thin film transistor DTr.

In addition, a first passivation layer 116a exposing the drain electrode 119 is formed on an entire surface of the substrate 101 including the source and drain electrodes 117 and 119, and above the first passivation layer 116a. A plate-shaped pixel electrode 125 is formed in contact with the drain electrode 119 through the drain contact hole 118.

In addition, the shield metal pattern 200 may be formed on the first passivation layer 116a to completely overlap the data line 105 and have a width d2 larger than the width d1 of the data line 105. It features.

At this time, the array substrate 101 for the fringe field switching mode liquid crystal display device of the present invention, since the data line 105 itself forms the source electrode 117, the shield metal pattern 200 is also formed on the source electrode 117. do.

The shield metal pattern 200 is made of a transparent conductive material, and the shield metal pattern 200 is preferably made of the same material in the same layer as the pixel electrode 125.

The shield metal pattern 200 is characterized in that a predetermined voltage is applied. Furthermore, a voltage equal to the common voltage applied to the common electrode 121 is preferably applied.

In this case, since the shield metal pattern 200 has a width d2 wider than that of the data line 105, the shield metal pattern 200 covers a part of the pixel area P, but is transparent, and thus does not affect the aperture ratio.

In addition, a second passivation layer 116b is formed on the entire surface of the substrate 101 on the shield metal pattern 200, and a common electrode (ie, corresponding to each pixel region P) is formed on the second passivation layer 116b. 121 is located.

The common electrode 121 includes an outermost common electrode 121a formed in parallel with the data line 105, an auxiliary common electrode 121b formed in parallel with the gate line 103, and an auxiliary common electrode 121b. And a plurality of central portion common electrodes 121c formed to be spaced apart from each other by a predetermined distance in parallel with the outermost common electrode 121a.

The common electrode 121 forms a fringe field together with the pixel electrode 125.

In the above-described array of fringe field switching mode liquid crystal display substrates of the present invention, the shield metal pattern 200 is further formed on the data line 105, thereby forming a gap between the data line 105 and the pixel electrode 125. The parasitic capacitance (Cdp) generated can be minimized.

That is, in the general fringe field switching mode liquid crystal display array substrate 101, the data wiring 105 and the pixel electrode 125 are formed on different layers with the second protective layer 116b interposed therebetween, thereby the data wiring. A parasitic capacitance Cdp is achieved using the second protective layer 116b positioned between the 105 and the pixel electrode 125 as a dielectric layer.

The parasitic capacitance Cdp acts as a resistor, affecting the level shift voltage (Vp) of the pixel voltage charged in the pixel electrode 125, thereby causing signal delay between the pixel electrode 125 and the data wiring 105. , Resulting in defects such as vertical crosstalk. In addition, the current consumption is increased. This is causing problems that affect the reliability.

Looking more closely at this, the parasitic capacitance can be defined as Equation 1:

(Equation 1)

Here,? Vp: level shift voltage, C _LC : capacitance by the liquid crystal layer, Cst: storage capacitance, Cdp: parasitic capacitance between the pixel electrode and the data wiring, Vgh: gate high voltage, and Vgl: gate low voltage.

Therefore, the parasitic capacitance Cdp generated between the data wiring 105 and the pixel electrode 125 affects the level shift voltage? Vp of the pixel voltage charged in the pixel electrode 125. When the parasitic capacitance Cdp is increased, interference between the pixel voltage charged in the pixel electrode 125 and the data signal supplied to the data wiring 105 is generated. As a result, vertical crosstalk and The same failure will occur.

Accordingly, in the array substrate 101 for the fringe field switching mode liquid crystal display device according to the exemplary embodiment of the present invention, the shield metal pattern 200 is positioned above the data line 105, thereby providing data wiring through the shield metal pattern 200. The electric field generated between the 105 and the pixel electrode 125 is cut off.

That is, the pixel electrode 125 forms a predetermined capacitance C with the shield metal pattern 200 positioned closer than the data wiring 105, thereby forming a gap between the data wiring 105 and the pixel electrode 125. The parasitic capacitance (Cdp) generated will be minimized.

In addition, a horizontal electric field formed between the outermost common electrode 121a in each pixel region P formed on the left and right sides of the data wiring 105 with respect to the data wiring 105 and the pixel electrodes 125 adjacent thereto. Minimize interference.

Through this, it is possible to prevent the occurrence of a defect such as vertical crosstalk and to prevent the consumption current from increasing.

In addition, in order to reduce the parasitic capacitance Cdp between the pixel electrode 125 and the data wiring 105, it is not necessary to form a wide interval between the pixel electrode 125 and the data wiring 105, thereby fringe-field switching mode liquid crystal display. The problem of lowering the aperture ratio of the device may be prevented from occurring.

Table (1) below is a simulation result comparing the parasitic capacitance between the data wiring and the pixel electrode and the parasitic capacitance between the data wiring and the pixel electrode according to the embodiment of the present invention.

Sample 1 Sample 2 Parasitic capacitance (Cdp) between data wiring and pixel electrode 1.82 1.80

Here, Sample 1 is a simulation result of measuring the parasitic capacitance value between the data wiring and the pixel electrode in a conventional fringe field switching mode liquid crystal display array substrate, and Sample 2 is a fringe field switching according to the second embodiment of the present invention. It is a simulation result of measuring the parasitic capacitance between the data wiring and the pixel electrode in the array liquid crystal display device.

Referring to Table (1), according to the second embodiment of the present invention, by forming a shield metal pattern to which the same voltage as the common electrode is applied, the data wiring and the data wiring and the shield metal pattern are not formed. It can be seen that the parasitic capacitance between the pixel electrodes is reduced.

This is because the shield metal pattern forms a predetermined capacitance with the pixel electrode, thereby reducing the parasitic capacitance generated between the data wiring and the pixel electrode, and by applying the same voltage as the common electrode as the shield metal pattern, the data wiring and the pixel electrode The parasitic capacitance generated in between is divided into two in series, it can be seen that the parasitic capacity is also reduced through this.

Table 2 below shows the results of simulating the occurrence of vertical crosstalk according to the parasitic capacitance between the data wiring and the pixel electrode.

Here, Sample 1 is a simulation result of measuring the parasitic capacitance value between the data wiring and the pixel electrode in a conventional fringe field switching mode liquid crystal display array substrate, and Sample 2 is a fringe field switching according to the second embodiment of the present invention. It is a simulation result of measuring the parasitic capacitance between the data wiring and the pixel electrode in the array liquid crystal display device.

Here, the measured value is a value obtained by measuring whether or not the luminance fluctuates due to vertical crosstalk when the luminance of the pattern and the region (gray) between the patterns is 100%.

That is, the luminance of the area between the black patterns of Sample 1 was measured to be 100.22%, and the luminance of the area between the blue patterns was measured to be 101.23%.

Referring to Table 2, Sample 1 shows that the luminance measurement value between the patterns fluctuates by up to 2%.

On the contrary, it can be seen that the luminance measurement value between the patterns of Sample 2 varies within 1%.

The parasitic between the data wiring and the pixel electrode is formed by forming a shield metal pattern to which the same voltage as the common electrode is applied on the data wiring according to the second embodiment of the present invention. By reducing the capacity, it can be seen that this can minimize the occurrence of vertical crosstalk.

As described above, the array substrate for the fringe field switching mode liquid crystal display device of the present invention can minimize the parasitic capacitance between the data wiring and the pixel electrode by forming a shield metal pattern on the data wiring.

Through this, it is possible to prevent the occurrence of a defect such as vertical crosstalk and to prevent the consumption current from increasing.

In addition, in order to reduce the parasitic capacitance between the pixel electrode and the data wiring, it is not necessary to form a wide interval between the pixel electrode and the data wiring, thereby preventing the problem of lowering the aperture ratio of the fringe field switching mode liquid crystal display. .

The present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention.

101: array substrate, 105: data wiring
111: gate electrode, 111a, 111b: first and second semiconductor layer contact holes
113: gate insulating film, 115: semiconductor layer (115a: active region, 115b, 115c: source and drain regions)
116a and 116b: first and second protective layers
117: source electrode, 118: drain contact hole, 119: drain electrode
121a: outermost common electrode, 121b: auxiliary common electrode, 121c: central common electrode
125: pixel electrode
200: shield metal pattern
P: pixel area, Tr: thin film transistor, TrA: switching area

Claims (9)

Gate wiring and data wiring intersecting each other with a gate insulating film interposed therebetween to form a plurality of pixel regions on a substrate;
A thin film transistor connected to the gate line and the data line;
A first protective layer covering the data line and the thin film transistor;
A pixel electrode positioned on the first passivation layer and connected to the thin film transistor;
A shield metal pattern positioned on the first passivation layer and corresponding to the data line;
A second protective layer covering the pixel electrode and the shield metal pattern;
Common electrode on the second passivation layer
An array substrate for a fringe field switching mode liquid crystal display device comprising a.
The method of claim 1,
And the shield metal pattern completely overlaps the data line, and has a width greater than the width of the data line.
The method of claim 1,
And the shield metal pattern is applied with the same voltage as that of the common electrode.
The method of claim 1,
And the shield metal pattern is formed of the same material of a transparent conductive material on the same layer as the pixel electrode.
The method of claim 1,
The common electrode may include an outermost common electrode formed at the outermost side of each pixel area parallel to the data line, an auxiliary common electrode formed to be parallel to the gate line, and branched from the auxiliary common electrode to the outermost common electrode. An array substrate for a fringe field switching mode liquid crystal display device having a plurality of central common electrodes formed side by side at a predetermined interval, wherein the pixel electrodes have a plate shape.
The method of claim 1,
And the pixel electrode includes an auxiliary pixel pattern connected to the thin film transistor, and a plurality of central pixel electrodes branching from the auxiliary pixel pattern, wherein the common electrode has a plate shape.
The method of claim 1,
The thin film transistor is an array substrate for a fringe field switching mode liquid crystal display device comprising a polysilicon semiconductor layer.
The method of claim 7, wherein
The polysilicon semiconductor layer is a low temperature poly-silicon (LTPS) type fringe field switching mode liquid crystal display device array substrate made of polycrystalline silicon.
The method of claim 1,
The thin film transistor is an array substrate for a fringe field switching mode liquid crystal display device comprising an amorphous silicon semiconductor layer.

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