CN114815423A - Display panel manufacturing method - Google Patents

Display panel manufacturing method Download PDF

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CN114815423A
CN114815423A CN202210475496.2A CN202210475496A CN114815423A CN 114815423 A CN114815423 A CN 114815423A CN 202210475496 A CN202210475496 A CN 202210475496A CN 114815423 A CN114815423 A CN 114815423A
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sub
pixel electrode
electrode
pixel
main
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CN114815423B (en
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任贵宁
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Suzhou China Star Optoelectronics Technology Co Ltd
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Suzhou China Star Optoelectronics Technology Co Ltd
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    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136286Wiring, e.g. gate line, drain line
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1337Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/137Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells characterised by the electro-optical or magneto-optical effect, e.g. field-induced phase transition, orientation effect, guest-host interaction or dynamic scattering
    • G02F1/13775Polymer-stabilized liquid crystal layers

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
  • Liquid Crystal (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Spectroscopy & Molecular Physics (AREA)

Abstract

The application provides a display panel manufacturing method; the manufacturing method of the display panel comprises the steps of manufacturing a voltage division wire electrically connected with a secondary pixel electrode, applying preset voltage to the voltage division wire when liquid crystal in the display panel is subjected to alignment treatment, enabling the electric field driving force of the secondary pixel electrode to the liquid crystal to be different from the electric field driving force of a main pixel electrode to the liquid crystal, forming a design that the pretilt angle of the liquid crystal in the secondary pixel is different from the pretilt angle of the liquid crystal in the main pixel, enabling the liquid crystal in the whole display panel to be arranged in a diversified mode, and improving the visual angle of the display panel.

Description

Display panel manufacturing method
Technical Field
The application relates to the technical field of display, in particular to a display panel manufacturing method.
Background
The PSVA (Polymer Stabilized vertical Aligned) liquid crystal display is widely applied to display products such as televisions and the like due to low product cost, high production yield and good product aging performance. However, with the continuous development of display technology and the improvement of quality requirements of consumers, the problem of poor viewing angle of PSVA products is more and more prominent in high-end product applications. At present, the liquid crystal display industry generally adopts an 8-domain design to ensure that the liquid crystal inclination angles of a main pixel and a secondary pixel are different when a liquid crystal screen is driven so as to improve the problem of a visual angle; however, the improvement effect of this method is very limited.
Therefore, the prior liquid crystal display has the technical problem of poor viewing angle.
Disclosure of Invention
The application provides a manufacturing method of a display panel, which is used for relieving the technical problem of poor viewing angle of the existing liquid crystal display.
The application provides a display panel manufacturing method, which comprises the following steps:
manufacturing an array substrate, wherein the array substrate comprises a plurality of sub-pixels, at least one sub-pixel comprises a main pixel and a sub-pixel adjacent to the main pixel, the array substrate further comprises a main pixel electrode arranged corresponding to the main pixel, a sub-pixel electrode arranged corresponding to the sub-pixel, and a voltage division wire, and the voltage division wire is electrically connected with the sub-pixel electrode;
manufacturing an opposite substrate on one side of the array substrate, wherein a gap is reserved between the array substrate and the opposite substrate;
filling liquid crystal between the array substrate and the opposite substrate;
and applying preset voltage to the sub-pixel electrode through the voltage division wiring, and irradiating the liquid crystal through ultraviolet light to form a pretilt angle.
In the display panel manufacturing method of the present application, the applying a preset voltage to the sub-pixel electrode through the voltage division wiring, and irradiating the liquid crystal through ultraviolet light to form a pretilt angle includes:
applying a preset voltage to the sub-pixel electrode through the voltage division wiring, so that the electric field intensity of the sub-pixel electrode area is different from the electric field intensity of the main pixel electrode area;
irradiating the liquid crystal by ultraviolet light, forming a first pretilt angle corresponding to the liquid crystal of the main pixel, and forming a second pretilt angle corresponding to the liquid crystal of the sub pixel, wherein the first pretilt angle is different from the second pretilt angle.
In the display panel manufacturing method of the present application, the applying a preset voltage to the sub-pixel electrode through the voltage dividing routing, so that the electric field intensity of the sub-pixel electrode area is different from the electric field intensity of the main pixel electrode area, includes:
applying an initial voltage to the main pixel electrode and the sub-pixel electrode;
and applying preset voltage to the secondary pixel electrode through the voltage division wiring, so that the voltage on the secondary pixel electrode is different from the voltage on the main pixel electrode.
In the display panel manufacturing method of the present application, the counter substrate includes a common electrode; the step of applying a preset voltage to the sub-pixel electrode through the voltage dividing wiring to enable the electric field intensity of the sub-pixel electrode area to be different from the electric field intensity of the main pixel electrode area further comprises:
and applying a common voltage to the common electrode, wherein an electric field of the sub-pixel electrode region is formed between the sub-pixel electrode and the common electrode, and an electric field of the main pixel electrode region is formed between the main pixel electrode and the common electrode.
In the display panel manufacturing method of the present application, the array substrate further includes a first transistor disposed between the main pixel and the sub-pixel; the applying an initial voltage to the main pixel electrode and the sub-pixel electrode includes:
applying an initial voltage to the main pixel electrode and the sub pixel electrode through the first transistor.
In the method for manufacturing a display panel of the present application, the array substrate further includes a plurality of data lines extending along the first direction and arranged along the second direction, and a plurality of scan lines extending along the second direction and arranged along the first direction;
at least one scanning line is electrically connected with the grid electrode of the first transistor, the voltage division wiring is electrically connected with the source electrode of the first transistor, and the sub-pixel electrode is electrically connected with the drain electrode of the first transistor.
In the display panel manufacturing method of the present application, the array substrate further includes a second transistor disposed between the main pixel and the sub-pixel; the applying a preset voltage to the sub-pixel electrode through the voltage dividing wiring comprises:
and providing a preset voltage to the voltage division wiring, wherein the preset voltage is applied to the secondary pixel electrode through the second transistor.
In the method for manufacturing the display panel, at least one of the scan lines is electrically connected to the gate of the second transistor, at least one of the data lines is electrically connected to the source of the second transistor, and the main pixel electrode and the sub-pixel electrode are both electrically connected to the drain of the second transistor.
In the display panel manufacturing method, the voltage dividing routing is located between two adjacent data lines;
at least one scanning line is arranged between the main pixel and the sub-pixel.
In the display panel manufacturing method of the present application, the sub-pixel electrode includes a first main electrode extending along a first direction, a second main electrode extending along a second direction, and a branch electrode connected to the first main electrode or the second main electrode;
at least part of the voltage division routing is overlapped with the first main electrode.
The beneficial effect of this application: the application provides a display panel manufacturing method, through setting up the partial pressure of being connected with secondary pixel electrode electric property and walk the line, when carrying out the alignment to the liquid crystal, walk the line to apply preset voltage to the partial pressure, make the electric field drive power of secondary pixel electrode to liquid crystal be different from the electric field drive power of main pixel electrode to liquid crystal, the design that the pretilt angle of liquid crystal is different in the formation secondary pixel and the pretilt angle of liquid crystal is in the main pixel, and then make the liquid crystal in the whole display panel present diversified arrangement, promote display panel's visual angle.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a display panel provided in an embodiment of the present application.
Fig. 2 is a schematic partial structure diagram of an array substrate in a display panel according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
An embodiment of the present application provides a display panel, please refer to fig. 1 and fig. 2, in which fig. 1 is a schematic structural diagram of the display panel provided in the embodiment of the present application, and fig. 2 is a schematic partial structural diagram of an array substrate in the display panel provided in the embodiment of the present application. The display panel comprises an array substrate 10, an opposite substrate 20 arranged opposite to the array substrate 10, and a liquid crystal layer 30 arranged between the array substrate 10 and the opposite substrate 20, wherein liquid crystals 301 are arranged in the liquid crystal layer 30. The array substrate 10 is provided with a plurality of driving wires, a driving circuit, a thin film transistor, a pixel electrode and the like; the opposite substrate 20 may be provided therein with a color film layer including a plurality of color filter blocks, a common electrode, and the like.
Specifically, the display panel includes a plurality of sub-pixels, at least one of which includes a main pixel 111 and a sub-pixel 110 disposed adjacent to the main pixel 111; the main pixel 111 includes a main pixel electrode 113, the sub-pixel 110 includes a sub-pixel electrode 112, and the main pixel electrode 113 and the sub-pixel electrode 112 respectively have four pixel domains, so that each of the sub-pixels includes eight pixel domains. It is understood that each of the pixel domains represents a pixel region in a sub-pixel of the display panel, and the pretilt angle of the liquid crystal in the pixel region is different from the pretilt angle of the liquid crystal in the adjacent pixel domain, so as to ensure that the display panel has a larger visualization angle.
The array substrate 10 further includes a voltage dividing trace 120, and the voltage dividing trace 120 is electrically connected to the sub-pixel electrode 112. When the liquid crystal 301 is aligned, the voltage dividing trace 120 provides a preset voltage to the sub-pixel electrode 112. Optionally, the preset voltage is a voltage greater than 0V, and when the liquid crystal 301 is subjected to alignment processing, the preset voltage changes the electric field intensity of the region corresponding to the sub-pixel electrode 112, so that the electric field intensity of the region corresponding to the sub-pixel electrode 112 is different from the electric field intensity of the region corresponding to the main pixel electrode 113, thereby adjusting a pre-tilt angle formed after the liquid crystal 301 is aligned, forming a design in which the pre-tilt angle of the liquid crystal 301 in the sub-pixel 110 is different from the pre-tilt angle of the liquid crystal 301 in the main pixel 111, so that the liquid crystal in the whole display panel is arranged in a diversified manner, and improving the visualization angle of the display panel.
Further, at least a part of the voltage dividing trace 120 overlaps with a bisector of the sub-pixel electrode 112. The bisector of the sub-pixel electrode 112 may be understood as a line bisecting the sub-pixel electrode 112, which may be a transverse bisector of the sub-pixel electrode 112 or a longitudinal bisector of the sub-pixel electrode 112.
Further, the sub-pixel electrode 112 includes a first main electrode 114 extending along a first direction Y, a second main electrode 115 extending along a second direction Y, and a first branch electrode 116 connected to the first main electrode 114 or the second main electrode 115; at least part of the voltage dividing trace 120 overlaps the first main electrode 114. Optionally, the first direction Y is perpendicular to the second direction X, the first main electrode 114 and the second main electrode 115 equally divide the sub-pixel electrode 112 into four pixel domains, and the first branch electrodes 116 are distributed in the four pixel domains of the sub-pixel electrode 112.
Further, the array substrate 10 further includes a plurality of data lines 130 extending along the first direction Y and arranged along the second direction X, and a plurality of scan lines 140 extending along the second direction X and arranged along the first direction Y; the voltage dividing routing 120 is disposed between two adjacent data lines 130; and at least one of the sub-pixel electrodes 112 and at least one of the main pixel electrodes 113 are further disposed between two adjacent data lines 130.
Further, the main pixel electrode 113 includes a third main electrode 117 extending along the first direction Y, a fourth main electrode 118 extending along the second direction Y, and a second branch electrode 119 connected to the third main electrode 117 or the fourth main electrode 118. The third main electrode 117 and the fourth main electrode 118 equally divide the main pixel electrode 113 into four pixel domains, and the second branch electrodes 119 are distributed in the four pixel domains of the main pixel electrode 113. The first main electrode 114, the second main electrode 115, the third main electrode 117 and the fourth main electrode 118 divide the sub-pixels into eight pixel domains, and the pretilt angles of the liquid crystals in the adjacent pixel domains are different, so as to ensure that the display panel has a larger visualization angle.
Further, at least a part of the voltage dividing trace 120 is located in the main pixel 111, and in the main pixel 111, the voltage dividing trace 120 overlaps with the third main electrode 117. However, there is no electrical connection between the voltage dividing trace 120 and the main pixel electrode 113.
Further, the array substrate 10 further includes a first transistor T1 and a second transistor T2 disposed between the main pixel 111 and the sub-pixel 110, the first transistor T1 and the second transistor T2 are disposed between two adjacent data lines 130, and at least one scan line 140 is disposed between the main pixel 111 and the sub-pixel 110. The display panel further includes a light-shielding layer disposed corresponding to an area between the main pixel electrode 113 and the sub-pixel electrode 112 and shielding the first transistor T1 and the second transistor T2.
At least one of the scan lines 140 is electrically connected to the gate of the first transistor T1, the voltage dividing trace 120 is electrically connected to the source of the first transistor T1, and the sub-pixel electrode 112 is electrically connected to the drain of the first transistor T1. Under the action of the signal provided by the scan line 140, the first transistor T1 is turned on or off, so as to adjust the electrical connection relationship between the voltage dividing trace 120 and the sub-pixel electrode 112. It can be understood that, during the liquid crystal alignment process and when the display panel performs the display function, the voltage dividing wire 120 is electrically connected to the sub-pixel electrode 112, and the voltage of the sub-pixel electrode 112 is pulled down, so that the sub-pixel electrode 112 and the main pixel electrode 113 have different voltages, thereby forming a design in which the pretilt angle of the liquid crystal 301 in the sub-pixel 110 is different from the pretilt angle of the liquid crystal 301 in the main pixel 111 during the liquid crystal alignment process, and increasing the visualization angle of the display panel when the display function is performed.
At least one of the scan lines 140 is electrically connected to the gate of the second transistor T2, at least one of the data lines 130 is electrically connected to the source of the second transistor T2, and at least one of the main pixel electrode 113 and the sub-pixel electrode 112 is electrically connected to the drain of the second transistor T2. Under the action of a signal provided by the scan line 140, the second transistor T2 is turned on or off, so as to adjust the electrical connection relationship between the data line 130 and the main pixel electrode 113 and/or the sub pixel electrode 112, and the main pixel electrode 113 and the sub pixel electrode 112 are respectively charged.
In summary, the display panel provided in this embodiment includes a plurality of sub-pixels, where the sub-pixels include a main pixel 111 and a sub-pixel 110; the display panel comprises an array substrate 10, an opposite substrate 20 and a liquid crystal layer 30, wherein the array substrate 10 comprises a voltage division wire 120 and a sub-pixel electrode 112, the voltage division wire 120 is arranged corresponding to the sub-pixel 110, the voltage division wire 120 is electrically connected with the sub-pixel electrode 112, and when the liquid crystal is aligned, the voltage division wire 120 provides a preset voltage for the sub-pixel electrode 112. The voltage division wire 120 has a preset voltage when the liquid crystal is aligned. This application is walked line 120 through setting up the partial pressure in subpixel 110 to walk line 120 through the partial pressure and provide preset voltage to subpixel electrode 112 when carrying out the alignment to liquid crystal, thereby make subpixel electrode 112 be different from the electric field drive power of main pixel electrode 113 to liquid crystal to the electric field drive power of liquid crystal, the design that the pretilt angle of liquid crystal is different in formation subpixel 110 interior liquid crystal and main pixel 111, make the liquid crystal in the whole display panel present diversified arrangement, improve display panel's visual angle.
Another embodiment of the present invention further provides a method for manufacturing a display panel, which can be used for manufacturing the display panel described in the above embodiment, and therefore, the features of the display panel described in the above embodiment are also applicable to the display panel manufactured by the method of the present embodiment. Specifically, with continuing reference to fig. 1 and fig. 2, the method for manufacturing a display panel includes the following steps:
step S101, manufacturing an array substrate 10, where the array substrate 10 includes a plurality of sub-pixels, at least one of the sub-pixels includes a main pixel 111 and a sub-pixel 110 adjacent to the main pixel 111, the array substrate 10 further includes a main pixel electrode 113 disposed corresponding to the main pixel 111, a sub-pixel electrode 112 disposed corresponding to the sub-pixel 110, and a voltage division wire 120, and the voltage division wire 120 is electrically connected to the sub-pixel electrode 112.
Specifically, the main pixel electrode 113 and the sub pixel electrode 112 respectively have four pixel domains, so that each of the sub pixels includes eight pixel domains.
The sub-pixel electrode 112 includes a first main electrode 114 extending along a first direction Y, a second main electrode 115 extending along a second direction Y, and a first branch electrode 116 connected to the first main electrode 114 or the second main electrode 115; at least part of the voltage dividing trace 120 overlaps the first main electrode 114. Optionally, the first direction Y is perpendicular to the second direction X, the first main electrode 114 and the second main electrode 115 equally divide the sub-pixel electrode 112 into four pixel domains, and the first branch electrodes 116 are distributed in the four pixel domains of the sub-pixel electrode 112.
The array substrate 10 further includes a plurality of data lines 130 extending along the first direction Y and arranged along the second direction X, and a plurality of scan lines 140 extending along the second direction X and arranged along the first direction Y; the voltage dividing routing 120 is disposed between two adjacent data lines 130; and at least one of the sub-pixel electrodes 112 and at least one of the main pixel electrodes 113 are further disposed between two adjacent data lines 130.
The main pixel electrode 113 includes a third main electrode 117 extending along the first direction Y, a fourth main electrode 118 extending along the second direction Y, and a second branch electrode 119 connected to the third main electrode 117 or the fourth main electrode 118. The third main electrode 117 and the fourth main electrode 118 equally divide the main pixel electrode 113 into four pixel domains, and the second branch electrodes 119 are distributed in the four pixel domains of the main pixel electrode 113. The first, second, third and fourth trunk electrodes 114, 115, 117 and 118 divide the sub-pixels into eight pixel domains.
At least a part of the voltage dividing trace 120 is located in the main pixel 111, and in the main pixel 111, the voltage dividing trace 120 overlaps with the third main electrode 117. However, there is no electrical connection between the voltage dividing trace 120 and the main pixel electrode 113.
The array substrate 10 further includes a first transistor T1 and a second transistor T2 disposed between the main pixel 111 and the sub-pixel 110, the first transistor T1 and the second transistor T2 are disposed between two adjacent data lines 130, and at least one scan line 140 is disposed between the main pixel 111 and the sub-pixel 110.
At least one of the scan lines 140 is electrically connected to the gate of the first transistor T1, the voltage dividing trace 120 is electrically connected to the source of the first transistor T1, and the sub-pixel electrode 112 is electrically connected to the drain of the first transistor T1. At least one of the scan lines 140 is electrically connected to the gate of the second transistor T2, at least one of the data lines 130 is electrically connected to the source of the second transistor T2, and at least one of the main pixel electrode 113 and the sub pixel electrode 112 is electrically connected to the drain of the second transistor T2.
Step S102, fabricating a counter substrate 20 on one side of the array substrate 10, wherein a gap is reserved between the array substrate 10 and the counter substrate 20.
Optionally, a color film layer including a plurality of color filter blocks, a common electrode, and the like are disposed in the opposite substrate 20, and the common electrode and the main pixel electrode 113 and the sub-pixel electrode 112 in the array substrate 10 are used together to generate a specific electric field to drive liquid crystal to deflect.
In step S103, a liquid crystal 301 is filled between the array substrate 10 and the counter substrate 20 to form a liquid crystal layer 30. Alternatively, an alignment film layer is disposed on a surface of the array substrate 10 opposite to the counter substrate 20, and the liquid crystal 301 is injected between the array substrate 10 and the counter substrate 20, and under the action of the alignment film layer, the liquid crystal 301 is aligned in a specific direction.
Step S104, applying a preset voltage to the sub-pixel electrode 112 through the voltage dividing trace 120, and irradiating the liquid crystal 301 with ultraviolet light to form a pretilt angle.
Specifically, the step S104 includes: applying an initial voltage to the main pixel electrode 113 and the sub-pixel electrode 112 through the first transistor T1, and applying a common voltage to the common electrode, an electric field of a sub-pixel electrode region is formed between the sub-pixel electrode 112 and the common electrode, and an electric field of a main pixel electrode region is formed between the main pixel electrode 113 and the common electrode; simultaneously providing the preset voltage to the voltage division wire 120, wherein the preset voltage is applied to the sub-pixel electrode 112 through the second transistor T2, so that the electric field intensity of the sub-pixel electrode area is different from the electric field intensity of the main pixel electrode area, and thus the deflection angle of the liquid crystal 301 corresponding to the sub-pixel 110 is different from the deflection angle of the liquid crystal 301 corresponding to the main pixel 111; the liquid crystal 301 is irradiated by ultraviolet light, so that the liquid crystal 301 is cured and shaped, a first pretilt angle is formed on the liquid crystal 301 corresponding to the main pixel 111, a second pretilt angle is formed on the liquid crystal 301 corresponding to the sub-pixel 110, and the first pretilt angle is different from the second pretilt angle, so that the liquid crystal 301 corresponding to the same sub-pixel is in a diversified arrangement mode, and the finally prepared display panel has a better visual angle effect.
In the method for manufacturing a display panel according to this embodiment, by providing the voltage division wire 120 electrically connected to the sub-pixel electrode 112, when the liquid crystal 301 is subjected to alignment treatment, a preset voltage is applied to the voltage division wire 120, so that the electric field driving force of the sub-pixel electrode 112 to the liquid crystal 301 is different from the electric field driving force of the main pixel electrode 113 to the liquid crystal 301, and a design in which the pretilt angle of the liquid crystal in the sub-pixel 110 is different from the pretilt angle of the liquid crystal in the main pixel 111 is formed, thereby allowing the liquid crystal in the entire display panel to be arranged in a diversified manner, and improving the visualization angle of the display panel.
It should be noted that, although the present application has been described with reference to specific examples, the above-mentioned examples are not intended to limit the present application, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application.

Claims (10)

1. A method for manufacturing a display panel is characterized by comprising the following steps:
manufacturing an array substrate, wherein the array substrate comprises a plurality of sub-pixels, at least one sub-pixel comprises a main pixel and a sub-pixel adjacent to the main pixel, the array substrate further comprises a main pixel electrode arranged corresponding to the main pixel, a sub-pixel electrode arranged corresponding to the sub-pixel, and a voltage division wire, and the voltage division wire is electrically connected with the sub-pixel electrode;
manufacturing an opposite substrate on one side of the array substrate, wherein a gap is reserved between the array substrate and the opposite substrate;
filling liquid crystal between the array substrate and the opposite substrate;
and applying preset voltage to the sub-pixel electrode through the voltage division wiring, and irradiating the liquid crystal through ultraviolet light to form a pretilt angle.
2. The method for manufacturing a display panel according to claim 1, wherein the applying a preset voltage to the sub-pixel electrode through the voltage dividing trace and forming a pretilt angle by irradiating the liquid crystal with ultraviolet light includes:
applying a preset voltage to the sub-pixel electrode through the voltage division wiring, so that the electric field intensity of the sub-pixel electrode area is different from the electric field intensity of the main pixel electrode area;
irradiating the liquid crystal by ultraviolet light, forming a first pretilt angle corresponding to the liquid crystal of the main pixel, and forming a second pretilt angle corresponding to the liquid crystal of the sub pixel, wherein the first pretilt angle is different from the second pretilt angle.
3. The method according to claim 2, wherein the applying a preset voltage to the sub-pixel electrode through the voltage dividing trace such that the electric field intensity of the sub-pixel electrode area is different from the electric field intensity of the main pixel electrode area comprises:
applying an initial voltage to the main pixel electrode and the sub-pixel electrode;
and applying preset voltage to the secondary pixel electrode through the voltage division wiring, so that the voltage on the secondary pixel electrode is different from the voltage on the main pixel electrode.
4. The method for manufacturing a display panel according to claim 3, wherein the counter substrate includes a common electrode; the step of applying a preset voltage to the sub-pixel electrode through the voltage dividing wiring to enable the electric field intensity of the sub-pixel electrode area to be different from the electric field intensity of the main pixel electrode area further comprises:
and applying a common voltage to the common electrode, wherein an electric field of the sub-pixel electrode region is formed between the sub-pixel electrode and the common electrode, and an electric field of the main pixel electrode region is formed between the main pixel electrode and the common electrode.
5. The method for manufacturing a display panel according to claim 4, wherein the array substrate further comprises a first transistor disposed between the main pixel and the sub-pixel; the applying an initial voltage to the main pixel electrode and the sub-pixel electrode includes:
applying an initial voltage to the main pixel electrode and the sub pixel electrode through the first transistor.
6. The method for manufacturing a display panel according to claim 5, wherein the array substrate further includes a plurality of data lines extending along the first direction and arranged along the second direction, and a plurality of scan lines extending along the second direction and arranged along the first direction;
at least one scanning line is electrically connected with the grid electrode of the first transistor, the voltage division wiring is electrically connected with the source electrode of the first transistor, and the sub-pixel electrode is electrically connected with the drain electrode of the first transistor.
7. The method for manufacturing a display panel according to claim 6, wherein the array substrate further comprises a second transistor disposed between the main pixel and the sub-pixel; the step of applying a preset voltage to the sub-pixel electrode through the voltage dividing wiring comprises:
and providing a preset voltage to the voltage division wiring, wherein the preset voltage is applied to the secondary pixel electrode through the second transistor.
8. The method of claim 7, wherein at least one of the scan lines is electrically connected to a gate of the second transistor, at least one of the data lines is electrically connected to a source of the second transistor, and the main pixel electrode and the sub-pixel electrode are both electrically connected to a drain of the second transistor.
9. The method according to claim 8, wherein the voltage dividing trace is located between two adjacent data lines;
at least one scanning line is arranged between the main pixel and the sub-pixel.
10. The method according to claim 1, wherein the sub-pixel electrodes comprise a first main electrode extending along a first direction, a second main electrode extending along a second direction, and a branch electrode connected to the first main electrode or the second main electrode;
at least part of the voltage division routing is overlapped with the first main electrode.
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