CN110174787B - Array substrate, manufacturing method thereof and display device - Google Patents
Array substrate, manufacturing method thereof and display device Download PDFInfo
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- CN110174787B CN110174787B CN201910369927.5A CN201910369927A CN110174787B CN 110174787 B CN110174787 B CN 110174787B CN 201910369927 A CN201910369927 A CN 201910369927A CN 110174787 B CN110174787 B CN 110174787B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
Abstract
The embodiment of the invention provides an array substrate, a manufacturing method thereof and a display device. The array substrate comprises a substrate base plate, and a scanning line, a data line, a common electrode line and a plurality of pixel units which are arranged on the substrate base plate, wherein each pixel unit comprises a thin film transistor, a main pixel electrode, a sub-pixel electrode and a common electrode, and the common electrode is not arranged in the area between the main pixel electrode of at least one pixel unit and the sub-pixel electrode of the pixel unit adjacent to the main pixel electrode, so that the interference of the voltage of the common electrode to the area between the main pixel electrode of the pixel unit and the sub-pixel electrode of the pixel unit adjacent to the main pixel electrode is reduced, the problem of dark fringes caused by disordered liquid crystal guiding due to the common electrode is solved, the light transmittance in the area is improved, and the picture display quality is improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a manufacturing method thereof and a display device.
Background
Currently, a Liquid Crystal Display (LCD) device is one of the most widely used displays, and the LCD includes a pair of panels provided with field generating electrodes such as pixel electrodes and a common electrode, and a Liquid Crystal layer disposed between the two panels. The liquid crystal display includes various modes such as a Twisted Nematic (TN) mode, an Electronically Controlled Birefringence (ECB) mode, a Vertical Alignment (VA) mode, and the like, wherein the VA mode is a common display mode having advantages of high contrast, wide viewing angle, no rubbing Alignment, and the like, but in the VA mode, a pixel usually generates a dark fringe due to poor liquid crystal molecular orientation, and the light transmittance of a display panel is seriously affected.
In order to improve the viewing angle performance of the panel, a Polymer Stabilized Vertical Alignment (PSVA) type pixel is gradually applied to the design of a large-sized television panel, but dark fringes exist in the PSVA type pixel design, and the picture quality is seriously affected.
Disclosure of Invention
In view of the above, it is necessary to provide an array substrate, a method for manufacturing the same, and a display device, which address the problem of dark fringes in PSVA type pixel design.
The invention provides an array substrate which comprises a substrate base plate, and a scanning line, a data line, a common electrode line and a plurality of pixel units which are arranged on the substrate base plate, wherein each pixel unit comprises at least two thin film transistors, a main pixel electrode, a secondary pixel electrode and a common electrode, the at least two thin film transistors are arranged above the scanning line and are respectively and electrically connected with the main pixel electrode and the secondary pixel electrode, the main pixel electrode and the secondary pixel electrode are respectively arranged on two sides of the scanning line, and the common electrode is not arranged in the area between the main pixel electrode of at least one pixel unit and the secondary pixel electrode of the pixel unit adjacent to the main pixel electrode.
In one embodiment, the common electrode includes a first common sub-electrode and a second common sub-electrode perpendicular to each other, and the first common sub-electrode is parallel to the data line;
in the same pixel unit, in the extending direction of the first common sub-electrode, the distance between the projection of the far end of the first common sub-electrode on the bottom-sinking substrate and the projection of the far end of the main pixel electrode on the substrate is 5-8 μm, wherein the far end of the first common sub-electrode is one end of the first common sub-electrode, which is far away from the scanning line, and the far end of the main pixel electrode is one end of the main pixel electrode, which is far away from the scanning line.
In one embodiment, each of the main pixel electrode and the sub-pixel electrode includes a peripheral connection portion, a plurality of stripe-shaped main stems, and a plurality of stripe-shaped pixel sub-electrodes connected to the main stems, where the main stems include a horizontal main stem and a vertical main stem perpendicular to each other, the horizontal main stem and the vertical main stem divide the pixel unit into a plurality of display domains, and the pixel sub-electrodes are located in the display domains;
the trunk of the pixel electrode covers the common electrode, and the projection distance of the far end of the vertical trunk of the main pixel and the far end of the first common sub-electrode corresponding to the far end of the vertical trunk of the main pixel on the substrate is 5-8 μm, wherein the far end of the vertical trunk of the main pixel is one end of the vertical trunk of the main pixel, which is far away from the scanning line.
In one embodiment, the projection distance of the far end of the vertical stem of the main pixel and the far end of the first common sub-electrode corresponding to the far end of the main pixel on the substrate is 6 μm.
In one embodiment, the pixel unit comprises a first thin film transistor, a second thin film transistor and a third thin film transistor;
the source electrode of the first thin film transistor is connected with the data line, and the drain electrode of the first thin film transistor is connected with the main pixel electrode and used for providing a data driving signal for the main pixel electrode;
the source electrode of the second thin film transistor is connected with the data line, and the drain electrode of the second thin film transistor is connected with the sub-pixel electrode and used for providing a data driving signal for the sub-pixel electrode;
and the source electrode of the third thin film transistor is connected with the source electrode of the second thin film transistor, and the drain electrode of the third thin film transistor is connected with the common electrode line and is used for driving the voltage of the signal for the data on the sub-pixel electrode.
In one embodiment, in one pixel unit, the gate of the first thin film transistor, the gate of the second thin film transistor and the gate of the third thin film transistor are connected to the same scan line, and the drain of the first thin film transistor and the drain of the second thin film transistor are connected to the same data line.
In one embodiment, a first conductive channel formed between the source and the drain of the first thin film transistor is U-shaped, a second conductive channel formed between the source and the drain of the second thin film transistor is U-shaped, and a third conductive channel formed between the source and the drain of the third thin film transistor is in-line.
Based on the same inventive concept, an embodiment of the present invention further provides a method for manufacturing an array substrate, where the method includes a step of forming a scan line, a data line, a common electrode, and a common electrode line, a step of forming at least two thin film transistors, and a step of forming a main pixel electrode and a sub-pixel electrode, where the step of forming the thin film transistors includes a step of forming a gate electrode, a source electrode, a drain electrode, and an active layer, where the at least two thin film transistors are disposed above the scan line and electrically connected to the main pixel electrode and the sub-pixel electrode, respectively, the main pixel electrode and the sub-pixel electrode are disposed on two sides of the scan line, respectively, and a region between the main pixel electrode of at least one pixel unit and the sub-pixel electrode of an adjacent pixel unit is not disposed with the common electrode.
In one embodiment, the common electrode includes a first common sub-electrode and a second common sub-electrode perpendicular to each other, and the first common sub-electrode is parallel to the data line;
in the extending direction of the first common sub-electrode, the distance between the projection of the far end of the first common sub-electrode on the bottom-sinking substrate and the projection of the far end of the main pixel electrode on the substrate is 5-8 μm, wherein the far end of the first common sub-electrode is one end of the first common sub-electrode, which is far away from the scanning line, and the far end of the main pixel electrode is one end of the main pixel electrode, which is far away from the scanning line.
Based on the same inventive concept, the invention also provides a display device, which comprises the array substrate of any one of the above claims.
In summary, embodiments of the present invention provide an array substrate, a method for manufacturing the same, and a display device. The array substrate comprises a substrate, and a scanning line, a data line, a common electrode line and a plurality of pixel units which are arranged on the substrate, wherein each pixel unit comprises at least two thin film transistors, a main pixel electrode, a sub-pixel electrode and a common electrode, the at least two thin film transistors are arranged above the scanning line and are respectively and electrically connected with the main pixel electrode and the sub-pixel electrode, the main pixel electrode and the sub-pixel electrode are respectively arranged on two sides of the scanning line, and the common electrode is not arranged in an area between the main pixel electrode of at least one pixel unit and the sub-pixel electrode of the pixel unit adjacent to the main pixel electrode. In the invention, the common electrode is not arranged in the area between the main pixel electrode of the pixel unit and the sub-pixel electrode of the adjacent pixel unit, so that the interference of the voltage of the common electrode to the area between the main pixel electrode of the pixel unit and the sub-pixel electrode of the adjacent pixel unit is reduced, the problem of dark fringes caused by disordered liquid crystal guiding due to the common electrode is solved, the light transmittance in the area is improved, and the picture display quality is improved.
Drawings
Fig. 1 is a top view of an array substrate according to an embodiment of the present invention;
fig. 2 is a schematic cross-sectional structure diagram of an array substrate according to an embodiment of the present invention;
fig. 3 is a top view of another array substrate according to an embodiment of the present invention;
fig. 4 is a schematic diagram of electric field distribution diagrams when there is no common electrode between adjacent pixel units and when there is a common electrode according to an embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, but rather should be construed as broadly as the present invention is capable of modification in various respects, all without departing from the spirit and scope of the present invention.
An embodiment of the present invention provides an array substrate, please refer to fig. 1 and fig. 2, the array substrate includes a substrate 900, and a scan line 100, a data line 200, a common electrode line 300 and a plurality of pixel units disposed on the substrate 900, where the pixel units include at least two thin film transistors, a main pixel electrode 400, a sub-pixel electrode 500 and a common electrode 600, the at least two thin film transistors are disposed above the scan line 100 and electrically connected to the main pixel electrode 400 and the sub-pixel electrode 500, respectively, the main pixel electrode 400 and the sub-pixel electrode 500 are disposed on two sides of the scan line 100, and no common electrode 600 is disposed in a region between the main pixel electrode 400 of at least one pixel unit and the sub-pixel electrode 500 of the pixel unit adjacent thereto.
It can be understood that in the PSVA type pixel design of 3T _8domain, the rotation angles of the liquid crystal molecules in the 4 display domains of the main display domain and the 4 display domains of the sub display domain in the same pixel unit are different by applying different voltages to the two domains (main pixel domain and sub pixel domain) of the same sub pixel, so as to improve the color shift problem. However, in the PSVA type pixel design, in the direction along which the data line 200 extends, liquid crystal molecules in the region between two adjacent pixel units, i.e., between the main pixel electrode 400 of one pixel unit and the sub-pixel electrode 500 adjacent to the pixel unit, are affected by the voltage of the common electrode 600, resulting in poor alignment and dark fringes. In this embodiment, the common electrode 600 is not disposed in the region between the main pixel electrode 400 of the pixel unit and the sub-pixel electrode 500 of the pixel unit adjacent to the main pixel electrode, so that interference of the voltage of the common electrode 600 on the liquid crystal molecule guiding in the region between two adjacent pixel units is reduced, the problem that the common electrode 600 causes liquid crystal guiding disorder to generate dark fringes is solved, the light transmittance in the region is improved, and the picture display quality is improved.
In one embodiment, referring to fig. 3 and 4, the common electrode 600 includes a first common sub-electrode 610 and a second common sub-electrode (not shown) perpendicular to each other, and the first common sub-electrode 610 is parallel to the data line 200; in the same pixel unit, in the extending direction of the first common sub-electrode 610, the distance between the projection of the distal end of the first common sub-electrode 610 on the bottom-sinking substrate and the projection of the distal end of the main pixel electrode 400 on the substrate 900 is 5-8 μm, where the distal end of the first common sub-electrode 610 is the end of the first common sub-electrode 610 far away from the scan line 100, and the distal end of the main pixel electrode 400 is the end of the main pixel electrode 400 far away from the scan line 100.
It can be understood that, for the array substrate of the 3T _8domain pixel design, a storage capacitor is formed by the overlapping portion of the common electrode 600 and the pixel electrode, and the storage capacitor is used for maintaining the driving voltage of the pixel unit when the gate of the thin film transistor is turned off. The first common sub-electrode 610 corresponds to the main pixel electrode 400 and the sub-pixel electrode 500, so that in an area between the main pixel electrode 400 of the pixel unit and the sub-pixel electrode 500 of the pixel unit adjacent to the main pixel electrode, liquid crystal molecules are subjected to double common voltages, the problem of poor orientation of the liquid crystal molecules is serious, and the dark fringe phenomenon is also serious. In the embodiment, the far end of the first common sub-electrode 610 is retracted by 5-8 μm, so that the phenomenon that liquid crystal molecules are subjected to double common voltages is avoided, the problem of poor guiding of the liquid crystal molecules generated in the region between the vertical stems of two adjacent pixel units is solved, and the light transmittance and the picture display quality are further improved.
In one embodiment, each of the main pixel electrode 400 and the sub-pixel electrode 500 includes a peripheral connection portion 410, a plurality of stripe-shaped main stems 420, and a plurality of stripe-shaped sub-pixel electrodes 430 connected to the main stems 420, the main stems include a horizontal main stem 421 and a vertical main stem 422 perpendicular to each other, the horizontal main stem 421 and the vertical main stem 422 divide the pixel unit into a plurality of display domains, and the sub-pixel electrodes 430 are located in the display domains. The trunk of the pixel electrode covers the common electrode 600, and the projection distance of the far end of the vertical trunk 422 of the main pixel and the far end of the first common sub-electrode 610 corresponding to the far end of the vertical trunk 422 of the main pixel on the substrate 900 is 5-8 μm, wherein the far end of the vertical trunk 422 of the main pixel is the end of the vertical trunk 422 of the main pixel far away from the scanning line 100.
It can be understood that in the present embodiment, the first common sub-electrode 610 corresponds to the vertical stem 422 of the main pixel electrode 400 and the vertical stem 422 of the sub-pixel electrode 500, and therefore in the region between the vertical stem 422 of the main pixel electrode 400 of the pixel unit and the vertical stem 422 of the sub-pixel electrode 500 of the pixel unit adjacent to the vertical stem 422 of the main pixel electrode 400 of the pixel unit, the liquid crystal molecules are subjected to the double common voltages, and the problem of poor orientation of the liquid crystal molecules is relatively serious. Therefore, the far end of the first common sub-electrode 610 is retracted by 5-8 μm, so that the phenomenon that liquid crystal molecules are subjected to double common voltages is avoided, the problem of poor liquid crystal molecule guiding in the area between the vertical main stems 422 of two adjacent pixel units is solved, and the light transmittance and the picture display quality are further improved.
In one embodiment, the projection distance of the far end of the vertical stem 422 of the main pixel and the far end of the first common sub-electrode 610 corresponding thereto on the substrate 900 is 6 μm. It can be understood that the distal end of the first common sub-electrode 610 is retracted by 6 μm, which can effectively reduce the problem of poor orientation of liquid crystal molecules generated in the region between the vertical stems 422 of two adjacent pixel units, and the display effect will not be affected by the smaller main storage capacitance due to the too small overlapping area between the main pixel electrode 400 and the common electrode 600 caused by the too short first common sub-electrode 610.
In one embodiment, the pixel unit includes a first thin film transistor TFT _1, a second thin film transistor TFT _2, and a third thin film transistor TFT _ 3;
the source electrode of the first thin film transistor TFT _1 is connected to the data line 200, and the drain electrode of the first thin film transistor TFT _1 is connected to the main pixel electrode 400, and is configured to provide a data driving signal to the main pixel electrode 400;
the source electrode of the second thin film transistor is connected to the data line 200, and the drain electrode of the second thin film transistor is connected to the sub-pixel electrode 500, and is configured to provide a data driving signal to the sub-pixel electrode 500;
the source of the third thin film transistor TFT _3 is connected to the source of the second thin film transistor TFT _2, and the drain of the third thin film transistor TFT _3 is connected to the common electrode line 300, and is configured to apply a voltage of a data driving signal to the sub-pixel electrode 500.
In one embodiment, in one pixel unit, the gate of the first thin film transistor TFT _1, the gate of the second thin film transistor TFT _2, and the gate of the third thin film transistor TFT _3 are connected to the same scan line 100, and the drain of the first thin film transistor TFT _1 and the drain of the second thin film transistor TFT _2 are connected to the same data line 200.
During the display process, a main storage capacitor is formed between the main pixel electrode 400 and the common electrode 600, and a sub storage capacitor is formed between the sub pixel electrode 500 and the common electrode 600. When the scan line 100 is turned on, the first thin film transistor TFT _1, the second thin film transistor TFT _2, and the third thin film transistor TFT _3 are simultaneously turned on, and the data line 200 charges the main pixel electrode 400 and the sub pixel electrode 500 with a data driving signal. Meanwhile, the third thin film transistor TFT _3 transfers a portion of the charges on the sub-pixel electrode 500 to the common electrode line 300, so that the voltage across the main storage capacitor is greater than the voltage across the storage capacitor, and the luminance of the area corresponding to the sub-pixel electrode 500 is lower than the luminance of the area corresponding to the main pixel electrode 400. In addition, the deflection angles of the liquid crystal molecules in the region corresponding to the main pixel electrode 400 and the region corresponding to the sub-pixel electrode 500 are different, so that the large viewing angle color cast phenomenon of the VA mode liquid crystal display is improved.
In one embodiment, a first conductive channel formed between the source and the drain of the first thin film transistor TFT _1 is U-shaped, a second conductive channel formed between the source and the drain of the second thin film transistor TFT _2 is U-shaped, and a third conductive channel formed between the source and the drain of the third thin film transistor TFT _3 is in-line shape. In a specific design, the source electrode of the first thin film transistor TFT _1 and the source electrode of the second thin film transistor TFT _2 may be designed to be U-shaped, so as to implement a U-shaped design of the thin film transistors, and reduce lengths of the source electrodes and the drain electrodes of the first thin film transistor TFT _1 and the second thin film transistor TFT _2 in the extending direction along the scan line 100, that is, reduce a distance of a width of a conductive channel in the extending direction along the scan line 100, so as to reduce a space required by the wiring, and implement a narrow frame design of the display panel.
In one embodiment, a width-to-length ratio of the first conductive channel is greater than a width-to-length ratio of the second conductive channel. It can be understood that the characteristics of the thin film transistor are related to the ratio of the width to the length of the conductive channel, and the larger the ratio of the width to the length of the conductive channel, the better the performance of the thin film transistor, so that the brightness of the region corresponding to the sub-pixel electrode 500 can be lower than that of the region corresponding to the main pixel electrode 400 by designing the ratio of the width to the length of the first conductive channel and the ratio of the width to the length of the second conductive channel, thereby further improving the large viewing angle color shift phenomenon of the VA-mode liquid crystal display.
In one embodiment, the array substrate further includes a gate insulating layer 700 and a passivation layer 800, the gate insulating layer 700 is disposed between the gate electrode of the thin film transistor and the source and drain electrodes disposed on the same layer, and the passivation layer 800 is disposed between the layer including the main pixel electrode and the sub pixel electrode and the layer including the source and drain electrodes.
Based on the same inventive concept, the embodiment of the present invention further provides a method for manufacturing an array substrate, where the method includes a step of forming a scan line 100, a data line 200, a common electrode 600, and a common electrode line 300, a step of forming a thin film transistor, and a step of forming a main pixel electrode 400 and a sub-pixel electrode 500, where the step of forming the thin film transistor includes a step of forming a gate, a source, a drain, and an active layer, where the at least two thin film transistors are disposed above the scan line 100 and electrically connected to the main pixel electrode 400 and the sub-pixel electrode 500, respectively, the main pixel electrode 400 and the sub-pixel electrode 500 are disposed on two sides of the scan line 100, and a region between the main pixel electrode 400 of at least one pixel unit and the sub-pixel electrode 500 of an adjacent pixel unit is not provided with the common electrode 600.
In one embodiment, the common electrode 600 includes a first common sub-electrode 610 and a second common sub-electrode perpendicular to each other, and the first common sub-electrode 610 is parallel to the data line 200; in the same pixel unit, in the extending direction of the first common sub-electrode 610, the distance between the projection of the distal end of the first common sub-electrode 610 on the bottom-sinking substrate and the projection of the distal end of the main pixel electrode 400 on the substrate 900 is 5-8 μm, where the distal end of the first common sub-electrode 610 is the end of the first common sub-electrode 610 far away from the scan line 100, and the distal end of the main pixel electrode 400 is the end of the main pixel electrode 400 far away from the scan line 100.
It can be understood that, in the present embodiment, the distal end of the first common sub-electrode 610 is retracted by 5 to 8 μm, so as to avoid the phenomenon that the liquid crystal molecules are subjected to two common voltages, thereby improving the problem of poor orientation of the liquid crystal molecules generated in the region between the vertical stems 422 of two adjacent pixel units, and further improving the light transmittance and the image display quality.
Taking the PSVA type array substrate designed by the 3T _8domain pixels as an example, the manufacturing method of the array substrate specifically includes the following steps:
step one, the common electrode 600, the common electrode line 300, the gate electrode of the first thin film transistor TFT _1, the gate electrode of the second thin film transistor, the gate electrode of the third thin film transistor TFT _3, and the scan line 100 are formed on the substrate 900. In this embodiment, the step of forming the common electrode 600, the common electrode line 300, the gate electrode and the scan line 100 on the substrate 900 includes: a metal film is deposited on the substrate 900, and then a pattern including the scan line 100, the gate electrode, the common electrode 600 and the common electrode line 300 is formed through a first patterning process, wherein the scan line 100, the gate electrode and the common electrode 600 are arranged at intervals. The common electrode 600 includes a first common sub-electrode 610 and a second common sub-electrode perpendicular to each other, and the first common sub-electrode 610 is parallel to the data line 200; in the same pixel unit, in the extending direction of the first common sub-electrode 610, the distance between the projection of the distal end of the first common sub-electrode 610 on the bottom-sinking substrate and the projection of the distal end of the main pixel electrode 400 on the substrate 900 is 5-8 μm, where the distal end of the first common sub-electrode 610 is the end of the first common sub-electrode 610 far away from the scan line 100, and the distal end of the main pixel electrode 400 is the end of the main pixel electrode 400 far away from the scan line 100.
In the invention, the patterning process may only comprise a photolithography process, or may comprise a photolithography process and an etching step, and may also comprise other processes for forming a predetermined pattern, such as printing, ink jetting, etc.; the photolithography process refers to a process of forming a pattern by using a photoresist, a mask plate, an exposure machine, and the like, including processes of film formation, exposure, development, and the like. The corresponding patterning process may be selected according to the structure formed in the present invention.
Step two, forming a gate insulating layer on the substrate 900 on which the common electrode 600, the common electrode line 300, the gate electrode of the first thin film transistor TFT _1, the gate electrode of the second thin film transistor TFT _2, the gate electrode of the third thin film transistor TFT _3, and the scan line 100 are formed. In this embodiment, a silicon nitride (SiNx) or silicon oxide (SiOx) layer is deposited on the substrate 900 after the first step to form a gate insulating layer. A first through hole is formed in the gate insulating layer, and a drain electrode of the third thin film transistor TFT _3 is electrically connected to the common electrode 600 through the first through hole.
And step three, forming the active layer on the substrate 900 on which the gate insulating layer is formed. In this embodiment, an amorphous silicon thin film layer is formed over the gate insulating layer by a plasma enhanced chemical vapor deposition method or other similar methods, and then the amorphous silicon is crystallized by a laser annealing process or a solid phase crystallization process to form a polysilicon thin film layer, and a pattern including a low temperature polysilicon active layer is formed by a second patterning process.
And fourthly, forming the data line 200, the source electrode and the drain electrode of the first thin film transistor TFT _1, the source electrode and the drain electrode of the second thin film transistor TFT _2, and the source electrode and the drain electrode of the third thin film transistor TFT _3 on the substrate 900 on which the active layer is formed. In this embodiment, the metal layer of the source and drain electrodes and the data line 200 is deposited first, and after exposure using photoresist and mask, the data line 200, the source and drain electrodes are patterned by etching. The etching method may be dry etching or wet etching, and the method is not limited. A first conductive channel formed between the source electrode and the drain electrode of the first thin film transistor TFT _1 is U-shaped, a second conductive channel formed between the source electrode and the drain electrode of the second thin film transistor TFT _2 is U-shaped, and a third conductive channel formed between the source electrode and the drain electrode of the third thin film transistor TFT _3 is in-line shape.
Step five, forming a passivation layer on the substrate 900 on which the data line 200, the source and drain electrodes of the first thin film transistor TFT _1, the source and drain electrodes of the second thin film transistor TFT _2, and the source and drain electrodes of the third thin film transistor TFT _3 are formed, and forming a second through hole and a third through hole penetrating through the passivation layer, wherein the main pixel electrode 400 is electrically connected with the drain electrode of the first thin film transistor TFT _1 through the second through hole, and the sub pixel electrode 500 is electrically connected with the drain electrode of the second thin film transistor TFT _2 through the third through hole. In this embodiment, the passivation layer protects the first thin film transistor TFT _1, the second thin film transistor TFT _2, and the third thin film transistor TFT _3, and prevents the first thin film transistor TFT _1, the second thin film transistor TFT _2, and the third thin film transistor TFT _3 from being corroded.
Step six, forming the main pixel electrode 400 and the sub-pixel electrode 500 on the substrate 900 on which the passivation layer is formed. Depositing a layer of Indium Tin Oxide (ITO) transparent conductive film on the passivation layer on the substrate 900 after the fifth step by using a magnetron sputtering method, and forming a pattern comprising a pixel electrode by a composition process, namely coating photoresist, exposing and developing, wet etching and stripping; and the through hole is filled with a conductive material for forming the pixel electrode, and the pixel electrode is electrically connected with the drain electrode through the through hole. Through the above steps, the array substrate provided by the embodiment of the invention is formed. In this embodiment, each of the main pixel electrode 400 and the sub-pixel electrode 500 includes a peripheral connection portion 410, a plurality of strip-shaped trunks, and a plurality of strip-shaped pixel sub-electrodes 430 connected to the trunks, where the trunks include a horizontal trunk 421 and a vertical trunk 422 that are perpendicular to each other, the pixel unit is divided into a plurality of display domains by the horizontal trunk 421 and the vertical trunk 422, and the pixel sub-electrodes 430 are located in the display domains.
Based on the same inventive concept, the invention also provides a display device, which comprises the array substrate of any one of the embodiments. Wherein, the display device can be: the display device comprises any product or component with a display function, such as a liquid crystal panel, electronic paper, an OLED panel, a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
In summary, embodiments of the present invention provide an array substrate, a method for manufacturing the same, and a display device. The array substrate comprises a substrate 900, and a scanning line 100, a data line 200, a common electrode line 300 and a plurality of pixel units which are arranged on the substrate 900, wherein the pixel units comprise a thin film transistor, a main pixel electrode 400, a sub-pixel electrode 500 and a common electrode 600, and the common electrode 600 is not arranged in the area between the main pixel electrode 400 of at least one pixel unit and the sub-pixel electrode 500 of the pixel unit adjacent to the main pixel electrode 400. In the invention, the common electrode 600 is not arranged in the region between the main pixel electrode 400 of the pixel unit and the sub-pixel electrode 500 of the adjacent pixel unit, so that the interference of the voltage of the common electrode 600 to the region between the main pixel electrode 400 of the pixel unit and the sub-pixel electrode 500 of the adjacent pixel unit is reduced, the problem that the common electrode 600 causes liquid crystal guide disorder to generate dark fringes is solved, the light transmittance in the region is improved, and the picture display quality is further improved.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (7)
1. An array substrate is characterized by comprising a substrate base plate, and a scanning line, a data line, a common electrode line and a plurality of pixel units which are arranged on the substrate base plate, wherein each pixel unit comprises at least two thin film transistors, a main pixel electrode, a sub-pixel electrode and a common electrode, the at least two thin film transistors are arranged above the scanning line and are respectively and electrically connected with the main pixel electrode and the sub-pixel electrode, the main pixel electrode and the sub-pixel electrode are respectively arranged on two sides of the scanning line, and the common electrode is not arranged in the area between the main pixel electrode of at least one pixel unit and the sub-pixel electrode of the pixel unit adjacent to the main pixel electrode;
the common electrode comprises a first common sub-electrode and a second common sub-electrode which are perpendicular to each other, and the first common sub-electrode is parallel to the data line;
the main pixel electrode and the sub-pixel electrode respectively comprise a peripheral connecting part, a plurality of strip-shaped main trunks and a plurality of strip-shaped pixel sub-electrodes connected with the main trunks, the main trunks comprise horizontal main trunks and vertical main trunks which are perpendicular to each other, the pixel units are divided into a plurality of display domain areas by the horizontal main trunks and the vertical main trunks, and the pixel sub-electrodes are located in the display domain areas;
the trunk of the pixel electrode covers the common electrode, in the same pixel unit, in the extending direction of the first common sub-electrode, the projection distance of the far end of the vertical trunk of the main pixel and the far end of the first common sub-electrode corresponding to the far end of the vertical trunk of the main pixel on the substrate is 5-8 μm, wherein the far end of the vertical trunk of the main pixel is one end of the vertical trunk of the main pixel, which is far away from the scanning line; the far end of the first common sub-electrode is the end of the first common sub-electrode far away from the scanning line, and the projection of the far end of the first common sub-electrode on the substrate base plate is closer to the scanning line than the projection of the far end of the main pixel electrode on the substrate base plate.
2. The array substrate of claim 1, wherein a projection distance of a distal end of the vertical stem of the main pixel and a distal end of the first common sub-electrode corresponding thereto on the substrate is 6 μm.
3. The array substrate of claim 1, wherein the pixel unit comprises a first thin film transistor, a second thin film transistor, and a third thin film transistor;
the source electrode of the first thin film transistor is connected with the data line, and the drain electrode of the first thin film transistor is connected with the main pixel electrode and used for providing a data driving signal for the main pixel electrode;
and the source electrode of the second thin film transistor is connected with the data line, and the drain electrode of the second thin film transistor is connected with the sub-pixel electrode and used for providing a data driving signal for the sub-pixel electrode.
4. The array substrate of claim 3, wherein in one pixel cell, the gate of the first thin film transistor, the gate of the second thin film transistor and the gate of the third thin film transistor are connected to a same scan line, and the source of the first thin film transistor and the source of the second thin film transistor are connected to a same data line.
5. The array substrate of claim 3, wherein a first conductive channel formed between the source and the drain of the first thin film transistor is U-shaped, a second conductive channel formed between the source and the drain of the second thin film transistor is U-shaped, and a third conductive channel formed between the source and the drain of the third thin film transistor is I-shaped.
6. The manufacturing method of the array substrate is characterized by comprising a step of forming a scanning line, a data line, a common electrode and a common electrode line, a step of forming at least two thin film transistors and a step of forming a main pixel electrode and a secondary pixel electrode, wherein the step of forming the thin film transistors comprises a step of forming a grid electrode, a source electrode, a drain electrode and an active layer, the at least two thin film transistors are arranged above the scanning line and are respectively and electrically connected with the main pixel electrode and the secondary pixel electrode, the main pixel electrode and the secondary pixel electrode are respectively arranged on two sides of the scanning line, and no common electrode is arranged in an area between the main pixel electrode of at least one pixel unit and the secondary pixel electrode of the pixel unit adjacent to the main pixel electrode;
the common electrode comprises a first common sub-electrode and a second common sub-electrode which are perpendicular to each other, and the first common sub-electrode is parallel to the data line;
the main pixel electrode and the sub-pixel electrode respectively comprise a peripheral connecting part, a plurality of strip-shaped main trunks and a plurality of strip-shaped pixel sub-electrodes connected with the main trunks, the main trunks comprise horizontal main trunks and vertical main trunks which are perpendicular to each other, the pixel units are divided into a plurality of display domain areas by the horizontal main trunks and the vertical main trunks, and the pixel sub-electrodes are located in the display domain areas;
the trunk of the pixel electrode covers the common electrode, in the same pixel unit, in the extending direction of the first common sub-electrode, the projection distance of the far end of the vertical trunk of the main pixel and the far end of the first common sub-electrode corresponding to the far end of the vertical trunk of the main pixel on the substrate is 5-8 μm, wherein the far end of the vertical trunk of the main pixel is one end of the vertical trunk of the main pixel, which is far away from the scanning line; the far end of the first common sub-electrode is the end of the first common sub-electrode far away from the scanning line, and the projection of the far end of the first common sub-electrode on the substrate base plate is closer to the scanning line than the projection of the far end of the main pixel electrode on the substrate base plate.
7. A display device comprising the array substrate according to any one of claims 1 to 5.
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| CN201910369927.5A CN110174787B (en) | 2019-05-06 | 2019-05-06 | Array substrate, manufacturing method thereof and display device |
| PCT/CN2020/088775 WO2020224591A1 (en) | 2019-05-06 | 2020-05-06 | Array substrate and manufacturing method therefor, and display device |
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| CN110174787B (en) * | 2019-05-06 | 2021-11-30 | 惠科股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN111077711A (en) * | 2019-12-30 | 2020-04-28 | Tcl华星光电技术有限公司 | Short-circuit bar structure, array substrate and display device |
| CN111308802B (en) * | 2020-03-12 | 2021-07-06 | Tcl华星光电技术有限公司 | Array substrate and display panel |
| WO2021184186A1 (en) * | 2020-03-17 | 2021-09-23 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN111474779A (en) * | 2020-05-13 | 2020-07-31 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and liquid crystal display panel |
| CN111628004A (en) * | 2020-05-18 | 2020-09-04 | 深圳市华星光电半导体显示技术有限公司 | Low-delay thin film transistor, array substrate and display panel |
| CN112017545A (en) * | 2020-09-03 | 2020-12-01 | Tcl华星光电技术有限公司 | Display panel and display device |
| CN112068371A (en) * | 2020-09-10 | 2020-12-11 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
| CN112363356B (en) * | 2020-11-17 | 2022-02-22 | 深圳市华星光电半导体显示技术有限公司 | Display panel |
| CN115151859B (en) * | 2020-12-04 | 2023-10-20 | 京东方科技集团股份有限公司 | Array substrate and display panel |
| CN113064299A (en) * | 2021-03-16 | 2021-07-02 | 深圳市华星光电半导体显示技术有限公司 | Liquid crystal display panel, preparation method thereof and liquid crystal display device |
| CN113192984A (en) * | 2021-04-22 | 2021-07-30 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| CN113485051B (en) * | 2021-06-30 | 2023-09-01 | 惠科股份有限公司 | Array substrate and display panel |
| CN113655649B (en) * | 2021-07-22 | 2023-10-24 | 京东方科技集团股份有限公司 | Display panel, preparation method thereof, display device, display system and display method |
| CN114624909B (en) * | 2022-03-28 | 2023-06-30 | 深圳市华星光电半导体显示技术有限公司 | Display module, manufacturing method thereof and electronic terminal |
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