WO2022042017A1 - 接口电路、数据传输电路以及存储器 - Google Patents

接口电路、数据传输电路以及存储器 Download PDF

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Publication number
WO2022042017A1
WO2022042017A1 PCT/CN2021/103707 CN2021103707W WO2022042017A1 WO 2022042017 A1 WO2022042017 A1 WO 2022042017A1 CN 2021103707 W CN2021103707 W CN 2021103707W WO 2022042017 A1 WO2022042017 A1 WO 2022042017A1
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Prior art keywords
circuit
clock
data
input buffer
circuits
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PCT/CN2021/103707
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English (en)
French (fr)
Inventor
林峰
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长鑫存储技术有限公司
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Priority to EP21856926.7A priority Critical patent/EP4006905A4/en
Priority to JP2022539728A priority patent/JP7320139B2/ja
Priority to KR1020227021310A priority patent/KR20220106787A/ko
Priority to US17/479,184 priority patent/US11842792B2/en
Publication of WO2022042017A1 publication Critical patent/WO2022042017A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals

Definitions

  • the embodiments of the present application relate to an interface circuit, a data transmission circuit, and a memory.
  • DRAM Dynamic Random Access Memory
  • Each memory cell usually includes a capacitor and a transistor.
  • the gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor.
  • the voltage signal on the word line can control the opening or closing of the transistor, and then through the bit line
  • the data information stored in the capacitor is read, or the data information is written into the capacitor through the bit line for storage.
  • DRAM can be divided into Double Data Rate (DDR) DRAM, GDDR (Graphics Double Data Rate) DRAM, and Low Power Double Data Rate (LPDDR) DRAM.
  • DDR Double Data Rate
  • GDDR Graphics Double Data Rate
  • LPDDR Low Power Double Data Rate
  • An embodiment of the present application provides an interface circuit, including: a clock pad for transmitting a clock signal; M data pads for transmitting a data signal; and M input buffer circuits, corresponding to the data pads one-to-one, Driven by the clock signal, each of the input buffer circuits receives the data signal transmitted by the data pad corresponding to the input buffer circuit; wherein, the clock pad and the data pad arranged in the first row, and the M data pads are arranged on both sides of the clock pad, half of the M data pads are arranged on each side, and the M input buffer circuits are arranged in the second Row, with the clock pad as a reference, an axis perpendicular to the first row is formed, the M input buffer circuits are arranged on both sides of the axis, and the M input buffer circuits are arranged on each side. In half, the distance between each of the input buffer circuits and the axis is smaller than the distance between the data pads corresponding to the input buffer circuit and the axis, and the M is an integer greater than or equal
  • An embodiment of the present application further provides a data transmission circuit, including: the above interface circuit; M serial-parallel conversion circuits, wherein the M serial-parallel conversion circuits correspond to the M input buffer circuits one-to-one, The output of the input buffer circuit is used as the input of the corresponding serial-parallel conversion circuit.
  • An embodiment of the present application further provides a memory including the above-mentioned interface circuit.
  • 1 is a schematic structural diagram of an interface circuit
  • FIG. 2 is a schematic structural diagram of an interface circuit provided by an embodiment of the present application.
  • FIG. 3 is another schematic structural diagram of an interface circuit provided by an embodiment of the present application.
  • FIG. 4 is another schematic structural diagram of an interface circuit provided by an embodiment of the present application.
  • FIG. 5 is a schematic layout diagram of an interface circuit provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of the layout corresponding to the interface circuit provided in FIG. 1;
  • FIGS. 7 to 9 are schematic diagrams of four structures of an interface circuit in which a data pad includes a command pad and an address pad provided by an embodiment of the application;
  • FIG. 10 is a schematic layout diagram of a data transmission circuit provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a memory provided by an embodiment of the present application applied to a storage system.
  • the write data sampling signal (Dqs signal or Wck signal) is used as the clock for writing data; during the write operation, the edges (rising and falling edges) of the Dqs or Wck signal should be timed with the data signal (DQ signal) ) at the center (substantially aligned at the center may also be allowed for timing margins).
  • the transmission path of the DQ signal is defined as the data path. The length of the data path will affect the time when the edge of the DQ signal reaches the data port of the device (such as the data port of the register).
  • the transmission path of the Dqs or Wck signal is defined as the clock path.
  • the length of the clock path Affects the time when the Dqs or Wck signal arrives at the device clock port (such as the clock port of a register), the difference between the data path of the DQ signal and the clock path of the Dqs or Wck signal (the edge of the Dqs or Wck signal and the center of the DQ signal
  • the time interval between tDQS2DQ or tWCK2DQ is defined as tDQS2DQ or tWCK2DQ.
  • the smaller tDQS2DQ or tWCK2DQ the more matched the data path and the clock path, and the better the corresponding circuit timing.
  • FIG. 1 is a schematic structural diagram of an interface circuit.
  • the interface circuit includes: a plurality of data pads 11 arranged side by side for transmitting data signals, a central axis AA1, and half of the plurality of data pads 11 are distributed on one side of the central axis AA1, and the other half are distributed on the central axis AA1.
  • the other side of the central axis AA1; the clock pad 13, the clock pad 13 is located at the central axis AA1; a plurality of input buffer circuits 14, corresponding to the data pad 11, and each input buffer circuit 14 to the corresponding data pad
  • the data paths between 11 and 11 are the same or basically the same within a certain error range.
  • a certain error range here can be understood, but not limited to, the error between different paths is within 1% or 3%; a plurality of output buffer circuits (not shown) correspond to the data pads 11, and each The timing paths between the output buffer circuits and the corresponding data pads 11 are the same; the clock receiving circuit 16 and the clock generating circuit 17, the clock receiving circuit 16 is electrically connected to the clock pad 13 for receiving the clock signal and transmitting the clock signal To the clock generation circuit 17, the clock generation circuit 17 receives the clock signal and generates a driving clock, and the input buffer circuit 14 receives the driving clock and the data signal and transmits the data signal.
  • DQ0/DQ1...DQ7 is used to mark the data pad 11, and Dqs is used to mark the clock pad 13 (Dqs is used as an example below, the application of Wck is the same or similar to Dqs, for example, in LPDDR4, the clock is called Dqs, In LPDDR5, the clock is called Wck), and the input buffer circuit 14 is marked with RX0/RX1...RX7, and the input buffer circuit 14 is also a receiving circuit.
  • the clock receiving circuit 16 is marked with RX_CLK
  • the clock generating circuit 17 is marked with CLKGEN.
  • the data path for transmitting the data signal of the data pad 11 to the corresponding input buffer circuit 14 is the first path
  • the timing path for transmitting the clock signal of the clock pad 13 to the corresponding input buffer circuit 14 is the second path.
  • different input buffer circuits 14 have the same first path, however, the farther the input buffer circuit 14 is from the clock pad 13, the longer the second path, and therefore, the farther from the clock pad 13, the longer the second path.
  • the larger the gap between the corresponding first path and the second path the larger the corresponding tDQS2DQ, and the more serious the problem of timing violation.
  • the input buffer circuit 14 that is farthest from the clock pad 13 corresponds to tDQS2DQ.
  • the data signals of different data pads 11 arrive at the corresponding input buffer circuits 14 close to each other.
  • the clock signal reaches the The time of the farthest input buffer circuit 14 (input buffer circuit 14 corresponding to DQ0) is the latest, and the time when the clock signal reaches the input buffer circuit 14 (input buffer circuit 14 corresponding to DQ3) closest to the clock pad 13 is the earliest,
  • This causes the input buffer circuit 14 closest to the clock pad 13 to receive and transmit the data signal first, while the input buffer circuit 14 farthest from the clock pad 13 transmits the data signal last, and the two input buffer circuits 14 transmit the data signal
  • the time gap is large.
  • the clock path of the input buffer circuit 14 corresponding to DQ3 matches the data path, it is not easy to match the clock path and data path of the input buffer circuit 14 corresponding to DQ0.
  • each data pad 11 has a corresponding first port d0/d1...d7
  • each input buffer circuit 14 has a second port r0/r1 connected to the first port of the corresponding data pad 11 respectively ...r7
  • each of the input buffer circuits 14 has a third port v0/v1...v7 connected to the clock generation circuit 17
  • the clock generation circuit 17 has a fourth port c0 connected to each of the input buffer circuits 14 on the side of the central axis AA1
  • the clock generation circuit 17 also has a fifth port c1 connected to each input buffer circuit 14 located on the other side of the central axis AA1.
  • the clock path of the clock signal is c0 ⁇ v0, and the data path of the data signal is d0 ⁇ r0; for RX1, the clock path of the clock signal is c1 ⁇ v1, and the data path of the data signal is d1 ⁇ r1; And so on; it is not difficult to find that for different input buffer circuits 14, the corresponding data paths are unchanged, but the input buffer circuit 14 that is closer to the central axis AA1 has a shorter clock path. Therefore, tDQS2DQ appears. different issues.
  • tDQS2DQ corresponding to different input buffer circuits 14 is quite different, and in the memory, there are strict requirements on the value of tDQS2DQ, for example, the value of tDQS2DQ is required to be no greater than 800ps, otherwise it will cause timing violation.
  • the embodiment of the present application provides an interface circuit, which shortens the clock path for transmitting the clock signal to each input buffer circuit by means of centralized layout of each input buffer circuit, thereby shortening tDQS2DQ, and further improving the problem of timing violation.
  • the interface circuit provided in this embodiment will be described in detail below with reference to the accompanying drawings.
  • FIG. 2 is a schematic structural diagram of an interface circuit provided by an embodiment of the present application.
  • the interface circuit includes: a clock pad 102 for transmitting a clock signal; M data pads 101 for transmitting a data signal; and M input buffer circuits 103 , one with the data pad 101 .
  • each input buffer circuit 103 receives the data signal transmitted by the data pad 101 corresponding to the input buffer circuit 103 under the driving of the clock signal; wherein, the clock pad 102 and the data pad 101 are arranged in the first row, M data pads 101 are arranged on both sides of the clock pad 102, and half of the M data pads 101 are arranged on each side, M input buffer circuits 103 are arranged in the second row, and are formed with the clock pad 102 as a reference Perpendicular to the axis AA1 of the first row, M input buffer circuits 103 are arranged on both sides of the axis AA1, half of the M input buffer circuits 103 are arranged on each side, and the distance between each input buffer circuit 103 and the axis AA1 is
  • M is an even number, for example, M is equal to 8
  • 4 data pads 101 are arranged on each side of the axis AA1
  • M is an odd number, for example, M is equal to 7
  • 3 data pads 101 are arranged on one side of the axis AA1
  • four data pads 101 are arranged on the other side.
  • M data pads and clock pads are arranged in the first row, M data pads are arranged on both sides of the clock pads, and take the data pads as a reference to form an axis perpendicular to the first row; M input pads
  • the buffer circuits are arranged on both sides of the axis, half of the M input buffer circuits are arranged on each side, and the distance between each input buffer circuit and the axis is smaller than the distance between the data pads corresponding to the input buffer circuit and the axis.
  • the clock path for transmitting the clock signal to each input buffer circuit is shortened, the matching degree between the clock path and the data path is improved, and the tDQS2DQ and timing are further reduced. violations; in addition, the power consumption of the interface circuit is reduced due to the reduced clock path.
  • the interface circuit can be applied to a DRAM, such as LPDDR4.
  • half of the M data pads 101 are located on one side of the axis AA1, and the other half of the M data pads 101 are located on the other side of the axis AA1.
  • the data pads 101 are used to transmit DQ signals, that is, the data signals are DQ signals.
  • each data pad 101 is marked with DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7; correspondingly, the number of input buffer circuits 103 is also 8, and each input buffer circuit 103 is denoted by RX0, RX1, RX2, RX3, RX4, RX5, RX6, and RX7. It can be understood that, in other embodiments, the number of data pads can be reasonably set according to the actual requirements of the interface circuit.
  • the clock pad 102 can be used to transmit a Dqs signal, that is, the clock signal is a Dqs signal, and the Dqs signal refers to a write clock signal or a read clock signal, and the clock pad 102 is marked with Dqs in FIG. 2 .
  • FIG. 3 is another schematic structural diagram of an interface circuit provided by an embodiment of the present application.
  • the clock pad 102 may be a differential input pad, including a first clock pad 112 and a second clock pad 122 , and the first clock pad 112 and the second clock pad 122 respectively transmit complementary clock signal.
  • the first clock pad 112 is denoted by Dqs_t, and the first clock pad 112 is used to transmit the Dqs_t clock signal
  • the second clock pad 122 is denoted by Dqs_c
  • the second clock pad 122 is used to transmit the Dqs_c clock. Signal.
  • the first clock pads 112 and the second clock pads 122 are arranged symmetrically with respect to the axis AA1.
  • the clock path between the first clock pad 112 and the input buffer circuit 103 on one side of the axis AA1 is the first clock path
  • the clock path between the second clock pad 122 and the input buffer circuit 103 on the other side of the axis AA1 is the second clock path.
  • the clock path, set in this way is beneficial to reduce the gap between the first clock path and the second clock path, thereby reducing or avoiding the adverse effect on tDQS2DQ caused by the large gap between the first clock path and the second clock path.
  • first clock pad and the second clock pad may also be arranged on the same side of the axis.
  • first row does not refer to the first row in which the clock pads 102 and the data pads 101 are located in the overall pads of the interface circuit, but only to illustrate that the clock pads 102 and the data pads 101 are the same.
  • the rows are arranged and the axis AA1 is illustrated for the convenience of definition.
  • the clock pads 102 and the data pads 101 may be located in any row of the overall pads of the interface circuit.
  • the "second row” does not refer to the second row where the input buffer circuits 103 are located in the overall pads of the interface circuit, but only to illustrate that the M input buffer circuits 103 are arranged in the same row and are soldered with the clock pads 102 and the data pads.
  • the disks 101 are located in different rows.
  • the M input buffer circuits 103 may be located in any row of the overall pads of the interface circuit, and one or more rows of pads may also be provided between the input buffer circuits 103 and the data pads 101 .
  • the interface circuit may further include: a clock processing circuit, which is electrically connected to the clock pad 102 and the M input buffer circuits 103 for receiving the clock signal and processing the clock signal as the M input buffer circuits 103 drive clock. That is to say, the input buffer circuit 103 is driven by a clock signal, but actually, the input buffer circuit 103 is driven by a driving clock generated by processing the clock signal.
  • a clock processing circuit which is electrically connected to the clock pad 102 and the M input buffer circuits 103 for receiving the clock signal and processing the clock signal as the M input buffer circuits 103 drive clock. That is to say, the input buffer circuit 103 is driven by a clock signal, but actually, the input buffer circuit 103 is driven by a driving clock generated by processing the clock signal.
  • the clock processing circuit coincides with the axis AA1, that is, the clock processing circuit is located at the position of the axis AA1. In this way, it is beneficial to reduce the difference of the clock paths required for the driving clock to be transmitted to the input buffer circuits 103 located on both sides of the axis AA1.
  • the above clock processing circuit is located at the position of the axis AA1, which does not mean that the clock processing circuit is completely symmetrical with respect to the axis AA1.
  • the clock circuit is roughly located at the position of AA1, and its center line is allowed to deviate from AA1 by a certain amount. value, such as a deviation of 10% or 20%.
  • the clock processing circuit includes a clock receiving circuit 114 and a clock generating circuit 115 .
  • the clock receiving circuit 114 is electrically connected to the clock pad 102 for receiving the clock signal, and the output of the clock receiving circuit 114 is used as the input of the clock generating circuit 115, and the clock generating circuit 115 is used for generating the driving clock.
  • the clock generation circuit 115 is located on the axis AA1. In FIG. 2 , the clock receiving circuit 114 is marked with RX_CLK, and the clock receiving circuit 115 is marked with CLKGEN.
  • the clock receiving circuit 114 includes: a first clock receiving circuit electrically connected to the first clock pad 112 for receiving the Dqs_t clock signal; a second clock receiving circuit electrically connected to the second clock pad 122 for receiving the Dqs_t clock signal; Receive the Dqs_c clock signal. And the first clock receiving circuit and the second clock circuit are arranged symmetrically with respect to the axis AA1.
  • the input buffer circuit 103 For the input buffer circuit 103, it receives the data signal under the driving of the clock signal, and continues to transmit the data signal. That is to say, when the data signal of the data pad 101 is transmitted to the input buffer circuit 103, the input buffer circuit 103 will accept the data signal only when the clock signal has also been transmitted to the input buffer circuit 103 Transmission out; if the data signal is transmitted to the input buffer circuit 103 and the clock signal has not been reached, the input buffer circuit 103 will not transmit the data signal.
  • the distance between each input buffer circuit 103 and the axis AA1 is smaller than the distance between the data pad 101 corresponding to the input buffer circuit 103 and the axis AA1 , that is, compared with the data pad 101 , each input buffer circuit 103 is farther toward the axis AA1 .
  • the axis AA1 is close together. Specifically, based on the axis AA1, the layout density of the M input buffer circuits 103 is greater than the layout density of the M data pads 101; for each data pad 101 and its corresponding input buffer circuit 103, the data The distance between the pad 101 and the axis AA1 is greater than the distance between the input buffer circuit 103 and the axis AA1. In addition, the closer the distance between the data pad 101 and the axis AA1 is, the closer the distance between the input buffer circuit 103 corresponding to the data pad 101 and the axis AA1 is.
  • the length of the input data path between each input buffer circuit 103 and the data pad 101 corresponding to the input buffer circuit 103 is the first length
  • the length of the clock path between each input buffer circuit 103 and the clock pad 102 is the second length
  • the first length is positively correlated with the second length. That is, for all the input buffer circuits 103, the larger the first length corresponds to the larger the second length, and the smaller the first length corresponds to the smaller the second length. That is to say, the farther the data pad 101 is from the axis AA1, the farther the corresponding input buffer circuit 103 is from the axis AA1; the farther the data pad 101 is from the axis AA1, the farther the corresponding input buffer circuit 103 is from the axis AA1. close.
  • the difference between the data path between each data pad 101 and the input buffer circuit 103 and the clock path between each clock pad 102 and the input buffer circuit 103 is reduced, thereby enabling the present embodiment to shorten different input
  • the tDQS2DQ of the buffer circuit 103 improves the matching degree between the clock paths and the data paths of the different input buffer circuits 103 , thereby improving the timing characteristics of the data signals transmitted by the different input buffer circuits 103 .
  • each data pad 101 has a corresponding first port d0/d1...d7
  • each input buffer circuit 103 has a second port r0/r1 connected to the first port of the corresponding data pad 101 respectively ... r7
  • each of the input buffer circuits 103 has a third port v0/v1...
  • the clock generation circuit 115 also has a fifth port c1 connected to each input buffer circuit 103 on the other side of the central axis AA1.
  • the clock path of the clock signal is c0 ⁇ v0, and the data path of the data signal is d0 ⁇ r0; for RX1, the clock path of the clock signal is c1 ⁇ v1, and the data path of the data signal is d1 ⁇ r1; And so on.
  • the data signal of the data pad 101 marked as DQ0 in FIG. 2 is transmitted to the corresponding input buffer circuit 103 through the first length transmission path, and the corresponding input buffer circuit is marked with RX0 in FIG.
  • the two-length transmission path is transmitted to the corresponding input buffer circuit 103; the first length refers to the length from point d0 to point v0, and the second length refers to the length from point c0 to point v0.
  • the clock signal is transmitted to RX0 after t1 time, so as to ensure that RX0 can transmit the data signal within t1 time after receiving the data signal; because the data pad 101 transmits the data signal DQ0 rate Getting higher and higher, the time that DQ0 maintains a high level "1" or a low level “0" is getting shorter and shorter, so the waiting time t1 is required to be smaller and smaller, and the first length (corresponding to the data path) and the first The two lengths (corresponding to the clock path) should be matched as much as possible.
  • the data signal of the data pad 101 marked DQ3 in FIG. 2 is transmitted to the corresponding input buffer circuit 103 via the first length transmission path, the corresponding input buffer circuit 103 is marked with RX3 in FIG. 2 , and the clock signal is transmitted via the second length.
  • the path is transmitted to the corresponding input buffer circuit 103; the first length refers to the length from point d3 to point v3, and the second length refers to the length from point c0 to point v3.
  • the clock signal is transmitted to RX3 after time t2, thereby ensuring that RX3 can transmit the data signal within t2 time after receiving the data signal.
  • this embodiment can improve the consistency of the data signals transmitted by RX0 and RX3.
  • each input buffer circuit 103 has different data paths, and each input buffer circuit 103 has different clock paths.
  • the longer the data path the longer the clock path. Therefore, in this embodiment, the time consistency of data signals transmitted by different input buffer circuits 103 can be improved, that is, better timing characteristics.
  • FIG. 4 is another schematic structural diagram of an interface circuit provided by an embodiment of the application.
  • the interface circuit may further include: a flag pad 106 for transmitting a flag signal; a flag buffer circuit 107 , which is connected to the flag pad Corresponding to 106, it is used for receiving the flag signal transmitted by the flag pad 106 under the driving of the clock signal; the flag output buffer circuit (not shown).
  • the flag signal is usually called a data mask inverter, which is used to indicate whether each data signal is inverted.
  • the flag pad 106 is usually called a DMI (data mask inverter) pad, a DM pad or a DBI pad. In FIG. 4, the DMI pair is used.
  • the flag pad 106 is marked, and the flag buffer circuit 107 is marked by DMI_RX.
  • the flag pads 106 are arranged in the first row and located between the data pads 101 and the clock pads 102 .
  • the flag buffer circuit 107 is arranged in the second row, on the same side of the axis AA1 as the flag pad 106, and between the input buffer circuit 103 and the axis AA1.
  • the distance between the mark buffer circuit 107 and the axis AA1 is smaller than the distance between the mark pad 106 corresponding to the mark buffer circuit 107 and the axis AA1.
  • FIG. 5 is a schematic layout diagram of an interface circuit provided by an embodiment of the present application.
  • the interface circuit may further include: M output buffer circuits 108 corresponding to the data pads 101 one-to-one, and each output buffer circuit 108 is in the Driven by the clock signal, the data signal is sent to the corresponding data pad 101 .
  • the output buffer circuit 108 is electrically connected to the clock pad in addition to the data pad 101 .
  • eight output buffer circuits 108 are illustrated with TX0 , TX1 , TX2 , TX3 , TX4 , TX5 , TX6 , and TX7 .
  • the output buffer circuit 108 is electrically connected to the clock pad 102 via the clock receiving circuit 114 and the clock generating circuit 115 .
  • each output buffer circuit 108 is located directly below the corresponding data pad 101 , or in other words, the distance between each output buffer circuit 108 and the axis AA1 is the same as the distance between the corresponding data pad 101 and the axis AA1 equal.
  • the above-mentioned same lengths or equal distances may also be approximately the same or approximately equal, and certain errors are allowed, and similar descriptions will not be repeated in the following.
  • the input buffer circuit 103 may include a multiplexer (mux) and a latch (latch).
  • the multiplexer receives the data signal, processes the data signal and outputs it to the latch, and the output of the latch is used as an input output of the buffer circuit 103 .
  • the interface circuit may further include: a plurality of power pads (not shown) and ground pads (not shown) for grounding or connecting to a fixed power supply.
  • a plurality of power supply pads, ground pads and data pads are located in the same row.
  • the interface circuit may further include: M optional input buffer circuits 109 , and the number of the optional input buffer circuits 109 is the same as that of the input buffer circuits 103 and arranged side by side with the input buffer circuits 103 , as shown in FIG. 5
  • An optional input buffer circuit 109 is shown as OPTION in .
  • the optional input buffer circuit 109 is located on both sides of the input buffer circuit 103 corresponding to the four data pads 101 located farthest from the central axis AA1.
  • the above-mentioned optional input buffer circuit 109 can play the role of DUMMY when it is not selected, that is, as a virtual input buffer circuit, which is used to match the working environment.
  • the optional input buffer circuit can be configured by configuring. 109 reselected.
  • Figure 6 is a schematic diagram of the layout corresponding to the interface circuit provided in Figure 1.
  • Figure 6 has an output buffer circuit and a capacitor. It should be noted that, for the convenience of comparison and description, Figure 6 also uses RX0, RX1...RX7 to illustrate the output buffer circuit , other circuits are illustrated by OTHERS in FIG. 6 , for example, OTHERS may be a capacitor.
  • the layout density of the input buffer circuit 103 in FIG. 5 is greater than the layout density of the input buffer circuit in FIG. 6 .
  • the clock path of the clock signal shown in FIG. 5 to the input buffer circuit corresponding to DQ6 is shorter than the clock path of the clock signal shown in FIG. 6 to the input buffer circuit corresponding to DQ6.
  • the data pad 101 is used as a DQ pad, and the data signal is a DQ signal as an example. It can be understood that, in other embodiments, the data pads can also be command/address pads or chip select pads, the corresponding data signals are command signals or address signals, and the interface circuit can be applied to LPDDR5. 7 to 9 are schematic diagrams of four structures of an interface circuit in which the data pad includes a command pad and an address pad.
  • the data pad 101 includes a plurality of command/address pads and a chip select pad.
  • the command/address pads are marked with CA0/CA1/CA2/CA3/CA4/CA5/CA6, and the chips are marked with CS. Select pads.
  • the command/address pad transmits the command/address signal
  • the chip select pad transmits the chip select signal
  • the clock pad 102 is marked with CK.
  • all input buffer circuits 103 are in the same row.
  • some of the input buffer circuits 103 are in the same row, and the remaining input buffer circuits 103 are in another row.
  • it can be set as follows: half of all the input buffer circuits 103 are in the same row, and the other half are in the same row, and the input buffer circuits 103 corresponding to which data pads 101 are in the same row can be arbitrarily selected to ensure that each input
  • the length of the input data path between the buffer circuit 103 and the data pad 101 corresponding to the input buffer circuit 103 is the first length
  • the length of the clock path between each input buffer circuit 103 and the clock pad 102 is the second length
  • the first length is positively related to the second length.
  • the clock pads may include a first clock pad 112 and a second clock pad 122 , the first clock pad 112 is denoted by CK_t, and the second clock pad 122 is denoted by CK_c.
  • An embodiment of the present application further provides a data transmission circuit, which includes the interface circuit in the above-mentioned embodiment, and also includes M serial-parallel conversion circuits, and the number of the M serial-parallel conversion circuits corresponds to the M input buffer circuits one-to-one.
  • the output of one input buffer circuit serves as the input of the corresponding serial-parallel conversion circuit.
  • FIG. 10 is a schematic plan layout diagram of a data transmission circuit provided in this embodiment.
  • the input buffer circuit 103 may include a multiplexer (mux) and a latch (latch).
  • the multiplexer receives a data signal, processes the data signal and outputs it to the latch, and the latch The output is used as the output of the input buffer circuit 103 .
  • the multiplexers corresponding to the eight input buffer circuits 103 are denoted by MUX0, MUX1, MUX2, MUX3, MUX4, MUX5, MUX6, and MUX7, and denoted by IB0, IB1, IB2, IB3, IB4, IB5, IB6, and IB7 8 latches corresponding to the input buffer circuits 103 .
  • the data transmission circuit includes: the interface circuit provided in the previous embodiment; M serial to parallel conversion circuits (Sequential to Parallel) S2P, M serial to parallel conversion circuits S2P and M input buffer circuits 103 in one-to-one correspondence, each The output of one input buffer circuit 103 serves as the input of the corresponding serial-to-parallel conversion circuit S2P.
  • serial-to-parallel conversion circuits S2P are arranged in the third row, and the transmission path lengths between each input buffer circuit 103 on the same side of the axis AA1 and the serial-to-parallel conversion circuit S2P corresponding to the input buffer circuit 103 are different.
  • the transmission path lengths between the latches 123 corresponding to each input buffer circuit 103 located on the same side of the axis AA1 and the corresponding serial-parallel conversion circuit S2P are different.
  • each serial-to-parallel conversion circuit S2P corresponds to the M data pads 101 one-to-one, and the distances from each serial-to-parallel conversion circuit S2P to the data pads 101 corresponding to the serial-to-parallel conversion circuit S2P are the same. It can be considered that each serial-to-parallel conversion circuit S2P is arranged directly below the corresponding data pad 101 .
  • the data transmission circuit further includes: M FIFO circuits, which correspond to M serial-to-parallel conversion circuits one-to-one; M parallel-to-serial conversion circuits (Parallel to Sequential) P2S, which correspond to M FIFO circuits.
  • the driving circuits corresponding to the eight data pads 101 are marked with DR0 , DR1 , DR2 , DR3 , DR4 , DR5 , DR6 , and DR7 .
  • the parallel-to-serial conversion circuit P2S is disposed directly below each data pad 101 and between adjacent latches, and is disposed in the same row as the latches.
  • the driving circuit is disposed directly under each data pad 101 and between the data pad 101 and the row where the multiplexer is located.
  • the driving circuit and the corresponding parallel-serial conversion circuit P2S constitute the output buffer circuit 108 .
  • the data transmission circuit may further include: a pre-driver circuit, the pre-driver circuit is electrically connected to the driver circuit and located between the driver circuit 204 and the parallel-serial conversion circuit P2S.
  • the pre-driving circuit may be located between adjacent multiplexers and arranged in the same row as the multiplexers.
  • the data transmission circuit may further include: an electrostatic discharge circuit, a capacitor, and the like.
  • the data transmission circuit further includes M optional input buffer circuits 109 , and the data of the M optional input buffer circuits 109 is the same as that of the input buffer circuits 103 and arranged side by side with the input buffer circuits 103 .
  • the optional input buffer circuit 109 For a detailed description of the optional input buffer circuit 109, reference may be made to the previous embodiment.
  • the optional input buffer circuit 109 includes optional multiplexers and optional latches, the optional multiplexers are arranged side by side with the multiplexers, and the optional latches are arranged side by side with the latches.
  • the optional multiplexer is denoted by MUX
  • the optional latch is denoted by IB.
  • the multiplexer and the latch which are farthest from the axis AA1 and do not play the role of signal transmission are used as the selectable multiplexer and the selectable latch, respectively.
  • Working environment matching means that for each data transmission unit DQ cell, latches or optional latches are distributed on both sides of each parallel-to-serial conversion circuit P2S. Consistent working environment, such as the same level of noise disturbance.
  • the data transfer unit DQ cell includes: an input buffer circuit 103, an optional input buffer circuit 109, a first-in-first-out circuit Output FIFO, a serial-to-parallel conversion circuit S2P, and a Drive circuit.
  • the data transmission unit DQ cell includes: an input buffer circuit 103, an optional input buffer circuit 109, a first-in-first-out circuit Output FIFO, a serial-parallel conversion circuit S2P and a driving circuit .
  • the data transmission unit DQ cell includes: two optional input buffer circuits 109, a first-in-first-out circuit Output FIFO, a serial-parallel conversion circuit S2P, and a driving circuit.
  • serial-to-parallel conversion circuit S2P and the first-in-first-out circuit Output FIFO in the same data transmission unit DQ cell are arranged in parallel, that is, the serial-to-parallel conversion circuit S2P and the first-in, first-out circuit Output FIFO in the same data transmission unit DQ cell are located in In the same row.
  • serial-to-parallel conversion circuit S2P and the first-in-first-out circuit Output FIFO in the same data transmission unit DQ cell are arranged side by side, that is, the serial-to-parallel conversion circuit S2P and the first-in-first-out circuit Output FIFO in the same data transmission unit DQ cell Located in different rows, and the first-in-first-out circuit Output FIFO is located between the serial-to-parallel conversion circuit S2P and the input buffer circuit 103 .
  • the FIFO circuits located in different data transmission units may also be arranged side by side.
  • FIG. 10 shows the bus BUS, the sense amplifier SA, and a plurality of memory blocks, wherein 8 memory blocks are shown as BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6, and BANK7.
  • the number of memory blocks can be reasonably set according to the required performance.
  • the dashed arrows show the data path and clock path during reading data from the memory block, that is, the data path and clock path in the process of reading data from the memory block to the corresponding data pad 101;
  • the solid line The arrows indicate the data path and the clock path during data writing to the memory block, that is, the data path and the clock path in the process of storing data from the data pad 101 to the corresponding memory block.
  • the solid arrows in the preceding figures also correspond to the data paths and clock paths during data writing
  • the dashed arrows correspond to the data paths and clock paths during data reading.
  • DQ6 transmits the data signal to the multiplexer MUX6, and the multiplexer MUX6 continues to transmit the data signal to the latch IB6; the signal provided by the clock generation circuit 115 After the clock path length is transmitted to the latch IB6; when the clock signal reaches the latch IB6, driven by the clock signal, the latch IB6 transmits the data signal to the serial-parallel conversion circuit S2P; the serial-parallel conversion circuit S2P will The data signal is transmitted to the bus BUS, and the data signal is amplified by the sense amplifier SA and stored in the corresponding memory block BANK6.
  • the clock path length required for the clock signal to reach the corresponding latch is shorter and the length of each clock path is shorter.
  • the difference is small, so the latch corresponding to DQ0/DQ1/DQ2/DQ3/DQ4/DQ5/DQ6/DQ7 transmits the data signal to the corresponding serial-parallel conversion circuit S2P with a small time delay, thus improving the corresponding input buffer circuit.
  • the matching degree of the data path and the clock path can reduce the difference in time required for writing data in different data pads 101 to the corresponding memory block, thereby improving the writing performance.
  • the data signal in the memory block BANK6 is amplified by the sense amplifier SA and then transmitted to the bus BUS; the data signal is transmitted to the corresponding FIFO circuit Output via the bus BUS FIFO; the first-in-first-out circuit Output FIFO transmits the data signal to the parallel-serial conversion circuit P2S, and the data signal reaches the DQ6 data pad through the parallel-serial conversion circuit P2S, the pre-driver circuit and the driver circuit DR6.
  • the layout of the centralized input buffer circuit is adopted, which shortens the length of the clock path required for transmitting the clock signal to each input buffer circuit, improves the matching degree between the clock path and the data path, and reduces the tDQS2DQ and timing violations.
  • the difference in the lengths of the clock paths corresponding to each input buffer circuit is small, which can satisfy the requirement of high matching degree between the clock path and the data path of each input buffer circuit at the same time.
  • the length of the clock path is shortened, the length of the wire for transmitting the clock signal is correspondingly shortened, so the power consumption of the data transmission circuit can be reduced to a certain extent.
  • an embodiment of the present application further provides a memory including the above-mentioned data transmission circuit.
  • FIG. 10 for a schematic structural diagram of the memory.
  • the above-mentioned memory can be applied to the storage system shown in FIG. 11 .
  • FIG. 11 is a schematic structural diagram in which the memory provided by the embodiment of the application is applied to the storage system, wherein the Memory Controller is the controller, the Memory is the memory, and the IO Circuit is an interface circuit.
  • Data Path is the data path
  • Array is the storage array.
  • the IO Circuit can be, for example, the interface circuit of the present application, and the Data Path can, for example, include the transmission circuit of the present application, DQ2/DQ3/DQ4/DQ5 are data pads, and Dqs are clock pads.
  • the memory can be memory such as DRAM, SRAM, MRAM, FeRAM, PCRAM, NAND or NOR.
  • the memory may be LPDDR4 memory or LPDDR5 memory.

Abstract

一种接口电路、数据传输电路以及存储器，涉及半导体技术领域，接口电路包括时钟焊盘(102)、数据焊盘(101)和输入缓冲电路(103)，时钟焊盘(102)与数据焊盘(101)布置于第一排，且M个数据焊盘(101)布置于时钟焊盘(102)的两侧，每一侧布置M个数据焊盘(101)的一半，M个输入缓冲电路(103)布置于第二排，以数据焊盘(101)为基准，形成垂直于第一排的轴线(AA1)，M个输入缓冲电路(103)布置于轴线(AA1)的两侧，每一侧布置M个输入缓冲电路(103)的一半，每一个输入缓冲电路(103)与轴线(AA1)的距离小于输入缓冲电路(103)对应的数据焊盘(101)与轴线(AA1)的距离。

Description

接口电路、数据传输电路以及存储器
交叉引用
本申请引用于2020年8月26日递交的名称为“接口电路、数据传输电路以及存储器”的第202010874189.2号中国专利申请，其通过引用被全部并入本申请。
技术领域
本申请实施例涉及一种接口电路、数据传输电路以及存储器。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连，字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
DRAM可以分为双倍速率同步(Double Data Rate，DDR)动态随机存储器、GDDR(Graphics Double Data Rate)动态随机存储器、低功耗双倍速率同步(Low Power Double Data Rate，LPDDR)动态随机存储器。随着DRAM应用的领域越来越多，如DRAM越来越多的应用于移动领域，用户对于DRAM速度、功耗等指标的要求越来越高。
发明内容
本申请实施例提供一种接口电路，包括：时钟焊盘，用于传输时钟信号；M个数据焊盘，用于传输数据信号；M个输入缓冲电路，与所述数据焊盘一一对应，每一个所述输入缓冲电路在所述时钟信号的驱动下，接收与所述输入缓冲电路对应的所述数据焊盘传输的所述数据信号；其中，所述时钟焊盘与所述数据焊盘布置于第一排，且所述M个数据焊盘布置于所述时钟焊盘的两侧，每一侧布置所述M个数据焊盘的一半，所述M个输入缓冲电路布置于第二排，以所述时钟焊盘为基准，形成垂直于所述第一排的轴线，所述M个输入缓冲电路布置于所述轴线的两侧，每一侧布置所述M个输入缓冲电路的一半，每一个所述输入缓冲电路与所述轴线的距离小于所述输入缓冲电路对应的所述数据焊盘与所述轴线的距离，所述M为大于等于2的整数。
本申请实施例还提供一种数据传输电路，包括：上述的接口电路；M个串并转换电路，所述M个串并转换电路与所述M个输入缓冲电路一一对应，每一个所述输入缓冲电路的输出作为对应的所述串并转换电路的输入。
本申请实施例还提供一种存储器，包括上述的接口电路。
附图说明
图1为一种接口电路的结构示意图；
图2为本申请实施例提供的接口电路的一种结构示意图；
图3为本申请实施例提供的接口电路的另一种结构示意图；
图4为本申请实施例提供的接口电路的又一种结构示意图；
图5为本申请实施例提供的接口电路的布局示意图；
图6为图1提供的接口电路对应的布局示意图；
图7至图9为本申请实施例提供的数据焊盘包括命令焊盘和地址焊盘的接口电路的四种结构示意图；
图10为本申请实施例提供的数据传输电路的布局示意图；
图11为本申请实施例提供的存储器应用于存储系统的一种结构示意图。
具体实施方式
在存储器中，写数据采样信号(Dqs信号或Wck信号)作为写数据的时钟；在写入操作时，Dqs或Wck信号的边沿(上升沿和下降沿)在时序上应当与数据信号(DQ信号)的中心处对齐(考虑到时序余量，也可能允许在中心处基本对齐)。DQ信号的传输路径定义为数据路径，数据路径的长短会影响DQ信号的边沿到达器件数据端口(例如寄存器的数据端口)的时间，Dqs或Wck信号的传输路径定义为时钟路径，时钟路径的长短会影响Dqs或Wck信号到达器件时钟端口(例如寄存器的时钟端口)的时间，将DQ信号的数据路径与Dqs或Wck信号的时钟路径的差异(Dqs或Wck信号的边沿和DQ信号的中心处之间的时间间隔)定义为tDQS2DQ或tWCK2DQ，tDQS2DQ或tWCK2DQ越小则数据路径与时钟路径越匹配，相应的电路时序越好。
现结合图1进行具体分析，图1为一种接口电路的结构示意图。
参考图1，接口电路包括：用于传输数据信号的多个并排设置的数据焊盘11，中心轴线AA1，且多个数据焊盘11的一半分布于中心轴线AA1的一侧，另一半分布于中心轴线AA1的另一侧；时钟焊盘13，时钟焊盘13位于中心轴线AA1处；多个输入缓冲电路14，与数据焊盘11对应，且每个输入缓冲电路 14到对应的数据焊盘11之间的数据路径相同或在一定误差范围内基本相同，考虑到实际电路设计和制造过程中，路径相同只是一种理想情况，此处以及下文所述路径相同，均包括在一定误差范围内基本相同的含义，这里的一定误差范围可以理解但不限于不同路径之间的误差在1％以内或3％以内；多个输出缓冲电路(未图示)，与数据焊盘11对应，且每个输出缓冲电路到对应的数据焊盘11之间的时序路径相同；时钟接收电路16和时钟产生电路17，时钟接收电路16与时钟焊盘13电连接，用于接收时钟信号并将时钟信号传输至时钟产生电路17，时钟产生电路17接收该时钟信号并产生驱动时钟，且输入缓冲电路14接收该驱动时钟以及数据信号并传输数据信号。
图1中以DQ0/DQ1…DQ7标示数据焊盘11，以Dqs标示时钟焊盘13(下文均以Dqs为例，Wck的应用情况与Dqs相同或相似，例如在LPDDR4中将时钟称为Dqs，而在LPDDR5中将时钟称为Wck)，以RX0/RX1…RX7标示输入缓冲电路14，该输入缓冲电路14也为接收电路，以RX_CLK标示时钟接收电路16，以CLK GEN标示时钟产生电路17。
数据焊盘11的数据信号传输至对应的输入缓冲电路14的数据路径为第一路径，时钟焊盘13的时钟信号传输至对应的输入缓冲电路14的时序路径为第二路径。在图1中，不同的输入缓冲电路14具有相同的第一路径，但是，距离时钟焊盘13越远的输入缓冲电路14具有的第二路径越长，因此，距离时钟焊盘13越远，相应的第一路径与第二路径之间的差距越大，导致对应的tDQS2DQ越大，且时序违例的问题越严重，图1中标示出了距离时钟焊盘13最远的输入缓冲电路14对应的tDQS2DQ。
不同的数据焊盘11的数据信号到达对应的输入缓冲电路14的时刻接近， 以图1中离时钟焊盘13最远和最近的输入缓冲电路14作为示例来说明，时钟信号达到离时钟焊盘13最远的输入缓冲电路14(DQ0对应的输入缓冲电路14)的时刻最晚，且时钟信号到达离时钟焊盘13最近的输入缓冲电路14(DQ3对应的输入缓冲电路14)的时刻最早，这就造成离时钟焊盘13最近的输入缓冲电路14最先接收并传输数据信号，而离时钟焊盘13最远的输入缓冲电路14最晚传输数据信号，两个输入缓冲电路14传输数据信号的时间差距大。相应的，如果DQ3对应的输入缓冲电路14的时钟路径与数据路径匹配，那么DQ0对应的输入缓冲电路14的时钟路径与数据路径就不太容易匹配。
具体地，结合图1，各数据焊盘11分别对应具有第一端口d0/d1……d7，各输入缓冲电路14分别具有与对应数据焊盘11的第一端口连接的第二端口r0/r1…r7，各输入缓冲电路14分别具有与时钟产生电路17连接的第三端口v0/v1…v7，时钟产生电路17具有与位于中心轴线AA1一侧的各输入缓冲电路14连接的第四端口c0，时钟产生电路17还具有与位于中心轴线AA1另一侧的各输入缓冲电路14连接的第五端口c1。对于RX0而言，时钟信号的时钟路径为c0→v0，数据信号的数据路径为d0→r0；对于RX1而言，时钟信号的时钟路径为c1→v1，数据信号的数据路径为d1→r1；依次类推；不难发现，对于不同的输入缓冲电路14而言，其对应的数据路径不变，但是距离中心轴线AA1越近的输入缓冲电路14具有的时钟路径越短，因此，就出现了tDQS2DQ差异较大的问题。
由上述分析可知，不同的输入缓冲电路14对应的tDQS2DQ差异较大，而在存储器中，对tDQS2DQ的值有严格的要求，例如要求tDQS2DQ的值不能大于800ps，否则会造成时序违例。
为解决上述问题，本申请实施例提供一种接口电路，通过集中布局各输入缓冲电路的方式，缩短了时钟信号传输至各输入缓冲电路的时钟路径，从而缩短了tDQS2DQ，进一步改善时序违例的问题。以下将结合附图对本实施例提供的接口电路进行详细说明。
图2为本申请实施例提供的接口电路的一种结构示意图。
参考图2，本实施例中，接口电路包括：时钟焊盘102，用于传输时钟信号；M个数据焊盘101，用于传输数据信号；M个输入缓冲电路103，与数据焊盘101一一对应，每一个输入缓冲电路103在时钟信号的驱动下，接收与输入缓冲电路103对应的数据焊盘101传输的数据信号；其中，时钟焊盘102与数据焊盘101布置于第一排，M个数据焊盘101布置于时钟焊盘102的两侧，且每一侧布置M个数据焊盘101的一半，M个输入缓冲电路103布置于第二排，以时钟焊盘102为基准形成垂直于第一排的轴线AA1，M个输入缓冲电路103布置于轴线AA1的两侧，每一侧布置M个输入缓冲电路103的一半，每一个输入缓冲电路103与轴线AA1的距离小于输入缓冲电路103对应的数据焊盘101与轴线AA1的距离，所述M为大于等于2的整数。当M为偶数时，例如M等于8，则轴线AA1的每一侧布置4个数据焊盘101；当M为奇数时，例如M等于7，则轴线AA1的一侧布置3个数据焊盘101，另一侧布置4个数据焊盘101。上文所述的“一半”，在M为偶数时，应当理解为M/2，而当M为奇数时，应当理解为(M-1)/2或(M+1)/2，下文出现的“一半”为类似的解释。
M个数据焊盘以及时钟焊盘布置于第一排，M个数据焊盘分别布置于时钟焊盘的两侧，且以数据焊盘为基准，形成垂直于第一排的轴线；M个输入缓冲电路布置于轴线的两侧，每一侧布置M个输入缓冲电路的一半，每一个输入 缓冲电路与轴线的距离小于输入缓冲电路对应的数据焊盘与轴线的距离。本发明申请实施例中，通过对输入缓冲电路进行集中化处理，缩短了时钟信号传输至各输入缓冲电路的时钟路径，提高了时钟路径与数据路径的匹配度，进而有利于减小tDQS2DQ和时序违例；此外，由于时钟路径减小，进而降低了接口电路的功率损耗。
以下将结合附图对本实施例提供的接口电路进行详细说明。
本实施例中，接口电路可应用于DRAM中，例如LPDDR4。
本实施例中，M个数据焊盘101的一半位于轴线AA1的一侧，M个数据焊盘101的另一半位于轴线AA1的另一侧。数据焊盘101用于传输DQ信号，即数据信号为DQ信号。
图2中以8个数据焊盘101作为示例，且以DQ0、DQ1、DQ2、DQ3、DQ4、DQ5、DQ6、DQ7对各数据焊盘101进行标示；相应的，输入缓冲电路103的数量也为8个，且以RX0、RX1、RX2、RX3、RX4、RX5、RX6、RX7对各输入缓冲电路103进行标示。可以理解的是，在其他实施例中，可以根据接口电路的实际需求，合理设置数据焊盘的数量。
时钟焊盘102可用于传输Dqs信号，即时钟信号为Dqs信号，Dqs信号指写时钟信号或读时钟信号，图2中以Dqs对时钟焊盘102进行标示。
图3为本申请实施例提供的接口电路的另一种结构示意图。如图3所示，时钟焊盘102可以为差分输入焊盘，包括第一时钟焊盘112以及第二时钟焊盘122，且第一时钟焊盘112与第二时钟焊盘122分别传输互补的时钟信号。具体地，图3中以Dqs_t标示第一时钟焊盘112，第一时钟焊盘112用于传输Dqs_t时钟信号；以Dqs_c标示第二时钟焊盘122，第二时钟焊盘122用于传输Dqs_c 时钟信号。
本实施例中，第一时钟焊盘112与第二时钟焊盘122相对于轴线AA1对称布置。第一时钟焊盘112与位于轴线AA1一侧的输入缓冲电路103的时钟路径为第一时钟路径，第二时钟焊盘122与位于轴线AA1另一侧的输入缓冲电路103的时钟路径为第二时钟路径，如此设置，有利于减小第一时钟路径与第二时钟路径的差距，从而减小或者避免由于第一时钟路径与第二时钟路径差距大对于tDQS2DQ造成的不良影响。
需要说明的是，在其他实施例中，第一时钟焊盘与第二时钟焊盘也可以布置于轴线同一侧。
还需要说明的是，关于“第一排”并非是指时钟焊盘102以及数据焊盘101位于接口电路整体焊盘中的第一排，仅是为了说明时钟焊盘102与数据焊盘101同排设置，且为了方便定义说明轴线AA1。在实际接口电路中，时钟焊盘102以及数据焊盘101可位于接口电路整体焊盘中的任意一排。
同样的，关于“第二排”并非指输入缓冲电路103位于接口电路整体焊盘中的第二排，仅是为了说明M个输入缓冲电路103同排设置，且与时钟焊盘102以及数据焊盘101位于不同排。在实际接口电路中，M个输入缓冲电路103可位于接口电路整体焊盘中的任意一排，且输入缓冲电路103与数据焊盘101之间还可以设置有一排或者多排焊盘。
本实施例中，接口电路还可以包括：时钟处理电路，与时钟焊盘102以及M个输入缓冲电路103均电连接，用于接收时钟信号，并将时钟信号进行处理后作为M个输入缓冲电路103的驱动时钟。也就是说，输入缓冲电路103在时钟信号的驱动下，实际为，输入缓冲电路103在对时钟信号进行处理生成的 驱动时钟的驱动下。
时钟处理电路与轴线AA1重合，即时钟处理电路位于轴线AA1所在位置。如此，有利于减小驱动时钟传输至位于轴线AA1两侧的输入缓冲电路103所需的时钟路径的差异。上述时钟处理电路位于轴线AA1所在位置，并不意味着时钟处理电路相对于轴线AA1完全对称，考虑到电路设计和制造的实际情况，时钟电路大致位于AA1所在的位置，允许其中心线偏离AA1一定的值，例如偏离10％或20％。
本实施例中，时钟处理电路包括时钟接收电路114和时钟产生电路115。时钟接收电路114与时钟焊盘102电连接，用于接收时钟信号，时钟接收电路114的输出作为时钟产生电路115的输入，时钟产生电路115用于产生驱动时钟。时钟产生电路115位于轴线AA1上。图2中，以RX_CLK对时钟接收电路114、CLK GEN对时钟接收电路115进行标示。
具体地，时钟接收电路114包括：与第一时钟焊盘112电连接的第一时钟接收电路，用于接收Dqs_t时钟信号；与第二时钟焊盘122电连接的第二时钟接收电路，用于接收Dqs_c时钟信号。且第一时钟接收电路与第二时钟电路相对于轴线AA1对称布置。
对于输入缓冲电路103而言，其在时钟信号的驱动下接受数据信号，并继续传输数据信号。也就是说，当数据焊盘101的数据信号传输至输入缓冲电路103时，只有在时钟信号也已经传输至输入缓冲电路103的情况下，输入缓冲电路103才会接受该数据信号并将数据信号传输出去；若数据信号传输至输入缓冲电路103且时钟信号还未达到，则输入缓冲电路103不会传输该数据信号。
本实施例中，每一个输入缓冲电路103与轴线AA1的距离小于输入缓冲电路103对应的数据焊盘101与轴线AA1的距离，即相较于数据焊盘101而言各输入缓冲电路103更向轴线AA1靠拢。具体地，以轴线AA1为基准，M个输入缓冲电路103的布局密集度大于M个数据焊盘101的布局密集度；对于每一数据焊盘101及其对应的输入缓冲电路103而言，数据焊盘101与轴线AA1之间的距离大于输入缓冲电路103与轴线AA1之间的距离。并且，数据焊盘101与轴线AA1的距离越近，与该数据焊盘101对应的输入缓冲电路103与轴线AA1的距离越近。
具体地，每一个输入缓冲电路103到该输入缓冲电路103对应的数据焊盘101之间的输入数据路径长度为第一长度，每一个输入缓冲电路103与时钟焊盘102之间的时钟路径长度为第二长度，且第一长度与第二长度成正相关。即，对于所有的输入缓冲电路103而言，第一长度越大对应的第二长度越大，第一长度越小对应的第二长度越小。也就是说，离轴线AA1越远的数据焊盘101，其对应的输入缓冲电路103离轴线AA1越远；离轴线AA1越近的数据焊盘101，其对应的输入缓冲电路103离轴线AA1越近。
相较于图1所示的每一输入缓冲电路与轴线的距离等于对应的数据焊盘与轴线的距离的方案而言，本实施例中，对于轴线AA1同一侧的每一数据焊盘101以及输入缓冲电路103来说，离时钟焊盘102最远的输入缓冲电路103的时钟路径减小，因而时钟信号能够更快的传输至离时钟焊盘102最远的输入缓冲电路103，从而减小数据信号达到而时钟信号未到达导致的信号延迟时间。相应的，每一输入缓冲电路103的时钟路径均有所减小，因此相应能够减小所有输入缓冲电路103的信号延迟时间。也就是说，本实施例能够减小tDQS2DQ， 减少时序违例，并减小时钟路径上所消耗的功率。
此外，每一数据焊盘101与输入缓冲电路103之间的数据路径与每一时钟焊盘102与输入缓冲电路103之间的时钟路径的差值减小，从而使得本实施例能够缩短不同输入缓冲电路103的tDQS2DQ，从而提高不同输入缓冲电路103的时钟路径和数据路径的匹配度，从而改善不同输入缓冲电路103传输数据信号的时序特性。
具体地，结合图2，各数据焊盘101分别对应具有第一端口d0/d1……d7，各输入缓冲电路103分别具有与对应数据焊盘101的第一端口连接的第二端口r0/r1…r7，各输入缓冲电路103分别具有与时钟产生电路115连接的第三端口v0/v1…v7，时钟产生电路115具有与位于中心轴线AA1一侧的各输入缓冲电路14连接的第四端口c0，时钟产生电路115还具有与位于中心轴线AA1另一侧的各输入缓冲电路103连接的第五端口c1。对于RX0而言，时钟信号的时钟路径为c0→v0，数据信号的数据路径为d0→r0；对于RX1而言，时钟信号的时钟路径为c1→v1，数据信号的数据路径为d1→r1；依次类推。
举例来说，图2中标记为DQ0的数据焊盘101的数据信号经由第一长度传输路径传输至对应的输入缓冲电路103，图2中以RX0标记该对应的输入缓冲电路，时钟信号经由第二长度传输路径传输至对应的输入缓冲电路103；第一长度指的是从d0点到v0点的长度，第二长度指从c0点到v0点的长度。当数据信号传输至RX0时，时钟信号经由t1时间后传输至RX0中，从而保证RX0能够在接收到数据信号后等待t1时间内将数据信号传输出去；由于数据焊盘101传输数据信号DQ0的速率越来越高，DQ0维持高电平“1”或低电平“0”的时间越来越短，从而要求等待时间t1要越来越小，进而要求第一长度(对应 数据路径)与第二长度(对应时钟路径)要尽可能的匹配。
图2中标记为DQ3的数据焊盘101的数据信号经由第一长度传输路径传输至对应的输入缓冲电路103，图2中以RX3标记该对应的输入缓冲电路103，时钟信号经由第二长度传输路径传输至对应的输入缓冲电路103；第一长度指从d3点到v3点的长度，第二长度指c0点到v3点的长度。当数据信号传输至输入缓冲电路103时，时钟信号经由t2时间后传输至RX3中，从而保证RX3能够在收到数据信号后等待t2时间内将数据信号传输出去。对于标记为DQ0和标记为DQ3的数据焊盘101而言，由于DQ0对应的输入缓冲电路103的第一长度与第二长度是匹配的，DQ3对应的输入缓冲电路103的第一长度与第二长度也是匹配的，因此t1与t2相等或近似相等。因此，本实施例能够提高RX0和RX3传输数据信号的一致性。
此外，结合图2，不难发现，对于每一输入缓冲电路103而言具有的数据路径各不相同，且各输入缓冲电路103具有的时钟路径也各不相同。对于不同的输入缓冲电路103其具有的数据路径越长相应具有的时钟路径也越长。因此，本实施例中能够提高不同的输入缓冲电路103传输数据信号的时间一致性，即更好的时序特性。
图4为本申请实施例提供的接口电路的又一种结构示意图，如图4所示，接口电路还可以包括：标志焊盘106，用于传输标志信号；标志缓冲电路107，与标志焊盘106对应，用于在时钟信号的驱动下，接收标志焊盘106传输的标志信号；标志输出缓冲电路(未标示)。
标志信号通常称为data mask inverter，用于标示每一个数据信号是否取反，标志焊盘106通常称为DMI(data mask inverter)焊盘、DM焊盘或者DBI 焊盘，图4中以DMI对标志焊盘106进行标示，以DMI_RX对标志缓冲电路107进行标示。
本实施例中，标志焊盘106布置于第一排，且位于数据焊盘101与时钟焊盘102之间。标志缓冲电路107布置于第二排，且与标志焊盘106位于轴线AA1同一侧，且位于输入缓冲电路103与轴线AA1之间。
另外，标志缓冲电路107与轴线AA1的距离小于标志缓冲电路107对应的标志焊盘106与轴线AA1的距离。
图5为本申请实施例提供的接口电路的布局示意图，如图5所示，接口电路还可以包括：M个输出缓冲电路108，与数据焊盘101一一对应，每一个输出缓冲电路108在时钟信号的驱动下，将数据信号发送对应的数据焊盘101。输出缓冲电路108除与数据焊盘101电连接外，还与时钟焊盘电连接。图5中以TX0、TX1、TX2、TX3、TX4、TX5、TX6、TX7示意出了8个输出缓冲电路108。
具体地，输出缓冲电路108经由时钟接收电路114和时钟产生电路115与时钟焊盘102电连接。
本实施例中，每一个输出缓冲电路108到输出缓冲电路108对应的数据焊盘101之间的输出数据路径长度相同。具体地，每一输出缓冲电路108位于对应的数据焊盘101的正下方，或者说，每一输出缓冲电路108与轴线AA1之间的距离与对应的数据焊盘101与轴线AA1之间的距离相等。同样的，考虑到电路设计和制造的实际情况，上述长度相同或距离相等也可以是近似相同或近似相等，允许存在一定误差，后面类似描述不再熬述。
输入缓冲电路103可以包括多路选择器(mux)和锁存器(latch)，多路 选择器接收数据信号，并将数据信号进行处理后输出给锁存器，且锁存器的输出作为输入缓冲电路103的输出。
接口电路还可以包括：多个电源焊盘(未图示)和接地焊盘(未图示)，用于接地或者接固定电源。其中多个电源焊盘以及接地焊盘与数据焊盘位于同一排。
如图5所示，接口电路还可以包括：M个可选输入缓冲电路109，且可选输入缓冲电路109的数量与输入缓冲电路103的数量相同，且与输入缓冲电路103并排设置，图5中以OPTION示意出了可选输入缓冲电路109。具体地，本实施例中，可选输入缓冲电路109位于处于离中心轴线AA1最远的4个数据焊盘101对应的输入缓冲电路103两侧。上述可选输入缓冲电路109例如在不选中的情况下可以起到DUMMY的作用，即当作虚拟输入缓冲电路，用于工作环境匹配，在某些情况下，可以通过配置将可选输入缓冲电路109重新选中。
图6为图1提供的接口电路对应的布局示意图，图6中具有输出缓冲电路以及电容，需要说明的是，为了便于对比说明，图6中也用RX0、RX1…RX7示意出了输出缓冲电路，图6中以OTHERS示意出其他电路，例如OTHERS可以是电容。
结合参考图5及图6，以时钟产生电路为基准，图5中的输入缓冲电路103的布局密集度大于图6中的输入缓冲电路布局密集度。以DQ6为例，图5所示的时钟信号到达DQ6对应的输入缓冲电路的时钟路径比图6所示的时钟信号到达DQ6对应的输入缓冲电路的时钟路径短。
上述均以数据焊盘101为DQ焊盘，数据信号为DQ信号作为示例。可以理解的是，在其他实施例中，数据焊盘也可以为命令/地址焊盘或片选焊盘， 相应的数据信号为命令信号或者地址信号，该接口电路可应用于LPDDR5中。图7至图9为数据焊盘包括命令焊盘和地址焊盘的接口电路的四种结构示意图。
如图7所示，数据焊盘101包括多个命令/地址焊盘以及一个片选焊盘，以CA0/CA1/CA2/CA3/CA4/CA5/CA6标示命令/地址焊盘，以CS标示片选焊盘。命令/地址焊盘传输命令/地址信号，片选焊盘传输片选信号，以CK标示时钟焊盘102。
在一个例子中，如图7所示，所有输入缓冲电路103处于同一排。
在另一个例子中，如图8所示，部分输入缓冲电路103处于同一排，剩余输入缓冲电路103处于另一同排。具体地，可以设置为：所有输入缓冲电路103中的一半处于同一排，另一半处于另一同排，且可以任意选取以哪些数据焊盘101对应的输入缓冲电路103处于同一排，保证每一个输入缓冲电路103到输入缓冲电路103对应的数据焊盘101之间的输入数据路径长度为第一长度，每一个输入缓冲电路103与时钟焊盘102之间的时钟路径长度为第二长度，第一长度与所述第二长度成正相关。
如图9所示，时钟焊盘可以包括第一时钟焊盘112以及第二时钟焊盘122，以CK_t标示第一时钟焊盘112，以CK_c标示第二时钟焊盘122。
有关输入缓冲电路103的详细描述，可参考前述详细说明，在此不再赘述。如前述分析，采用如图7-图9所示的接口电路，也具有减小tDQS2DQ，减少时序违例，并减小时钟路径上所消耗的功率的有益效果。
本申请实施例还提供一种数据传输电路，包括上述实施例中的接口电路，还包括M个串并转换电路，且M个串并转换电路的数量与M个输入缓冲电路 一一对应，每一个输入缓冲电路的输出作为对应的串并转换电路的输入。图10为本实施例提供的数据传输电路的平面布局示意图。
参考图10，输入缓冲电路103可以包括多路选择器(mux)和锁存器(latch)，多路选择器接收数据信号，并将数据信号进行处理后输出给锁存器，且锁存器的输出作为输入缓冲电路103的输出。图10中以MUX0、MUX1、MUX2、MUX3、MUX4、MUX5、MUX6、MUX7标示8个输入缓冲电路103对应的多路选择器，以IB0、IB1、IB2、IB3、IB4、IB5、IB6、IB7标示8个输入缓冲电路103对应的锁存器。本实施例中，数据传输电路包括：前述实施例提供的接口电路；M个串并转换电路(Sequential to Parallel)S2P，M个串并转换电路S2P与M个输入缓冲电路103一一对应，每一个输入缓冲电路103的输出作为对应的串并转换电路S2P的输入。
具体地，M个串并转换电路S2P布置于第三排，位于轴线AA1同一侧的每一个输入缓冲电路103与输入缓冲电路103对应的串并转换电路S2P之间的传输路径长度各不相同。
更具体地，位于轴线AA1同一侧的每一个输入缓冲电路103对应的锁存器123与对应的串并转换电路S2P之间的传输路径长度各不相同。
此外，M个串并转换电路S2P与M个数据焊盘101一一对应，且每一个串并转换电路S2P到该串并转换电路S2P对应的数据焊盘101的距离相同。可以认为，每一串并转换电路S2P布局在对应数据焊盘101的正下方。
本实施例中，数据传输电路还包括：M个先入先出电路Output FIFO，与M个串并转换电路一一对应；M个并串转换电路(Parallel to Sequential)P2S，与M个先入先出电路(First Input First Output)Output FIFO一一对应，每一个 先入先出电路Output FIFO的输出作为先入先出电路Output FIFO对应的并串转换电路P2S的输入；M个驱动电路，与M个并串转换电路P2S一一对应，每一个并串转换电路P2S的输出作为并串转换电路P2S对应的驱动电路的输入；且M个驱动电路还与M个数据焊盘101一一对应。图10中以DR0、DR1、DR2、DR3、DR4、DR5、DR6、DR7标示了8个数据焊盘101对应的驱动电路。本实施例中，并串转换电路P2S设置在每一数据焊盘101正下方，且位于相邻锁存器之间，与锁存器同排设置。驱动电路设置在每一数据焊盘101正下方，且位于数据焊盘101与多路选择器所在排之间。
可以理解的是，驱动电路与对应的并串转换电路P2S构成输出缓冲电路108。
数据传输电路还可以包括：预驱动电路，预驱动电路与驱动电路电连接，且位于驱动电路204与并串转换电路P2S之间。本实施例中，预驱动电路可以位于相邻多路选择器之间，且与多路选择器同排设置。
数据传输电路还可以包括：静电泄放电路以及电容等。
数据传输电路还包括：M个可选输入缓冲电路109，且M个可选输入缓冲电路109的数据与输入缓冲电路103的数量相同，且与输入缓冲电路103并排设置。有关可选输入缓冲电路109的详细说明，可参考前一实施例。
具体地，可选输入缓冲电路109包括可选多路选择器以及可选锁存器，可选多路选择器与多路选择器并排设置，可选锁存器与锁存器并排设置，图10中以MUX标示可选多路选择器，以IB标示可选锁存器。如前述所述，距离轴线AA1最远的不起到信号传输的作用的多路选择器以及锁存器分别作为可选多路选择器以及可选锁存器。
本实施例中，M个输入缓冲电路103和/或M个可选输入缓冲电路109中的两个、M个串并转换电路S2P中的一个、M个先入先出电路Output FIFO中的一个、M个并串转换电路P2S中的一个以及M个驱动电路中的一个，共同组成一个数据传输单元DQ cell，每一个数据传输单元DQ cell的工作环境匹配。
工作环境匹配指的是，对于每一数据传输单元DQ cell而言，每一并串转换电路P2S两侧均分布有锁存器或者可选锁存器，因此，每一个串并转换电路S2P的工作环境一致，如受到的噪音干扰程度一致。
例如，对于标示为DQ5的数据焊盘而言，数据传输单元DQ cell包括：一个输入缓冲电路103、一个可选输入缓冲电路109、一个先入先出电路Output FIFO、一个串并转换电路S2P以及一个驱动电路。对于标示为DQ4的数据焊盘而言，数据传输单元DQ cell包括：一个输入缓冲电路103、一个可选输入缓冲电路109、一个先入先出电路Output FIFO、一个串并转换电路S2P以及一个驱动电路。对于标示为DQ6的数据焊盘而言，数据传输单元DQ cell包括：两个可选输入缓冲电路109、一个先入先出电路Output FIFO、一个串并转换电路S2P以及一个驱动电路。
在一个例子中，同一数据传输单元DQ cell中的串并转换电路S2P和先入先出电路Output FIFO并列设置，即同一数据传输单元DQ cell中的串并转换电路S2P和先入先出电路Output FIFO位于同一排。
在另一个例子中，同一数据传输单元DQ cell中的串并转换电路S2P和先入先出电路Output FIFO并排设置，即同一数据传输单元DQ cell中的串并转换电路S2P和先入先出电路Output FIFO位于不同排，且先入先出电路Output  FIFO位于串并转换电路S2P与输入缓冲电路103之间。
此外，在其他实施例中，位于不同的数据传输单元中的先入先出电路也可以并排设置。
为了便于理解，图10中示意出了总线BUS、感测放大器SA以及多个存储块，其中，以BANK0、BANK1、BANK2、BANK3、BANK4、BANK5、BANK6、BANK7示意出了8个存储块。在其他实施例中，存储块的数量可以根据所需的性能合理设置。
图10中，虚线箭头示意出了从存储块中读取数据期间的数据路径以及时钟路径，即将数据从存储块中读取至对应的数据焊盘101过程中的数据路径以及时钟路径；实线箭头示意出了向存储块写入数据期间的数据路径以及时钟路径，即将数据从数据焊盘101存入至对应的存储块过程中的数据路径和时钟路径。需要说明的是，前述附图中的实线箭头也对应指的是写入数据期间对应的数据路径以及时钟路径，虚线箭头对应指的是读取数据期间的数据路径以及时钟路径。
以下结合附图对本实施例提供的数据传输电路的工作原理进行说明：
在写入数据期间：以DQ6数据焊盘为例，DQ6将数据信号传输至多路选择器MUX6中，多路选择器MUX6继续将数据信号传输至锁存器IB6中；时钟产生电路115提供的信号经由时钟路径长度后传输至锁存器IB6；当时钟信号到达锁存器IB6后，在时钟信号的驱动下，锁存器IB6将数据信号传输至串并转换电路S2P；串并转换电路S2P将数据信号传输至总线BUS，且数据信号经由感测放大器SA放大后存储至对应的存储块BANK6。如前述接口电路的相关分析可知，对于DQ0/DQ1/DQ2/DQ3/DQ4/DQ5/DQ6/DQ7而言，时钟信号 到达对应的锁存器所需经历的时钟路径长度较短且各时钟路径长度差异较小，因此DQ0/DQ1/DQ2/DQ3/DQ4/DQ5/DQ6/DQ7对应的锁存器将数据信号传输至对应的串并转换电路S2P的时间延迟小，从而提高了各输入缓冲电路对应的数据路径和时钟路径的匹配度，减小了不同数据焊盘101中的数据写入至对应存储块所需的时间的差值，从而改善了写入性能。
在读取数据期间：继续以DQ6数据焊盘为例，例如从存储块BANK6中的数据信号经由感测放大器SA放大后传输至总线BUS；数据信号经由总线BUS传输至对应的先入先出电路Output FIFO；先入先出电路Output FIFO将数据信号传输至并串转换电路P2S，数据信号经由并串转换电路P2S、预驱动电路以及驱动电路DR6后到达DQ6数据焊盘。
本实施例提供的数据传输电路中，采用集中输入缓冲电路的布局方式，缩短了时钟信号传输至各输入缓冲电路所需的时钟路径长度，提高了时钟路径与数据路径的匹配度，从而减小了tDQS2DQ和时序违例。各输入缓冲电路对应的时钟路径长度相差较小，能够同时满足各输入缓冲电路的时钟路径与数据路径匹配度高的需求。
此外，由于时钟路径长度缩短，相应缩短了传输时钟信号的导线的长度，因此可以在一定程度上降低数据传输电路的功耗。
相应的，本申请实施例还提供一种存储器，包括上述的数据传输电路。具体地，有关存储器的结构示意图可参考图10。上述存储器可以应用于图11所示的存储系统中，图11为本申请实施例提供的存储器应用于存储系统的一种结构示意图，其中Memory Controller为控制器，Memory为存储器，IO Circuit为接口电路，Data Path为数据路径，Array为存储阵列。IO Circuit例如可以为 本申请的接口电路，Data Path例如可以包括本申请的传输电路，DQ2/DQ3/DQ4/DQ5为数据焊盘，Dqs为时钟焊盘。
存储器可以为DRAM、SRAM、MRAM、FeRAM、PCRAM、NAND或NOR等存储器。例如，存储器可以为LPDDR4存储器或者LPDDR5存储器。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。

Claims (20)

  1. 一种接口电路，包括：
    时钟焊盘，用于传输时钟信号；
    M个数据焊盘，用于传输数据信号；
    M个输入缓冲电路，与所述数据焊盘一一对应，每一个所述输入缓冲电路在所述时钟信号的驱动下，接收与所述输入缓冲电路对应的所述数据焊盘传输的所述数据信号；
    其中，所述时钟焊盘与所述数据焊盘布置于第一排，且所述M个数据焊盘布置于所述时钟焊盘的两侧，每一侧布置所述M个数据焊盘的一半，所述M个输入缓冲电路布置于第二排，以所述时钟焊盘为基准，形成垂直于所述第一排的轴线，所述M个输入缓冲电路布置于所述轴线的两侧，每一侧布置所述M个输入缓冲电路的一半，每一个所述输入缓冲电路与所述轴线的距离小于所述输入缓冲电路对应的所述数据焊盘与所述轴线的距离，所述M为大于等于2的整数。
  2. 如权利要求1所述的接口电路，其中，每一个所述输入缓冲电路到所述输入缓冲电路对应的所述数据焊盘之间的输入数据路径长度为第一长度，每一个所述输入缓冲电路与所述时钟焊盘之间的时钟路径长度为第二长度，所述第一长度与所述第二长度成正相关。
  3. 如权利要求1所述的接口电路，其中，所述时钟焊盘为差分输入焊盘，包括第一时钟焊盘和第二时钟焊盘，所述第一时钟焊盘与所述第二时钟焊盘分别传输互补的所述时钟信号。
  4. 如权利要求3所述的接口电路，其中，所述第一时钟焊盘与所述第二时钟焊盘相对于所述轴线对称布置。
  5. 如权利要求1所述的接口电路，还包括：时钟处理电路，与所述时钟焊盘和所述M个输入缓冲电路均电连接，用于接收所述时钟信号，并将所述时钟信号进行处理后作为所述M个输入缓冲电路的驱动时钟。
  6. 如权利要求5所述的接口电路，其中，所述时钟处理电路包括时钟接收电路和时钟产生电路，所述时钟接收电路与所述时钟焊盘电连接，用于接收所述时钟信号，所述时钟接收电路的输出作为所述时钟产生电路的输入，所述时钟产生电路用于产生所述驱动时钟。
  7. 如权利要求1所述的接口电路，还包括：
    标志焊盘，用于传输标志信号；
    标志缓冲电路，与所述标志焊盘对应，用于在所述时钟信号的驱动下，接收所述标志焊盘传输的所述标志信号。
  8. 如权利要求7所述的接口电路，其中，所述标志焊盘布置于所述第一排，且位于所述数据焊盘与所述时钟焊盘之间；所述标志缓冲电路布置于所述第二排，且与所述标志焊盘位于所述轴线的同一侧，且位于所述输入缓冲电路与所述轴线之间；所述标志缓冲电路与所述轴线的距离小于所述标志缓冲电路对应的所述标志焊盘与所述轴线的距离。
  9. 如权利要求1所述的接口电路，还包括：M个输出缓冲电路，与所述数据焊盘一一对应，每一个所述输出缓冲电路在所述时钟信号的驱动下，将所述数据信号发送至对应的数据焊盘。
  10. 如权利要求9所述的接口电路，其中，每一个所述输出缓冲电路到所述输出缓冲电路对应的所述数据焊盘之间的输出数据路径长度相同。
  11. 如权利要求1所述的接口电路，其中，所述输入缓冲电路包括多路选择器和锁存器，所述多路选择器接收所述数据信号，并将所述数据信号处理后输出给所述锁存器，所述锁存器的输出作为所述输入缓冲电路的输出。
  12. 一种数据传输电路，包括权利要求1至11任一所述的接口电路，还包括：M个串并转换电路，所述M个串并转换电路与所述M个输入缓冲电路一一对应，每一个所述输入缓冲电路的输出作为对应的所述串并转换电路的输入。
  13. 如权利要求12所述的数据传输电路，其中，所述M个串并转换电路布置于第三排，位于所述轴线同一侧的每一个所述输入缓冲电路与所述输入缓冲电路对应的所述串并转换电路之间的传输路径长度各不相同。
  14. 如权利要求12所述的数据传输电路，其中，所述M个串并转换电路与所述M个数据焊盘一一对应，且每一个所述串并转换电路到所述串并转换电路对应的所述数据焊盘的距离相同。
  15. 如权利要求12所述的数据传输电路，还包括：
    M个先入先出电路，与所述M个串并转换电路一一对应；
    M个并串转换电路，与所述M个先入先出电路一一对应，每一个所述先入先出电路的输出作为所述先入先出电路对应的所述并串转换电路的输入；
    M个驱动电路，与所述M个并串转换电路一一对应，每一个所述并串转换电路的输出作为所述并串转换电路对应的所述驱动电路的输入；所述M个驱动电路还与所述M个数据焊盘一一对应。
  16. 如权利要求15所述的数据传输电路，还包括M个可选输入缓冲电路，所述M个可选输入缓冲电路的数量与所述输入缓冲电路的数量相同，且与所述输入缓冲电路并排设置。
  17. 如权利要求16所述的数据传输电路，其中，所述M个输入缓冲电路和/或所述M个可选输入缓冲电路中的两个、所述M个串并转换电路中的一个、所述M个先入先出电路中的一个、所述M个并串转换电路中的一个以及所述M个驱动电路中的一个，共同组成一个数据传输单元，每一个所述数据传输单元的工作环境匹配。
  18. 如权利要求17所述的数据传输电路，其中，同一所述数据传输单元中的所述串并转换电路和所述先入先出电路并排或并列设置。
  19. 如权利要求17所述的数据传输电路，其中，位于不同的所述数据传输单元中的先入先出电路并排设置。
  20. 一种存储器，包括权利要求12至19任一所述的数据传输电路。
PCT/CN2021/103707 2020-08-26 2021-06-30 接口电路、数据传输电路以及存储器 WO2022042017A1 (zh)

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