WO2022041330A1 - 驱动电路及其驱动方法、显示装置 - Google Patents

驱动电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2022041330A1
WO2022041330A1 PCT/CN2020/114817 CN2020114817W WO2022041330A1 WO 2022041330 A1 WO2022041330 A1 WO 2022041330A1 CN 2020114817 W CN2020114817 W CN 2020114817W WO 2022041330 A1 WO2022041330 A1 WO 2022041330A1
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Prior art keywords
switch
state
transistor
driving
write
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PCT/CN2020/114817
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English (en)
French (fr)
Inventor
曹海明
管延庆
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武汉华星光电技术有限公司
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Priority to US17/260,994 priority Critical patent/US20230274688A1/en
Publication of WO2022041330A1 publication Critical patent/WO2022041330A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present application relates to the field of display technology, and in particular, to a driving circuit and a driving method thereof, and a display device.
  • the display requirements can not only meet the high-frequency dynamic picture display with smoother picture quality, but also meet the low power consumption requirements of ordinary display, and respond to high-frequency display.
  • dynamic frame rate technology came into being.
  • the pixel circuit in the display area needs to have the characteristics of strong charging ability and strong image maintenance ability.
  • the charging ability is strong It means that the charging time of each line of the pixel circuit is extremely short in the high frequency state, and the strong image maintenance capability means that the time of each frame is prolonged in the low frequency state.
  • Traditional amorphous silicon technology, low temperature polysilicon technology and metal oxide technology cannot meet the requirements of ultra-low frequency and ultra-high frequency display at the same time.
  • Low Temperature Polycrystalline Oxide (LTPO) technology combines low temperature polysilicon (Low Temperature Polycrystalline Oxide, LTPO) technology Poly-silicon, referred to as LTPS) and indium gallium zinc oxide (Indium
  • LTPS Low Temperature Polycrystalline Oxide
  • IGZO indium gallium zinc oxide
  • metal oxide transistors are usually used with the characteristics of ultra-low off-state leakage current, so as to make and drive transistors
  • the gate-connected transistor has a metal oxide active layer, so as to achieve the purpose of maintaining the voltage level of the gate of the driving transistor in a low frequency state.
  • the transistor with the metal oxide active layer connected to the gate of the driving transistor is usually in the off state, and the off state has the metal oxide active layer.
  • the negative bias stress of the transistor of the layer causes the negative shift of the threshold voltage of the transistor with the metal oxide active layer, and the negative shift of the threshold voltage easily leads to the gate leakage of the driving transistor, which eventually leads to the failure of low frequency display.
  • the purpose of the present application is to provide a driving circuit, a driving method thereof, and a display device, so as to solve the problem that when the metal oxide transistor is in the off state, the negative bias stress causes the negative shift of the threshold voltage, which leads to the gate leakage of the driving transistor and causes the low frequency Displays the problem of invalidation.
  • the present application provides a drive circuit
  • the drive circuit includes:
  • a driving transistor which is electrically connected to the light emitting diode and used for providing a driving current to the light emitting diode;
  • a first switch connected to the gate of the drive transistor, in a first state in the previous frame and in a second state in the current frame;
  • a second switch the first switch is connected between the gate of the driving transistor and the second switch, is in the second state in the previous frame, and is in the first state in the current frame a state;
  • the first state is one of an on-and-off switching state and a continuous-on state
  • the second state is the other of an on-and-off switching state and a continuous-on state.
  • both the first switch and the second switch include transistors having metal oxide active layers.
  • the drive circuit further includes:
  • a first initialization switch connected to the anode of the light emitting diode, in the first state in the previous frame, and in the second state in the current frame;
  • the second initialization switch is connected between the initialization signal line and the first initialization switch
  • the first initialization switch is connected between the second initialization switch and the anode of the light emitting diode
  • the second state is in the previous frame and the first state is in the current frame.
  • both the first initialization switch and the second initialization switch include transistors having metal oxide active layers.
  • the drive circuit further includes a capacitor, one end of the capacitor is connected to the gate of the drive transistor, and the other end of the capacitor is connected to the anode of the light emitting diode and the first initialization switch.
  • the drive circuit further includes:
  • a first write switch connected to one of the source or drain of the drive transistor, in the first state in the previous frame, and in all the states in the current frame the second state;
  • a second write switch is connected between the first write switch and the data line, the first write switch is connected to the second write switch and the drive transistor One of the source or drain is in the second state in the previous frame and in the first state in the current frame.
  • both the first write switch and the second write switch include transistors having metal oxide active layers.
  • the second switch is connected between the first switch and the other of the source and the drain of the driving transistor.
  • the drive circuit further includes:
  • the first light emission control transistor is connected between one of the source electrode and the drain electrode of the driving transistor and the anode of the light emitting diode;
  • a second light emission control transistor is connected between the other one of the source electrode and the drain electrode of the driving transistor and the power supply signal line.
  • the driving transistor, the first light emission control transistor and the second light emission control transistor are all transistors having a polysilicon active layer.
  • the second switch is connected between the data line and the first switch.
  • the on and off switching states include an on state and an off state, and the duration corresponding to the on state in the on and off switching states is shorter than the duration corresponding to the off state.
  • a driving method of the above-mentioned driving circuit comprises the following steps:
  • the first switch is in the first state, and the second switch is in the second state;
  • the first switch is in the second state, and the first switch is in the first state.
  • a display device comprising the above-mentioned driving circuit.
  • the present application provides a driving circuit, a driving method thereof, and a display device.
  • a first switch connected to a gate of a driving transistor in a first state in a previous frame, and in a second state in a current frame;
  • the second switch connected in series is in the second state in the previous frame and in the first state in the current frame;
  • the first state is one of the on and off switching state and the continuous on state, and the second state is on and The other of the off-switching state and the continuously-on state, such that both the first switch and the second switch alternately experience negative bias stress in the on- and off-switching states due to the normally off-state and during the continuous-on state.
  • the threshold voltage of the metal oxide transistor will be.
  • the characteristics of recovery avoid the threshold voltage drift of the first switch and the second switch, increase the stability of the first switch and the second switch, avoid the problem of low frequency display failure caused by the gate leakage of the driving transistor caused by poor stability, and solve the traditional technology
  • the transistor connected to the gate of the driving transistor is usually in an off state, resulting in a negative shift of the threshold voltage, causing the gate leakage of the driving transistor to cause low-frequency display failure.
  • the alternating on and off switching states of the first switch and the second switch can prevent crosstalk of the signal written to the gate of the driving transistor.
  • 1A is an equivalent circuit diagram of a driving circuit according to a first embodiment of the present application
  • FIG. 1B is a timing diagram corresponding to the equivalent circuit diagram of the driving circuit according to the first embodiment of the present application.
  • 2B is a timing diagram corresponding to the equivalent circuit diagram of the driving circuit of Comparative Example 1;
  • 3A is an equivalent circuit diagram of a driving circuit according to a second embodiment of the present application.
  • 3B is a timing diagram corresponding to the equivalent circuit diagram of the driving circuit according to the second embodiment of the present application.
  • 4A is an equivalent circuit diagram of a driving circuit according to a third embodiment of the present application.
  • FIG. 4B is a timing diagram corresponding to the equivalent circuit diagram of the driving circuit according to the third embodiment of the present application.
  • the present application provides a display device, which may include an organic light emitting diode display panel, wherein the organic light emitting diode display panel includes a plurality of organic light emitting diodes.
  • the display device may also include a display panel using micro-light-emitting diodes (Micro-LEDs) as display pixels, wherein the micro-LEDs are inorganic light-emitting diodes with a size of less than or equal to 50 microns.
  • Micro-LEDs micro-light-emitting diodes
  • the display device may also include a backlight module with a sub-millimeter light emitting diode (Mini-LED) as a light-emitting unit, wherein the sub-millimeter light emitting diode is an inorganic light emitting diode with a size of 50 ⁇ m-200 ⁇ m.
  • Mini-LED sub-millimeter light emitting diode
  • the display device includes a plurality of driving circuits arranged in an array.
  • the driving circuit includes a light emitting diode and a driving transistor, the driving transistor is electrically connected with the light emitting diode, and the driving transistor is used for providing a driving current to the light emitting diode.
  • the stable potential of the gate of the driving transistor is beneficial to improve the light-emitting effect of the light-emitting diode.
  • the potential of the gate of the driving transistor is required to be stable for a long time to make the light emitting. The diode emits light steadily.
  • the driving circuit can be applied to organic light emitting diode display panels and display panels with micro light emitting diodes as display pixels, and the light emission can be controlled by controlling the magnitude of the driving current (pulse amplitude modulation) or the duration of the LED receiving the driving current (pulse width modulation).
  • the light emitted by the diode corresponds to the gray scale, so that the display device can display different gray scales.
  • the driving circuit can also be applied to the backlight module with sub-millimeter light-emitting diodes as the backlight light-emitting unit. By controlling the size of the driving current and the driving time of the driving current, the brightness of the backlight emitted by the backlight module can be controlled, and the sub-millimeter light emission can be controlled by partition.
  • the brightness of the diode can be adjusted by partition to control the brightness of the backlight so as to improve the display contrast and reduce the power consumption.
  • FIG. 1A is an equivalent circuit diagram of the driving circuit according to the first embodiment of the present application.
  • the driving circuit includes a driving transistor T1, a first switch T2A, a second switch T2B, a capacitor Cst and a light emitting diode LED.
  • the light emitting diode LED includes an anode and a cathode, the cathode of the light emitting diode LED is connected to the first power signal line VSS, and the anode of the light emitting diode LED is connected to the source of the driving transistor T1.
  • the light emitting diode LED is used to receive driving current to emit light.
  • the first power signal line VSS inputs a first power signal.
  • the light emitting diode LED is selected from any one of organic light emitting diodes, micro light emitting diodes and sub-millimeter light emitting diodes. Specifically, the light emitting diode LED is an organic light emitting diode.
  • the driving transistor T1 has a low temperature polysilicon active layer.
  • the driving transistor is an N-type transistor.
  • the gate of the drive transistor T1 is connected to the first switch T2A and the first end of the capacitor C, the source of the drive transistor T1 is connected to the second end of the capacitor C and the anode of the light emitting diode LED, and the drain of the drive transistor T1 is connected to the second end of the capacitor C and the anode of the light emitting diode LED.
  • the power signal line VDD is connected.
  • the second power supply signal line VDD is used for inputting the second power supply signal.
  • the turned-on driving transistor T1 outputs a driving current to the anode of the light emitting diode LED.
  • the driving transistor T1 may also be a P-type transistor.
  • One end of the capacitor Cst is connected to the gate of the driving transistor T1, and the other end of the capacitor Cst is connected to the anode of the light emitting diode LED.
  • the capacitor Cst is used to maintain the voltage of the gate of the driving transistor T1 to ensure that the light emitting diode LED emits light for one frame.
  • the first switch T2A is connected to the gate of the driving transistor T1, and the first switch T2A is connected between the gate of the driving transistor T1 and the second switch T2B.
  • the second switch T2B is connected between the data line DATA and the first switch T2A.
  • the first switch T2A and the second switch T2B as a whole jointly control whether the data signal input from the data line DATA is written to the gate of the driving transistor T1.
  • Both the first switch T2A and the second switch T2B include transistors having metal oxide active layers, and both are N-type transistors.
  • the source of the first switch T2A is connected to the gate of the driving transistor T1
  • the drain of the first switch T2A is connected to the source of the second switch T2B
  • the gate of the first switch T2A is connected to the first scan signal line SCAN1.
  • the gate of the second switch T2B is connected to the second scan signal line SCAN2
  • the source of the second switch T2B is connected to the drain of the first switch T2A
  • the drain of the second switch T2B is connected to the data line DATA.
  • Both the first switch T2A and the second switch T2B include transistors with a metal oxide active layer, so that in the process of driving the light-emitting diode LED to emit light by the driving transistor T1, the first switch T2A and the second switch T2B both have a lower off-state
  • the leakage current can avoid abnormal display of the light-emitting diode LED due to the potential change of the gate of the driving transistor T1 during the light-emitting process of the driving transistor T1 driving the light-emitting diode LED.
  • the first switch T2A is in the first state in the previous frame F1 and is in the second state in the current frame F2; the second switch T2B is in the second state in the previous frame F1 and in the first state in the current frame F2.
  • the first state is one of the on-and-off switching state and the continuous-on state, and the second state is the other of the on-and-off switching state and the continuous-on state.
  • the duration of the previous frame F1 and the current frame F2 are the same.
  • One of the first switch T2A and the second switch 2B is in the on and off switching state in the same frame, and the other is in the continuous on state to control whether the data signal of the frame is written to the gate of the driving transistor T1.
  • the first switch T2A When the first switch T2A is in the ON and OFF switching states for one frame, the first switch T2A is in the ON state for part of the frame, and is in the OFF state for part of the frame, and the first switch T2A is in the ON state and off state. Since the data signal input from the data line DATA is written to the gate of the driving transistor T1 for a short period of time, the first switch T2A is turned on for a short period of time in the on and off switching states.
  • the duration of one frame is 16667 microseconds (1/60s), there are a total of 2433 lines of driving circuits, and the duration of each row of driving circuits is 6.85 microseconds, that is, when the scanning frequency is 60Hz, the duration of one frame (16667 microseconds) ), the time corresponding to the simultaneous conduction of the first switch T2A and the second switch T2B to write the data signal is 6.85 microseconds, and the first switch T2A is in the off state for most of the remaining time.
  • the first switch T2A is continuously on, the first switch T2A is always on.
  • the second switch T2B is the same as the first switch T2A in the on and off switching states and the continuous on state, and will not be described in detail here.
  • the metal oxide transistor is negatively biased in the off state, and the metal oxide transistor is positively biased in the on state. Since the duration corresponding to the ON state of the first switch T2A and the second switch T2B is shorter than the duration corresponding to the OFF state when the ON state and the OFF state are switched during one frame time, the first switch T2A and the second switch T2B are affected by the ON state during one frame time. The time of the negative bias stress is relatively long, and the threshold voltages of the first switch T2A and the second switch T2B are negatively shifted when they are in the on and off switching states for one frame time.
  • the first switch T2A and the second switch T2B are continuously turned on in another frame time, so that the first switch T2A and the second switch T2B are subjected to forward biasing force in another frame time.
  • the time when the first switch T2A is negatively biased in one frame time and the time when it is positively biased in another frame time is close to avoid the threshold voltage of the first switch T2A from drifting.
  • the time when the second switch T2B is subjected to negative bias stress in one frame is close to the time when the second switch T2B is subjected to positive bias stress, so as to prevent the threshold voltage of the second switch T2B from drifting.
  • the first switch T2A and the second switch T2B have good stability to avoid the gate leakage of the driving transistor caused by the negative shift of the threshold voltage of the first switch T2A and the second switch T2B, thereby avoiding the failure of low-frequency display, which is beneficial to the realization of Higher stability, lower power consumption and better viewing angle experience.
  • the first switch T2A is in a continuous conduction state in the previous frame, and is in an on and off switching state in the current frame
  • the second switch T2B is in an on and off switching state in the previous frame, and is in a continuous conduction state in the current frame.
  • the ON state is used to prevent the threshold voltages of the first switch T2A and the second switch T2B from drifting.
  • one of the first switch T2A and the second switch T2B is used as a switch in the previous frame and the current frame, respectively, to avoid crosstalk of the data signal written to the gate of the driving transistor.
  • FIG. 1B is a timing diagram corresponding to the equivalent circuit diagram of the driving circuit according to the first embodiment of the present application.
  • the first switch T2A is in the first state
  • the second switch T2B is in the second state
  • the first switch T2A is in the second state
  • the second switch T2B is in the first state.
  • the first scan signal line SCAN1 is continuously inputting a high-level first scan signal, and the first switch T2A is in a continuously conducting state; the second scan signal line SCAN2 is input in two time periods.
  • the second scan signal of a high level and the second scan signal of a low level are input in the remaining period, the second switch T2B is in an on and off switching state, and in a period when the second scan signal line SCAN2 writes a high level, the data
  • the line DATA writes a data signal to the gate of the driving transistor T1.
  • the first scan signal line SCAN1 inputs a high-level first scan signal for two periods and a low-level first scan signal for the remaining periods, and the first switch T2A is in an on and off switching state.
  • the data line DATA writes a data signal;
  • the second scan signal line SCAN2 continuously inputs a second scan signal of a high level, and the second switch T2B is in a continuously on state.
  • FIG. 2A is an equivalent circuit diagram of the driving circuit of Comparative Example 1
  • FIG. 2B is a timing diagram corresponding to the equivalent circuit diagram of the driving circuit of Comparative Example 1.
  • the driving circuit shown in FIG. 2A includes a driving transistor T1, a switching transistor T2, a capacitor Cst and a light emitting diode LED.
  • the driving transistor T1 is an N-type transistor with a low temperature polysilicon active layer.
  • the switching transistor T2 is an N-type transistor having a metal oxide active layer.
  • the anode of the light emitting diode LED is connected to the source of the driving transistor T1, and the cathode of the light emitting diode LED is connected to the first power supply signal line VSS.
  • the gate of the driving transistor T1 is connected to the source of the switching transistor T2 and one end of the capacitor Cst, the drain of the driving transistor T1 is connected to the second power supply signal line VDD, the source of the driving transistor T1 is connected to the anode of the light emitting diode LED and the capacitor Cst the other end of the connection.
  • the gate of the switching transistor T2 is connected to the first scan signal line SCAN1, the drain of the switching transistor T2 is connected to the data line DATA, and the source of the switching transistor T2 is connected to the gate of the driving transistor T1 and one end of the capacitor Cst.
  • One end of the capacitor Cst is connected to the gate of the driving transistor T1 and the source of the switching transistor T2, and the other end of the capacitor Cst is connected to the source of the driving transistor T1 and the anode of the light emitting diode LED.
  • the switching transistor T2 is in the off state most of the time of each frame, which causes the switching transistor T2 to be continuously affected by negative bias stress. Due to the poor negative bias stress performance of the metal oxide transistor, the switching transistor T2 The negative shift of the threshold voltage of the switching transistor T2 causes the negative shift of the threshold voltage of the switching transistor T2 to easily lead to the leakage of the gate of the driving transistor T1, thus resulting in low frequency failure display.
  • FIG. 3A is an equivalent circuit diagram of the driving circuit according to the second embodiment of the present application
  • FIG. 3B is a timing diagram corresponding to the equivalent circuit diagram of the driving circuit according to the second embodiment of the present application.
  • the driving circuit includes a second light-emitting control transistor T1, a driving transistor T2, a first light-emitting control transistor T3, a write switch T4, a compensation switch, an initialization switch T6, a capacitor Cst, and a light-emitting diode LED.
  • the light emitting diode LED is the same as the light emitting diode LED of the driving circuit in the first embodiment, and will not be described in detail here.
  • the compensation switch is connected between one of the drain and source of the driving transistor T2 and the gate of the driving transistor T2, so that the gate of the driving transistor T2 and one of the drain and the source of the driving transistor T2 electrical connection between.
  • the compensation switch includes a first switch T51 and a second switch T52.
  • the first switch T51 is connected to the gate of the driving transistor T2 and one end of the capacitor Cst
  • the first switch T51 is connected between the gate of the driving transistor T2 and the second switch T52
  • the second switch T52 is connected to the first switch T51 and the driving between the source and the drain of the transistor T2.
  • the gate of the first switch T51 is connected to the fifth scan signal line SCAN5A, and the fifth scan signal line SCAN5A is used for inputting the fifth scan signal.
  • the gate of the second switch T52 is connected to the sixth scan signal line SCAN5B, and the sixth scan signal line SCAN5B is used to input the sixth scan signal.
  • the first switch T51 and the second switch T52 as a whole control the electrical connection between the gate of the driving transistor T2 and one of the source and the drain of the driving transistor T2.
  • the driving transistor T2 is an N-type transistor with a low temperature polysilicon active layer
  • both the first switch T51 and the second switch T52 are N-type transistors with a metal oxide active layer.
  • the second switch T52 is connected between the drain of the driving transistor T2 and the first switch T51.
  • the first switch T51 and the second switch T52 may also be P-type transistors.
  • the first light-emitting control transistor T3 and the second light-emitting control transistor T1 are both N-type transistors having a low temperature polysilicon active layer.
  • the first light-emitting control transistor T3 is connected between the source of the driving transistor T2 and the anode of the light-emitting diode LED, the gate of the first light-emitting control transistor T3 is connected to the second light-emitting control signal line EM2, and the second light-emitting control signal line EM2 is used for
  • the second light-emitting control light-emitting signal is input, and the first light-emitting control transistor T3 is configured to output the driving current output by the driving transistor T2 to the anode of the light-emitting diode according to the second light-emitting control signal.
  • the second light-emitting control transistor T1 is connected between the drain of the driving transistor T2 and the second power supply signal line VDD, the gate of the second light-emitting control transistor T1 is connected to the first light-emitting control signal line EM1, and the first light-emitting control signal line EM1 is used for For inputting the first light-emitting control signal, the second light-emitting control transistor T1 is used for outputting the second power signal to the drain of the driving transistor T2.
  • the light emitting diode LED is connected between the first light emission control transistor T3 and the first power signal line VSS.
  • the write switch T4 is an N-type transistor with a low temperature polysilicon active layer.
  • the source of the write switch T4 is connected to the source of the driving transistor T2, the drain of the write switch T4 is connected to the data line DATA, the data line DATA is used for inputting data signals, and the gate of the write switch T4 is connected to the fourth scan signal
  • the line SCAN4 is connected, and the fourth scan signal line SCAN4 is used for inputting the fourth scan signal.
  • the write switch T4 is used to write the data signal to the source of the driving transistor T2 according to the fourth scan signal.
  • the initialization switch T6 is an N-type transistor with a low temperature polysilicon active layer.
  • the gate of the initialization switch T6 is connected to the seventh scan signal line STN
  • the drain of the initialization switch T6 is connected to the initialization signal line Vinit
  • the source of the initialization switch T6 is connected to the anode of the light emitting diode LED and the other end of the capacitor Cst, wherein,
  • the initialization signal line Vinit is used for inputting the initialization signal
  • the seventh scan signal line STN inputs the seventh scan signal.
  • the initialization switch T6 is used to transmit an initialization signal to the anode of the light emitting diode LED according to the seventh scan signal, so as to realize the initialization of the anode of the light emitting diode LED, and realize the initialization of the gate of the driving transistor T2 through the capacitor Cst.
  • One end of the capacitor Cst is connected to the gate of the driving transistor T2 and the first switch T51, and the other end of the capacitor Cst is connected to the source of the initialization switch T6 and the anode of the light emitting diode LED.
  • the previous frame F1 sequentially includes an initialization phase, a threshold voltage compensation and data writing phase, and a light-emitting phase.
  • the seventh scan signal line STN inputs a high-level seventh scan signal, and the initialization switch T6 is turned on;
  • the first light-emitting control signal line EM1 inputs a high-level first light-emitting control signal, and the second light-emitting control transistor T1 On;
  • the fifth scan signal line SCAN5A inputs a high-level fifth scan signal, and the first switch T51 is turned on;
  • the sixth scan signal line SCAN5B inputs a high-level sixth scan signal, and the second switch T52 is turned on.
  • the second light-emitting control signal line EM2 inputs a second light-emitting control signal of a low level, and the first light-emitting control transistor T3 is turned off.
  • the fourth scan signal line SCAN4 inputs a fourth scan signal of a low level, and the write switch T4 is turned off.
  • the turned-on initialization switch T6 transmits the initialization signal to the anode of the light emitting diode LED.
  • the turned-on first switch T51 and the turned-on second switch T52 combine with the capacitor Cst to realize the initialization of the gate of the driving transistor T2.
  • the first switch T51 , the second switch T52 , the initialization transistor T6 and the writing switch T4 are all turned on.
  • the turned-on first switch T51 and the turned-on second switch T52 electrically connect the drain of the driving transistor T2 and the gate of the driving transistor T2.
  • the write switch T4 writes the data signal input from the data line DATA to the source of the driving transistor T2.
  • initialization transistor T6 is conducive to further initialization of the anode of the light-emitting diode LED, and avoids the floating of one end of the capacitor Cst connected to the light-emitting diode LED when the gate voltage of the driving transistor T2 is written, causing the anode of the light-emitting diode LED to float.
  • the voltage is unstable, and the light-emitting diode emits abnormal light.
  • the first light-emitting control transistor T3, the second light-emitting control transistor T1 and the driving transistor T2 are all turned on, and the driving current output by the driving transistor T2 is transmitted to the light-emitting diode LED through the turned-on first light-emitting control transistor T3, and the light-emitting diode LED glows.
  • the first switch T51 is in an on state
  • the second switch T52 is in an off state.
  • the initialization switch T6 and the write switch T4 are both turned off.
  • the first switch T51 is in a continuously conducting state.
  • the second switch T52 is in the ON state in the initialization stage, the threshold voltage compensation and the data writing stage, and is in the OFF state in other periods, that is, the second switch T52 is in the ON and OFF switching states, as described above
  • the on-time in one frame is much shorter than the off-time.
  • the first switch T51 is subjected to the forward bias stress in the previous frame, and the second switch T52 is mainly subjected to the negative bias stress in the previous frame.
  • the current frame F2 also sequentially includes an initialization phase, a threshold voltage compensation and a data writing phase, and a light-emitting phase.
  • the working states of the first switch T51 and the second switch T52 are switched.
  • the first switch T51 is in the on and off switching state in the current frame F2, and is the same as the second switch T52 is in the on and off switching state in the previous frame; the second switch T52 is in the continuous on state in the current frame.
  • the first switch T51 is mainly subjected to the negative bias stress, so that the threshold voltage of the first switch T51 is recovered from the drift caused by the forward bias stress in the previous frame.
  • the second switch T52 is subjected to a forward bias stress, so that the threshold voltage of the second switch T52 is recovered from the drift in the previous frame due to the negative bias stress.
  • the threshold voltages of the first switch T51 and the second switch T52 will not drift, which improves the stability of the first switch T51 and the second switch T52 and avoids negative threshold voltages when the first switch T51 and the second switch T52 are in the off state.
  • the direction drift leads to leakage, so as to avoid leakage of the gate of the driving transistor T2 through the first switch T51 and the second switch T52 during the light-emitting stage, resulting in failure of low-frequency display.
  • first switch T51 and the second switch T52 in this embodiment as a whole function to electrically connect the gate and drain of the driving transistor T2, while the first embodiment The function of the first switch T51 and the second switch T52 as a whole is to write the data signal to the gate of the driving transistor T2.
  • the common point between this embodiment and the first embodiment is that one of the first switch T51 and the second switch T52 is connected to the gate of the driving transistor, and the first switch T51 and the second switch T52 are connected in series. It can be understood that the inventive concept of the present application is not only applicable to the 2T1C drive circuit of the first embodiment and the 6T1C drive circuit of the second embodiment, but also to other drive circuits, such as a 7T1C circuit.
  • FIG. 4A is an equivalent circuit diagram of the driving circuit according to the third embodiment of the present application
  • FIG. 4B is a timing diagram corresponding to the equivalent circuit diagram of the driving circuit according to the third embodiment of the present application.
  • the driving circuit shown in FIG. 4A is basically similar to the driving circuit shown in FIG. 3A, except that the initialization switch includes a first initialization switch T61 and a second initialization switch T62, and the first initialization switch T61 and the second initialization switch T62 both include The transistor of the metal oxide active layer; the write switch includes a first write switch T41 and a second write switch T42, the first write switch T41 and the second write switch T42 both include transistors with a metal oxide active layer.
  • the first initialization switch T61 is connected to the anode of the light emitting diode LED, and is in the first state in the previous frame F1 and in the second state in the current frame F2.
  • the second initialization switch T62 is connected between the initialization signal line Vinit and the first initialization switch T61, the first initialization switch T61 is connected between the second initialization switch T62 and the anode of the light emitting diode LED, and is in the second state in the previous frame F1 , and is in the first state in the current frame F2.
  • the gate of the first initialization switch T61 is connected to the eighth scan signal line STNA, and the eighth scan signal line STNA is used for inputting the eighth scan signal.
  • the gate of the second initialization switch T62 is connected to the ninth scan signal line STNB, and the ninth scan signal line STNB is used for inputting the ninth scan signal.
  • Both the second initialization switch T62 and the first initialization switch T61 are N-type transistors.
  • Both the first initialization switch T61 and the second initialization switch T62 include transistors with a metal oxide active layer, which is beneficial to prevent the anode of the light emitting diode LED from being shunted through the closed first initialization switch T61 and the closed second initialization switch T62 to avoid emitting light.
  • Diode LEDs have problems with uneven brightness when displaying low grayscales.
  • the eighth scan signal line STNA continuously inputs the eighth scan signal of high level
  • the ninth scan signal line STNB alternately inputs the ninth scan signal of high level and low level.
  • the eighth scan signal line STNA alternately inputs a high-level and a low-level eighth scan signal
  • the ninth scan signal line STNB continuously inputs a high-level ninth scan signal.
  • the first initialization switch T61 is usually in the continuous on state in the previous frame F1, and is in the on and off switching state in the current frame F2 (the duration corresponding to the on state is shorter than the duration corresponding to the off state).
  • the first initialization switch T61 is in the on state.
  • the previous frame F1 is subjected to forward bias stress and the current frame F2 is subjected to negative bias stress, so that the first initialization switch T61 is alternately subjected to forward bias stress and negative bias stress, so as to avoid the threshold voltage drift of the first initialization switch T61 .
  • the second initialization switch T62 is in the ON and OFF switching state in the previous frame F1, and is in the continuous ON state in the current frame F2, the second initialization switch T62 is negatively biased in the previous frame and is in a positive direction in the current frame. bias stress, so that the second initialization switch T62 is alternately subjected to forward bias stress and negative bias stress, so as to avoid the threshold voltage drift of the second initialization switch T62.
  • the performance of the first initialization switch T61 and the second initialization switch T62 is stable in the off state, so as to avoid the leakage of electricity when the first initialization switch T61 and the second initialization switch T62 are turned off due to threshold voltage drift.
  • the first write switch T41 is connected to one of the source or the drain of the driving transistor T2, and is in the first state in the previous frame and in the second state in the current frame.
  • the second write switch T42 is connected between the first write switch T41 and the data line DATA, and the first write switch T41 is connected between the second write switch T42 and one of the source or drain of the driving transistor T2 , in the second state in the previous frame, and in the first state in the current frame.
  • the gate of the first write switch T41 is connected to the tenth scan signal line SCAN4A, and the tenth scan signal line SCAN4A is used for inputting the tenth scan signal.
  • the gate of the second write switch T42 is connected to the eleventh scan signal line SCAN4B, and the eleventh scan signal line SCAN4B is used for inputting the eleventh scan signal.
  • Both the first write switch T41 and the second write switch T42 are N-type transistors.
  • the first write switch T41 is connected to the source of the driving transistor T2.
  • Both the first write switch T41 and the second write switch T42 include transistors with a metal oxide active layer to prevent the potential of the source of the driving transistor T2 from leaking through the closed first write switch T41 and the second switch T42 .
  • the tenth scan signal line SCAN4A continuously inputs the tenth scan signal of high level
  • the eleventh scan signal line SCAN4B inputs the eleventh scan signal of high level for part of the time and The eleventh scan signal of low level is input in the remaining time
  • the tenth scan signal line SCAN4A inputs the tenth scan signal of high level for part of the time and the tenth scan signal of low level for the remaining time.
  • the eleventh scan signal line SCAN4B continuously inputs a high-level eleventh scan signal.
  • the first write switch T41 is in the continuous on state in the previous frame and is in the on and off switching state in the current frame.
  • the first write switch T41 is alternately subjected to forward bias stress and negative bias stress to avoid the first
  • the threshold voltage of the write switch T41 exhibits a negative shift.
  • the second write switch T42 is in the on and off switching state in the previous frame and is in the continuous on state in the current frame.
  • the threshold voltage of the second write switch T42 has a negative shift.
  • the performance of the first writing switch T41 and the second writing switch T42 is stable, and the potential fluctuation of the source electrode of the driving transistor T2 is avoided.

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Abstract

提供一种驱动电路及其驱动方法、显示装置，通过使与驱动晶体管(T1)的栅极连接的第一开关(T2A)在前一帧(F1)处于第一状态，且在当前帧(F2)处于第二状态；与第一开关(T2A)串联的第二开关(T2B)在前一帧(F1)处于第二状态，且在当前帧(F2)处于第一状态，第一状态为导通和截止切换状态以及持续导通状态中的一者，第二状态为导通和截止切换状态以及持续导通状态中的另一者。

Description

驱动电路及其驱动方法、显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种驱动电路及其驱动方法、显示装置。
 背景技术
随着显示技术的发展，用户对于显示的要求越来越高，显示要求能够满足画质更流畅的高频动态画面显示的同时，还要满足普通显示的低功耗需求，响应于高频显示和普通显示的需求，动态帧频技术应运而生。对于同时满足超低频（频率：1Hz-5Hz）及超高频（频率：120Hz-360Hz）的显示面板，显示区的像素电路需要具有充电能力强以及画面维持能力强的特点，其中，充电能力强是指像素电路在高频状态时每行充电时间极短，画面维持能力强是指在低频状态时每帧的时间延长。传统的非晶硅技术、低温多晶硅技术以及金属氧化物技术均无法同时满足超低频及超高频显示的要求。
低温多晶硅金属氧化物（Low Temperature Polycrystalline Oxide，LTPO）技术结合了低温多晶硅（Low Temperature Poly-silicon，简称LTPS）及氧化铟镓锌（Indium Gallium Zinc Oxide, 简称IGZO）两种技术的优点，使显示面板同时具有强驱动能力和低功耗的特点，其已成为显示领域炙手可热的技术。目前，逐渐将低温多晶硅金属氧化物技术应用扩展至低频及高频显示领域，其中，对于低频显示的像素电路设计，通常利用金属氧化物晶体管具有超低关态漏电流的特点，使与驱动晶体管的栅极连接的晶体管具有金属氧化物有源层，以实现低频状态时驱动晶体管的栅极的电压准位保持的目的。然而，由于金属氧化物晶体管自身的负向偏压应力表现较差，与驱动晶体管的栅极连接且具有金属氧化物有源层的晶体管通常处于关态，处于关态的具有金属氧化物有源层的晶体管受负向偏压应力的作用导致具有金属氧化物有源层的晶体管的阈值电压负向漂移，阈值电压负向漂移容易导致驱动晶体管的栅极漏电，最终导致低频显示失效。
因此，有必要提出一种技术方案以解决金属氧化物晶体管处于关态时受负向偏压应力作用使得阈值电压负向漂移导致驱动晶体管的栅极漏电使得低频显示失效的问题。
 技术问题
本申请的目的在于提供一种驱动电路及其驱动方法、显示装置，以解决金属氧化物晶体管处于关态时受负向偏压应力作用使得阈值电压负向漂移导致驱动晶体管的栅极漏电使得低频显示失效的问题。
 技术解决方案
为实现上述目的，本申请提供一种驱动电路，所述驱动电路包括：
发光二极管；
驱动晶体管，所述驱动晶体管与所述发光二极管电性连接，用于向所述发光二极管提供驱动电流；
第一开关，所述第一开关与所述驱动晶体管的栅极连接，在前一帧处于第一状态，且在当前帧处于第二状态；以及
第二开关，所述第一开关连接于所述驱动晶体管的栅极和所述第二开关之间，在所述前一帧处于所述第二状态，且在所述当前帧处于所述第一状态；
所述第一状态为导通和截止切换状态、持续导通状态中的一者，所述第二状态为导通和截止切换状态、持续导通状态中的另一者。
在上述驱动电路中，所述第一开关和所述第二开关均包括具有金属氧化物有源层的晶体管。
在上述驱动电路中，所述驱动电路还包括：
第一初始化开关，所述第一初始化开关与所述发光二极管的阳极连接，在所述前一帧处于所述第一状态，且在所述当前帧处于所述第二状态；以及
第二初始化开关，所述第二初始化开关连接于初始化信号线和所述第一初始化开关之间，所述第一初始化开关连接于所述第二初始化开关和所述发光二极管的阳极之间，在所述前一帧处于所述第二状态，且在所述当前帧处于所述第一状态。
在上述驱动电路中，所述第一初始化开关和第二初始化开关均包括具有金属氧化物有源层的晶体管。
在上述驱动电路中，所述驱动电路还包括电容器，所述电容器的一端连接所述驱动晶体管的栅极，所述电容器的另一端连接所述发光二极管的阳极和所述第一初始化开关。
在上述驱动电路中，所述驱动电路还包括：
第一写入开关，所述第一写入开关连接所述驱动晶体管的源极或漏极中的一者，在所述前一帧处于所述第一状态，且在所述当前帧处于所述第二状态；以及
第二写入开关，所述第二写入开关连接于所述第一写入开关和数据线之间，所述第一写入开关连接于所述第二写入开关和所述驱动晶体管的源极或漏极中的一者之间，在所述前一帧处于所述第二状态，且在所述当前帧处于所述第一状态。
在上述驱动电路中，所述第一写入开关和所述第二写入开关均包括具有金属氧化物有源层的晶体管。
在上述驱动电路中，所述第二开关连接于所述第一开关和所述驱动晶体管的源极和漏极中的另一者之间。
在上述驱动电路中，所述驱动电路还包括：
第一发光控制晶体管，所述第一发光控制晶体管连接于所述驱动晶体管的源极和漏极中的一者和所述发光二极管的阳极之间；
第二发光控制晶体管，所述第二发光控制晶体管连接于所述驱动晶体管的源极和漏极中的另一者和电源信号线之间。
在上述驱动电路中，所述驱动晶体管、所述第一发光控制晶体管以及所述第二发光控制晶体管均为具有多晶硅有源层的晶体管。
在上述驱动电路中，所述第二开关连接于数据线和所述第一开关之间。
在上述驱动电路中，所述导通和截止切换状态包括导通状态和截止状态，所述导通和截止切换状态中所述导通状态对应的时长小于所述截止状态对应的时长。
一种上述驱动电路的驱动方法，所述方法包括如下步骤：
在前一帧，所述第一开关处于所述第一状态，所述第二开关处于所述第二状态；
在当前帧，所述第一开关处于所述第二状态，所述第一开关处于所述第一状态。
一种显示装置，所述显示装置包括上述驱动电路。
 有益效果
本申请提供一种驱动电路及其驱动方法、显示装置，通过使与驱动晶体管的栅极连接的第一开关在前一帧处于第一状态，且在当前帧处于第二状态；与第一开关串联的第二开关在前一帧处于第二状态，且在当前帧处于第一状态；第一状态为导通和截止切换状态以及持续导通状态中的一者，第二状态为导通和截止切换状态以及持续导通状态中的另一者，以使得第一开关和第二开关均交替经受在导通和截止切换状态中由于通常处于截止状态时产生的负向偏应力和在持续导通时产生的正向偏应力，利用金属氧化物晶体管在受负向偏应力作用后施加正向偏应力或者受正向偏应力作用后施加负向偏应力时，金属氧化物晶体管的阈值电压会恢复的特点，避免第一开关和第二开关的阈值电压漂移，增加第一开关和第二开关的稳定性，避免稳定性不佳导致驱动晶体管的栅极漏电导致低频显示失效问题，解决传统技术中与驱动晶体管的栅极连接的晶体管通常处于关态导致阈值电压负向漂移引起驱动晶体管的栅极漏电导致低频显示失效的问题。另外，第一开关和第二开关交替地处于导通和截止切换状态能避免写入至驱动晶体管的栅极的信号出现串扰。
 附图说明
图1A为本申请第一实施例驱动电路的等效电路图；
图1B为本申请第一实施例驱动电路的等效电路图对应的时序图；
图2A为对比例1的驱动电路的等效电路图；
图2B为对比例1的驱动电路的等效电路图对应的时序图；
图3A为本申请第二实施例驱动电路的等效电路图；
图3B为本申请第二实施例驱动电路的等效电路图对应的时序图；
图4A为本申请第三实施例驱动电路的等效电路图；
图4B为本申请第三实施例驱动电路的等效电路图对应的时序图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请提供一种显示装置，显示装置可以包括有机发光二极管显示面板，其中，有机发光二极管显示面板包括多个有机发光二极管。显示装置也可以包括以微型发光二极管（Micro-LED）作为显示像素的显示面板，其中，微型发光二极管为尺寸小于或等于50微米的无机发光二极管。显示装置也可以包括以次毫米发光二极管（Mini-LED）作为发光单元的背光模组，其中，次毫米发光二极管为尺寸在50微米-200微米的无机发光二极管。
为了使显示装置发光以进行显示。显示装置包括多个阵列排布的驱动电路。驱动电路包括发光二极管以及驱动晶体管，驱动晶体管与发光二极管电性连接，驱动晶体管用于向发光二极管提供驱动电流。驱动晶体管驱动发光二极管发光过程中，驱动晶体管的栅极的电位稳定有利于提高发光二极管的发光效果，特别是低频显示过程中，要求驱动晶体管的栅极的电位稳定维持较长时间，以使得发光二极管稳定的发光。
驱动电路可以应用于有机发光二极管显示面板以及以微型发光二极管作为显示像素的显示面板，可以通过控制驱动电流的大小（脉冲幅度调制）或者发光二极管接收驱动电流的时长（脉冲宽度调制）以控制发光二极管发出的光对应的灰阶，以使显示装置显示不同的灰阶。驱动电路也可以应用于以次毫米发光二极管作为背光发光单元的背光模组，通过控制驱动电流的大小和驱动电流的驱动时长，以控制背光模组发出的背光的亮度，通过分区控制次毫米发光二极管的亮度，以分区调控背光源的亮度从而实现提高显示对比度以及降低功耗的作用。
为了便于描述本申请的技术方案，以下以驱动电路应用于显示面板以实现显示发光为例进行说明。
请参阅图1A，其为本申请第一实施例驱动电路的等效电路图。驱动电路包括驱动晶体管T1、第一开关T2A、第二开关T2B、电容器Cst以及发光二极管LED。
发光二极管LED包括阳极以及阴极，发光二极管LED的阴极与第一电源信号线VSS连接，发光二极管LED的阳极与驱动晶体管T1的源极连接。发光二极管LED用于接收驱动电流以发光。第一电源信号线VSS输入第一电源信号。发光二极管LED选自有机发光二极管、微型发光二极管以及次毫米发光二极管中的任意一种。具体地，发光二极管LED为有机发光二极管。
驱动晶体管T1具有低温多晶硅有源层。驱动晶体管为N型晶体管。驱动晶体管T1的栅极与第一开关T2A以及电容器C的第一端连接，驱动晶体管T1的源极与电容器C的第二端以及发光二极管LED的阳极连接，驱动晶体管T1的漏极与第二电源信号线VDD连接。第二电源信号线VDD用于输入第二电源信号。导通的驱动晶体管T1输出驱动电流至发光二极管LED的阳极。在其他实施例中，驱动晶体管T1也可以为P型晶体管。
电容器Cst的一端连接驱动晶体管T1的栅极，电容器Cst的另一端连接发光二极管LED的阳极。电容器Cst用于维持驱动晶体管T1的栅极的电压，以保证发光二极管LED在一帧的时间发光。
第一开关T2A与驱动晶体管T1的栅极连接，第一开关T2A连接于驱动晶体管T1的栅极和第二开关T2B之间。第二开关T2B连接于数据线DATA和第一开关T2A之间。第一开关T2A和第二开关T2B作为一个整体共同控制数据线DATA输入的数据信号是否写入至驱动晶体管T1的栅极。
第一开关T2A和第二开关T2B均包括具有金属氧化物有源层的晶体管，且均为N型晶体管。第一开关T2A的源极与驱动晶体管T1的栅极连接，第一开关T2A的漏极与第二开关T2B的源极连接，第一开关T2A的栅极与第一扫描信号线SCAN1连接。第二开关T2B的栅极与第二扫描信号线SCAN2连接，第二开关T2B的源极与第一开关T2A的漏极连接，第二开关T2B的漏极与数据线DATA连接。
第一开关T2A和第二开关T2B均包括具有金属氧化物有源层的晶体管，使得驱动晶体管T1驱动发光二极管LED发光的过程中，第一开关T2A和第二开关T2B均具有较低的关态漏电流，避免驱动晶体管T1驱动发光二极管LED发光过程中驱动晶体管T1的栅极的电位变化导致发光二极管LED出现非正常显示。
第一开关T2A在前一帧F1处于第一状态，且在当前帧F2处于第二状态；第二开关T2B在前一帧F1处于第二状态，且在当前帧F2处于第一状态。第一状态为导通和截止切换状态、持续导通状态中的一种，第二状态为导通和截止切换状态、持续导通状态中的另一种。前一帧F1和当前帧F2的时长相同。第一开关T2A和第二开关2B中的一者在同一帧处于导通和截止切换状态，另一者处于持续导通状态，以控制该帧数据信号是否写入至驱动晶体管T1的栅极。
第一开关T2A在一帧处于导通和截止切换状态时，第一开关T2A在一帧的部分时间处于导通状态，且在一帧的部分时间处于截止状态，第一开关T2A在导通状态和截止状态之间切换。由于数据线DATA输入的数据信号写入至驱动晶体管T1的栅极的时间较短，使得第一开关T2A在导通和截止切换状态中导通的时间较短。例如一帧的时长为16667微秒（1/60s），总共有2433行的驱动电路，每一行驱动电路导通的时长为6.85微秒，即扫描频率为60Hz时，一帧时长（16667微秒）中，对应第一开关T2A和第二开关T2B同时导通以写入数据信号的时间为6.85微秒，剩余大部分时间第一开关T2A均处于截止状态。第一开关T2A在持续导通状态时，第一开关T2A一直处于导通状态。第二开关T2B在导通和截止切换状态、持续导通状态与第一开关T2A相同，此处不作详述。
金属氧化物晶体管在截止状态时受负向偏应力，金属氧化物晶体管在导通状态时受正向偏应力。由于一帧时间处于导通和截止切换状态时，第一开关T2A和第二开关T2B导通状态对应的时长小于截止状态对应的时长，导致第一开关T2A和第二开关T2B在一帧时间受负向偏应力的时间较长，第一开关T2A和第二开关T2B的阈值电压在一帧时间处于导通和截止切换状态时发生负向漂移。通过第一开关T2A和第二开关T2B在另一帧时间处于持续导通状态，以使得第一开关T2A和第二开关T2B在另一帧时间受正向偏应力的作用。第一开关T2A在一帧时间受负向偏应力和在另一帧时间受正向偏应力的时间接近，避免第一开关T2A的阈值电压发生漂移。第二开关T2B在一帧时间受负向偏应力和另一帧受正向偏应力的时间接近，避免第二开关T2B的阈值电压发生漂移。因此，第一开关T2A和第二开关T2B具有良好的稳定性，避免第一开关T2A和第二开关T2B的阈值电压负向漂移导致驱动晶体管的栅极漏电，从而避免低频显示失效，有利于实现更高稳定性、更低功耗以及更好视角体验。
具体地，第一开关T2A在前一帧处于持续导通状态，在当前帧处于导通和截止切换状态；第二开关T2B在前一帧处于导通和截止切换状态，在当前帧处于持续导通状态，以避免第一开关T2A和第二开关T2B的阈值电压发生漂移。且第一开关T2A和第二开关T2B中的一者分别在前一帧和当前帧中作为开关使用，避免写入至驱动晶体管的栅极的数据信号发生串扰。
请参阅图1B，其为本申请第一实施例驱动电路的等效电路图对应的时序图。在前一帧，第一开关T2A处于第一状态，第二开关T2B处于第二状态；在当前帧，第一开关T2A处于第二状态，第二开关T2B处于第一状态。
在本实施例中，在前一帧F1，第一扫描信号线SCAN1持续输入高电平的第一扫描信号，第一开关T2A处于持续导通状态；第二扫描信号线SCAN2在两个时段输入高电平的第二扫描信号且剩余时段输入低电平的第二扫描信号，第二开关T2B处于导通和截止切换状态，在第二扫描信号线SCAN2写入高电平的一个时段，数据线DATA写入数据信号至驱动晶体管T1的栅极。在当前帧F2，第一扫描信号线SCAN1在两个时段输入高电平的第一扫描信号且剩余时段输入低电平的第一扫描信号，第一开关T2A处于导通和截止切换状态，在第一扫描信号线SCAN1写入高电平的一个时段，数据线DATA写入数据信号；第二扫描信号线SCAN2持续输入高电平的第二扫描信号，第二开关T2B处于持续导通状态。
请参阅图2A及图2B，图2A为对比例1的驱动电路的等效电路图，图2B为对比例1的驱动电路的等效电路图对应的时序图。图2A所示驱动电路包括驱动晶体管T1、开关晶体管T2、电容器Cst以及发光二极管LED。
驱动晶体管T1为N型且具有低温多晶硅有源层的晶体管。开关晶体管T2为N型且具有金属氧化物有源层的晶体管。发光二极管LED的阳极与驱动晶体管T1的源极连接，发光二极管LED的阴极与第一电源信号线VSS连接。驱动晶体管T1的栅极与开关晶体管T2的源极以及电容器Cst的一端连接，驱动晶体管T1的漏极与第二电源信号线VDD连接，驱动晶体管T1的源极与发光二极管LED的阳极以及电容器Cst的另一端连接。开关晶体管T2的栅极与第一扫描信号线SCAN1连接，开关晶体管T2的漏极与数据线DATA连接，开关晶体管T2的源极与驱动晶体管T1的栅极以及电容器Cst的一端连接。电容器Cst的一端与驱动晶体管T1的栅极以及开关晶体管T2的源极连接，电容器Cst的另一端与驱动晶体管T1的源极以及发光二极管LED的阳极连接。
由图2B可知，开关晶体管T2在每一帧的大部分时间处于截止状态，导致开关晶体管T2持续受负向偏应力的作用，由于金属氧化物晶体管的负向偏应力表现较差，开关晶体管T2的阈值电压负向漂移，导致开关晶体管T2的阈值电压负向漂移容易导致驱动晶体管T1的栅极漏电，从而导致低频失效显示。
请参阅图3A及图3B，图3A为本申请第二实施例驱动电路的等效电路图，图3B为本申请第二实施例驱动电路的等效电路图对应的时序图。驱动电路包括第二发光控制晶体管T1、驱动晶体管T2、第一发光控制晶体管T3、写入开关T4、补偿开关、初始化开关T6、电容器Cst以及发光二极管LED。其中，发光二极管LED与第一实施例中驱动电路的发光二极管LED相同，此处不作详述。
补偿开关连接于驱动晶体管T2的漏极、源极中的一者和驱动晶体管T2的栅极之间，以使得驱动晶体管T2的栅极和驱动晶体管T2的漏极、源极中的一者之间电性连接。补偿开关包括第一开关T51以及第二开关T52。第一开关T51与驱动晶体管T2的栅极以及电容器Cst的一端连接，第一开关T51连接于驱动晶体管T2的栅极和第二开关T52之间，第二开关T52连接于第一开关T51和驱动晶体管T2的源极、漏极中的一者之间。第一开关T51的栅极与第五扫描信号线SCAN5A连接，第五扫描信号线SCAN5A用于输入第五扫描信号。第二开关T52的栅极与第六扫描信号线SCAN5B连接，第六扫描信号线SCAN5B用于输入第六扫描信号。第一开关T51和第二开关T52作为一个整体控制驱动晶体管T2的栅极和驱动晶体管T2的源极、漏极中的一者之间电性连接。
具体地，驱动晶体管T2为具有低温多晶硅有源层的N型晶体管，第一开关T51和第二开关T52均为具有金属氧化物有源层的N型晶体管。第二开关T52连接于驱动晶体管T2的漏极和第一开关T51之间。在其他实施例中，第一开关T51和第二开关T52也可以为P型晶体管。
第一发光控制晶体管T3和第二发光控制晶体管T1均为N型且具有低温多晶硅有源层的晶体管。第一发光控制晶体管T3连接于驱动晶体管T2的源极和发光二极管LED的阳极之间，第一发光控制晶体管T3的栅极连接第二发光控制信号线EM2，第二发光控制信号线EM2用于输入第二发光控制发光信号，第一发光控制晶体管T3用于根据第二发光控制信号将驱动晶体管T2输出的驱动电流输出至发光二极管的阳极。第二发光控制晶体管T1连接于驱动晶体管T2的漏极和第二电源信号线VDD之间，第二发光控制晶体管T1的栅极连接第一发光控制信号线EM1，第一发光控制信号线EM1用于输入第一发光控制信号，第二发光控制晶体管T1用于将第二电源信号输出至驱动晶体管T2的漏极。发光二极管LED连接于第一发光控制晶体管T3和第一电源信号线VSS之间。
写入开关T4为N型且具有低温多晶硅有源层的晶体管。写入开关T4的源极与驱动晶体管T2的源极连接，写入开关T4的漏极与数据线DATA连接，数据线DATA用于输入数据信号，写入开关T4的栅极与第四扫描信号线SCAN4连接，第四扫描信号线SCAN4用于输入第四扫描信号。写入开关T4用于根据第四扫描信号将数据信号写入至驱动晶体管T2的源极。
初始化开关T6为N型且具有低温多晶硅有源层的晶体管。初始化开关T6的栅极与第七扫描信号线STN连接，初始化开关T6的漏极与初始化信号线Vinit连接，初始化开关T6的源极与发光二极管LED的阳极以及电容器Cst的另一端连接，其中，初始化信号线Vinit用于输入初始化信号，第七扫描信号线STN输入第七扫描信号。初始化开关T6用于根据第七扫描信号将初始化信号传输至发光二极管LED的阳极，以实现发光二极管LED阳极的初始化，且通过电容器Cst 实现驱动晶体管T2的栅极的初始化。
电容器Cst的一端连接驱动晶体管T2的栅极以及第一开关T51，电容器Cst的另一端连接初始化开关T6的源极以及发光二极管LED的阳极。
前一帧F1依次包括初始化阶段、阈值电压补偿以及数据写入阶段以及发光阶段。
在初始化阶段，第七扫描信号线STN输入高电平的第七扫描信号，初始化开关T6导通；第一发光控制信号线EM1输入高电平的第一发光控制信号，第二发光控制晶体管T1导通；第五扫描信号线SCAN5A输入高电平的第五扫描信号，第一开关T51导通；第六扫描信号线SCAN5B输入高电平的第六扫描信号，第二开关T52导通。第二发光控制信号线EM2输入低电平的第二发光控制信号，第一发光控制晶体管T3截止。第四扫描信号线SCAN4输入低电平的第四扫描信号，写入开关T4截止。导通的初始化开关T6将初始化信号传输至发光二极管LED的阳极。导通的第一开关T51和导通的第二开关T52结合电容器Cst实现驱动晶体管T2的栅极的初始化。
在阈值电压补偿及数据写入阶段，第一开关T51、第二开关T52、初始化晶体管T6以及写入开关T4均导通。导通的第一开关T51和导通的第二开关T52使得驱动晶体管T2的漏极以及驱动晶体管T2的栅极电性连接。写入开关T4将数据线DATA输入的数据信号写入至驱动晶体管T2的源极。初始化晶体管T6导通有利于进一步地对发光二极管LED的阳极进行初始化，避免在驱动晶体管T2的栅极写入电压时出现电容器Cst与发光二极管LED连接的一端浮置，导致发光二极LED的阳极电压不稳定，发光二极管出现非正常发光。
在发光阶段，第一发光控制晶体管T3、第二发光控制晶体管T1以及驱动晶体管T2均导通，驱动晶体管T2输出的驱动电流通过导通的第一发光控制晶体管T3传输至发光二极管LED，发光二极管LED发光。第一开关T51处于导通状态，第二开关T52处于截止状态。初始化开关T6以及写入开关T4均处于截止状态。
在前一帧，第一开关T51处于持续导通状态。在前一帧，第二开关T52在初始化阶段以及阈值电压补偿以及数据写入阶段处于导通状态，在其他时段均处于截止状态，即第二开关T52处于导通和截止切换状态，如前所述，一帧中导通的时长远小于截止的时长。第一开关T51在前一帧受正向偏应力的作用，第二开关T52在前一帧主要受负向偏应力的作用。
当前帧F2也依次包括初始化阶段、阈值电压补偿以及数据写入阶段、发光阶段。其中，第一开关T51和第二开关T52的工作状态发生切换。第一开关T51在当前帧F2处于导通和截止切换状态，且与第二开关T52在前一帧处于导通和截止切换状态相同；第二开关T52在当前帧处于持续导通状态。在当前帧，第一开关T51主要受负向偏应力，使得第一开关T51的阈值电压在前一帧由于正向偏应力发生的漂移得到恢复。在当前帧，第二开关T52受正向偏应力，使得第二开关T52的阈值电压在前一帧由于负向偏应力发生的漂移得到恢复。第一开关T51和第二开关T52的阈值电压不会发生漂移，提高了第一开关T51和第二开关T52的稳定性，避免第一开关T51和第二开关T52处于关态时由于阈值电压负向漂移导致漏电，从而避免驱动晶体管T2的栅极在发光阶段通过第一开关T51和第二开关T52出现漏电，导致低频显示失效。
本实施例与第一实施例的区别在于，本实施例中第一开关T51和第二开关T52作为一个整体的作用在于使驱动晶体管T2的栅极和漏极电性连接，而第一实施例中第一开关T51和第二开关T52作为一个整体的作用在于使数据信号写入至驱动晶体管T2的栅极。本实施例与第一实施例的共同点在于，第一开关T51和第二开关T52中的一者与驱动晶体管的栅极连接，且第一开关T51和第二开关T52串联。可以理解的是，本申请的发明构思不仅适用于第一实施例的2T1C驱动电路以及第二实施例的6T1C驱动电路，也可以适应于其他驱动电路，例如7T1C电路等。
请参阅图4A以及图4B，图4A为本申请第三实施例驱动电路的等效电路图，图4B为本申请第三实施例驱动电路的等效电路图对应的时序图。图4A所示驱动电路与图3A所示驱动电路基本相似，不同之处在于，初始化开关包括第一初始化开关T61和第二初始化开关T62，第一初始化开关T61和第二初始化开关T62均包括具有金属氧化有源层的晶体管；写入开关包括第一写入开关T41和第二写入开关T42，第一写入开关T41和第二写入开关T42均包括具有金属氧化有源层的晶体管。
第一初始化开关T61与发光二极管LED的阳极连接，在前一帧F1处于第一状态，且在当前帧F2处于第二状态。第二初始化开关T62连接于初始化信号线Vinit和第一初始化开关T61之间，第一初始化开关T61连接于第二初始化开关T62和发光二极管LED的阳极之间，在前一帧F1处于第二状态，且在当前帧F2处于第一状态。第一初始化开关T61的栅极与第八扫描信号线STNA连接，第八扫描信号线STNA用于输入第八扫描信号。第二初始化开关T62的栅极与第九扫描信号线STNB连接，第九扫描信号线STNB用于输入第九扫描信号。第二初始化开关T62和第一初始化开关T61均为N型晶体管。
第一初始化开关T61和第二初始化开关T62均包括具有金属氧化有源层的晶体管，有利于避免发光二极管LED的阳极通过关闭的第一初始化开关T61和关闭的第二初始化开关T62分流，避免发光二极管LED显示低灰阶时出现亮度不均的问题。
如图4B所示，在前一帧F1，第八扫描信号线STNA持续输入高电平的第八扫描信号，第九扫描信号线STNB交替地输入高电平和低电平的第九扫描信号。在当前帧F2，第八扫描信号线STNA交替地输入高电平和低电平的第八扫描信号，第九扫描信号线STNB持续输入高电平的第九扫描信号。
第一初始化开关T61在前一帧F1通常处于持续导通状态，且在当前帧F2处于导通和截止切换状态（导通状态对应的时长小于截止状态对应的时长），第一初始化开关T61在前一帧F1受正向偏应力且在当前帧F2受负向偏应力，使得第一初始化开关T61交替地受正向偏应力和负向偏应力作用，避免第一初始化开关T61的阈值电压漂移。第二初始化开关T62在前一帧F1处于导通和截止切换状态，且在当前帧F2处于持续导通状态，第二初始化开关T62在前一帧受负向偏应力且在当前帧受正向偏应力，使得第二初始化开关T62交替地受正向偏应力和负向偏应力作用，避免第二初始化开关T62的阈值电压漂移。第一初始化开关T61和第二初始化开关T62在关态时性能稳定，避免第一初始化开关T61和第二初始化开关T62由于阈值电压漂移而出现关闭时漏电。
第一写入开关T41连接驱动晶体管T2的源极或漏极中的一者，在前一帧处于第一状态，且在当前帧处于第二状态。第二写入开关T42连接于第一写入开关T41和数据线DATA之间，第一写入开关T41连接于第二写入开关T42和驱动晶体管T2的源极或漏极中一者之间，在前一帧处于第二状态，且在当前帧处于第一状态。第一写入开关T41的栅极与第十扫描信号线SCAN4A连接，第十扫描信号线SCAN4A用于输入第十扫描信号。第二写入开关T42的栅极与第十一扫描信号线SCAN4B连接，第十一扫描信号线SCAN4B用于输入第十一扫描信号。第一写入开关T41和第二写入开关T42均为N型晶体管。第一写入开关T41连接驱动晶体管T2的源极。
第一写入开关T41和第二写入开关T42均包括具有金属氧化物有源层的晶体管，避免驱动晶体管T2的源极的电位通过关闭的第一写入开关T41和第二开关T42而漏电。
如图4B所示，在前一帧F1，第十扫描信号线SCAN4A持续输入高电平的第十扫描信号，第十一扫描信号线SCAN4B在部分时间输入高电平的第十一扫描信号且剩余时间输入低电平的第十一扫描信号；在当前帧F2，第十扫描信号线SCAN4A在部分时间输入高电平的第十扫描信号且剩余时间输入低电平的第十扫描信号，第十一扫描信号线SCAN4B持续输入高电平的第十一扫描信号。
第一写入开关T41在前一帧处于持续导通状态且在当前帧处于导通和截止切换状态，第一写入开关T41交替地受正向偏应力和负向偏应力作用，避免第一写入开关T41的阈值电压出现负向漂移。第二写入开关T42在前一帧处于导通和截止切换状态且在当前帧处于持续导通状态，第二写入开关T42交替地受正向偏应力和负向偏应力的作用，避免第二写入开关T42的阈值电压出现负向漂移。第一写入开关T41和第二写入开关T42的性能稳定，避免驱动晶体管T2的源极的电位出现波动。
以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种驱动电路，其中，所述驱动电路包括：
    发光二极管；
    驱动晶体管，所述驱动晶体管与所述发光二极管电性连接，用于向所述发光二极管提供驱动电流；
    第一开关，所述第一开关与所述驱动晶体管的栅极连接，在前一帧处于第一状态，且在当前帧处于第二状态；以及
    第二开关，所述第一开关连接于所述驱动晶体管的栅极和所述第二开关之间，在所述前一帧处于所述第二状态，且在所述当前帧处于所述第一状态；
    所述第一状态为导通和截止切换状态、持续导通状态中的一者，所述第二状态为导通和截止切换状态、持续导通状态中的另一者。
  2. 根据权利要求1所述的驱动电路，其中，所述第一开关和所述第二开关均包括具有金属氧化物有源层的晶体管。
  3. 根据权利要求1所述的驱动电路，其中，所述驱动电路还包括：
    第一初始化开关，所述第一初始化开关与所述发光二极管的阳极连接，在所述前一帧处于所述第一状态，且在所述当前帧处于所述第二状态；以及
    第二初始化开关，所述第二初始化开关连接于初始化信号线和所述第一初始化开关之间，所述第一初始化开关连接于所述第二初始化开关和所述发光二极管的阳极之间，在所述前一帧处于所述第二状态，且在所述当前帧处于所述第一状态。
  4. 根据权利要求3所述的驱动电路，其中，所述第一初始化开关和第二初始化开关均包括具有金属氧化物有源层的晶体管。
  5. 根据权利要求3所述的驱动电路，其中，所述驱动电路还包括电容器，所述电容器的一端连接所述驱动晶体管的栅极，所述电容器的另一端连接所述发光二极管的阳极和所述第一初始化开关。
  6. 根据权利要求1所述的驱动电路，其中，所述驱动电路还包括：
    第一写入开关，所述第一写入开关连接所述驱动晶体管的源极或漏极中的一者，在所述前一帧处于所述第一状态，且在所述当前帧处于所述第二状态；以及
    第二写入开关，所述第二写入开关连接于所述第一写入开关和数据线之间，所述第一写入开关连接于所述第二写入开关和所述驱动晶体管的源极或漏极中的一者之间，在所述前一帧处于所述第二状态，且在所述当前帧处于所述第一状态。
  7. 根据权利要求6所述的驱动电路，其中，所述第一写入开关和所述第二写入开关均包括具有金属氧化物有源层的晶体管。
  8. 根据权利要求6所述的驱动电路，其中，所述第二开关连接于所述第一开关和所述驱动晶体管的源极和漏极中的另一者之间。
  9. 根据权利要求1所述的驱动电路，其中，所述驱动电路还包括：
    第一发光控制晶体管，所述第一发光控制晶体管连接于所述驱动晶体管的源极和漏极中的一者和所述发光二极管的阳极之间；
    第二发光控制晶体管，所述第二发光控制晶体管连接于所述驱动晶体管的源极和漏极中的另一者和电源信号线之间。
  10. 根据权利要求9所述的驱动电路，其中，所述驱动晶体管、所述第一发光控制晶体管以及所述第二发光控制晶体管均为具有多晶硅有源层的晶体管。
  11. 根据权利要求1所述的驱动电路，其中，所述第二开关连接于数据线和所述第一开关之间。
  12. 根据权利要求1所述的驱动电路，其中，所述导通和截止切换状态包括导通状态和截止状态，所述导通和截止切换状态中所述导通状态对应的时长小于所述截止状态对应的时长。
  13. 一种如权利要求1所述驱动电路的驱动方法，其中，所述方法包括如下步骤：
    在前一帧，所述第一开关处于所述第一状态，所述第二开关处于所述第二状态；
    在当前帧，所述第一开关处于所述第二状态，所述第一开关处于所述第一状态。
  14. 一种显示装置，其中，所述显示装置包括驱动电路，所述驱动电路包括：
    发光二极管；
    驱动晶体管，所述驱动晶体管与所述发光二极管电性连接，用于向所述发光二极管提供驱动电流；
    第一开关，所述第一开关与所述驱动晶体管的栅极连接，在前一帧处于第一状态，且在当前帧处于第二状态；以及
    第二开关，所述第一开关连接于所述驱动晶体管的栅极和所述第二开关之间，在所述前一帧处于所述第二状态，且在所述当前帧处于所述第一状态；
    所述第一状态为导通和截止切换状态、持续导通状态中的一者，所述第二状态为导通和截止切换状态、持续导通状态中的另一者。
  15. 根据权利要求14所述的显示装置，其中，所述第一开关和所述第二开关均包括具有金属氧化物有源层的晶体管。
  16. 根据权利要求14所述的显示装置，其中，所述第二开关连接于数据线和所述第一开关之间。
  17. 根据权利要求14所述的显示装置，其中，所述驱动电路还包括：
    第一写入开关，所述第一写入开关连接所述驱动晶体管的源极或漏极中的一者，在所述前一帧处于所述第一状态，且在所述当前帧处于所述第二状态；以及
    第二写入开关，所述第二写入开关连接于所述第一写入开关和数据线之间，所述第一写入开关连接于所述第二写入开关和所述驱动晶体管的源极或漏极中的一者之间，在所述前一帧处于所述第二状态，且在所述当前帧处于所述第一状态。
  18. 根据权利要求17所述的显示装置，其中，所述第一写入开关和所述第二写入开关均包括具有金属氧化物有源层的晶体管。
  19. 根据权利要求17所述的显示装置，其中，所述第二开关连接于所述第一开关和所述驱动晶体管的源极和漏极中的另一者之间。
  20. 根据权利要求14所述的显示装置，其中，所述导通和截止切换状态包括导通状态和截止状态，所述导通和截止切换状态中所述导通状态对应的时长小于所述截止状态对应的时长。
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