WO2022039062A1 - Procédé de fabrication de carte de circuit imprimé - Google Patents

Procédé de fabrication de carte de circuit imprimé Download PDF

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Publication number
WO2022039062A1
WO2022039062A1 PCT/JP2021/029460 JP2021029460W WO2022039062A1 WO 2022039062 A1 WO2022039062 A1 WO 2022039062A1 JP 2021029460 W JP2021029460 W JP 2021029460W WO 2022039062 A1 WO2022039062 A1 WO 2022039062A1
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Prior art keywords
copper plating
layer
electrolytic copper
via hole
plating layer
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PCT/JP2021/029460
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English (en)
Japanese (ja)
Inventor
公幸 野原
利徳 佐藤
慎也 喜多村
洋一 中島
豪志 信國
Original Assignee
Ｍｇｃエレクトロテクノ株式会社
米沢ダイヤエレクトロニクス株式会社
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Application filed by Ｍｇｃエレクトロテクノ株式会社, 米沢ダイヤエレクトロニクス株式会社 filed Critical Ｍｇｃエレクトロテクノ株式会社
Priority to CN202180056317.5A priority Critical patent/CN116076159A/zh
Priority to KR1020237005193A priority patent/KR20230050343A/ko
Priority to JP2022543890A priority patent/JPWO2022039062A1/ja
Publication of WO2022039062A1 publication Critical patent/WO2022039062A1/fr

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/422—Plated through-holes or plated via connections characterised by electroless plating method; pretreatment therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards

Definitions

  • the present invention relates to a method for manufacturing a printed wiring board that forms a via hole by a laser.
  • Printed wiring boards are being miniaturized by using a CO 2 laser, for example, in the formation of via holes in the build-up method.
  • Examples of the method for forming a via hole using a CO 2 laser include the following methods. First, an insulating layer and a conductive layer are formed in this order on an inner layer substrate on which an inner layer circuit is formed, a dry film is laminated on the surface of the conductive layer, and then the dry film is exposed and developed to form a hole for forming a via hole. To form.
  • the conductive layer is etched using a dry film as an etching resist to form holes for forming via holes in the conductive layer, and then the conductive layer is used as a mask for laser to form via holes in the insulating layer with a CO 2 laser.
  • Patent Document 1 In the method described in Patent Document 1, first, a conductor pattern is formed on an insulating substrate, an insulating resin layer is formed on the conductor pattern, the surface of the insulating resin layer is roughened, and the surface of the insulating resin layer is electroless. Form a copper plating film. Next, a photosensitive resin layer is formed on the electroless copper plating film, and the photosensitive resin layer is exposed and developed to form a plating resist for forming a via hole, leaving a portion for forming a via hole.
  • an electrolytic copper plating film having holes for forming via holes is formed on the electrolytic copper plating film, and after removing the plating resist, the electrolytic copper plating film is used as an etching resist for etching. A hole for forming a via hole is formed in the electroless copper plating film.
  • a via hole is formed in the insulating resin layer with a CO 2 laser.
  • an electrolytic copper plating film that serves as a mask for a laser is formed by using a plating resist for forming a via hole, so that there is a problem of overetching unlike the case where a hole for forming a via hole is formed by etching. It is possible to reduce the diameter of the via hole.
  • the present invention has been made based on such a problem, and provides a method for manufacturing a printed wiring board capable of reducing the hole diameter of a via hole and improving the formability of a conductor pattern. With the goal.
  • the present inventors formed a multilayer plate by laminating an insulating layer and an electrolytic copper foil in this order on an inner layer substrate on which an inner layer circuit was formed, and then removed the electrolytic copper foil from the multilayer plate.
  • the present invention is as follows. [1] A process of laminating an insulating layer and an electrolytic copper foil in this order on an inner layer substrate on which an inner layer circuit is formed to form a multilayer board. A step of removing the electrolytic copper foil from the multilayer plate to expose the insulating layer, After exposing the insulating layer, a step of providing an electroless copper plating layer on the surface of the insulating layer, and A step of providing a resist layer on the electroless copper plating layer and performing exposure and development to form a resist pattern in which a portion forming a via hole is left.
  • a method for manufacturing a printed wiring board which comprises a step of forming a via hole by removing a portion of the insulating layer not covered with the mask by a laser after forming the mask.
  • the method for manufacturing a printed wiring board according to [1] wherein the average value of the top diameter of the via hole is 25 ⁇ m or less.
  • the method for manufacturing a printed wiring board according to [1] which comprises a step of removing scum after forming the resist pattern and before providing the electrolytic copper plating layer.
  • the insulating layer and the electrolytic copper foil are laminated in this order on the inner layer substrate on which the inner layer circuit is formed to form a multilayer board, and then the electrolytic copper foil is removed from the multilayer board.
  • the surface shape of the electrolytic copper foil can be transferred to the surface of the insulating layer, and the variation in the surface roughness of the insulating layer can be reduced.
  • an electroless plating layer is provided on the surface of the insulating layer, a resist pattern is formed on which a portion forming a via hole is left, and then an electrolytic plating layer is provided, and this electrolytic plating layer is used as an etching resist for electroless plating. Since the layer is etched to form a mask for forming a via hole, the problem of over-etching can be avoided. Therefore, the diameter of the via hole can be reduced, and the formability of the conductor pattern can be improved.
  • the present embodiment will be described in detail, but the present invention is not limited thereto, and various modifications are made without departing from the gist thereof. Is possible.
  • the inner layer circuit 12 is formed on the insulating substrate 11 to form the inner layer substrate 13 (inner layer substrate forming step).
  • the inner layer substrate 13 can be manufactured by a conventionally known method. To explain the manufacturing process of the inner layer substrate 13 by giving an example, for example, first, a through hole (not shown) is formed in an insulating substrate 11 made of a resin substrate such as a glass epoxy type or a polyimide type, and the upper and lower parts of the insulating substrate 11 are formed.
  • Electrolytic copper plating is performed on both sides and the inner peripheral surface of the through hole using electroless copper plating as a base.
  • a resist pattern is formed on the surface, a conductor pattern 12a and a through-hole conductor (not shown) are formed as an inner layer circuit 12 by etching, and the hollow portion of the through-hole conductor is filled with a hole-filling resin such as epoxy to make it flat. To become.
  • the insulating layer 14 and the electrolytic copper foil 15 are laminated in this order on the inner layer substrate 13 to form the multilayer plate 16 (multilayer plate forming step).
  • an insulating prepreg or a resin sheet is laminated as an insulating layer 14 on an inner layer substrate 13, and an electrolytic copper foil 15 is laminated on the insulating prepreg or a resin sheet and pressure-bonded.
  • the prepreg include a semi-cured state in which a fibrous reinforcing material such as glass cloth or carbon fiber is impregnated with a thermosetting resin mixed with additives such as a curing agent and a coloring material.
  • the resin sheet examples include those obtained by semi-curing a thermosetting resin mixed with additives such as a curing agent and a coloring material.
  • the thermosetting resin used for the prepreg or the resin sheet include a polyimide resin, a liquid crystal polyester, an epoxy compound, a cyanate ester compound, a maleimide compound, a phenol compound, a polyphenylene ether compound, a benzoxazine compound, an organic group-modified silicone compound and polymerization. Examples include compounds having possible unsaturated groups.
  • the multilayer plate 16 for example, a copper foil with a resin layer having an insulating resin layer formed on the electrolytic copper foil 15 is used, the resin layer is used as the insulating layer 14, and the resin layer is brought into contact with the inner layer substrate 13. It may be formed by laminating and crimping. Examples of the material constituting the resin layer include the same materials as the above-mentioned prepreg or resin sheet.
  • the multilayer board 16 is formed by, for example, applying a liquid resin such as an insulating epoxy on the inner layer substrate 13 with a spin coater or the like and then heat-curing to form an insulating layer 14, and an electrolytic copper foil 15 is formed on the insulating layer 14. May be laminated and crimped.
  • the thickness of the insulating layer 14 is preferably, for example, 5 ⁇ m to 40 ⁇ m.
  • the thickness of the electrolytic copper foil 15 is preferably, for example, 1 ⁇ m to 20 ⁇ m.
  • crimping for example, a prepreg or a resin sheet is placed above and below (front and back) of the inner layer substrate, and laminated molding is performed at a pressure of 3.0 MPa and a temperature of 220 ° C. for 60 minutes. As a result, the surface shape of the electrolytic copper foil 15 is transferred to the surface of the insulating layer 14.
  • the surface roughness Ra of the electrolytic copper foil 15 on the insulating layer 14 side is preferably 0.01 ⁇ m to 2.0 ⁇ m, and the maximum height roughness Rz of the electrolytic copper foil 15 on the insulating layer 14 side is 0.5 ⁇ m. It is preferably 10.0 ⁇ m.
  • the electrolytic copper foil 15 is completely removed from the multilayer plate 16 by etching or the like, and the insulating layer 14 is exposed on the entire surface (electrolytic copper foil removing step).
  • the aqueous solution used as the etching solution is not particularly limited, and examples thereof include those using hydrochloric acid and cupric chloride aqueous solution, and those using sulfuric acid and hydrogen peroxide aqueous solution.
  • an electroless copper plating layer 17 having a thickness of, for example, 0.4 ⁇ m to 2 ⁇ m is formed on the surface of the insulating layer 14 by electroless copper plating (electroless copper plating step).
  • electroless copper plating for example, an alkaline bath using formaldehyde as a reducing agent is used.
  • a dry film is heat-bonded onto the electrolytic copper plating layer 17 to provide a resist layer so that only the portion of the via hole 21 formed in the subsequent step remains. Is exposed and developed to form a resist pattern 18 in which a portion forming a via hole 21 is left (resist pattern forming step).
  • the laminating of the resist layer is 50 ° C. to 140 ° C.
  • the crimping pressure is 1 kgf / cm 2 to 15 kgf / cm 2
  • the crimping time is 5 seconds to 300 seconds.
  • a predetermined portion of the resist layer is irradiated with active energy rays to perform exposure to cure the resist layer in the irradiated portion.
  • Irradiation of the active energy rays may be performed through a mask pattern, or a direct drawing method of directly irradiating the active energy rays may be used.
  • the active energy ray include ultraviolet rays, visible rays, electron beams, and X-rays, and ultraviolet rays are particularly desirable.
  • the irradiation amount of ultraviolet rays is approximately 10 mJ / cm 2 to 1000 mJ / cm 2 .
  • the development after exposure is not particularly limited as long as it elutes the unexposed portion in a limited manner, but a developing solution such as an alkaline aqueous solution, an aqueous developer, or an organic solvent is used.
  • a developing method for example, a known method such as spraying, rocking dipping, brushing, scraping or the like can be used.
  • the thickness of the resist pattern 18 (that is, the thickness of the resist layer) is thicker than the thickness of the electrolytic plating layer 19 formed in the subsequent step, and is preferably 5 ⁇ m to 20 ⁇ m, for example.
  • scum resist residue
  • plasma cleaning or the like scum removing step
  • the resist pattern 18 is used as a plating resist, and the surface of the electroless copper plating layer 17 is subjected to electrolytic copper plating, for example, electrolytic copper plating having a thickness of 1 ⁇ m to 10 ⁇ m.
  • the layer 19 is formed (electrolytic copper plating step). Specifically, for example, the plating treatment is performed at a bath temperature of 22 ° C. and a current density of 1.0 A / dm 2 .
  • the plating solution composition is, for example, a mixed solution of copper sulfate (for example, 120 g / L), sulfuric acid (for example, 80 g / L) and chloride ion (for example, 50 mg / L), and an appropriate amount of additives is added.
  • the additive include a method using a polyether compound (polymer), an organic sulfur compound (Brightener) and a quaternized amine compound (leveler).
  • the resist pattern is removed using a resist stripping solution or the like (resist pattern removing step).
  • the electrolytic copper plating layer 19 is used as an etching resist, and the electrolytic copper plating layer 17 is etched by flash etching or the like to etch the electrolytic copper plating layer 17.
  • a mask 20 for forming a via hole composed of the 17 and the electrolytic copper plating layer 19 is formed (mask forming step).
  • a specific etching method for example, a known method such as spraying, rocking dipping, or the like can be used.
  • the liquid composition include a method using an aqueous solution of sulfuric acid and hydrogen peroxide.
  • a portion of the insulating layer 14 that is not covered with the mask 20 is subjected to a CO 2 laser or the like.
  • the via hole 21 is formed by removing it with the laser of the above (via hole forming step).
  • the conditions of the CO 2 laser used are narrowed down to a beam diameter of 1 ⁇ m to 50 ⁇ m.
  • the laser processing of the via hole 21 is performed until the conductor pattern 12a under the insulating layer 14 is exposed. Thereby, the hole diameter of the via hole 21 can be reduced, and for example, the top diameter of the formed via hole 21 can be set to 25 ⁇ m or less on average.
  • the top diameter of the via hole 21 is the hole diameter on the surface side when the via hole 21 is formed.
  • the via conductor 22 is formed in the via hole 21, and the conductor pattern 23 is formed on the insulating layer 14 (via conductor / conductor pattern forming step). Specifically, for example, the via conductor 22 and the conductor pattern 23 are formed by electroless copper plating and via-filling copper plating on the mask 20 and the via hole 21 composed of the electrolytic copper plating layer and the electrolytic copper plating layer.
  • the insulating layer 14 and the electrolytic copper foil 15 are laminated in this order on the inner layer substrate 13 on which the inner layer circuit 12 is formed to form the multilayer plate 16, and then the multilayer plate 16 is formed. Since the electrolytic copper foil 15 is removed from the surface, the surface shape of the electrolytic copper foil 15 can be transferred to the surface of the insulating layer 14, and the variation in the surface roughness of the insulating layer 14 can be reduced. Further, an electrolytic plating layer 17 is provided on the surface of the insulating layer 14, a resist pattern 18 is formed on the resist pattern 18 in which a portion forming a via hole 21 is left, and then an electrolytic plating layer 19 is provided, and the electrolytic plating layer 19 is provided.
  • the electroless plating layer 17 is etched as an etching resist to form a mask 20 for forming a via hole, the problem of overetching can be avoided. Therefore, the diameter of the via hole 21 can be reduced, and the formability of the conductor pattern 23 can be improved.
  • Example 1 A printed wiring board was produced as follows (see FIGS. 1 to 3).
  • the inner layer circuit 12 was formed on both sides of a glass cloth base material BT resin copper-clad laminate (conductor thickness 12 ⁇ m, thickness 0.1 mm, CCL-HL832NS manufactured by Mitsubishi Gas Chemical Company, Inc.) by a subtractive method.
  • BT resin copper-clad laminate conductor thickness 12 ⁇ m, thickness 0.1 mm, CCL-HL832NS manufactured by Mitsubishi Gas Chemical Company, Inc.
  • a chemical solution of MEC Co., Ltd. was used to roughen the copper surface of the inner layer substrate 13.
  • the inner layer substrate 13 was washed with CA5330, the copper surface was roughened with CZ8101 after washing with water, and after washing with water, rust was prevented with CL8300 and dried with water.
  • the etching amount of CZ8101 was 1 ⁇ m.
  • a horizontal line spray device was used to roughen the copper surface.
  • the mask 20 for forming the via hole is formed by using the SAP (Semi Adaptive Process) method. Therefore, first, the electrolytic copper foil 15 on the surface layer of the multilayer plate 16 was removed by etching with hydrochloric acid and a cupric chloride aqueous solution at a liquid temperature of 48 ° C., and then washed and dried with water.
  • the device used was a horizontal line spray type (manufactured by Tokyo Kakoki Co., Ltd.).
  • FIG. 1 (E) A dry film resist was laminated on the electroless copper plating layer 17, and exposed and developed to form a resist pattern 18.
  • the dry film resist used was RD-1207 of Hitachi Kasei Kogyo Co., Ltd. with a thickness of 7 ⁇ m, and the laminator used was an ONC device.
  • the laminating pressure was 0.4 MPa and the laminating temperature was 110 ° C.
  • a potassium carbonate aqueous solution was used for development after exposure.
  • the equipment of Tokyo Kakoki Co., Ltd. was used at a liquid temperature of 30 ° C.
  • the copper plating bath temperature was 22 ° C., and Okuno Pharmaceutical Industry's Top Lucina SF was used as an additive for levelers, brioners, and polymers.
  • As the copper plating bath a mixed solution of copper sulfate, sulfuric acid and hydrochloric acid was used.
  • the multilayer plate 16 was racked on the plating jig, and the swelling tank, the etching tank, and the neutralization tank were immersed and rocked to remove smears.
  • the equipment of Almex PE Co., Ltd. was used for the immersion swing.
  • the chemical solution used was an up-death process manufactured by C. Uyemura & Co., Ltd. Updes MDS-37 was used as the swelling solution, Updes MDE-40 and ELC-SH mixed solution was used as the etching solution, and Updes MDN-62 was used for neutralization.
  • the temperature of the etching tank was 80 ° C., and the etching tank was immersed for 10 minutes.
  • the copper plating bath temperature was 22 ° C.
  • CU-BRITE TH4 a filling liquid for through holes manufactured by Roam & Haas Electronic Materials Co., Ltd., was used as an additive for a leveler, a brioner, and a polymer.
  • As the copper plating bath a mixed solution of copper sulfate, sulfuric acid and hydrochloric acid was used.
  • Comparative Example 1 A printed wiring board was produced as follows. 4 and 5 show each step of the method for manufacturing a printed wiring board according to Comparative Example 1.
  • the inner layer circuit 112 was formed on both sides of a glass cloth base material BT resin copper-clad laminate (copper body thickness 12 ⁇ m, thickness 0.1 mm, CCL-HL832NS manufactured by Mitsubishi Gas Chemical Company, Inc.) by a subtractive method.
  • BT resin copper-clad laminate copper body thickness 12 ⁇ m, thickness 0.1 mm, CCL-HL832NS manufactured by Mitsubishi Gas Chemical Company, Inc.
  • a chemical solution of MEC Co., Ltd. was used to roughen the copper surface of the inner layer substrate 113.
  • the copper surface was roughened with CZ8101 and the etching amount was set to 1 ⁇ m.
  • a horizontal line spray device was used to roughen the copper surface.
  • the mask 120 for forming the via hole is formed by using the subtractive method.
  • a resist layer was formed on the upper and lower sides (front and back) of the multilayer plate 116 with a dry film resist, and exposed and developed to form a resist pattern 118.
  • the dry film resist used was RD-1215 manufactured by Hitachi Chemical Industries, Ltd. with a thickness of 15 ⁇ m, and the laminator used was an ONC device.
  • the laminating pressure was 0.4 MPa and the laminating temperature was 110 ° C.
  • the exposure used INPREX3650 of Adtech Engineering Co., Ltd. A potassium carbonate aqueous solution was used for development after exposure.
  • the ultrathin copper foil 115 was etched to form the mask 120, and the resist pattern 118 was removed. Etching was performed with hydrochloric acid and an aqueous solution of cupric chloride. R-100S of Mitsubishi Gas Chemical Company, Inc. was used for peeling the resist pattern 118. A spray-type device manufactured by Tokyo Kakoki Co., Ltd. was used for the processes from development to etching and peeling.
  • CU-BRITE TH4 a filling liquid for through holes manufactured by Roam & Haas Electronic Materials Co., Ltd., was used as an additive for levelers, brighteners, and polymers.
  • As the copper plating bath a mixed solution of copper sulfate, sulfuric acid and hydrochloric acid was used.
  • Comparative Example 2 A printed wiring board was produced as follows. In Comparative Example 2, the same reference numerals are used for the components corresponding to those of the first embodiment (the present embodiment).
  • the inner layer substrate 13 is manufactured and the copper surface of the inner layer substrate 13 is roughened, and then Ajinomoto Co., Inc. resin is used as an insulating layer 14 on the upper and lower sides (front and back) of the inner layer substrate 13.
  • a sheet (GX92) was placed.
  • the inner layer substrate 13 on which the insulating layer 14 is arranged is laminated with a vacuum laminator of Nikko Material Co., Ltd. under the conditions of a temperature of 100 ° C. and a laminating pressure of about 7 kgf, dried at 150 ° C. for 30 minutes, and then attached to the inner layer substrate 13.
  • the insulating layer 14 was laminated to form a multilayer board.
  • the mask 20 for forming the via hole is formed by using the SAP method.
  • the multilayer plate was racked on the Desmia jig, and the immersion and rocking were performed in the expansion tank, the etching tank, and the neutralization tank.
  • An apparatus of Almex PE Co., Ltd. for immersion rocking was used.
  • the chemical solution used was an up-death process manufactured by C. Uyemura & Co., Ltd.
  • the desmear temperature conditions were swelling 70 ° C., etching 80 ° C., and neutralization 40 ° C..
  • the desmear treatment at this time was performed not for the purpose of removing smear in the laser hole, but for the purpose of improving the adhesion of the electroless copper plating by roughening the surface of the resin sheet surface and increasing the peel strength.
  • the multilayer plate was racked on the plating jig and immersed and rocked in the electroless copper plating tank to form the electroless copper plating layer 17.
  • an apparatus of Almex PE Co., Ltd. was used for immersion rocking.
  • the chemical solution used was a mixture of Sulcup PEA manufactured by C. Uyemura & Co., Ltd. and formaldehyde.
  • the liquid temperature of the electroless copper plating was set to 36 ° C., and the immersion was shaken for 20 minutes.
  • a dry film resist was laminated on the electroless copper plating layer 17, and exposed and developed to form a resist pattern 18.
  • the dry film resist used was RD-1215 manufactured by Hitachi Chemical Industries, Ltd. with a thickness of 15 ⁇ m, and the laminator used was an ONC device.
  • the laminating pressure was 0.4 MPa and the laminating temperature was 110 ° C.
  • the multilayer plate was racked on the plating jig, and the swelling tank, the etching tank, and the neutralization tank were immersed and rocked to remove smears.
  • An apparatus of Almex PE Co., Ltd. for immersion rocking was used.
  • the chemical solution used was an up-death process manufactured by C. Uyemura & Co., Ltd. Updes MDS-37 was used as the swelling solution, Updes MDE-40 and ELC-SH mixed solution was used as the etching solution, and Updes MDN-62 was used for neutralization.
  • the temperature of the etching tank was 80 ° C., and the etching tank was immersed for 10 minutes.
  • the copper plating bath temperature was 22 ° C.
  • CU-BRITE TH4 a filling liquid for through holes manufactured by Roam & Haas Electronic Materials Co., Ltd., was used as an additive for a leveler, a brioner, and a polymer.
  • As the copper plating bath a mixed solution of copper sulfate, sulfuric acid and hydrochloric acid was used.
  • Example 1 (Characteristic evaluation) The characteristics of Example 1 and Comparative Examples 1 and 2 were measured by the following methods.
  • Example 1 As Example 1, after preparing the inner layer substrate 13, roughening the copper surface of the inner layer substrate 13, laminating treatment for forming the multilayer plate 16, total etching of the surface layer copper, and forming the electroless copper plating layer 17. An electrolytic copper plating layer 19 was formed on the electrolytic copper plating layer 17, and a test piece was obtained. Further, as Comparative Example 1, a test piece was obtained by manufacturing the inner layer substrate 113, roughening the copper surface of the inner layer substrate 113, and laminating for forming the multilayer plate 116.
  • Comparative Example 2 after the inner layer substrate 13 is manufactured, the copper surface of the inner layer substrate 13 is roughened, the insulating layer 14 is laminated and molded, the insulating layer 14 is roughened, and the electrolytic-free copper plating layer 17 is formed. An electrolytic copper plating layer 19 was formed on the electrolytic copper plating layer 17, and a test piece was obtained. Twenty test pieces were prepared for each of Example 1 and Comparative Examples 1 and 2. The peel strength was measured for each test piece, and the average value of the peel strength and the variation in the peel strength were obtained. For the peel strength, the lower layer of the test piece was fixed to a plate or the like, the end of the plating layer was pulled perpendicular to the direction of the fixed plate, and the load value required for peeling was measured. The results obtained are shown in Table 1.
  • Example 1 [Evaluation of surface roughness]
  • the insulating layer 14 and the electrolytic copper foil 15 were laminated on the inner layer substrate 13 to form a multilayer plate 16, and then the electrolytic copper foil 15 was removed, and the surface roughness of the insulating layer 14 was measured.
  • the insulating layer 114 and the electrolytic copper foil 115 were laminated on the inner layer substrate 113 to form a multilayer plate 116, and then the electrolytic copper foil 115 was removed, and the surface roughness of the insulating layer 114 was measured.
  • the insulating layer 14 was laminated on the inner layer substrate 13 and subjected to desmear treatment, and then the surface roughness of the insulating layer 14 was measured. The surface roughness was measured by using a laser microscope Co., Ltd. KEYENCE VK-X1000 and adjusting the magnification to 150 times. As surface roughness parameters, Ra value and Rz value were measured at 10 points each.
  • the SAP method of Example 1 was able to process a smaller diameter than the subtractive method of Comparative Example 1, and the degree of variation was small. Further, in the evaluation of the peel strength, the SAP method of Example 1 had a smaller variation in the peel strength than the SAP method with desmear of Comparative Example 2. Further, in the evaluation of the surface roughness, the SAP method of Example 1 has a large variation in the surface roughness Ra and the value and the variation of the surface roughness Rz are larger than those of the SAP method with desmear in Comparative Example 2. rice field. That is, according to this embodiment, it was found that the hole diameter of the via hole can be reduced and the formability of the conductor pattern can be improved.
  • the hole diameter of the via hole can be reduced and the formability of the conductor pattern can be improved. It can be effectively used as a manufacturing method for printed wiring boards that support high integration and high density of communication equipment.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

Le problème décrit par la présente invention est de fournir un procédé de fabrication d'une carte de circuit imprimé, grâce auquel le diamètre de trou d'un trou d'interconnexion peut être réduit et l'aptitude au formage d'un motif conducteur peut être améliorée. La solution selon l'invention porte sur une couche d'isolation 14 et sur une feuille de cuivre électrolytique 15 qui sont stratifiées dans cet ordre sur un substrat de couche interne 13, après quoi la feuille de cuivre électrolytique 15 est retirée. Ensuite, une couche de placage de cuivre autocatalytique 17 est disposée sur la surface de la couche d'isolation 14, et un motif de réserve 18 est formé sur celle-ci, le motif de réserve 18 laissant une partie où un trou d'interconnexion est formé. Ensuite, le motif de réserve 18 est utilisé en tant que réserve de placage, une couche de cuivrage électrolytique est disposée sur la surface de la couche de cuivrage autocatalytique 17, et le motif de réserve 18 est retiré, après quoi la couche de placage de cuivre autocatalytique 17 est gravée à l'aide de la couche de placage de cuivre électrolytique en tant que réserve de gravure, et un masque pour une formation de trou d'interconnexion est formé. Une fois que le masque est formé, une partie de la couche d'isolation 14, non recouverte par le masque, est retirée à l'aide d'un laser, et le trou d'interconnexion est formé.
PCT/JP2021/029460 2020-08-15 2021-08-07 Procédé de fabrication de carte de circuit imprimé WO2022039062A1 (fr)

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CN202180056317.5A CN116076159A (zh) 2020-08-15 2021-08-07 印刷电路板的制造方法
KR1020237005193A KR20230050343A (ko) 2020-08-15 2021-08-07 프린트 배선판의 제조방법
JP2022543890A JPWO2022039062A1 (fr) 2020-08-15 2021-08-07

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220375787A1 (en) * 2021-05-18 2022-11-24 Applied Materials, Inc. Methods of micro-via formation for advanced packaging
WO2024029431A1 (fr) * 2022-08-04 2024-02-08 三菱瓦斯化学株式会社 Procédé de production de carte de circuit imprimé

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1154920A (ja) * 1997-08-05 1999-02-26 Ibiden Co Ltd プリント配線板の製造方法
JP2000059033A (ja) * 1998-08-04 2000-02-25 Sumitomo Kinzoku Electro Device:Kk 多層回路基板及びその製造方法
JP2006179822A (ja) * 2004-12-24 2006-07-06 Cmk Corp プリント配線板とその製造方法
JP2009283668A (ja) * 2008-05-22 2009-12-03 Sharp Corp プリント配線板の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1154920A (ja) * 1997-08-05 1999-02-26 Ibiden Co Ltd プリント配線板の製造方法
JP2000059033A (ja) * 1998-08-04 2000-02-25 Sumitomo Kinzoku Electro Device:Kk 多層回路基板及びその製造方法
JP2006179822A (ja) * 2004-12-24 2006-07-06 Cmk Corp プリント配線板とその製造方法
JP2009283668A (ja) * 2008-05-22 2009-12-03 Sharp Corp プリント配線板の製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220375787A1 (en) * 2021-05-18 2022-11-24 Applied Materials, Inc. Methods of micro-via formation for advanced packaging
US11705365B2 (en) * 2021-05-18 2023-07-18 Applied Materials, Inc. Methods of micro-via formation for advanced packaging
WO2024029431A1 (fr) * 2022-08-04 2024-02-08 三菱瓦斯化学株式会社 Procédé de production de carte de circuit imprimé

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JPWO2022039062A1 (fr) 2022-02-24
TW202211739A (zh) 2022-03-16
CN116076159A (zh) 2023-05-05

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