WO2022028122A1 - 电容器的制作方法及电容器阵列结构、半导体存储器 - Google Patents

电容器的制作方法及电容器阵列结构、半导体存储器 Download PDF

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Publication number
WO2022028122A1
WO2022028122A1 PCT/CN2021/100735 CN2021100735W WO2022028122A1 WO 2022028122 A1 WO2022028122 A1 WO 2022028122A1 CN 2021100735 W CN2021100735 W CN 2021100735W WO 2022028122 A1 WO2022028122 A1 WO 2022028122A1
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layer
isolation
substrate
capacitor
etched
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PCT/CN2021/100735
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English (en)
French (fr)
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占康澍
夏军
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长鑫存储技术有限公司
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Priority to US17/594,922 priority Critical patent/US11889676B2/en
Publication of WO2022028122A1 publication Critical patent/WO2022028122A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor

Definitions

  • the present disclosure relates to, but is not limited to, a manufacturing method of a capacitor, a capacitor array structure, and a semiconductor memory.
  • DRAM Dynamic Random Access Memory
  • the gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor; the voltage signal on the word line can control the opening or closing of the transistor, and then read the data information stored in the capacitor through the bit line, Or write data information into the capacitor through the bit line for storage.
  • the integration of DRAM continues to increase, and the lateral dimensions of components continue to shrink, making capacitors with higher aspect ratios and more difficult manufacturing processes.
  • the chips in the edge region of the wafer are invalid chips, and the pattern in the edge region of the wafer will have the risk of collapse and peeling during the etching process, thereby destroying the integrity of the capacitor in the central region of the wafer.
  • the wafer contamination and the contamination of the process chamber of the wafer are caused, which reduces the yield rate and production efficiency of the chip.
  • Embodiments of the present disclosure provide a method for fabricating a capacitor, a capacitor array structure, and a semiconductor memory, so as to solve the problem that the wafer edge is prone to collapse and peeling during the capacitor etching process.
  • a method for manufacturing a container including:
  • a wafer is provided, the wafer includes a plurality of chips distributed in an array, and the chips have a same substrate; a substrate to be etched is formed on the substrate; the substrate to be etched includes at least one sacrificial layer and at least one supporting layer; the sacrificial layer and the supporting layer are alternately arranged, and the side of the substrate to be etched away from the substrate is the first supporting layer;
  • the wafer includes a central region and an edge region surrounding the central region;
  • a first hard mask layer with a first pattern in the central area is formed on the substrate to be etched; the first pattern includes through holes arranged in an array; and the first hard mask layer is used as a mask to etch Etching the substrate to be etched to form a capacitor hole; no capacitor hole is formed in the edge region;
  • a lower electrode layer is deposited on the bottom and sidewalls of the capacitor hole, and part of the substrate to be etched is removed layer by layer; a capacitor dielectric layer and an upper electrode layer are sequentially formed on the lower electrode layer.
  • the width of the edge region is less than or equal to 8 mm.
  • the method further includes:
  • the first support layer of the edge region chip is removed.
  • removing the first support layer of the edge region chip includes:
  • the first support layer of the chip in the edge region is exposed through a photolithography process, and the exposed first support layer is etched to form an edge region exposing the sacrificial layer.
  • exposing the first support layer of the edge region chip through a photolithography process includes:
  • the thickness of the first photoresist is 50 nm ⁇ 200 nm.
  • the substrate to be etched includes: sequentially forming a second sacrificial layer, a second supporting layer, a first sacrificial layer and a first supporting layer in a direction away from the substrate;
  • removing part of the substrate to be etched layer by layer includes:
  • the first openings are in one-to-one correspondence with the second openings.
  • forming a first hard mask layer having a first pattern in a central area on the substrate to be etched includes:
  • a second isolation layer is formed on the first isolation sidewall pattern, the second isolation layer of the chip in the central area is exposed by a photolithography process, and the second isolation layer is etched to form the second isolation layer in the second direction.
  • Two isolation sidewall patterns, the second isolation layer of the edge area chip remains;
  • the first pattern is formed where the first isolation sidewall pattern and the second isolation sidewall pattern do not overlap, and the first isolation sidewall pattern and the second isolation sidewall pattern are used as masks for etching,
  • the first pattern is transferred to a first hard mask layer to form the first hard mask layer having the first pattern in the central region.
  • the first hard mask layer includes a single-layer or multi-layer structure.
  • the first isolation sidewall patterns are formed through a patterning process.
  • forming a second isolation layer on the first isolation sidewall pattern includes:
  • a buffer layer is filled between the first isolation sidewall patterns, and a second hard mask layer is deposited on the first isolation sidewall patterns and the buffer layer; and a portion of the second hard mask layer is formed by etching a linear second hard mask pattern, depositing a second isolation layer covering the second hard mask layer and the buffer layer, the second isolation layer including a top surface, a bottom surface and sidewalls connecting the top surface and the bottom surface .
  • exposing the second isolation layer in the central region through a photolithography process, and etching the second isolation layer to form a second isolation sidewall pattern comprising: in the second isolation layer A negative second photoresist is applied on the isolation layer, and the edge region of the wafer is exposed through a blank mask, and the second photoresist in the edge region is retained after development; removed by an etching process The top surface and the bottom surface of the second isolation layer in the central region, with sidewalls remaining, form the second isolation sidewall pattern.
  • the thickness of the second photoresist is 50-200 nm.
  • a capacitor array structure fabricated by the method for fabricating a capacitor provided by any embodiment of the present disclosure.
  • a semiconductor memory including the capacitor array structure provided in any embodiment of the present disclosure; and a transistor layer, where the transistor layer includes transistors arranged in one-to-one correspondence with the capacitors.
  • a substrate to be etched is first formed to prepare a capacitor hole, the substrate to be etched includes at least one sacrificial layer and at least one supporting layer, the sacrificial layers and the supporting layers are alternately arranged, and the topmost layer is is a first support layer, the wafer includes a central area and an edge area surrounding the central area, and continues to form a first hard mask layer with a first pattern in the central area on the substrate to be etched, and the first pattern includes an array arrangement
  • the first hard mask layer is used as a mask to etch the above-mentioned substrate to be etched to form a capacitor hole, because the first hard mask layer in the wafer edge area does not form a through hole, so the edge area is not formed.
  • a capacitor hole is formed, and then a lower electrode layer is deposited on the capacitor hole, and the substrate to be etched is removed layer by layer, and a capacitor dielectric layer and an upper electrode layer are formed in sequence.
  • the film layer structure in the edge region will not form an incomplete (patterned) structure, thereby avoiding the collapse of the capacitor structure in the edge region and affecting the overall yield of the wafer due to process reasons, thereby improving the overall yield of the wafer. Capacitor production quality and production efficiency.
  • FIG. 1 is a schematic flowchart of a method for manufacturing a capacitor provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic plan view of a wafer provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of forming a substrate to be etched on a substrate according to an embodiment of the present disclosure
  • FIG. 4 is a schematic structural diagram of forming a first photoresist on a substrate to be etched according to an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of etching the first support layer in the edge region provided by an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of forming a first hard mask layer on a substrate to be etched according to an embodiment of the present disclosure
  • FIG. 7 is a top view of the first hard mask layer in FIG. 6;
  • FIG. 8 is a schematic structural diagram of forming a capacitor hole on a substrate to be etched according to an embodiment of the present disclosure
  • FIG. 9 is a schematic structural diagram of depositing a lower electrode on a capacitor hole provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of forming a first opening on the first support layer according to an embodiment of the present disclosure
  • FIG. 11 is a schematic structural diagram of a comparative example of depositing a lower electrode on a capacitor hole provided by an embodiment of the present disclosure
  • FIG. 12 is a schematic flowchart of another method for manufacturing a capacitor provided by an embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of forming a first opening on a first support layer provided by an embodiment of the present disclosure
  • FIG. 14 is a schematic structural diagram of a comparative example of forming a first opening on a first support layer provided by an embodiment of the present disclosure
  • 15 is a schematic structural diagram of removing the first sacrificial layer based on the first opening provided by an embodiment of the present disclosure
  • 16 is a schematic structural diagram of forming a second opening in the second support layer according to an embodiment of the present disclosure
  • 17 is a schematic structural diagram of removing the second sacrificial layer based on the second opening provided by an embodiment of the present disclosure
  • FIG. 18 is a schematic flowchart of another method for manufacturing a capacitor provided by an embodiment of the present disclosure.
  • FIG. 19 is a schematic structural diagram of forming a first isolation sidewall pattern on a first hard mask layer provided by an embodiment of the present disclosure
  • 20 is a schematic structural diagram of forming a second isolation sidewall pattern on a second mask layer provided by an embodiment of the present disclosure
  • 21 is a top view of a first isolation sidewall pattern provided by an embodiment of the present disclosure.
  • FIG. 22 is a top view of a second isolation sidewall pattern provided by an embodiment of the present disclosure.
  • FIG. 23 is a top view of a first hard mask layer and a second mask layer provided by an embodiment of the present disclosure
  • FIG. 24 is a schematic flowchart of another method for manufacturing a capacitor provided by an embodiment of the present disclosure.
  • 25 is a schematic structural diagram of filling a buffer layer between the first isolation sidewall patterns according to an embodiment of the present disclosure
  • 26 is a schematic structural diagram of forming a second isolation layer provided by an embodiment of the present disclosure.
  • 27 is a schematic structural diagram of coating a negative second photoresist on the second isolation layer provided by an embodiment of the present disclosure
  • FIG. 28 is a schematic structural diagram of forming a second isolation sidewall pattern provided by an embodiment of the present disclosure.
  • 29 is a schematic structural diagram of a capacitor array structure provided by an embodiment of the present disclosure.
  • FIG. 30 is a schematic structural diagram of a semiconductor memory provided by an embodiment of the present disclosure.
  • FIG. 1 is a schematic flowchart of a method for manufacturing a capacitor provided by an embodiment of the present disclosure. As shown in FIG. 1 , the method in this embodiment includes the following steps:
  • the wafer 1 includes a plurality of chips distributed in an array, and the chips have a same substrate 10; a substrate 11 to be etched is formed on the substrate 10; the substrate 11 to be etched includes at least one sacrificial layer 112 and at least one supporting layer 111; the sacrificial layer 112 and the supporting layer 111 are alternately arranged, and the side of the substrate 11 to be etched away from the substrate 10 is the first supporting layer 111a.
  • a wafer 1 is provided, and the wafer 1 may be undoped single crystal silicon or single crystal doped with impurities Silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI) wafers, etc.
  • SOI silicon-on-insulator
  • SSOI silicon-on-insulator
  • SiGeOI silicon-germanium-on-insulator
  • SiGeOI silicon-germanium-on-insulator
  • GeOI germanium-on-insulator
  • the wafer 1 is composed of a plurality of chips D1 (die) distributed in an array, and each of the chips D1 includes an array area of a storage area (for arranging a capacitor structure) and a peripheral area of a circuit control area.
  • the capacitance of the array area in the edge area S1 of the wafer 1 is easily collapsed and peeled off, thereby affecting the die yield of the central area S2.
  • the present disclosure solves the problem of the edge area S1 capacitor column by avoiding the formation of a capacitor structure in the edge area S1. Collapse problem, thereby improving wafer yield.
  • the chip substrates 10 are all formed by the same process, that is, the plurality of chips all have the same substrate 10 , and in the embodiments of the present disclosure, we can describe a single chip or two chips among them. As shown in FIG. 3 , FIG.
  • FIG. 3 is a schematic structural diagram of forming a substrate to be etched 11 on a substrate 10 according to an embodiment of the present disclosure, wherein A2 is an array area, A1 is a peripheral area, and the substrate 10 includes capacitive contacts (not shown), when the capacitor is formed, a base to be etched 11 is formed on the substrate 10, the base to be etched 11 includes at least one sacrificial layer 112 and at least one supporting layer 111, and the sacrificial layer 112 and the supporting layer 111 are alternately arranged, and the side of the substrate 11 to be etched away from the wafer 1 is the first supporting layer 111a, that is, the top layer of the substrate 11 to be etched is the first supporting layer 111a.
  • the above-mentioned setting of the substrate 11 to be etched is used for the etching of the capacitor hole 11a in the subsequent capacitor fabrication process.
  • two layers of support layers 111 and two layers of sacrificial layers 112 may be provided.
  • the number of the above-mentioned support layers 111 and sacrificial layers 112 The number of layers of the layer 111 and the sacrificial layer 112 may be multiple layers, among which, 2 to 5 layers are suitable.
  • an etch stop layer 113 is further formed between the substrate 10 and the sacrificial layer 112 .
  • the wafer 1 includes a central area S2 and an edge area S1 surrounding the central area S2.
  • the wafer 1 may include a central area S2 and an edge area S1 surrounding the central area S2 , that is, the chips D1 distributed in the array may be divided into chips D1 in the central area S2 and chips D1 in the edge area S1 .
  • the central area S2 refers to the chips D1 distributed in the central area S2
  • the edge area S1 refers to the chips D1 distributed in the edge area S1.
  • the width L1 of the edge region S1 may be less than or equal to 8 mm to maximize the utilization of the effective chip area in the wafer 1 .
  • the first support layer 111 a in the edge region S1 is removed.
  • the first support layer 111a in the edge region S1 is first removed, because the capacitor hole 11a is not formed in the edge region S1, that is, the first support layer in the edge region S1 111a and the lower support layer 111 will not be fixedly connected by the lower electrode, so that when the sacrificial layer 112 is subsequently etched by forming an opening for the first support layer 111a, the first support layer 111a in the edge region S1 is not connected to the lower layer.
  • the support layer 111 forms a fixed connection and collapses or peels off, thereby affecting the yield of the chip D1 in the central area S2.
  • Removing the first support layer 111a in the edge region S1 may include: exposing the first support layer 111a of the chip in the edge region S1 through a photolithography process, and etching the exposed first support layer 111a.
  • the first support layer 111a may be etched by wet etching or dry etching.
  • the first supporting layer 111a is wet-etched by hot phosphoric acid, and the specific etching method of the first supporting layer 111a is not limited in this embodiment.
  • the first support layer 111 a of the chip D1 in the edge region S1 exposed through the photolithography process may include: A positive first photoresist 12 is coated on the etching substrate 11 ; the edge region S1 of the wafer 1 is exposed through a blank mask; the edge region S1 exposing the sacrificial layer 112 is formed after developing.
  • a positive first photoresist 12 is coated on the substrate 11 to be etched.
  • the photoresist in the exposed area is etched away.
  • the unexposed photoresist is etched away.
  • a positive first photoresist 12 is applied, and the edge region S1 is exposed to light.
  • the first support layer 111a of the edge region S1 is exposed.
  • the edge region S1 of the wafer 1 is exposed (by shot) through a blank mask. Then, the first support layer 111a in the edge region S1 is etched, as shown in FIG.
  • FIG. 5 is a schematic structural diagram of etching the first support layer 111a in the edge region S1 according to an embodiment of the present disclosure.
  • the first support layer 111a in the edge region S1 is removed to obtain the chip structure in the edge region S1 shown in Fig. 5.
  • the first support layer 111a in the center region S2 is not removed.
  • the chip structure of the central region S2 shown in FIG. 5 is obtained.
  • the thickness L2 of the first photoresist 12 may be 50-200 nm, wherein, it may be 80-120 nm.
  • FIG. 6 is a schematic structural diagram of forming a first hard mask layer 13 on the substrate 11 to be etched according to an embodiment of the present disclosure.
  • the first hard mask layer 13 includes a first pattern in the central area S2 16.
  • the first pattern 16 includes through holes 131 arranged in an array, as shown in FIG. 7, which is a top view of the first hard mask layer 13 in FIG.
  • the shape of the 131 may be a circle, or of course other geometric figures such as a rectangle, and as shown in FIG. 6 and FIG. 7 , no through hole 131 is formed in the edge region S1 .
  • the substrate 11 to be etched is etched, as shown in FIG.
  • a schematic diagram of the structure of the capacitor hole 11a, the capacitor hole 11a is formed by etching the substrate 11 to be etched, and the capacitor hole 11a and the through hole 131 are arranged in a one-to-one correspondence. Since no through holes 131 are formed in the first hard mask layer 13 in the edge region S1, when the substrate to be etched 11 is etched using the first hard mask layer 13 as a mask, the substrate to be etched in the edge region S1 The capacitor hole 11a is not formed in 11. In the present disclosure, by not forming capacitor holes 11a in the chip in the edge region S1 of the wafer 1, the risk of collapse and peeling of the capacitor column in the edge region S1 in the subsequent process is avoided, thereby affecting the chip yield in the central region S2 of the wafer 1.
  • FIG. 10 is a schematic structural diagram of forming a first opening 1111 on the first support layer 111 a provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of a comparative example of depositing a lower electrode layer 14 on a capacitor hole 11a provided by an embodiment of the present disclosure. The comparative example shown in FIG.
  • the edge region S1 of the capacitor shown in FIG. 9 does not form an incomplete pattern of the first support layer 111a, which effectively avoids the influence of the first support layer 111a on the capacitor manufacturing process.
  • the material of the lower electrode layer 14 includes a compound formed by one or both of metal nitride and metal silicide, such as titanium nitride (Titanium Nitride), titanium silicide (Titanium Silicide), nickel silicide (Titanium Silicide), silicon Titanium nitride (TiSixNy), wherein, in this embodiment, the material of the lower electrode layer 14 is titanium nitride; The lower electrode layer 14 on the sidewalls and the bottom of the capacitor hole 11a.
  • metal nitride and metal silicide such as titanium nitride (Titanium Nitride), titanium silicide (Titanium Silicide), nickel silicide (Titanium Silicide), silicon Titanium nitride (TiSixNy), wherein, in this embodiment, the material of the lower electrode layer 14 is titanium nitride; The lower electrode layer 14 on the sidewalls and the bottom of the capacitor hole 11a.
  • the substrate 11 to be etched is firstly formed to prepare the capacitor hole 11a, and the substrate 11 to be etched includes at least one sacrificial layer 112 and at least one supporting layer 111.
  • the sacrificial layer 112 and The supporting layers 111 are arranged alternately, and the topmost layer is the first supporting layer 111a.
  • the wafer 1 includes a central area S2 and an edge area S1 surrounding the central area S2. Continue to form the first pattern 16 on the substrate 11 to be etched.
  • the first pattern 16 includes through holes 131 arranged in an array, and the substrate 11 to be etched is etched using the first hard mask layer 13 as a mask to form capacitor holes 11a, because the first hard mask layer 13 is used as a mask to etch the substrate 11 to be etched.
  • the through hole 131 is not formed in the edge region S1 of the film layer 13, so the capacitor hole 11a is not formed in the edge region S1.
  • the lower electrode layer 14 is deposited on the capacitor hole 11a, and the substrate 11 to be etched is removed layer by layer, and sequentially formed Capacitive dielectric layer and upper electrode layer.
  • the capacitor structure in the edge region S1 in the prior art is prevented from being collapsed due to process reasons and affecting the overall yield of the wafer 1, thereby improving the production quality and production efficiency of the capacitor.
  • the first support layer 111 a in the edge region S1 is not stably connected to the lower level 14 and the lower support layer 111 from peeling off when the sacrificial layer 112 is subsequently etched. , resulting in contamination of wafer 1.
  • the substrate 11 to be etched may include: a second sacrificial layer 112 b , a second supporting layer 111 b , a first sacrificial layer 112 a and a first supporting layer formed in sequence in a direction away from the substrate 10 111a, the process of removing part of the substrate 11 to be etched layer by layer is shown in FIG. 12 , which is a schematic flowchart of another method for fabricating a capacitor provided by an embodiment of the present disclosure, including the following steps:
  • the substrate 11 to be etched includes a second sacrificial layer 112 b , a second supporting layer 111 b , a first sacrificial layer 112 a and a first supporting layer 111 a which are sequentially arranged on the wafer 1 .
  • the removal operations are sequentially performed according to the sequence of the first support layer 111a, the first sacrificial layer 112a, the second support layer 111b and the second sacrificial layer 112b.
  • the material of the sacrificial layer 112 includes silicon oxide or BPSG, the sacrificial layer 112 may be doped with boron or phosphorus, and the material of the support layer 111 includes any one of silicon nitride, silicon oxynitride, and silicon carbonitride one or a combination of any two or more.
  • first openings 1111 are formed in the first supporting layer 111a, as shown in FIG.
  • a schematic diagram of the structure of the opening 1111, the S2 area in FIG. 13 is the cross section along the a-a' direction in FIG.
  • the first supporting layer 111a is removed by dry etching Bottom electrode layer 14 on top. After that, the first support layer 111a is opened to expose the first sacrificial layer 112a under the first opening 1111.
  • the first support layer 111a is not provided in the edge region S1 of the wafer 1, and the first opening 1111 in the edge region S1 is transferred. onto the first sacrificial layer 112a.
  • 14 is a schematic structural diagram of a comparative example in which the first opening 1111 is formed on the first support layer 111 a provided by the embodiment of the present disclosure. In FIG. 14 , the first support layer 111 a ′ is not removed in the edge region S1 ′, and in FIG.
  • the first opening 1111' of the edge region S1' is formed on the first support layer 111a', and because the When the sacrificial layer 112a' is etched, the first support layer 111a' in the edge region S1' is completely peeled off due to lack of connection with the lower electrical level layer.
  • FIG. 15 is a schematic structural diagram of removing the first sacrificial layer 112 a based on the first opening 1111 provided by an embodiment of the present disclosure. In this embodiment, based on the first opening 1111 , all the first sacrificial layers shown in FIG. 13 are removed by wet etching. sacrificial layer 112a.
  • FIG. 16 is a schematic structural diagram of forming a second opening 1112 in the second supporting layer 111b according to an embodiment of the present disclosure. This embodiment is based on the second opening 1112 to expose the second sacrificial layer 112b.
  • the openings 1111 correspond one-to-one with the second openings 1112 shown in FIG. 16 .
  • the second sacrificial layer 112b is removed by wet etching.
  • FIG. 17 is a schematic structural diagram of removing the second sacrificial layer 112b based on the second opening 1112 according to an embodiment of the present disclosure.
  • a wet etching method is used to remove the first sacrificial layer shown in FIG. 16 .
  • the substrate 11 to be etched is completely etched away.
  • the capacitor dielectric layer and the upper electrode layer can be further formed, thereby forming a complete capacitor structure.
  • the first supporting layer 111a in the edge region S1 is removed before etching the capacitor hole 11a, so that when the substrate 11 to be etched is etched, the first supporting layer 111a is in the first supporting layer 111a.
  • the first opening 1111 is formed, the first opening 1111 is transferred to the first sacrificial layer 112a, so that the edge region S1 does not cause peeling of the first supporting layer 111a.
  • FIG. 18 is a schematic flowchart of another method for fabricating a capacitor according to an embodiment of the present disclosure. After removing the first support layer 111 a in the edge region S1 , forming a first pattern on the substrate to be etched 11 including the center region S2 having a first pattern The process of the first hard mask layer 13 of 16 may include the following steps:
  • FIG. 19 is a schematic structural diagram of forming a first isolation sidewall pattern 13a on the first hard mask layer 13 according to an embodiment of the present disclosure, forming a first hard mask layer 13 on the first supporting layer 111a, and First isolation sidewall patterns 13 a are formed on the first hard mask layer 13 .
  • the above-mentioned first isolation sidewall patterns 13a may be formed by a patterning process.
  • the above-mentioned first isolation sidewall patterns 13a may be formed by a self-aligned double patterning process including but not limited to.
  • the first hard mask layer 13 may include a single-layer or multi-layer structure, and its material may be selected from materials such as polysilicon, silicon oxide, ACL, or SOH.
  • FIG. 20 is a schematic structural diagram of forming a second isolation sidewall pattern 15a on the first isolation sidewall pattern 13a according to an embodiment of the present disclosure, forming a second isolation layer 15 on the first isolation sidewall pattern 13a, and performing photolithography
  • the second isolation sidewall pattern 15a is only disposed in the central region S2, the second isolation layer 15 in the edge region S1 is not etched, and the second isolation layer 15 in the edge region S1 is retained. Therefore, the capacitor hole 11a in the edge region S1 is prevented from being formed in the subsequent process, thereby effectively preventing the impact of the collapse of the capacitor structure on the yield of the whole wafer 1 in the subsequent process when the edge region S1 has a capacitor structure.
  • the first pattern 16 is formed where the first isolation sidewall pattern 13a and the second isolation sidewall pattern 15a do not overlap, and the first isolation sidewall pattern 13a and the second isolation sidewall pattern 15a are used as masks for etching, and the The first pattern 16 is transferred to the first hard mask layer 13 to form the first hard mask layer 13 having the first pattern 16 in the central region S2.
  • FIG. 21 is a top view of the first isolation sidewall pattern 13a provided by an embodiment of the present disclosure.
  • the first isolation sidewall pattern 13a may include a plurality of first strip structures 131a arranged in parallel with each other.
  • 22 which is a top view of the second isolation sidewall pattern 15a provided by an embodiment of the present disclosure
  • the second isolation sidewall pattern 15a may also include a plurality of second strip-shaped structures arranged in parallel to each other 151a
  • the first strip-shaped structure 131a can be set to extend along the first direction X
  • the second strip-shaped structure 151a can be set to extend along the second direction Y.
  • the first direction X and the second direction Y intersect, for example, the first The included angle between the direction X and the second direction Y is 60-120 degrees.
  • FIG. 23 is a first isolation sidewall pattern 13a and a second isolation sidewall pattern provided by an embodiment of the present disclosure.
  • 15a the first pattern 16 is formed where the first isolation sidewall pattern 13a and the second isolation sidewall pattern 15a do not overlap.
  • the first isolation sidewall pattern 13a and the second isolation sidewall pattern 15a are used as masks to transfer the first pattern 16 to the first hard mask layer 13 to obtain the structure shown in FIG. The first hard mask layer 13 of the pattern 16 .
  • the second isolation layer 15 in the edge region S1 is entirely covered on the substrate 10 because it is not etched into the second isolation sidewall pattern 15a in step S320 .
  • the isolation sidewall pattern 15a is used as a mask to etch the first hard mask layer 13
  • the first pattern 16 is not formed on the first hard mask layer 13 in the edge region S1.
  • the first pattern 16 includes through holes 131 arranged in an array. It is convenient to use the first hard mask layer 13 as a mask to form the capacitor holes 11 a corresponding to the through holes 131 in a one-to-one manner.
  • the formation process of the first pattern 16 of the first hard mask layer 13 is described in detail. Specifically, the first isolation sidewall pattern 13a and the second isolation sidewall pattern 15a are superimposed and formed.
  • the second isolation layer 15 in the edge region S1 is reserved to prevent the second isolation layer 15 in the edge region S1 from forming a pattern, thereby preventing the edge region S1 from forming the capacitor hole 11a in the subsequent process, thereby effectively preventing the edge region
  • S1 has a capacitor structure, the impact of the collapse of the capacitor structure on the yield of the overall wafer 1 in the subsequent process.
  • FIG. 24 is a schematic flowchart of another method for fabricating a capacitor according to an embodiment of the present disclosure. After removing the first support layer 111 a in the edge region S1 , a first hard layer including the first pattern 16 is formed on the substrate 11 to be etched. The process of the mask layer 13 may also include the following steps:
  • FIG. 25 is a schematic structural diagram of filling the buffer layer 17 between the first isolation sidewall patterns 13a according to an embodiment of the present disclosure.
  • the layer 17 is planarized so that the buffer layer 17 exists only in the portion between the first stripe structures 131a in the first isolation sidewall pattern 13a. In other embodiments, the planarized buffer layer 17 may also cover the top of the first isolation sidewall pattern 13a.
  • FIG. 26 FIG.
  • 26 is a schematic structural diagram of forming the second isolation layer 15 according to an embodiment of the present disclosure, forming a second hard mask layer 18 on the buffer layer 17 , and patterning the second hard mask layer 18 forms a linear second hard mask pattern 18a.
  • the extending direction of the linear second hard mask pattern 18a also extends according to the second direction Y.
  • the second isolation layer 15 is deposited on the second hard mask layer 18, and the second isolation layer 15 completely covers the linear second hard mask pattern 18a, so that the second isolation layer 15 includes the top surface 151, the bottom Surface 152 and sidewall 153 .
  • a negative second photoresist 19 is coated on the second isolation layer 15 , as shown in FIG. 27 .
  • the thickness of the second photoresist 19 may be 50-200 nm, wherein, it may be 80-120 nm.
  • the top surface 151 and the bottom surface 152 of the second isolation layer 15 in the central region S2 are removed by an etching process, the sidewalls 153 are retained, and a second isolation sidewall pattern 15a is formed.
  • the wafer 1 with negative photoresist needs to be coated with positive photoresist as a whole, and the chip array area A2 is exposed and developed to expose the second isolation layer 15 of the chip array area A2 , because there is negative photoresist on the chip in the edge area S1, the second isolation layer 15 of the chip in the edge area S1 is retained as a whole during etching, while the second isolation layer 15 in the chip array area A2 in the central area S2 is
  • the second isolation sidewall patterns 15a are formed by etching.
  • FIG. 28 is a schematic structural diagram of forming a second isolation sidewall pattern 15a provided by an embodiment of the present disclosure.
  • the top surface 151 and the bottom surface 152 of the second isolation layer 15 in the central region S2 are removed by an etching process, Only the sidewalls 153 remain, and the second isolation sidewall patterns 15a are formed. Specifically, the top surface 151 and the bottom surface 152 of the second isolation layer 15 in the chip array area A2 of the central area S2 are removed to form the second isolation sidewall pattern 15a.
  • the etched pattern in the edge region S1 is transferred to the second photoresist 19 , but not transferred to the second isolation layer 15 , preventing the edge region S1 from forming a capacitor structure, thereby ensuring the reliability of the capacitor manufacturing environment.
  • the first pattern 16 is formed where the first isolation sidewall pattern 13a and the second isolation sidewall pattern 15a do not overlap, and the first isolation sidewall pattern 13a and the second isolation sidewall pattern 15a are used as masks for etching, and the The first pattern 16 is transferred to the first hard mask layer 13 to form the first hard mask layer 13 having the first pattern 16 .
  • the specific process of the second isolation sidewall pattern 15a is described in detail, and when the second isolation sidewall pattern 15a is formed, the second isolation layer in the edge region S1 is retained by the negative second photoresist 19 15.
  • the second isolation layer 15 in the edge region S1 is prevented from being patterned, thereby avoiding the risk of peeling off of the second isolation layer 15 in the edge region S1, and effectively protecting the capacitor structure array.
  • FIG. 29 is a schematic structural diagram of a capacitor array structure provided by an embodiment of the present disclosure.
  • the capacitor array structure provided by an embodiment of the present disclosure is manufactured by the manufacturing method of a capacitor provided by any embodiment of the present disclosure, including array arrangement. of multiple capacitors 2.
  • the capacitor array structure in this embodiment has the technical features of the manufacturing method of the capacitor provided by any embodiment of the present disclosure, and has the beneficial effects of the manufacturing method of the capacitor provided by any embodiment of the present disclosure.
  • FIG. 30 is a schematic structural diagram of a semiconductor memory provided by an embodiment of the present disclosure.
  • An embodiment of the present disclosure also provides a semiconductor memory, including the capacitor array structure provided by any embodiment of the present disclosure 3;
  • a transistor layer 4 is also included, and the transistor layer 4 includes transistors 5 arranged in a one-to-one correspondence with the capacitors 2 for writing and reading signals to the capacitors.
  • a substrate to be etched is first formed to prepare a capacitor hole, and the substrate to be etched includes at least one sacrificial layer and at least one supporting layer, The sacrificial layers and the supporting layers are alternately arranged, and the topmost layer is the first supporting layer, the wafer includes a central area and an edge area surrounding the central area, and a first hard disk having a first pattern in the central area is continuously formed on the substrate to be etched.
  • the first pattern includes through holes arranged in an array, and the substrate to be etched is etched with the first hard mask layer as a mask to form capacitor holes, because the first hard mask layer in the wafer edge area does not No through hole is formed, so no capacitor hole is formed in the edge region. Then, a lower electrode layer is deposited on the capacitor hole, and the substrate to be etched is removed layer by layer, and a capacitor dielectric layer and an upper electrode layer are formed in sequence.
  • the film layer structure in the edge region will not form an incomplete (patterned) structure, thereby avoiding the collapse of the capacitor structure in the edge region and affecting the overall yield of the wafer due to process reasons, thereby improving the overall yield of the wafer. Capacitor production quality and production efficiency.

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Abstract

本公开公开了一种电容器的制作方法及电容器阵列结构、半导体存储器，其中，电容器的制作方法包括：提供衬底；在衬底上形成待刻蚀基底；晶圆包括中心区域和边缘区域；在待刻蚀基底上形成中心区域具有第一图案的第一硬掩膜层；以第一硬掩膜层为掩膜刻蚀待刻蚀基底，形成电容孔；沉积下电极层；依次形成电容介质层和上电极层。

Description

电容器的制作方法及电容器阵列结构、半导体存储器
[根据细则91更正 12.11.2021]　
本公开要求在2020年08月05日提交中国专利局、申请号为202010778901.9、发明名称为“电容器的制作方法及电容器阵列结构、半导体存储器”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及但不限于一种电容器的制作方法及电容器阵列结构、半导体存储器。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连；字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
随着制程工艺持续演进，DRAM集成度不断提高，元件横向尺寸不断地微缩，使得电容器具有较高的纵横比，制作工艺愈加困难。具体的，在制作电容器工艺过程中，晶圆边缘区域的芯片是无效芯片，且在刻蚀过程中晶圆边缘区域图形会出现塌陷和剥落的风险，从而破坏晶圆中心区域部分电容器的完整，造成晶圆污染以及晶圆的工艺腔体的污染，降低了芯片的良率和生产效率。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种电容器的制作方法及电容器阵列结构、半导体存储器，以解决电容器刻蚀过程中，晶圆边缘容易出现塌陷和剥落的问题。
根据本公开实施例提供了一种容器的制作方法，包括：
提供一晶圆，所述晶圆包含多个阵列分布的芯片，所述芯片具有一相同衬 底；在所述衬底上形成待刻蚀基底；所述待刻蚀基底包括至少一层牺牲层和至少一层支撑层；所述牺牲层和所述支撑层交替设置，且所述待刻蚀基底远离所述衬底的一侧为第一支撑层；
所述晶圆包括中心区域和围绕所述中心区域的边缘区域；
在所述待刻蚀基底上形成在中心区域具有第一图案的第一硬掩膜层；所述第一图案包括阵列排布的通孔；以所述第一硬掩膜层为掩膜刻蚀所述待刻蚀基底，形成电容孔；所述边缘区域未形成电容孔；
在所述电容孔的底部和侧壁上沉积下电极层，并逐层去除部分所述待刻蚀基底；依次在所述下电极层上形成电容介质层和上电极层。
根据本公开的一些实施例，在由所述中心区域指向所述边缘区域的方向上，所述边缘区域的宽度小于或等于8mm。
根据本公开的一些实施例，在所述衬底上形成待刻蚀基底后，还包括：
去除所述边缘区域芯片的第一支撑层。
根据本公开的一些实施例，去除所述边缘区域芯片的第一支撑层，包括：
通过光刻工艺暴露出所述边缘区域芯片的第一支撑层，刻蚀暴露的第一支撑层,形成暴露所述牺牲层的边缘区域。
根据本公开的一些实施例，通过光刻工艺暴露出所述边缘区域芯片的第一支撑层包括：
在所述待刻蚀基底上涂敷正性的第一光刻胶；通过空白掩模版对所述晶圆的所述边缘区域进行曝光；显影、刻蚀后形成所述暴露牺牲层的边缘区域。
根据本公开的一些实施例，所述第一光刻胶的厚度为50nm～200nm。
根据本公开的一些实施例，所述待刻蚀基底包括：在远离所述衬底的方向上，依次形成第二牺牲层、第二支撑层、第一牺牲层和第一支撑层；
其中，逐层去除部分所述待刻蚀基底，包括：
在所述第一支撑层内形成第一开口，以暴露出所述第一牺牲层；所述晶圆的边缘区域的第一开口转移至所述第一牺牲层；
基于所述第一开口，去除所述第一牺牲层；
于所述第二支撑层内形成第二开口，以暴露出所述第二牺牲层；
基于所述第二开口，去除所述第二牺牲层；
所述第一开口与所述第二开口一一对应。
根据本公开的一些实施例，在所述待刻蚀基底上形成在中心区域具有第一图案的第一硬掩膜层，包括：
形成第一硬掩膜层，在所述第一硬掩膜层上形成第一方向的第一隔离侧壁图案；
在所述第一隔离侧壁图案上形成第二隔离层，通过光刻工艺暴露中心区域芯片的所述第二隔离层，并对所述第二隔离层进行刻蚀，形成第二方向的第二隔离侧壁图案，所述边缘区域芯片的第二隔离层保留；
所述第一隔离侧壁图案和所述第二隔离侧壁图案未重叠的地方形成所述第一图案，以所述第一隔离侧壁图案和第二隔离侧壁图案为掩膜刻蚀，将所述第一图案传输至第一硬掩膜层，形成所述在中心区域具有第一图案的第一硬掩膜层。
根据本公开的一些实施例，所述第一硬掩膜层包括单层或多层结构。
根据本公开的一些实施例，通过图案化工艺形成所述第一隔离侧壁图案。
根据本公开的一些实施例，在所述第一隔离侧壁图案上形成第二隔离层包括：
在所述第一隔离侧壁图案间填充缓冲层，并在所述第一隔离侧壁图案和所述缓冲层上沉积第二硬掩模层；刻蚀部分所述第二硬掩模层形成线性第二硬掩模图案，沉积第二隔离层覆盖所述第二硬掩模层及所述缓冲层，所述第二隔离层包括顶部表面、底部表面和连接顶部表面及底部表面的侧壁。
根据本公开的一些实施例，通过光刻工艺暴露中心区域的所述第二隔离层，并对所述第二隔离层进行刻蚀，形成第二隔离侧壁图案，包括：在所述第二隔离层上涂敷负性的第二光刻胶，通过空白掩模版对所述晶圆的边缘区域进行曝光，显影后所述边缘区域的所述第二光刻胶保留；通过刻蚀工艺去除中心区域的所述第二隔离层的顶部表面和底部表面，保留侧壁，形成所述第二隔离侧壁图案。
根据本公开的一些实施例，所述第二光刻胶的厚度为50-200nm。
根据本公开的一些实施例，提供了一种电容器阵列结构，由本公开任意实施例提供的电容器的制作方法制成。
根据本公开的一些实施例，提供了一种半导体存储器，包括本公开任意实施例提供的电容器阵列结构；晶体管层，所述晶体管层包括与所述电容器一一对应设置的晶体管。
本公开中，在电容器的制作过程中，首先形成待刻蚀基底以制备电容孔，待刻蚀基底包括至少一层牺牲层和至少一层支撑层，牺牲层和支撑层交替设置，并且最顶层的为第一支撑层，晶圆包括中心区域和围绕中心区域的边缘区域，继续在待刻蚀基底上形成在中心区域具有第一图案的第一硬掩膜层，第一图案包括阵列排布的通孔，以第一硬掩膜层为掩膜刻蚀上述待刻蚀基底，形成电容孔，因为晶圆边缘区域的第一硬掩模层并未形成通孔，所以边缘区域则未形成电容孔，之后在电容孔上沉积下电极层，并逐层去除待刻蚀基底，并依次形成电容介质层和上电极层。本实施例通过不在晶圆边缘区域设置电容结构则边缘区域的膜层结构不会形成非完整(图案化)结构，从而避免边缘区域电容结构因工艺原因倒塌而影响晶圆整体良率，进而提高电容器的生产品质和生产效率。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种电容器的制作方法的流程示意图；
图2是本公开实施例提供的晶圆的平面结构示意图；
图3是本公开实施例提供的在衬底上形成待刻蚀基底的结构示意图；
图4是本公开实施例提供的在待刻蚀基底上形成第一光刻胶的结构示意图；
图5是本公开实施例提供的对边缘区域的第一支撑层进行刻蚀的结构示意 图；
图6是本公开实施例提供的在待刻蚀基底上形成第一硬掩膜层的结构示意图；
图7是图6中的第一硬掩膜层的俯视图；
图8是本公开实施例提供的在待刻蚀基底上形成电容孔的结构示意图；
图9是本公开实施例提供的在电容孔上沉积下电极的结构示意图；
图10是本公开实施例提供的在第一支撑层上形成第一开口的结构示意图；
图11是本公开实施例提供的在电容孔上沉积下电极的对比例的结构示意图；
图12是本公开实施例提供的另一种电容器的制作方法的流程示意图；
图13是本公开实施例提供的在第一支撑层上形成第一开口的结构示意图；
图14是本公开实施例提供的在第一支撑层上形成第一开口的对比例的结构示意图；
图15是本公开实施例提供的基于第一开口去除第一牺牲层的结构示意图；
图16是本公开实施例提供的于第二支撑层内形成第二开口的结构示意图；
图17是本公开实施例提供的基于第二开口去除第二牺牲层的结构示意图；
图18是本公开实施例提供的另一种电容器的制作方法的流程示意图；
图19是本公开实施例提供的在第一硬掩膜层上形成第一隔离侧壁图案的结构示意图；
图20是本公开实施例提供的在第二掩膜层上形成第二隔离侧壁图案的结构示意图；
图21是本公开实施例提供的第一隔离侧壁图案的俯视图；
图22是本公开实施例提供的第二隔离侧壁图案的俯视图；
图23是本公开实施例提供的一种第一硬掩膜层和第二掩膜层的俯视图；
图24是本公开实施例提供的另一种电容器的制作方法的流程示意图；
图25是本公开实施例提供的在第一隔离侧壁图案间填充缓冲层的结构示意图；
图26是本公开实施例提供的形成第二隔离层的结构示意图；
图27是本公开实施例提供的第二隔离层上涂敷负性的第二光刻胶的结构示意图；
图28是本公开实施例提供的形成第二隔离侧壁图案的结构示意图；
图29是本公开实施例提供的一种电容器阵列结构的结构示意图；
图30是本公开实施例提供的一种半导体存储器的结构示意图。
具体实施方式
下面结合附图和实施例对本公开作详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释本公开，而非对本公开的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本公开相关的部分而非全部结构。
本公开实施例提供了一种电容器的制作方法，图1是本公开实施例提供的一种电容器的制作方法的流程示意图，如图1所示，本实施例的方法包括如下步骤：
S110、提供一晶圆1，晶圆1包含多个阵列分布的芯片，芯片具有一相同衬底10；在衬底10上形成待刻蚀基底11；待刻蚀基底11包括至少一层牺牲层112和至少一层支撑层111；牺牲层112和支撑层111交替设置，且待刻蚀基底11远离衬底10的一侧为第一支撑层111a。
如图2所示，图2是本公开实施例提供的晶圆1的平面结构示意图，提供一晶圆1，上述晶圆1可以是未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)晶圆等，所述晶圆1由多个阵列分布的芯片D1(die)构成，且每个芯片D1都包含存储区域的阵列区(用于设置电容结构)和电路控制区域的外围区。在电容器制作过程中，晶圆1边缘区域S1的阵列区电容容易倒塌和剥落，从而影响中心区域S2晶粒良率，本公开通过避免在边缘区域S1形成电容结构，来解决边缘区域S1电容柱倒塌问题，从而提高晶圆良率。
可以理解所述芯片衬底10都由相同工艺形成，即所述多个芯片都具有相同的衬底10，在本公开实施例中，我们可以就其中单个或两个芯片进行阐述。如 图3所示，图3是本公开实施例提供的在衬底10上形成待刻蚀基底11的结构示意图，其中A2为阵列区，A1为外围区，所述衬底10包含电容触点(未示出)，在形成电容器时，在衬底10上形成待刻蚀基底11，待刻蚀基底11包括至少一层牺牲层112和至少一层支撑层111，并且牺牲层112和支撑层111交替设置，且待刻蚀基底11远离晶圆1的一侧为第一支撑层111a，也即，待刻蚀基底11的顶层为第一支撑层111a。上述待刻蚀基底11的设置用于后续电容器制作工艺中电容孔11a的刻蚀。示例性的，如图3所示，本实施例可设置两层支撑层111和两层牺牲层112，上述支撑层111和牺牲层112的数量可以依据后续电容器所需要的高度进行设定，支撑层111和牺牲层112的层叠数量可以为多层，其中，以2～5层为宜。本实施例中，衬底10和牺牲层112之间还形成一层刻蚀停止层113。
S120、晶圆1包括中心区域S2和围绕中心区域S2的边缘区域S1。
继续参考图2，晶圆1可包括中心区域S2和围绕中心区域S2的边缘区域S1，即所述阵列分布的芯片D1可以分为中心区域S2的芯片D1和边缘区域S1的芯片D1。在本公开实施例中，中心区域S2指的是中心区域S2分布的芯片D1，边缘区域S1则指的是边缘区域S1分布的芯片D1。
继续参考图2，在由中心区域S2指向边缘区域S1的方向上，边缘区域S1的宽度L1可以小于或等于8mm，以最大化利用晶圆1中有效芯片的面积。
继续参考图2和图3，在一实施例中，在衬底10上形成待刻蚀基底11后，去除边缘区域S1的第一支撑层111a。
本实施例在衬底10上形成待刻蚀基底11后，首先去除边缘区域S1的第一支撑层111a，这是因为由于边缘区域S1未形成电容孔11a，即边缘区域S1的第一支撑层111a和下层支撑层111之间不会通过下电级固定连接，导致后续在通过对第一支撑层111a形成开口去刻蚀牺牲层112时，边缘区域S1的第一支撑层111a因为没有与下层支撑层111形成固定连接而倒塌或剥离，从而影响中心区域S2的芯片D1的良率。通过在形成待刻蚀基底11后去除边缘区域S1的第一支撑层111a，从而可以避免上述情况的发生，提高电容器的生产品质。
去除边缘区域S1的第一支撑层111a，可以包括：通过光刻工艺暴露出边缘区域S1芯片的第一支撑层111a，刻蚀暴露的第一支撑层111a。本实施例可以 通过湿法刻蚀或干法刻蚀第一支撑层111a。例如，通过热磷酸对第一支撑层111a进行湿法刻蚀，本实施例对第一支撑层111a的具体刻蚀方法不进行限定。
图4是本公开实施例提供的在待刻蚀基底11上形成第一光刻胶12的结构示意图，通过光刻工艺暴露出边缘区域S1的芯片D1的第一支撑层111a可以包括：在待刻蚀基底11上涂敷正性的第一光刻胶12；通过空白掩模版对晶圆1的边缘区域S1进行曝光；显影后形成暴露牺牲层112的边缘区域S1。
如图4所示，在待刻蚀基底11上涂覆正性的第一光刻胶12，对于正性的光刻胶，曝光显影后，刻蚀掉的为被曝光区域的光刻胶，而对于负性的光刻胶，曝光显影后，刻蚀掉的是未被曝光的光刻胶。本实施例通过涂敷正性的第一光刻胶12，并对边缘区域S1进行曝光，显影后，将边缘区域S1的第一支撑层111a暴露出来。具体的，本实施例通过空白掩膜版对晶圆1的边缘区域S1进行曝光(by shot)。之后通过对边缘区域S1的第一支撑层111a进行刻蚀，如图5所示，图5是本公开实施例提供的对边缘区域S1的第一支撑层111a进行刻蚀的结构示意图，在图4所示晶圆结构的基础上，将边缘区域S1的第一支撑层111a去除后得到图5所示的边缘区域S1的芯片结构，对应的，中心区域S2的第一支撑层111a未被去除，得到图5所示的中心区域S2的芯片结构。第一光刻胶12的厚度L2可以为50-200nm，其中，可以为80-120nm。
S130、在待刻蚀基底11上形成包括在中心区域S2具有第一图案16的第一硬掩膜层13；第一图案16包括阵列排布的通孔131；以第一硬掩膜层13为掩膜刻蚀待刻蚀基底11，形成电容孔11a；所述边缘区域S1则未形成通孔131。
如图6所示，图6是本公开实施例提供的在待刻蚀基底11上形成第一硬掩膜层13的结构示意图，第一硬掩膜层13包括在中心区域S2具有第一图案16，第一图案16包括阵列排布的通孔131，如图7所示，图7是图6中的第一硬掩膜层13的俯视图，在平行于晶圆1所在平面内，通孔131的形状可以为圆形，当然也可以为矩形等其他几何图形，并且由图6和图7所示，边缘区域S1则未形成通孔131。将上述带有通孔131第一硬掩膜层13作为掩膜，对待刻蚀基底11进行刻蚀，如图8所示，图8是本公开实施例提供的在待刻蚀基底11上形成电容孔11a的结构示意图，在待刻蚀基底11刻蚀形成电容孔11a，电容孔11a与通孔131一一对应设置。由于在边缘区域S1的第一硬掩膜层13未形成通孔 131，因此在以第一硬掩膜层13作掩膜对待刻蚀基底11进行刻蚀时，边缘区域S1的待刻蚀基底11上未形成电容孔11a。本公开通过不对晶圆1边缘区域S1的芯片形成电容孔11a，进而避免后续工艺中边缘区域S1的电容柱容易出现倒塌和剥落的风险，从而影响晶圆1中心区域S2的芯片良率。
S140、在电容孔11a的底部和侧壁上沉积下电极层14，并逐层去除部分待刻蚀基底11；依次在下电极层14上形成电容介质层和上电极层。
在刻蚀待刻蚀基底11上形成电容孔11a后，其中，边缘区域S1的待刻蚀基底11未形成电容孔11a，将第一硬掩膜层13去除，如图9所示，图9是本公开实施例提供的在电容孔11a上沉积下电极层14的结构示意图，将第一硬掩膜层13去除后，在电容孔11a的底部和侧壁上均沉积有下电极层14，之后逐层将部分待刻蚀基底11去除，具体的，如图10所示，图10是本公开实施例提供的在第一支撑层111a上形成第一开口1111的结构示意图，通过在第一支撑层111a形成第一开口1111去刻蚀牺牲层112时，边缘区域S1并未形成第一支撑层111a的非完整图形。第一开口1111可以为三个电容孔11a之间的开口，也可以为4个或6个电容孔11a之间的开口，在本实施例中不做限定。参考图11，图11是本公开实施例提供的在电容孔11a上沉积下电极层14的对比例的结构示意图，图11中示出的对比例在形成待刻蚀基底11’时，并未将边缘区域S1’的第一支撑层111a’去除，则在电容孔11a’的底部和侧壁上均沉积下电极层14’之后，通过第一开口去刻蚀牺牲层时，中心区域S2’的第一支撑层通过下电极层14和下层支撑层稳固连接，而边缘区域S1’的第一支撑层111a’在刻蚀掉牺牲层后会直接剥离，从而污染电容器的制作环境，而本实施例提供的如图9所示的电容器的边缘区域S1未形成第一支撑层111a的非完整图形，有效避免第一支撑层111a对电容器制程的影响。
可采用原子层沉积工艺(Atomic Layer Deposition，ALD)或等离子蒸气沉积工艺(Chemical Vapor Deposition，CVD)于电容孔11a的侧壁及底部，以及待刻蚀基底11的上表面沉积下电极层14，下电极层14的材料包括金属氮化物及金属硅化物中的一种或两种所形成的化合物，如氮化钛(Titanium Nitride)，硅化钛(Titanium Silicide)，硅化镍(Titanium Silicide)，硅氮化钛(TiSixNy)，其中，本实施例中，下电极层14的材料为氮化钛；然后，再采用刻蚀工艺去除位于待刻蚀基底11上表面的下电极材料层，保留的位于电容孔11a的侧壁及底部的下电极 层14。
本公开实施例中，在电容器的制作过程中，首先形成待刻蚀基底11以制备电容孔11a，待刻蚀基底11包括至少一层牺牲层112和至少一层支撑层111，牺牲层112和支撑层111交替设置，并且最顶层的为第一支撑层111a，晶圆1包括中心区域S2和围绕中心区域S2的边缘区域S1，继续在待刻蚀基底11上形成包括第一图案16的第一硬掩膜层13，第一图案16包括阵列排布的通孔131，以第一硬掩膜层13为掩膜刻蚀上述待刻蚀基底11，形成电容孔11a，因为第一硬掩膜层13的边缘区域S1并未形成通孔131，所以边缘区域S1则未形成电容孔11a，之后在电容孔11a上沉积下电极层14，并逐层去除待刻蚀基底11，并依次形成电容介质层和上电极层。本实施例通过不在晶圆1边缘区域S1设置电容结构，从而避免现有技术中边缘区域S1的电容结构因工艺原因倒塌而影响晶圆1整体良率，进而提高电容器的生产品质和生产效率。
此外，通过去除边缘区域S1的第一支撑层111a，而避免后续在刻蚀牺牲层112时，边缘区域S1的第一支撑层111a因没有下电级14与下层支撑层111稳固连接而造成剥离，导致污染晶圆1。
继续参考图9和图13，待刻蚀基底11可以包括：在远离衬底10的方向上，依次形成的第二牺牲层112b、第二支撑层111b、第一牺牲层112a和第一支撑层111a，则逐层去除部分待刻蚀基底11的过程如图12所示，图12是本公开实施例提供的另一种电容器的制作方法的流程示意图，包括如下步骤：
S210、在第一支撑层111a内形成第一开口1111，以暴露出第一牺牲层112a；晶圆1的边缘区域S1的第一开口1111转移至第一牺牲层112a。
如图9、图13所示，待刻蚀基底11包括依次设置在晶圆1上的第二牺牲层112b、第二支撑层111b、第一牺牲层112a和第一支撑层111a，在逐层去除待刻蚀基底11的过程中，依照第一支撑层111a、第一牺牲层112a、第二支撑层111b和第二牺牲层112b的顺序依次进行去除操作。
需要注意的是，牺牲层112的材质包括氧化硅或BPSG，牺牲层112中可以掺杂有硼或磷，支撑层111的材质包括氮化硅、氮氧化硅、碳氮化硅中的任意一种或任意两种以上的组合。本实施例在去除待刻蚀基底11时，首先将第一支撑层111a内形成第一开口1111，如图13所示，图13是本公开实施例提供的在 第一支撑层111a上形成第一开口1111的结构示意图，图13中S2区域为图10中沿a-a'方向的截面，在对第一支撑层111a形成第一开口1111之前，通过干法刻蚀去除第一支撑层111a顶部的下电极层14。之后将第一支撑层111a开口，暴露出第一开口1111之下的第一牺牲层112a，晶圆1的边缘区域S1并未设置第一支撑层111a，则边缘区域S1的第一开口1111转移至第一牺牲层112a上。图14是本公开实施例提供的在第一支撑层111a上形成第一开口1111的对比例的结构示意图，图14中为边缘区域S1’未去除第一支撑层111a’的情形，则在图14中的第一支撑层111a’上形成第一开口1111’后，边缘区域S1’的第一开口1111’形成在第一支撑层111a’上，又因为在基于第一开口1111’对第一牺牲层112a’进行刻蚀时，边缘区域S1’第一支撑层111a’因缺少下电级层的连接而发生整体脱落。
S220、基于第一开口1111，采用湿法刻蚀的方式去除第一牺牲层112a。
图15是本公开实施例提供的基于第一开口1111去除第一牺牲层112a的结构示意图，本实施例基于第一开口1111，采用湿法刻蚀的方式去除图13所示的全部的第一牺牲层112a。
S230、于第二支撑层111b内形成第二开口1112，以暴露出第二牺牲层112b，第一开口1111与第二开口1112一一对应。
图16是本公开实施例提供的于第二支撑层111b内形成第二开口1112的结构示意图，本实施例基于第二开口1112，从而暴露处第二牺牲层112b，图15示出的第一开口1111与图16示出的第二开口1112一一对应。
S240、基于第二开口1112，采用湿法刻蚀的方式去除第二牺牲层112b。
图17是本公开实施例提供的基于第二开口1112去除第二牺牲层112b的结构示意图，本实施例基于第二开口1112，采用湿法刻蚀的方法去除图16上所示的第一牺牲层112a，至此将待刻蚀基底11全部刻蚀掉，可在此基础上，继续形成电容介质层和上电极层，从而形成完整的电容器结构。
本实施例提供的电容器的制作方法，因为在刻蚀电容孔11a之前，将边缘区域S1的第一支撑层111a去除，使得在对待刻蚀基底11进行刻蚀时，在第一支撑层111a内形成第一开口1111的时候，第一开口1111被转移至第一牺牲层112a上，则边缘区域S1不会产生第一支撑层111a的剥落情况。
图18是本公开实施例提供的另一种电容器的制作方法的流程示意图，在去除边缘区域S1的第一支撑层111a之后，在待刻蚀基底11上形成包括在中心区域S2具有第一图案16的第一硬掩膜层13的过程，可以包括如下步骤：
S310、形成第一硬掩膜层13，在第一硬掩膜层13上形成第一隔离侧壁图案13a。
图19是本公开实施例提供的在第一硬掩膜层13上形成第一隔离侧壁图案13a的结构示意图，在第一支撑层111a上形成一层第一硬掩膜层13，并在第一硬掩膜层13上形成第一隔离侧壁图案13a。上述第一隔离侧壁图案13a可以通过图案化工艺形成，在具体示例中，可采用包括但不限于自对准双重图案化工艺形成上述第一隔离侧壁图案13a。第一硬掩模层13可以包括单层或多层结构，其材料可以选自多晶硅、氧化硅、ACL或SOH等材料。
S320、在第一隔离侧壁图案13a上形成第二隔离层15，通过光刻工艺暴露中心区域S2的第二隔离层15，并对第二隔离层15进行刻蚀，形成第二隔离侧壁图案15a，边缘区域S1的第二隔离层15保留。
图20是本公开实施例提供的在第一隔离侧壁图案13a上形成第二隔离侧壁图案15a的结构示意图，在第一隔离侧壁图案13a上形成第二隔离层15，并通过光刻工艺仅在中心区域S2进行第二隔离侧壁图案15a的设置，边缘区域S1的第二隔离层15未被刻蚀，则边缘区域S1的第二隔离层15被保留。从而避免边缘区域S1在后续工艺中形成电容孔11a，进而有效防止因边缘区域S1具有电容结构时，在后续制程中电容结构倒塌对整体晶圆1良率的影响。
S330、第一隔离侧壁图案13a和第二隔离侧壁图案15a未重叠的地方形成第一图案16，以第一隔离侧壁图案13a和第二隔离侧壁图案15a为掩膜刻蚀，将第一图案16传输至第一硬掩膜层13，形成所述在中心区域S2具有第一图案16的第一硬掩膜层13。
如图21所示，图21是本公开实施例提供的第一隔离侧壁图案13a的俯视图，可知，第一隔离侧壁图案13a可以包括多个相互平行设置的第一条状结构131a，同理，如图22所示，图22是本公开实施例提供的第二隔离侧壁图案15a的俯视图，可知，第二隔离侧壁图案15a也可以包括多个相互平行设置的第二条状结构151a，可设定第一条状结构131a沿第一方向X延伸，第二条状结构 151a沿第二方向Y延伸，本实施例中第一方向X和第二方向Y相交，例如，第一方向X和第二方向Y夹角为60-120度。
将第一隔离侧壁图案13a和第二隔离侧壁图案15a叠加，得到图23所示结构，图23是本公开实施例提供的一种第一隔离侧壁图案13a和第二隔离侧壁图案15a的俯视图，则第一隔离侧壁图案13a和第二隔离侧壁图案15a未重叠的地方形成第一图案16。本实施例以第一隔离侧壁图案13a和第二隔离侧壁图案15a为掩膜将第一图案16转移至第一硬掩膜层13，得到如图6所示的结构，形成具有第一图案16的第一硬掩膜层13。同时，边缘区域S1的第二隔离层15因在步骤S320中未被刻蚀成第二隔离侧壁图案15a而整体覆盖在衬底10上，因此在以第一隔离侧壁图案13a和第二隔离侧壁图案15a为掩膜刻蚀第一硬掩膜层13时，边缘区域S1的第一硬掩膜层13未形成第一图案16。如图6所示，第一图案16包括阵列设置的通孔131。便于后续以第一硬掩膜层13为掩膜，形成与通孔131一一对应设置的电容孔11a。
本实施例具体对第一硬掩膜层13的第一图案16的形成过程进行详述，具体通过第一隔离侧壁图案13a和第二隔离侧壁图案15a叠加形成，并且在形成第二隔离侧壁图案15a时，保留边缘区域S1的第二隔离层15，避免边缘区域S1的第二隔离层15形成图案，从而避免边缘区域S1在后续工艺中形成电容孔11a，进而有效防止因边缘区域S1具有电容结构时，在后续制程中电容结构倒塌对整体晶圆1良率的影响。
图24是本公开实施例提供的另一种电容器的制作方法的流程示意图，在去除边缘区域S1的第一支撑层111a之后，在待刻蚀基底11上形成包括第一图案16的第一硬掩膜层13的过程，还可以包括如下步骤：
S410、形成第一硬掩膜层13，在第一硬掩膜层13上形成第一隔离侧壁图案13a。
S420、在第一隔离侧壁图案13a间填充缓冲层17，并在第一隔离侧壁图案13a和缓冲层17上沉积第二硬掩模层18。
S430、刻蚀部分第二硬掩模层18形成线性第二硬掩模图案18a，沉积第二隔离层15覆盖第二硬掩模层18及缓冲层17，第二隔离层15包括顶部表面151、底部表面152和侧壁153。
上述步骤S420和步骤S430即为在第一隔离侧壁图案13a上形成第二隔离层15的过程，具体的，在图19的基础上，在第一隔离侧壁图案13a上形成缓冲层17，如图25所示，图25是本公开实施例提供的在第一隔离侧壁图案13a间填充缓冲层17的结构示意图，在第一隔离侧壁图案13a上形成缓冲层17后，并对缓冲层17进行平坦化处理，使得缓冲层17仅存在于第一隔离侧壁图案13a内的第一条形结构131a之间的部分。在其它实施例中，平坦化后的缓冲层17也可以覆盖第一隔离侧壁图案13a的顶部。如图26所示，图26是本公开实施例提供的形成第二隔离层15的结构示意图，在缓冲层17上形成一层第二硬掩膜层18，并图案化第二硬掩膜层18形成线性第二硬掩模图案18a，本实施例中线性第二硬掩模图案18a的延伸方向同样按照第二方向Y进行延伸。在此基础上，在第二硬掩模层18上沉积第二隔离层15，则第二隔离层15完全覆盖线性第二硬掩模图案18a，从而第二隔离层15包括顶部表面151、底部表面152和侧壁153。
S440、在第二隔离层15上涂敷负性的第二光刻胶19。
S450、通过空白掩模版对所述晶圆1的边缘区域S1进行曝光，显影后边缘区域S1的第二光刻胶19保留。
在图26所示结构基础上，在第二隔离层15上涂覆负性的第二光刻胶19，如图27所示，图27是本公开实施例提供的第二隔离层15上涂敷负性的第二光刻胶19的结构示意图，在第二隔离层15上涂覆整层的负性的第二光刻胶19，并对边缘区域S1进行曝光(具体可以通过空白掩模版对晶圆1的边缘区域S1进行by shot曝光)，则边缘区域S1的第二光刻胶19被保留下来，中心区域S2的第二光刻胶19被去除。第二光刻胶19的厚度可以为50-200nm，其中，可以为80-120nm。
S460、通过刻蚀工艺去除中心区域S2的第二隔离层15的顶部表面151和底部表面152，保留侧壁153，形成第二隔离侧壁图案15a。
继续参考图20，具体的需对具有负性光刻胶的晶圆1整体涂布正性光刻胶，对芯片阵列区A2进行曝光、显影，暴露出芯片阵列区A2的第二隔离层15，由于边缘区域S1芯片上有负性光刻胶，因此刻蚀时，边缘区域S1芯片的第二隔离层15整体被保留下来，而中心区域S2的芯片阵列区A2的第二隔离层15被 刻蚀形成第二隔离侧壁图案15a。
上述步骤S440～S460即为通过光刻工艺暴露中心区域S2的第二隔离层15，并对第二隔离层15进行刻蚀，形成第二隔离侧壁图案15a的过程。如图28所示，图28是本公开实施例提供的形成第二隔离侧壁图案15a的结构示意图，通过刻蚀工艺去除中心区域S2的第二隔离层15的顶层表面151和底层表面152，仅保留侧壁153，形成了第二隔离侧壁图案15a。具体的是去除中心区域S2芯片阵列区A2的第二隔离层15的顶层表面151和底层表面152，形成第二隔离侧壁图案15a。需要注意的是，因为边缘区域S1的第二光刻胶19被保留，则对第二隔离层15进行刻蚀的过程中，边缘区域S1被刻蚀的图形转移至第二光刻胶19上，而未被转移至第二隔离层15，防止边缘区域S1形成电容结构，从而保证电容器制作环境的可靠性。
S470、第一隔离侧壁图案13a和第二隔离侧壁图案15a未重叠的地方形成第一图案16，以第一隔离侧壁图案13a和第二隔离侧壁图案15a为掩膜刻蚀，将第一图案16传输至第一硬掩膜层13，形成具有第一图案16的第一硬掩膜层13。
本实施例具体对第二隔离侧壁图案15a的具体过程进行详述，并且在形成第二隔离侧壁图案15a时，通过负性的第二光刻胶19保留边缘区域S1的第二隔离层15，避免边缘区域S1的第二隔离层15形成图案，从而避免了边缘区域S1的第二隔离层15的剥落的风险，有效保护电容器结构阵列。
本公开实施例还提供一种电容器阵列结构。图29是本公开实施例提供的一种电容器阵列结构的结构示意图，如图29所示，本公开实施例提供的电容器阵列结构由本公开任意实施例提供的电容器的制作方法制成，包括阵列设置的多个电容器2。本实施例中电容器阵列结构具有本公开任意实施例提供的电容器的制作方法具有的技术特征，具有本公开任意实施例提供的电容器的制作方法的有益效果。
基于同一构思，如图30所示，图30是本公开实施例提供的一种半导体存储器的结构示意图，本公开实施例还提供了一种半导体存储器，包括本公开任意实施例提供的电容器阵列结构3；此外，还包括晶体管层4，晶体管层4包括与电容器2一一对应设置的晶体管5，用于对电容器进行信号的写入和读取。
本领域技术人员在考虑说明书及实践的公开后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由下面的权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限制。
工业实用性
本公开的电容器的制作方法及电容器阵列结构、半导体存储器，在电容器的制作过程中，首先形成待刻蚀基底以制备电容孔，待刻蚀基底包括至少一层牺牲层和至少一层支撑层，牺牲层和支撑层交替设置，并且最顶层的为第一支撑层，晶圆包括中心区域和围绕中心区域的边缘区域，继续在待刻蚀基底上形成在中心区域具有第一图案的第一硬掩膜层，第一图案包括阵列排布的通孔，以第一硬掩膜层为掩膜刻蚀上述待刻蚀基底，形成电容孔，因为晶圆边缘区域的第一硬掩模层并未形成通孔，所以边缘区域则未形成电容孔，之后在电容孔上沉积下电极层，并逐层去除待刻蚀基底，并依次形成电容介质层和上电极层。本实施例通过不在晶圆边缘区域设置电容结构则边缘区域的膜层结构不会形成非完整(图案化)结构，从而避免边缘区域电容结构因工艺原因倒塌而影响晶圆整体良率，进而提高电容器的生产品质和生产效率。

Claims (15)

  1. 一种电容器的制作方法，其中，所述电容器的制作方法包括：
    提供一晶圆，所述晶圆包含多个阵列分布的芯片，所述芯片具有一相同衬底；在所述衬底上形成待刻蚀基底；所述待刻蚀基底包括至少一层牺牲层和至少一层支撑层；所述牺牲层和所述支撑层交替设置，且所述待刻蚀基底远离所述衬底的一侧为第一支撑层；
    所述晶圆包括中心区域和围绕所述中心区域的边缘区域；
    在所述待刻蚀基底上形成在中心区域具有第一图案的第一硬掩膜层；所述第一图案包括阵列排布的通孔；以所述第一硬掩膜层为掩膜刻蚀所述待刻蚀基底，形成电容孔；所述边缘区域未形成电容孔；
    在所述电容孔的底部和侧壁上沉积下电极层，并逐层去除部分所述待刻蚀基底；依次在所述下电极层上形成电容介质层和上电极层。
  2. 根据权利要求1所述的电容器的制作方法，其中，
    在由所述中心区域指向所述边缘区域的方向上，所述边缘区域的宽度小于或等于8mm。
  3. 根据权利要求1所述的电容器的制作方法，在所述衬底上形成待刻蚀基底后，还包括：
    去除所述边缘区域芯片的第一支撑层。
  4. 根据权利要求3所述的电容器的制作方法，其中，去除所述边缘区域芯片的第一支撑层，包括：
    通过光刻工艺暴露出所述边缘区域芯片的第一支撑层，刻蚀暴露的第一支撑层,形成暴露所述牺牲层的边缘区域。
  5. 根据权利要求4所述的电容器的制作方法，其中，通过光刻工艺暴露出所述边缘区域芯片的第一支撑层包括：
    在所述待刻蚀基底上涂敷正性的第一光刻胶；通过空白掩模版对所述晶圆的所述边缘区域进行曝光；显影、刻蚀后形成所述暴露牺牲层的边缘区域。
  6. 根据权利要求5所述的电容器的制作方法，其中，所述第一光刻胶的厚度为50nm～200nm。
  7. 根据权利要求1所述的电容器的制作方法，其中，所述待刻蚀基底包括：在远离所述衬底的方向上，依次形成第二牺牲层、第二支撑层、第一牺牲层和第一支撑层；
    逐层去除部分所述待刻蚀基底，包括：
    在所述第一支撑层内形成第一开口，以暴露出所述第一牺牲层；所述晶圆的边缘区域的第一开口转移至所述第一牺牲层；
    基于所述第一开口，去除所述第一牺牲层；
    于所述第二支撑层内形成第二开口，以暴露出所述第二牺牲层；
    基于所述第二开口，去除所述第二牺牲层；
    所述第一开口与所述第二开口一一对应。
  8. 根据权利要求1所述的电容器的制作方法，其中，在所述待刻蚀基底上形成在中心区域具有第一图案的第一硬掩膜层，包括：
    形成第一硬掩膜层，在所述第一硬掩膜层上形成第一方向的第一隔离侧壁图案；
    在所述第一隔离侧壁图案上形成第二隔离层，通过光刻工艺暴露中心区域芯片的所述第二隔离层，并对所述第二隔离层进行刻蚀，形成第二方向的第二隔离侧壁图案，所述边缘区域芯片的第二隔离层保留；
    所述第一隔离侧壁图案和所述第二隔离侧壁图案未重叠的地方形成所述第一图案，以所述第一隔离侧壁图案和第二隔离侧壁图案为掩膜刻蚀，将所述第一图案传输至第一硬掩膜层，形成所述在中心区域具有第一图案的第一硬掩膜层。
  9. 根据权利要求8所述的电容器的制作方法，其中，
    所述第一硬掩膜层包括单层或多层结构。
  10. 根据权利要求8所述的电容器的制作方法，其中，
    通过图案化工艺形成所述第一隔离侧壁图案。
  11. 根据权利要求8所述的电容器的制作方法，其中，在所述第一隔离侧壁图案上形成第二隔离层包括：
    在所述第一隔离侧壁图案间填充缓冲层，并在所述第一隔离侧壁图案和所述缓冲层上沉积第二硬掩模层；刻蚀部分所述第二硬掩模层形成线性第二硬掩模图案，沉积第二隔离层覆盖所述第二硬掩模层及所述缓冲层，所述第二隔离层包括顶部表面、底部表面和连接顶部表面及底部表面的侧壁。
  12. 根据权利要求11所述的电容器的制作方法，其中，通过光刻工艺暴露中心区域的所述第二隔离层，并对所述第二隔离层进行刻蚀，形成第二隔离侧壁图案，包括：在所述第二隔离层上涂敷负性的第二光刻胶，通过空白掩模版对所述晶圆的边缘区域进行曝光，显影后所述边缘区域的所述第二光刻胶保留；通过刻蚀工艺去除中心区域的所述第二隔离层的顶部表面和底部表面，保留侧壁，形成所述第二隔离侧壁图案。
  13. 根据权利要求12所述的电容器的制作方法，其中，
    所述第二光刻胶的厚度为50-200nm。
  14. 一种电容器阵列结构，其中，由上述权利要求1-13任一项所述的电容器的制作方法制成。
  15. 一种半导体存储器，其中，包括；权利要求14所述的电容器阵列结构；
    晶体管层，所述晶体管层包括与所述电容器一一对应设置的晶体管。
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