WO2022188310A1 - 半导体结构制作方法及半导体结构 - Google Patents

半导体结构制作方法及半导体结构 Download PDF

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WO2022188310A1
WO2022188310A1 PCT/CN2021/103733 CN2021103733W WO2022188310A1 WO 2022188310 A1 WO2022188310 A1 WO 2022188310A1 CN 2021103733 W CN2021103733 W CN 2021103733W WO 2022188310 A1 WO2022188310 A1 WO 2022188310A1
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pattern transfer
layer
transfer layer
semiconductor structure
film
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PCT/CN2021/103733
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English (en)
French (fr)
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邵波
刘欣然
王春阳
孙玉乐
李振兴
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长鑫存储技术有限公司
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Priority to US17/593,851 priority Critical patent/US20230238249A1/en
Publication of WO2022188310A1 publication Critical patent/WO2022188310A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto

Definitions

  • Embodiments of the present application relate to the technical field of semiconductor manufacturing, and in particular, to a method for fabricating a semiconductor structure and a semiconductor structure.
  • the dynamic random access memory includes a capacitor structure and a transistor structure, the capacitor structure is connected with the transistor structure, and the data stored in the capacitor structure can be read through the transistor structure.
  • the capacitor structure includes a substrate and a dielectric layer disposed on the substrate, the dielectric layer is provided with a capacitor hole, and a capacitor tube is disposed in the capacitor hole.
  • a dielectric layer is first formed on the substrate, and a pattern transfer layer is formed on the dielectric layer.
  • the pattern transfer layer has holes, and the dielectric layer is etched along the holes by dry etching to form capacitor holes in the dielectric layer.
  • the top surface of the pattern transfer layer away from the substrate is relatively rough.
  • the rough top surface is likely to cause ion scattering, resulting in poor dimensional accuracy of the formed capacitor holes and affecting the capacitance of the capacitor structure. performance.
  • an embodiment of the present application provides a method for fabricating a semiconductor structure, including:
  • the film structure comprising a dielectric layer
  • the film layer structure is etched through the holes to form capacitor holes in the film layer structure.
  • an embodiment of the present application further provides a semiconductor structure, which is manufactured by the above-mentioned method for fabricating a semiconductor structure.
  • a film layer structure is formed on a substrate, the film layer structure includes a dielectric layer, a pattern transfer layer is formed on the film layer structure, and multiple definitions are defined on the pattern transfer layer.
  • a hole is formed, and the pattern transfer layer is planarized; the film structure is etched through the holes to form capacitor holes in the film structure; before the capacitor holes are formed, the top surface of the pattern transfer layer is flattened.
  • the flat top surface of the pattern transfer layer can avoid ion scattering, thereby avoiding bulging on the sidewall of the formed capacitor hole or tilting of the capacitor hole, improving the dimensional accuracy of the capacitor hole and improving the performance of the capacitor structure.
  • FIG. 1 is a flowchart of a method for fabricating a semiconductor structure provided by an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a semiconductor structure fabrication method provided by an embodiment of the present application after forming a second pattern transfer layer;
  • Fig. 3 is the partial enlarged view of A place in Fig. 2;
  • FIG. 4 is a schematic structural diagram of the semiconductor structure fabrication method provided by the embodiment of the present application after forming the holes;
  • FIG. 5 is a schematic structural diagram of the top surface of the pattern transfer layer after planarization processing is performed in the method for fabricating a semiconductor structure provided by an embodiment of the present application;
  • FIG. 6 is a schematic structural diagram of a semiconductor structure fabrication method provided by an embodiment of the present application after a capacitor hole is formed.
  • capacitor hole capacitor hole
  • 30 first pattern transfer layer
  • DRAM Dynamic Random Access Memory
  • DRAM generally includes a capacitor structure and a transistor structure.
  • the capacitor structure is connected to the transistor structure, and the data stored in the capacitor structure can be read through the transistor structure.
  • the capacitor structure includes a substrate and a dielectric layer disposed on the substrate, the dielectric layer is provided with a capacitor hole, and a capacitor tube is disposed in the capacitor hole.
  • a dielectric layer is first formed on the substrate, and a pattern transfer layer is formed on the dielectric layer.
  • the pattern transfer layer has holes, and the dielectric layer is etched along the holes by dry etching to form capacitor holes in the dielectric layer.
  • the top surface of the pattern transfer layer away from the substrate is relatively rough.
  • the rough top surface is likely to cause ion scattering, which may easily lead to the bending of the capacitor hole or the unevenness of the inner wall of the capacitor hole, making the The formed capacitor holes have poor dimensional accuracy, which affects the performance of the capacitor structure.
  • Embodiments of the present application provide a method for fabricating a semiconductor structure and a semiconductor structure. After the pattern transfer layer is formed, the top surface of the pattern transfer layer away from the substrate is planarized, so that ion scattering is avoided during etching, and the formation of The dimensional accuracy of the capacitor hole is improved, thereby improving the performance of the capacitor structure.
  • the method for fabricating a semiconductor structure includes:
  • the substrate 10 serves as the base of the semiconductor structure for supporting other layers formed in subsequent steps.
  • the material of the substrate 10 may include silicon nitride or the like, and the material of the substrate 10 is not limited in this embodiment.
  • the method for fabricating the semiconductor structure provided in this embodiment further includes:
  • the specific steps of fabricating the film layer structure 20 may include: sequentially stacking a dielectric layer 202 and a top film layer 201 on the substrate 10 .
  • the top film layer 201 is located on the side of the dielectric layer 202 away from the substrate 10 , and the material of the top film layer 201 may include titanium nitride or the like.
  • the dielectric layer 202 may include a first dielectric layer 203 , an intermediate film layer 204 and a second dielectric layer 205 that are sequentially stacked on the substrate 10 . That is, the intermediate film layer 204 is located between the first dielectric layer 203 and the second dielectric layer 205 , and the first dielectric layer 203 is disposed close to the substrate 10 , and the second dielectric layer 205 is disposed close to the top film layer 201 .
  • the material of the first dielectric layer 203 may include oxides such as silicon oxide
  • the material of the intermediate film layer 204 may include titanium nitride or the like
  • the material of the second dielectric layer 205 may also include oxides such as silicon oxide.
  • the bottom surface of the first dielectric layer 203 is bonded to the substrate 10
  • the top surface of the first dielectric layer 203 is bonded to the bottom surface of the intermediate film layer 204
  • the top surface of the intermediate film layer 204 is bonded to the bottom surface of the second dielectric layer 205 . Bonding, the top surface of the second dielectric layer 205 is bonded to the top film layer 201 ;
  • the materials of the middle film layer 204 and the top film layer 201 may be the same, so as to reduce the types of materials constituting the film layer structure 20 and facilitate the fabrication of the film layer structure 20 .
  • both the middle film layer 204 and the top film layer 201 may be titanium nitride layers composed of titanium nitride.
  • first dielectric layer 203 and the second dielectric layer 205 may be the same, so as to further reduce the types of materials constituting the membrane structure 20 and facilitate the fabrication of the membrane structure 20 .
  • first dielectric layer 203 and the second dielectric layer 205 may be oxide layers composed of oxides, such as silicon oxide or the like.
  • the method for fabricating the semiconductor structure provided in this embodiment further includes:
  • the plurality of holes 301 defined on the pattern transfer layer may be formed by etching; for example, a photolithography layer may be formed on the pattern transfer layer first, and the photolithography layer may be masked. Film, exposure and other processes are used to form an etching pattern on the photoresist layer; then, the pattern transfer layer is etched by using the photoresist layer as a mask to form holes 301 on the pattern transfer layer.
  • the holes 301 in this embodiment can also be formed in other ways, and this embodiment is not limited to the sequence.
  • the method for fabricating the semiconductor structure provided in this embodiment further includes:
  • S104 Perform a planarization process on the top surface of the pattern transfer layer away from the substrate.
  • the planarization process can make the top surface of the pattern transfer layer away from the substrate 10 flat, so as to facilitate the subsequent process.
  • the top surface of the pattern transfer layer away from the substrate 10 may be processed by chemical mechanical polishing (CMP), so that the top surface of the pattern transfer layer is relatively flat.
  • CMP chemical mechanical polishing
  • the planarization of the pattern transfer layer in this embodiment is not limited to chemical mechanical polishing, and other methods may also be used to planarize the pattern transfer layer.
  • the method for fabricating the semiconductor structure provided in this embodiment further includes:
  • the film layer structure 20 is etched along the hole 301 to form the capacitor hole 206 .
  • a plurality of conductive regions 101 can be formed on the substrate 10 , and after the capacitor holes 206 are formed, the bottom of each capacitor hole 206 can extend into the substrate 10 and be combined with one conductive region 101 .
  • a capacitor plate is formed in the capacitor hole 206, and the capacitor plate can be connected to the conduction region 101 to form a capacitance structure of the dynamic random access memory.
  • the transistor structure of the dynamic random access memory can pass through the conduction region 101 and the capacitance structure.
  • the corresponding capacitor plates in the capacitor are connected to read data in the capacitor structure or write data into the capacitor structure.
  • the film layer structure 20 may be etched through the hole 301 by dry etching, so as to form the capacitor hole 206 in the film layer structure 20 .
  • the capacitor holes 206 are formed by dry etching, which simplifies the fabrication of the capacitor holes 206 .
  • FIGS. 3-6 when the first pattern transfer layer 30 is formed, protrusions 303 and depressions 302 are easily formed on the top surface of the first pattern transfer layer 30, so that the top surface of the first pattern transfer layer 30 is relatively rough; Before etching, the top surface of the pattern transfer layer can be flattened to make the top surface of the pattern transfer layer relatively flat; compared with the rough top surface, in the process of dry etching, ions can be avoided in the pattern transfer.
  • the top surface of the layer compared with the rough top surface of the pattern transfer layer, the top surface of the film structure 20 at the edge of the capacitor hole 206 caused by ion scattering can be prevented from being damaged during etching, thereby making the top surface of the film structure 20 away from the substrate 10 relatively flat , to further improve the performance of the capacitor structure.
  • a film layer structure 20 is formed on the substrate 10, the film layer structure 20 includes a dielectric layer 202, a pattern transfer layer is formed on the film layer structure 20, and a plurality of holes 301 are defined on the pattern transfer layer, and The pattern transfer layer is planarized; after that, the film structure 20 is etched through the holes 301 to form capacitor holes 206 in the film structure 20 ; before the capacitor holes 206 are formed, the top surface of the pattern transfer layer is planarized In the process of etching, the flat top surface of the pattern transfer layer can avoid ion scattering, thereby avoiding bulging on the sidewalls of the formed capacitor holes 206 or tilting of the capacitor holes 206, which improves the dimensional accuracy of the capacitor holes 206 and improves the performance of the capacitor structure.
  • a pattern transfer layer is formed on the film layer structure 20 , and the specific steps of defining a plurality of holes 301 on the pattern transfer layer include:
  • a first pattern transfer layer 30 and a second pattern transfer layer 40 are sequentially formed on the film layer structure 20, and the second mask layer has a hole pattern 401; then the hole pattern 401 is transferred to the first pattern transfer layer 30 , to form the hole 301 .
  • the first pattern transfer layer 30 may be a polysilicon layer composed of polysilicon, and the second pattern transfer layer 40 may also be an oxide layer composed of oxide. In this embodiment, the first pattern transfer layer 30 and the second pattern transfer layer The material of the layer 40 is not limited.
  • the first pattern transfer layer 30 and the second pattern transfer layer 40 are formed by stacking on the film layer structure 20 in sequence, and the hole pattern 401 on the second pattern transfer layer 40 includes: etching the second pattern transfer layer 40, To form a predetermined hole, the predetermined hole extends into the first pattern transfer layer 30 . The predetermined hole extends into the first pattern transfer layer 30 , which can reduce the depth requirement for etching the second pattern transfer layer 40 , thereby simplifying the fabrication difficulty of the semiconductor structure.
  • a first photolithography layer may be formed on the second pattern transfer layer 40, and then processes such as masking, exposing, etc. are performed on the first photolithography layer, so that the first photoresist layer is A first etching pattern is formed on the etching layer, and then the second pattern transfer layer 40 is etched by using the first photoresist layer as a mask to form a hole pattern 401 composed of predetermined holes.
  • the specific step of transferring the hole pattern 401 to the first pattern transfer layer 30 may include, after the hole pattern 401 is formed on the second pattern transfer layer 40 , a second light pattern may be formed on the second pattern transfer layer 40 . Then, the second lithography layer is subjected to processes such as masking and exposing to form a second etching pattern on the second lithography layer.
  • the projection of the second etch pattern on the substrate 10 can be the same as that of the first etch pattern on the substrate.
  • the projection on the substrate 10 is completely coincident, and then the second lithography layer is used as a mask to etch to the substrate 10 to form the hole 301; since the projection of the second etching pattern on the substrate 10 is completely the same as the projection of the first etching pattern on the substrate 10 By overlapping, the formed holes 301 and the hole pattern 401 are directly opposite, and then the hole pattern 401 is transferred to the first pattern transfer layer 30 .
  • the first pattern transfer layer 30 may be etched to the substrate 10 by using the second pattern transfer layer 40 as a mask, or the holes may be etched into the substrate 10.
  • the mold pattern 401 is transferred to the first pattern transfer layer 30 , thereby forming the hole 301 .
  • transferring the hole pattern 401 to the first pattern transfer layer 30 to form the hole 301 further includes: the hole 301 extends into the film structure 20 .
  • the specific steps of planarizing the top surface of the pattern transfer layer away from the substrate 10 include: removing the second pattern transfer layer 40 , and removing the first pattern transfer layer 30 away from the substrate 10 .
  • the top surface of the substrate 10 is planarized.
  • the second pattern transfer layer 40 may be removed by chemical mechanical polishing (CMP), and the top surface of the first pattern transfer layer 30 away from the substrate 10 may be planarized by chemical mechanical polishing.
  • CMP chemical mechanical polishing
  • the fabrication is simple and the top surface of the first pattern transfer layer 30 is relatively flat after processing.
  • an embodiment of the present application further provides a semiconductor structure, which is manufactured by the method for fabricating the semiconductor structure in the above-mentioned embodiment.
  • the semiconductor structure may be a capacitor structure in a dynamic random access memory, and the dynamic random access memory further includes a transistor structure connected to the capacitor structure, and the data stored in the capacitor structure can be read through the transistor structure, or the data stored in the capacitor structure can be written through the transistor structure. data.
  • a film structure 20 is formed on the substrate 10, the film structure 20 includes a dielectric layer 202, a pattern transfer layer is formed on the film structure 20, and a plurality of holes 301 are defined on the pattern transfer layer.
  • the pattern transfer layer is planarized; after that, the film layer structure 20 is etched through the holes 301 to form capacitor holes 206 in the film layer structure 20; before the capacitor holes 206 are formed, the top surface of the pattern transfer layer is flattened During the etching process, the flat top surface of the pattern transfer layer can avoid ion scattering, thereby avoiding bulging on the sidewall of the formed capacitor hole 206 or tilting of the capacitor hole 206, which improves the dimensional accuracy of the capacitor hole 206. The performance of the capacitor structure is improved.

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Abstract

一种半导体结构制作方法及半导体结构，该半导体结构制作方法包括：在基底（10）上形成膜层结构（20），在膜层结构（20）上形成第一图形转移层（30），第一图形转移层（30）上定义多个孔洞（301），并对第一图形转移层（30）进行平坦化处理；通过孔洞（301）蚀刻膜层结构（20），以在膜层结构（20）中形成电容孔洞（206）；在形成电容孔洞（206）之前，对第一图形转移层（30）的顶面进行了平坦化处理，在进行蚀刻的过程中，平坦的第一图形转移层（30）顶面可以避免发生离子散射，进而避免形成的电容孔洞（206）侧壁出现鼓包、或者电容孔洞（206）倾斜，提高了电容孔洞（206）的尺寸精度，提高了电容结构的性能。

Description

半导体结构制作方法及半导体结构
本申请要求于2021年03月12日提交中国专利局，申请号为202110269758.5，申请名称为“半导体结构制作方法及半导体结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及半导体制造技术领域，尤其涉及一种半导体结构制作方法及半导体结构。
背景技术
随着存储设备技术的逐渐发展，动态随机存储器(Dynamic Random Access Memory，简称DRAM)以其较高的密度以及较快的读写速度逐渐应用在各种电子设备中。动态随机存储器包括电容结构和晶体管结构，电容结构与晶体管结构连接，通过晶体管结构可以读取电容结构内存储的数据。
相关技术中，电容结构包括基底以及设置在基底上的介质层，介质层上设置有电容孔洞，电容孔洞内设置有电容管。制作时，先在基底上形成介质层，并在介质层上形成图形转移层，图形转移层上具有孔洞，通过干法蚀刻的方式沿孔洞蚀刻介质层，以在介质层中形成电容孔洞。
然而，在形成图形转移层时，图形转移层背离基底的顶面较为粗糙，在蚀刻介质层的过程中，粗糙的顶面容易造成离子散射，使得形成的电容孔洞尺寸精度差，影响电容结构的性能。
发明内容
第一方面，本申请实施例提供了一种半导体结构制作方法，包括：
提供基底；
在所述基底上形成膜层结构，所述膜层结构包括介质层；
在所述膜层结构上形成图形转移层，所述图形转移层上定义多个孔洞；
对所述图形转移层背离所述基底的顶面进行平坦化处理；
通过所述孔洞蚀刻所述膜层结构，以在所述膜层结构中形成电容孔洞。
第二方面，本申请实施例还提供一种半导体结构，通过如上所述的半导体结构制作方法制得。
结合上述技术方案，本申请实施例提供的半导体结构制作方法及半导体结构，在基底上形成膜层结构，膜层结构包括介质层，在膜层结构上形成图形转移层，图形转移层上定义多个孔洞，并对图形转移层进行平坦化处理；通过孔洞蚀刻膜层结构，以在膜层结构中形成电容孔洞；在形成电容孔洞之前，对图形转移层的顶面进行了平坦化处理，在进行蚀刻的过程中，平坦的图形转移层顶面可以避免发生离子散射，进而避免形成的电容孔洞侧壁出现鼓包、或者电容孔洞倾斜，提高了电容孔洞的尺寸精度， 提高了电容结构的性能。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的半导体结构制作方法的流程图；
图2为本申请实施例提供的半导体结构制作方法中形成第二图形转移层后的结构示意图；
图3为图2中A处的局部放大图；
图4为本申请实施例提供的半导体结构制作方法中在形成孔洞后的结构示意图；
图5为本申请实施例提供的半导体结构制作方法中对图形转移层的顶面进行平坦化处理后的结构示意图；
图6为本申请实施例提供的半导体结构制作方法中形成电容孔洞后的结构示意图。
附图标记说明：
10：基底；                     101：导通区；
20：膜层结构；                 201：顶部膜层；
202：介质层；                  203：第一介质层；
204：中间膜层；                205：第二介质层；
206：电容孔洞；                30：第一图形转移层；
301：孔洞；                    302：凹陷；
303：凸起；                    40：第二图形转移层；
401：孔型图案。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
动态随机存储器(Dynamic Random Access Memory，简称DRAM)一般包括电容结构和晶体管结构，电容结构与晶体管结构连接，通过晶体管结构可以读取电容结构内存储的数据。
相关技术中，电容结构包括基底以及设置在基底上的介质层，介质层上设置有电容孔洞，电容孔洞内设置有电容管。制作时，先在基底上形成介质层，并在介质层上形成图形转移层，图形转移层上具有孔洞，通过干法蚀刻的方式沿孔洞蚀刻介质层，以在介质层中形成电容孔洞。
然而，在形成图形转移层时，图形转移层背离基底的顶面较为粗糙，在蚀刻介质层的过程中，粗糙的顶面容易造成离子散射，容易导致电容孔洞弯曲或者电容孔洞内 壁凸凹不平，使得形成的电容孔洞尺寸精度差，影响电容结构的性能。
本申请实施例提供一种半导体结构制作方法及半导体结构，通过在形成图形转移层后，对图形转移层背离基底的顶面进行平坦化处理，进而在进行蚀刻时，避免离子散射，提高了形成的电容孔洞尺寸精度，进而提高了电容结构的性能。
请参照图1，本实施例提供的半导体结构制作方法包括：
S101：提供基底。
请参照图2，基底10作为半导体结构的基础，用于支撑后续步骤中形成的其他膜层。基底10的材质可以包括氮化硅等，本实施例对基底10的材质不作限制。
在形成基底10之后，本实施例提供的半导体结构制作方法还包括：
S102：在基底上形成膜层结构，膜层结构包括介质层。
继续参照图2，示例性的，制作膜层结构20的具体步骤可以包括：在基底10上依次堆叠形成介质层202和顶部膜层201。其中，顶部膜层201位于介质层202背离基底10的一侧，顶部膜层201的材质可以包括氮化钛等。
进一步地，介质层202可以包括在基底10上依次堆叠形成的第一介质层203、中间膜层204以及第二介质层205。也就是说，中间膜层204位于第一介质层203和第二介质层205之间，并且第一介质层203靠近基底10设置，第二介质层205靠近顶部膜层201设置。
其中，第一介质层203的材质可以包括氧化硅等氧化物，中间膜层204的材质可以包括氮化钛等，第二介质层205的材质也可以包括氧化硅等氧化物。
在一些实施例中，第一介质层203的底面与基底10接合，第一介质层203的顶面与中间膜层204的底面接合，中间膜层204的顶面与第二介质层205的底面接合，第二介质层205的顶面与顶部膜层201接合；使得第一介质层203、中间膜层204、第二介质层205以及顶部膜层201构成膜层结构20。
在上述实现方式中，中间膜层204和顶部膜层201的材质可以相同，以减少构成膜层结构20的材料种类，以便于膜层结构20的制作。示例性的，中间膜层204和顶部膜层201的可以均为由氮化钛构成的氮化钛层。
进一步地，第一介质层203和第二介质层205的材质可以相同，以进一步减少构成膜层结构20的材料种类，以便于膜层结构20的制作。示例性的，第一介质层203和第二介质层205可以均由氧化物构成的氧化物层，如氧化硅等。
本实施例提供的半导体结构制作方法在形成膜层结构20之后还包括：
S103：在膜层结构上形成图形转移层，图形转移层上定义多个孔洞。
请参照图3，本实施例中，图形转移层上定义的多个孔洞301，可以通过蚀刻的方式形成；示例性的，可以先在图形转移层上形成光刻层，对光刻层进行掩膜、曝光等工艺，以在光刻层上形成蚀刻图形；之后以光刻层为掩膜蚀刻图形转移层，以在图形转移层上形成孔洞301。当然，本实施例中的孔洞301还可以通过其他的方式形成，本实施例并不依次为限。
在形成图形转移层之后，本实施提供的半导体结构制作方法还包括：
S104：对图形转移层背离基底的顶面进行平坦化处理。
如图5所示，平坦化处理可以使图形转移层背离基底10的顶面变得平坦，以利于 后续工艺的进行。示例性的，可以通过化学机械抛光(CMP)的方法对图形转移层背离基底10的顶面进行处理，以使得图形转移层的顶面较为平坦。当然本实施例中对图形转移层进行平坦化处理并不限于化学机械抛光，还可以采用其他的方式对图形转移层进行平坦化处理。
在对图形转移层进行平坦化处理之后，本实施例提供的半导体结构制作方法还包括：
S105：通过孔洞蚀刻膜层结构，以在膜层结构中形成电容孔洞206。
请参照图6，其中，沿孔洞301蚀刻膜层结构20，以形成电容孔洞206，电容孔洞206的底部向基底10延伸，电容孔洞206的底部可以与基底10接触。进一步地，在形成基底10时，可以在基底10上形成多个导通区101，在形成电容孔洞206之后，每一电容孔洞206的底部可以延伸至基底10内并与一个导通区101结合。在后续过程中，在电容孔洞206内形成电容极板，电容极板可以与导通区101连接，以形成动态随机存储器的电容结构，动态随机存储器的晶体管结构可以通过导通区101与电容结构中对应的电容极板连接，以实现电容结构中数据的读取或者向电容结构中写入数据。
本实施例中，可以采用干法蚀刻的方式通过孔洞301蚀刻膜层结构20，以在膜层结构20中形成电容孔洞206。通过干法蚀刻的方式形成电容孔洞206，简化了电容孔洞206的制作难度。如图3-图6所示，在形成第一图形转移层30时，第一图形转移层30的顶面容易形成凸起303和凹陷302，使得第一图形转移层30的顶面较为粗糙；在进行蚀刻之前，对图形转移层的顶面进行平坦化处理，可以使得图形转移层的顶面较为平坦；与粗糙的顶面相比，在进行干法蚀刻的过程中，可以避免离子在图形转移层顶面发生散射，进而避免形成的电容孔洞206侧壁出现鼓包、或者电容孔倾斜等问题，提高了电容孔洞206的尺寸精度，提高了电容结构的性能。另外，与粗糙的图形转移层顶面相比，在进行蚀刻时还可以避免离子散射引起的电容孔洞206边缘的膜层结构20顶面损伤，进而使得膜层结构20背离基底10的顶面较为平坦，以进一步提高电容结构的性能。
本实施提供的半导体结构制作方法，在基底10上形成膜层结构20，膜层结构20包括介质层202，在膜层结构20上形成图形转移层，图形转移层上定义多个孔洞301，并对图形转移层进行平坦化处理；之后，通过孔洞301蚀刻膜层结构20，以在膜层结构20中形成电容孔洞206；在形成电容孔洞206之前，对图形转移层的顶面进行了平坦化处理，在进行蚀刻的过程中，平坦的图形转移层顶面可以避免发生离子散射，进而避免形成的电容孔洞206侧壁出现鼓包、或者电容孔洞206倾斜，提高了电容孔洞206的尺寸精度，提高了电容结构的性能。
继续参照图2-图4，本实施例提供的半导体结构制作方法，在膜层结构20上形成图形转移层，图形转移层上定义多个孔洞301的具体步骤包括：
在膜层结构20上依次堆叠形成第一图形转移层30和第二图形转移层40，第二掩膜层上具有孔型图案401；之后将孔型图案401转移至第一图形转移层30上，以形成孔洞301。
其中，第一图形转移层30可以为由多晶硅构成的多晶硅层，第二图形转移层40也可为由氧化物构成的氧化物层，本实施例对第一图形转移层30和第二图形转移层 40的材质不做限制。
本实施例中，在膜层结构20上依次堆叠形成第一图形转移层30和第二图形转移层40，第二图形转移层40上具有孔型图案401包括：蚀刻第二图形转移层40，以形成预设孔，预设孔延伸至第一图形转移层30内。预设孔延伸至第一图形转移层30内，可以降低蚀刻第二图形转移层40的深度要求，进而简化半导体结构的制作难度。
示例性的，在形成第二图形转移层40之后，可以在第二图形转移层40上形成第一光刻层，之后对第一光刻层进行掩膜、曝光等工艺，以在第一光刻层上形成第一蚀刻图案，之后以第一光刻层为掩膜蚀刻第二图形转移层40，以形成由预设孔构成的孔型图案401。
进一步地，将孔型图案401转移至第一图形转移层30的具体步骤可以包括，在第二图形转移层40上形成孔型图案401后，可以在第二图形转移层40上形成第二光刻层，之后对第二光刻层进行掩膜、曝光等工艺，以在第二光刻层上形成第二蚀刻图案，第二蚀刻图案在基底10上的投影可以与第一蚀刻图案在基底10上的投影完全重合，之后以第二光刻层为掩膜向基底10蚀刻，以形成孔洞301；由于第二蚀刻图案在基底10上的投影与第一蚀刻图案在基底10上的投影完全重合，使得形成的孔洞301与孔型图案401正对，进而将孔型图案401转移至第一图形转移层30上。当然在其他的实现方式中，在形成第二图形转移层40上形成孔型图案401之后，可以以第二图形转移层40为掩膜向基底10蚀刻第一图形转移层30，也可以将孔型图案401转移至第一图形转移层30上，进而形成孔洞301。
本实施例中，将孔型图案401转移至第一图形转移层30上，以形成孔洞301还包括：孔洞301延伸至膜层结构20内。如此设置，可以降低蚀刻第一图形转移层30的深度要求，进而简化半导体结构的制作难度。
请照图4和图5，在上述实现方式中，对图形转移层背离基底10的顶面进行平坦化处理的具体步骤包括：去除第二图形转移层40，并对第一图形转移层30背离基底10的顶面进行平坦化处理。
具体地，可以通过化学机械抛光(CMP)的方式去除第二图形转移层40，并对第一图形转移层30背离基底10的顶面进行平坦化处理，通过化学机械抛光的方式进行平坦化处理，制作简单并且处理后第一图形转移层30的顶面较为平坦。
继续参照图2-图6，本申请实施例还提供一种半导体结构，通过上述实施例中的半导体结构制作方法制得。
其中，半导体结构可以为动态随机存储器中的电容结构，动态随机存储器还包括与电容结构连接的晶体管结构，通过晶体管结构可以读取电容结构内存储的数据，或者通过晶体管结构向电容结构内写入数据。
本实施提供的半导体结构，制作时，在基底10上形成膜层结构20，膜层结构20包括介质层202，在膜层结构20上形成图形转移层，图形转移层上定义多个孔洞301，并对图形转移层进行平坦化处理；之后，通过孔洞301蚀刻膜层结构20，以在膜层结构20中形成电容孔洞206；在形成电容孔洞206之前，对图形转移层的顶面进行了平坦化处理，在进行蚀刻的过程中，平坦的图形转移层顶面可以避免发生离子散射，进 而避免形成的电容孔洞206侧壁出现鼓包、或者电容孔洞206倾斜，提高了电容孔洞206的尺寸精度，提高了电容结构的性能。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (15)

  1. 一种半导体结构制作方法，包括：
    提供基底；
    在所述基底上形成膜层结构，所述膜层结构包括介质层；
    在所述膜层结构上形成图形转移层，所述图形转移层上定义多个孔洞；
    对所述图形转移层背离所述基底的顶面进行平坦化处理；
    通过所述孔洞蚀刻所述膜层结构，以在所述膜层结构中形成电容孔洞。
  2. 根据权利要求1所述的半导体结构制作方法，其中，在所述膜层结构上形成图形转移层，所述图形转移层上定义多个孔洞包括：
    在所述膜层结构上依次堆叠形成第一图形转移层和第二图形转移层，所述第二图形转移层上具有孔型图案；
    将所述孔型图案转移至所述第一图形转移层上，以形成孔洞。
  3. 根据权利要求2所述的半导体结构制作方法，其中，对所述图形转移层背离所述基底的顶面进行平坦化处理包括：
    去除所述第二图形转移层，并对所述第一图形转移层背离所述基底的顶面进行平坦化处理。
  4. 根据权利要求3所述的半导体结构制作方法，其中，去除所述第二图形转移层，并对所述第一图形转移层背离所述基底的顶面进行平坦化处理包括：
    通过化学机械抛光的方法去除所述第二图形转移层，并且对所述第一图形转移层背离所述基底的顶面进行平坦化处理。
  5. 根据权利要求2所述的半导体结构制作方法，其中，所述第一图形转移层为多晶硅层，所述第二图形转移层为氧化物层。
  6. 根据权利要求2所述的半导体结构制作方法，其中，在所述膜层结构上依次堆叠形成第一图形转移层和第二图形转移层，所述第二图形转移层上具有孔型图案：
    蚀刻所述第二图形转移层，以形成预设孔，所述预设孔延伸至所述第一图形转移层内。
  7. 根据权利要求2所述的半导体结构制作方法，其中，将所述孔型图案转移至所述第一图形转移层上，以形成孔洞还包括：
    所述孔洞延伸至所述膜层结构内。
  8. 根据权利要求1所述的半导体结构制作方法，其中，在所述基底上形成膜层结构，所述膜层结构包括介质层包括：
    在所述基底上依次堆叠形成介质层和顶部膜层。
  9. 根据权利要求8所述的半导体结构制作方法，其中，所述介质层包括：在所述基底上依次堆叠形成的第一介质层、中间膜层以及第二介质层。
  10. 根据权利要求9所述的半导体结构制作方法，其中，所述中间膜层和所述顶部膜层的材质相同。
  11. 根据权利要求10所述的半导体结构制作方法，其中，所述中间膜层和所述顶部膜层均为氮化钛层。
  12. 根据权利要求9所述的半导体结构制作方法，其中，所述第一介质层和所述第 二介质层的材质相同。
  13. 根据权利要求12所述的半导体结构制作方法，其中，所述第一介质层和所述第二介质层均为氧化物层。
  14. 根据权利要求1所述的半导体结构制作方法，其中，通过所述孔洞蚀刻所述膜层结构，以在所述膜层结构中形成电容孔洞包括：
    采用干法蚀刻的方式通过所述孔洞蚀刻所述膜层结构，以在所述膜层结构中形成电容孔洞。
  15. 一种半导体结构，通过权利要求1-14任一项所述的半导体结构制作方法制得。
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